Chip maintenance method and device, electronic equipment, storage medium and computer program product

Abstract

The invention provides a chip maintenance method and device, electronic equipment, a storage medium and a computer program product, and relates to the technical field of storage and calculation integration, and the method comprises the following steps: during a model operation period, based on a preset update period corresponding to each network layer in a model, updating the network layer in the model; updating a corresponding weight parameter of each network layer in the storage and calculation integrated chip; wherein the preset updating period is determined before the model is deployed in the storage and calculation integrated chip; the preset updating period is determined by performing a simulation test on each network layer based on the data drift characteristic of the storage and calculation integrated chip; the preset updating period is used for meeting the expected precision of the model. Through the scheme in the embodiment of the invention, the energy consumption of chip weight updating can be reduced, and the performance of the chip is improved.

Description

Technical Field

[0001] The present application relates to the technical field of integrated storage and computing chips, and in particular to a chip maintenance method, device, electronic device, storage medium and computer program product. Background Art

[0002] In related technologies, storage-computing integration is a technology that uses storage units to deploy model weights to realize calculations. By writing the weight parameters of the artificial intelligence (AI) model into the storage-computing unit, converting the input data into voltage and loading it onto the storage-computing array, the matrix multiplication calculation of the model can be completed. However, due to the irrational characteristics of new materials and new devices, after the model weight parameters are deployed in the storage-computing integration chip based on analog computing, the deployed weights will drift over time, and the model's reasoning accuracy will gradually decrease with the model deployment time.

[0003] In response to the above problems, there are basically two types of existing technologies. One is to continuously refresh device data through hardware design, which will increase chip power consumption. The other is through software design, or to perform periodic testing on the deployed model weights. When the reasoning accuracy drops to a certain level, the entire model weights are redeployed, or a unified fixed update cycle is directly adopted for all models. Regardless of whether the update cycle is applicable to the specific model reasoning accuracy, the model weight parameters are uniformly redeployed according to a fixed cycle. In this way, the existence of periodic testing will also lead to increased chip power consumption, and because it usually takes a lot of time to rewrite the entire model weight, the model will not be able to provide services normally during this period of time, affecting the performance of the chip. Summary of the invention

[0004] A chip maintenance method, device, electronic device, storage medium and computer program product provided in the embodiments of the present application can reduce the power consumption of the chip and improve the performance of the chip.

[0005] The technical solution of this application is implemented as follows:

[0006] The present application embodiment provides a chip maintenance method, including:

[0007] During the model operation, based on the preset update period corresponding to each network layer in the model, the weight parameters corresponding to each network layer in the storage and computing integrated chip are updated;

[0008] Among them, the preset update cycle is determined before the model is deployed on the storage and computing integrated chip, and the preset update cycle is determined based on the data drift characteristics of the storage and computing integrated chip, by simulation testing for each network layer; the preset update cycle is used to meet the expected accuracy of the model.

[0009] In the above scheme, during the model operation, based on the preset update period corresponding to each network layer in the model, before updating the corresponding weight parameters of each network layer in the storage-computing integrated chip, the method further includes:

[0010] Based on the acquired data drift characteristics, a simulation test is performed on each network layer of the model to determine the drift duration corresponding to each network layer; wherein the drift duration is the maximum duration that meets the expected accuracy condition;

[0011] Determine, based on the data drift characteristic and the drift duration corresponding to each of the network layers, an initial update period corresponding to each of the network layers that satisfies the expected accuracy;

[0012] Perform mutation and iterative update for each of the initial update cycles until a preset condition is met, and then stop to determine the preset update cycle corresponding to each of the network layers.

[0013] In the above solution, the data drift characteristic is determined based on the change of the first test data written in the sample chip over time.

[0014] In the above scheme, based on the acquired data drift characteristics, a simulation test is performed on each network layer of the model to determine the longest drift duration corresponding to each network layer that meets the expected accuracy condition, including:

[0015] Compile and deploy the model to a sample chip, and record the storage and computing units where the weights of each network layer are deployed in the sample chip;

[0016] Writing the second test data into the sample chip for simulation testing, and performing weight drift simulation on the storage and computing unit corresponding to each of the network layers based on the data drift characteristics, and determining the test result corresponding to each of the network layers; wherein, when performing weight drift simulation on the storage and computing unit corresponding to each of the network layers, the weights of the storage and computing units corresponding to other network layers remain unchanged;

[0017] Based on a comparison result of the test accuracy corresponding to the test result and the expected accuracy, the drift duration with the longest duration under the condition of satisfying the expected accuracy is determined.

[0018] In the above scheme, the weight drift simulation is performed on the storage and computing unit corresponding to each of the network layers based on the data drift characteristics to determine the test result corresponding to each of the network layers, including:

[0019] Querying a predetermined simulation weight corresponding to a predetermined drift duration in a data set; wherein the data set is determined based on the data drift characteristics and includes a correspondence between a plurality of drift durations and corresponding simulation weights;

[0020] The calculation result of the storage and computing unit corresponding to each network layer is determined based on the predetermined simulation weight, and the calculation result is passed to the next storage and computing unit until the last storage and computing unit outputs the test result.

[0021] In the above solution, the predetermined drift duration includes: a first drift duration and a second drift duration that are adjacent; the second drift duration is greater than the first drift duration; the first drift duration corresponds to a first test result, and the second drift duration corresponds to a second test result;

[0022] The determining, based on a comparison result of the test accuracy corresponding to the test result and the expected accuracy, of the drift duration with the longest duration under the condition of satisfying the expected accuracy comprises one of the following:

[0023] If the comparison result indicates that the test accuracy corresponding to the first test result is not less than the expected accuracy, and the test accuracy corresponding to the second test result is less than the expected accuracy, then determining the first drift duration to be the longest drift duration that satisfies the expected accuracy condition;

[0024] If the comparison result indicates that the test accuracy corresponding to the first test result and the second test result is greater than the expected accuracy, then the test accuracy corresponding to the third drift duration is compared with the expected accuracy until the drift duration that meets the expected accuracy is determined; wherein the third drift duration is a duration greater than the second drift duration;

[0025] If the comparison result indicates that the test accuracy corresponding to the first test result and the second test result respectively is less than the expected accuracy, the test accuracy corresponding to the fourth drift duration is compared with the expected accuracy until the drift duration that meets the expected accuracy is determined; wherein the fourth drift duration is a duration that is less than the first drift duration.

[0026] In the above solution, determining the initial update period that satisfies the expected accuracy corresponding to each network layer based on the data drift characteristics and the drift duration corresponding to each network layer includes:

[0027] Determining a maximum drift duration in each of the drift durations, and determining a ratio of each of the drift durations to the maximum drift duration;

[0028] A fifth drift duration and a sixth drift duration are queried in the data set; wherein the fifth drift duration satisfies: the test accuracy of the model determined based on the duration of each network layer determined by multiplying the fifth drift duration and each ratio is not less than the expected accuracy; the sixth drift duration satisfies: the test accuracy of the model determined based on the duration of each network layer determined by multiplying the sixth drift duration and each ratio is less than the expected accuracy;

[0029] The initial update period corresponding to each of the network layers is determined based on the product of the fifth drift duration and each of the ratios.

[0030] In the above scheme, performing mutation and iterative updating for each of the initial update cycles until a preset condition is met and stopping, and determining the preset update cycle corresponding to each of the network layers, includes:

[0031] Determine a first average update rate corresponding to a first group of update cycles; wherein the first group of update cycles is composed of each of the initial update cycles;

[0032] Performing mutation update on the first group of update cycles to determine multiple groups of second group update cycles;

[0033] If the first average update rate is greater than the second average update rate corresponding to each group of the second group update periods, a mutation update is performed on the second group update periods with the lowest average update rate to determine multiple groups of third group update periods, and the process continues until it is determined that the N+1th average update rate is greater than the Nth average update rate, and the update period in the Nth group update period is determined to be the preset update period corresponding to each of the network layers.

[0034] The present application also provides a chip maintenance device, including:

[0035] An updating unit, used to update the weight parameters corresponding to each network layer in the storage-computing integrated chip based on a preset update period corresponding to each network layer in the model during the model operation;

[0036] Among them, the preset update cycle is determined before the model is deployed on the storage and computing integrated chip, and the preset update cycle is determined based on the data drift characteristics of the storage and computing integrated chip, by simulation testing for each network layer; the preset update cycle is used to meet the expected accuracy of the model.

[0037] An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein the memory stores a computer program that can be run on the processor, and the processor implements the steps in the above method when executing the computer program.

[0038] An embodiment of the present application further provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps in the above method are implemented.

[0039] An embodiment of the present application also provides a computer program product, including a computer program, which implements the steps in the above method when executed by a processor.

[0040] In an embodiment of the present application, during the operation of the model, based on the preset update period corresponding to each network layer in the model, the corresponding weight parameters of each network layer in the storage-computing integrated chip are updated. Wherein, the preset update period is determined before the model is deployed on the storage-computing integrated chip, and the preset update period is determined based on the data drift characteristics of the storage-computing integrated chip by simulation testing for each network layer; the preset update period is used to meet the expected accuracy of the model. In this way, since there is no need to perform periodic testing when updating the weights of the weight storage-computing integrated chip, the power consumption of the chip during periodic testing is saved, and since the scheme in the embodiment of the present application is for updating the weights of each network layer, the update time is shorter than the scheme in the related art for updating the weights of all network layers of the model, and the impact on the chip service is smaller, thereby improving the performance of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 An optional effect schematic diagram of the related technology provided by the embodiment of the present application;

[0042] Figure 2 An optional flowchart of a chip maintenance method provided in an embodiment of the present application;

[0043] Figure 3 An optional flowchart of a chip maintenance method provided in an embodiment of the present application;

[0044] Figure 4 An optional effect schematic diagram of the chip maintenance method provided in the embodiment of the present application;

[0045] Figure 5 An optional effect schematic diagram of the chip maintenance method provided in the embodiment of the present application;

[0046] Figure 6 An optional effect schematic diagram of the chip maintenance method provided in the embodiment of the present application;

[0047] Figure 7 An optional flowchart of a chip maintenance method provided in an embodiment of the present application;

[0048] Figure 8An optional flowchart of a chip maintenance method provided in an embodiment of the present application;

[0049] Fig. 9 An optional flowchart of a chip maintenance method provided in an embodiment of the present application;

[0050] Fig.10 An optional effect schematic diagram of the chip maintenance method provided in the embodiment of the present application;

[0051] Fig.11 An optional flowchart of a chip maintenance method provided in an embodiment of the present application;

[0052] Fig.12 An optional flowchart of a chip maintenance method provided in an embodiment of the present application;

[0053] Fig.13 An optional flowchart of a chip maintenance method provided in an embodiment of the present application;

[0054] Fig.14 A schematic diagram of the structure of a chip maintenance device provided in an embodiment of the present application;

[0055] Fig.15 A hardware entity schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0056] In order to make the purpose, technical solutions and advantages of the present application clearer, the technical solutions of the present application are further elaborated in detail below in conjunction with the drawings and embodiments. The described embodiments should not be regarded as limiting the present application. All other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.

[0057] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0058] If similar descriptions of "first / second" appear in the application documents, the following instructions are added. In the following description, the terms "first\second\third" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0059] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0060] Among the related technologies, storage-computing integration is a technology that uses storage units to implement computing. It can effectively solve the "memory" and "power consumption wall" problems caused by the repeated transfer of data between the processor and the memory in traditional von Neumann architecture chips, and is expected to become a localized solution for artificial intelligence computing chips with higher computing power and higher energy efficiency. Figure 1 , is the working principle of the integrated storage and computing chip based on memristor (Resistive Random Access Memory, RRAM). First, the conductance value of the memristor cross array is adjusted according to the weight matrix B data, and then the voltage is input to the memristor cross array according to the input matrix A data. Based on Ohm's law and Kirchhoff's law, the output current of the memristor array is the output matrix C. It can be seen that by writing the weight parameters of the AI ​​model into the storage and computing unit, converting the input data into voltage and loading it onto the storage and computing array, the matrix multiplication calculation of the model can be completed. However, due to the irrational characteristics of new materials and new devices, after the storage and computing chip based on analog computing deploys the model weight parameters, the deployed weights will drift over time, and the inference accuracy of the model will gradually decrease with the model deployment time.

[0061] There are three main disadvantages to frequently refreshing device data through hardware design: first, constantly refreshing devices will significantly increase power consumption, thereby significantly reducing the low-power advantage of storage-computing technology; second, there are many storage-computing technology devices, and many storage devices have limited erasable lifespans. Frequent device refreshes will significantly reduce the chip's service life; third, it increases hardware complexity.

[0062] The solution of performing periodic testing and overall model update during model service through software design has three disadvantages: first, periodic testing will also increase power consumption, and the current storage and computing chips are usually used in end-side systems with extremely high power consumption requirements; second, it usually takes a long time to rewrite the entire model weight, and the model will not be able to provide services normally during this period; third, storing test data sets in the actual operating environment takes up storage space, and the current storage and computing chips are mostly used in end-side systems with very limited resources.

[0063] In view of the above technical problems, the present application embodiment provides a chip maintenance method, please refer to Figure 2 , is an optional flow chart of the chip maintenance method provided in the embodiment of the present application, which will be combined with Figure 2 The steps shown are explained:

[0064] S101. During the operation of the model, based on the preset update period corresponding to each network layer in the model, the corresponding weight parameters of each network layer in the storage-computing integrated chip are updated; wherein, the preset update period is determined before the model is deployed on the storage-computing integrated chip, and the preset update period is determined based on the data drift characteristics of the storage-computing integrated chip, by performing simulation tests on each network layer; the preset update period is used to meet the expected accuracy of the model.

[0065] In an embodiment of the present application, before the model is deployed on the storage-computing integrated chip, the chip maintenance device obtains the data drift characteristics of the storage-computing integrated chip determined by the test. Based on the data drift characteristics of the storage-computing integrated chip, the simulation drift weight of each network layer of the model under the predetermined drift duration is determined. Then the test data is input into the model to perform a simulation test based on the simulation drift weight to determine the test result when the weight drifts for each network layer, and then based on the comparison result of the test accuracy corresponding to the test result and the expected accuracy, the preset update period corresponding to each network layer is determined, and the preset update period of each network layer is stored. During the operation of the model, when the time since the last update of the weight corresponding to any network layer reaches the time of the corresponding preset update period, the weight parameter of the network layer is used to update the corresponding weight parameter of the network layer in the storage-computing integrated chip.

[0066] The model may be an AI model. The execution subject of determining the preset update cycle may be other devices with corresponding functions. After determining the preset update cycle corresponding to each network layer, the other devices may send the corresponding preset update cycle to the chip maintenance device. The chip maintenance device may be a server or terminal with corresponding storage and computing integrated chip maintenance functions.

[0067] In the embodiment of the present application, a software solution is used to maintain the model. By testing the data drift characteristics of the storage and computing integrated chip, the model is simulated according to the data drift characteristics of the chip before the model is deployed (usually in the compilation stage), and the preset update cycle of the weight data of each layer of the model is obtained. The preset update cycle of each layer of weights is stored when the model is deployed, and the weight of each network layer in the storage and computing integrated chip is updated according to the set update cycle during the model maintenance period. This solution can be implemented by pure software, without the problem of high-frequency refresh of device data in hardware design. At the same time, it can solve the power consumption problem caused by repeated testing during the model operation service and the problem of storage space occupied by storing test data sets, and the model weight is updated in units of each layer of the network, which has technical advantages such as lower power consumption and shorter update time for the entire model weight update.

[0068] In an embodiment of the present application, during the operation of the model, based on the preset update period corresponding to each network layer in the model, the corresponding weight parameters of each network layer in the storage-computing integrated chip are updated. Wherein, the preset update period is based on the data drift characteristics of the storage-computing integrated chip before the model is deployed on the storage-computing integrated chip, and a simulation test is performed on each network layer to determine the update period that meets the expected accuracy of the model. In this way, since there is no need to perform periodic testing when updating the weights of the weight storage-computing integrated chip, the power consumption of the chip during periodic testing is saved, and since the scheme in the embodiment of the present application updates the weight of each network layer, the update time is shorter than the scheme in the related art that updates the weights of all network layers of the model, and the impact on the service of the chip is smaller, thereby improving the performance of the chip.

[0069] See also Figure 3 , is an optional flow chart of the chip maintenance method provided in the embodiment of the present application, Figure 2 Before S101 shown in the figure, the following steps may also be included: S201 to S203, which are described in combination:

[0070] S201. Based on the acquired data drift characteristics, a simulation test is performed on each network layer of the model to determine the drift duration corresponding to each network layer; wherein the drift duration is the maximum duration that meets the expected accuracy condition.

[0071] In the embodiment of the present application, before determining the preset update cycle, the chip maintenance device can obtain the data drift characteristics of the same type of chips. Based on the data drift characteristics, weight drift is performed for each network layer to determine the test accuracy of the model corresponding to the drift weight under different drift durations. Among the drift durations corresponding to multiple test accuracies, the longest drift duration that meets the expected accuracy condition is determined.

[0072] In an embodiment of the present application, the chip maintenance device can determine a data set based on data drift characteristics. The data set is determined based on the data drift characteristics, including the correspondence between multiple drift durations and corresponding simulation weights. The chip maintenance device can use the binary search method or the incremental search method to search and determine the drift weights under different drift durations in the data set, and then perform a weight drift test on each network layer of the model based on the different drift weights to determine the test accuracy of the model. Determine the longest drift duration that meets the expected accuracy conditions among the drift durations corresponding to multiple test accuracies.

[0073] In the embodiment of the present application, the data drift characteristic is determined based on the change of the first test data written in the sample chip over time. Exemplarily, the data drift characteristic can be determined by a third-party device, which writes the first test data into the sample chip and monitors and records the change of the first test data written into the sample chip over time to determine the data drift characteristic.

[0074] In the embodiment of the present application, the data drift characteristics determined by the third-party device may include two categories: ordered directional drift and normal distribution drift.

[0075] Method for determining ordered directional drift: Taking a certain memristor-based integrated memory and computing chip as an example, the memory and computing unit stores data by applying a pulse voltage between two metal plates to allow the doped metal oxide to form a conductive channel. The conductivity of the device is the stored data. However, as time goes by, the doped metal oxide in the device will become more and more disordered, and the conductivity will gradually decrease. For this type of chip, the data drift characteristics of the chip can be determined by writing the maximum value to the chip memory and computing unit, and then tracking and recording the average change in the memory and computing unit data. For example, combined with Figure 4 , the first test data in the chip gradually decreases with the change of time, then the data drift characteristics of the chip are determined to be classified as ordered directional drift. In order to shorten the test time, the storage and computing units can be divided into several batches, and different sizes of data are written to each batch. The storage and computing units in each batch are tracked to obtain the drift characteristics of the device in the data segment, and then the complete drift characteristics are assembled. For example, the storage and computing units are divided into 20 batches, and 100%, 95%, 90%..., 5% of the maximum data are written respectively. The data of these storage and computing units are tracked and tested when they drift to 95%, 90%, 85%...0%, and the complete drift characteristics of the device can be formed.

[0076] Method for determining normal distribution drift: For this type of chip, for different data in the effective storage range, such as the effective storage range of an 8-bit precision chip is [-127, 127], select a batch of storage and computing units to write these data, track and statistically analyze the distribution of stored data over time, and record the standard deviation at different times. Figure 5 This is the data distribution diagram with shorter writing time. Figure 6 This is a data distribution diagram for a longer data writing time. It can be seen that as time goes by, the variance of the data distribution of the storage and computing unit continues to increase, and the data randomness becomes stronger, so it can be determined that the chip has a normal distribution drift.

[0077] S202: Based on the data drift characteristics and the drift duration corresponding to each of the network layers, determine an initial update period corresponding to each of the network layers that meets the expected accuracy.

[0078] In an embodiment of the present application, the chip maintenance device determines the maximum drift duration with the longest duration among the drift durations corresponding to each network layer. The ratio of each drift duration to the maximum drift duration is determined. The chip maintenance device finds different drift durations in the data set. The duration corresponding to each network layer of the model is determined based on the product of the different drift durations found and each ratio, and the drift weight corresponding to each network layer under the corresponding duration is determined based on the data drift characteristics, and the test accuracy of the model under the weight is determined by testing. The longest drift duration that meets the expected accuracy is determined among the different drift durations, and the initial update period corresponding to each network layer is determined by multiplying the determined longest drift duration with the ratio of each network layer.

[0079] S203: Perform mutation and iterative update for each of the initial update cycles until a preset condition is met, and then stop to determine the preset update cycle corresponding to each of the network layers.

[0080] In the embodiment of the present application, the chip maintenance device determines the first average update rate corresponding to the first group of update cycles formed by each initial update cycle. Then, a variation update is performed for each initial update cycle to determine the second group of update cycles, and the second average update rate corresponding to the second group of update cycles is compared with the first average update rate. Based on the comparison result, the second group of update cycles is further varied and iteratively updated until it is determined that the latest average update rate is greater than the previous average update rate, and the group of update cycles corresponding to the previous average update rate is determined to be the preset update cycle.

[0081] In an embodiment of the present application, in the model compilation stage, in addition to the given model, it is also necessary to configure the model test data set (and the actual results corresponding to the test data) and the expected accuracy of the model, and then compile the model normally, confirm the model network weight deployment position and the model reasoning control flow, and then simulate the model network layer by layer according to the obtained chip drift characteristics (stored in the storage and computing integrated chip compiler) to obtain the preset update cycle corresponding to each network layer of the model based on the specified test data set and expected accuracy.

[0082] In the embodiment of the present application, based on the acquired data drift characteristics, simulation tests are performed for each network layer of the model to determine the longest drift duration corresponding to each network layer that meets the expected accuracy conditions; based on the data drift characteristics and the drift duration corresponding to each network layer, the initial update period that meets the expected accuracy is determined for each network layer; mutation iterative updates are performed for each initial update period until the preset conditions are met, and the preset update period corresponding to each network layer is determined. In this way, the weight parameters corresponding to each network layer can be updated based on the preset update period when the storage-computing integrated chip is updated, which saves time and reduces the impact on chip performance compared to the solution of updating the weights of all network layers of the model in the related art.

[0083] See also Figure 7 , is an optional flow chart of the chip maintenance method provided in the embodiment of the present application, Figure 2 S201 shown in the figure can also be implemented by S301 to S303, and the combined steps are described as follows:

[0084] S301, compile and deploy the model to a sample chip, and record the storage and computing units where the weights of each network layer are deployed in the sample chip.

[0085] In the embodiment of the present application, during the model simulation stage, the chip maintenance device can deploy the model variation to the sample chip. The weight deployment position (storage and computing unit of weight deployment) and model reasoning control flow of each network layer in the model during the compilation process are recorded. Among them, the model reasoning control flow is used to indicate the data flow between the storage and computing units during the simulation test.

[0086] In an embodiment of the present application, based on the determined model inference control flow and weight deployment location, the weights of each network layer of the model can be deployed to the corresponding position of the storage and computing integrated chip during model deployment in the application phase, and the corresponding model inference control flow can be configured.

[0087] S302: Write the second test data into the sample chip for simulation testing, and perform weight drift simulation on the storage and computing unit corresponding to each of the network layers based on the data drift characteristics to determine the test result corresponding to each of the network layers.

[0088] In an embodiment of the present application, before the simulation test of the model, it is necessary to obtain the second test data, the actual result corresponding to the second test data, and the expected accuracy of the model. The chip maintenance device writes the second test data into the sample chip where the model is deployed, and the second test data is transmitted and calculated inside the sample chip according to the model reasoning control flow. During each simulation test of the model (each simulation test only determines the test result of a corresponding network layer), the different drift weights of the storage and calculation units corresponding to each network layer are determined based on the data drift characteristics, and the different calculation results of the corresponding network layer during each simulation test are determined based on the different drift weights, and the calculation results are passed to the storage and calculation units of the next network layer until the test results of the model corresponding to different drift weights during each simulation test are determined.

[0089] Among them, when the weight drift simulation is performed on the storage and computing unit corresponding to each of the network layers, the weights of the storage and computing units corresponding to other network layers remain unchanged.

[0090] S303: Based on a comparison result of the test accuracy corresponding to the test result and the expected accuracy, determine the longest drift duration that meets the expected accuracy condition.

[0091] In the embodiment of the present application, the chip maintenance device compares the test results of different drift weights with the actual results obtained to determine the test accuracy, and compares the test accuracy with the expected accuracy obtained to determine the comparison results corresponding to different drift weights. Determine the drift weight corresponding to the comparison result that meets the expected accuracy in the comparison result, and determine the duration corresponding to the drift weight as the drift duration corresponding to each network layer based on the data drift characteristics.

[0092] In the embodiment of the present application, the deployment model is compiled to the sample chip, and the storage computing unit and model reasoning control flow of the weight deployment of each network layer in the sample chip are recorded; wherein, the model reasoning control flow is used to indicate the data flow between the storage computing units during the simulation test; the second test data is written into the sample chip for simulation test, and the weight drift simulation is performed for the storage computing unit corresponding to each network layer based on the data drift characteristics, and the test result corresponding to each network layer is determined; wherein, when the weight drift simulation is performed for the storage computing unit corresponding to each network layer, the weight of the storage computing unit corresponding to other network layers remains unchanged; based on the comparison result of the test accuracy corresponding to the test result and the expected accuracy, the drift duration with the longest duration under the condition of meeting the expected accuracy is determined. In this way, simulation tests are performed for each network layer of the model to determine the drift duration corresponding to each network layer, and the weights of the storage computing units corresponding to other network layers are maintained unchanged, which can reduce the drift interference of other network layers during the simulation test of each network layer, and the determined drift duration is more accurate.

[0093] See also Figure 8 , is an optional flow chart of the chip maintenance method provided in the embodiment of the present application, Figure 7 S302 shown in the figure can also be implemented by S401 to S402, and the combined steps are described as follows:

[0094] S401. Query a predetermined simulation weight corresponding to a predetermined drift duration in a data set; wherein the data set is determined based on the data drift characteristics, and includes a correspondence between multiple drift durations and corresponding simulation weights.

[0095] In an embodiment of the present application, the chip maintenance device determines a data set based on data drift characteristics, and the data set includes a correspondence between multiple drift durations and corresponding simulation weights. The chip maintenance device can query the drift duration in the data set based on a binary search method or a gradually increasing search method, and a predetermined simulation weight corresponding to the predetermined drift duration.

[0096] Exemplarily, the chip maintenance device can search for the predetermined simulation weight corresponding to each drift duration in the data set in the order of drift duration based on a gradually increasing search method. The chip maintenance device can also search for the predetermined simulation weights corresponding to 100 days and 101 days in the data set for the first time based on a binary search method.

[0097] S402. Determine the calculation result of the storage and computing unit corresponding to each network layer based on the predetermined simulation weight, and pass the calculation result to the next storage and computing unit until the last storage and computing unit outputs the test result.

[0098] In the embodiment of the present application, the chip maintenance device can determine the calculation result of the storage and calculation unit corresponding to the network layer based on the predetermined simulation weight and the data transmitted to the corresponding network layer. The calculation result is transmitted to the next storage and calculation unit indicated by the model reasoning control flow for calculation, until the last storage and calculation unit calculates and outputs the test result corresponding to the network.

[0099] In an embodiment of the present application, when there are at least two predetermined simulation weights determined, a simulation test can be performed for each predetermined simulation weight to determine the test result of each predetermined simulation weight corresponding to each network layer.

[0100] In an embodiment of the present application, a predetermined simulation weight corresponding to a predetermined drift duration is queried in a data set. The calculation result of the storage and computing unit corresponding to each network layer is determined based on the predetermined simulation weight, and the calculation result is passed to the next storage and computing unit indicated by the model reasoning control flow until the last storage and computing unit outputs the test result. In this way, the model is simulated and tested based on the predetermined simulation weight corresponding to each network layer to output the test result, which can avoid the influence of the drift of the storage and computing units of other network layers to the greatest extent, thereby ensuring the accuracy of the output test results and improving the accuracy of the test precision. In the case of a high test precision, the preset update period finally determined can also ensure the calculation accuracy of the model after being updated according to the preset update period.

[0101] The illustrated S303 can also be implemented by the following steps: S3031 to S3033. The predetermined drift duration includes: a first drift duration and a second drift duration that are adjacent; the second drift duration is greater than the first drift duration; the first drift duration corresponds to a first test result, and the second drift duration corresponds to a second test result.

[0102] S3031. If the comparison result indicates that the test accuracy corresponding to the first test result is not less than the expected accuracy, and the test accuracy corresponding to the second test result is less than the expected accuracy, then determine that the first drift duration is the longest drift duration that meets the expected accuracy condition.

[0103] In an embodiment of the present application, the chip maintenance device can sequentially search for the first drift duration and the corresponding first drift weight in the data set based on a gradually increasing search method, determine the first test result based on the first drift weight and the data transmitted to each network layer, determine the corresponding test accuracy based on the first test result and the true result, and compare the test accuracy with the expected accuracy. The chip maintenance device then sequentially searches for the second drift duration and the corresponding second drift weight adjacent to the first drift weight in the data set based on a gradually increasing search method, determines the second test result based on the second drift weight and the data transmitted to each network layer, determines the corresponding test accuracy based on the second test result and the true result, and compares the test accuracy with the expected accuracy. If the comparison result indicates that the test accuracy corresponding to the first test result is not less than the expected accuracy, and the test accuracy corresponding to the second test result is less than the expected accuracy, then the first drift duration is determined to be the longest drift duration that meets the expected accuracy condition.

[0104] In an embodiment of the present application, the chip maintenance device can find the adjacent first drift duration and second drift duration in the data set based on the binary search method, and determine the first drift weight corresponding to the first drift duration and the second drift weight corresponding to the second drift duration. A first test result is determined based on the first drift weight and the data transmitted to each network layer, and the corresponding test accuracy is determined based on the first test result and the true result, and the test accuracy is compared with the expected accuracy. A second test result is determined based on the second drift weight and the data transmitted to each network layer, and the corresponding test accuracy is determined based on the second test result and the true result, and the test accuracy is compared with the expected accuracy. If the comparison result indicates that the test accuracy corresponding to the first test result is not less than the expected accuracy, and the test accuracy corresponding to the second test result is less than the expected accuracy, then the first drift duration is determined to be the drift duration with the longest duration that meets the expected accuracy condition.

[0105] S3032. If the comparison result indicates that the test accuracy corresponding to the first test result and the second test result respectively is greater than the expected accuracy, the test accuracy corresponding to the third drift duration is compared with the expected accuracy until the drift duration that meets the expected accuracy is determined; wherein the third drift duration is a duration greater than the second drift duration.

[0106] In an embodiment of the present application, the chip maintenance device can find the adjacent first drift duration and second drift duration in the data set based on the binary search method, and determine the first test result corresponding to the first drift duration and the second test result corresponding to the second drift duration. The corresponding test accuracy is determined based on the first test result and the second test result, respectively, and the test accuracy corresponding to the first test result and the second test result is compared with the expected accuracy. If the comparison result indicates that the test accuracy corresponding to the first test result and the second test result is greater than the expected accuracy, the test accuracy corresponding to the third drift duration is compared with the expected accuracy until the drift duration that meets the expected accuracy is determined; wherein, the third drift duration is a duration greater than the second drift duration.

[0107] S3033. If the comparison result indicates that the test accuracy corresponding to the first test result and the second test result respectively is less than the expected accuracy, the test accuracy corresponding to the fourth drift duration is compared with the expected accuracy until the drift duration that meets the expected accuracy is determined; wherein the fourth drift duration is a duration that is less than the first drift duration.

[0108] In an embodiment of the present application, the chip maintenance device can find the adjacent first drift duration and second drift duration in the data set based on the binary search method, and determine the first test result corresponding to the first drift duration and the second test result corresponding to the second drift duration. The corresponding test accuracy is determined based on the first test result and the second test result, respectively, and the test accuracy corresponding to the first test result and the second test result is compared with the expected accuracy. If the comparison result indicates that the test accuracy corresponding to the first test result and the second test result is respectively less than the expected accuracy, the test accuracy corresponding to the fourth drift duration is compared with the expected accuracy until the drift duration that meets the expected accuracy is determined; wherein, the fourth drift duration is a duration less than the first drift duration.

[0109] Exemplary, combined Fig. 9 . The chip maintenance device searches for the predetermined drift duration M of 100 days and 101 days based on the binary search method. Starting from M=100 days, the model test accuracy corresponding to M=100 and 101 days is calculated first. Case 1 is that the model accuracy is lower than expected at 100 days, so the calculation starts from M=50 days. Case 2 is that the model accuracy meets expectations at 100 days and is lower than expected at the 101st day, so M=100 is the search result. Case 3 is that the model meets expectations at drifting 100 days and 101 days, so the calculation starts from M=200 days, and so on to determine the final drift duration.

[0110] See also Fig.10, is an optional flow chart of the chip maintenance method provided in the embodiment of the present application, Figure 3 S202 shown in the figure can also be implemented by S501 to S503, and the combined steps are described as follows:

[0111] S501 . Determine a maximum drift duration in each drift duration, and determine a ratio of each drift duration to the maximum drift duration.

[0112] In an embodiment of the present application, the chip maintenance device determines a maximum drift duration among the drift durations corresponding to multiple network layers of the model, and determines a ratio of each drift duration to the maximum drift duration.

[0113] In the embodiment of the present application, it is assumed that the drift durations of the N-layer network of the model are T1, T2..., TN. The maximum value is selected as the allowable drift duration of the i-th layer, that is, Ti = max{T1, T2..., TN}, and the ratio of the drift duration of each layer to Ti is calculated, which are T1 / Ti, T2 / Ti..., TN / Ti respectively.

[0114] S502. Query the fifth drift duration and the sixth drift duration in the data set; wherein the fifth drift duration satisfies: the test accuracy of the model determined based on the duration of each network layer determined by multiplying the fifth drift duration and each of the ratios is not less than the expected accuracy; the sixth drift duration satisfies: the test accuracy of the model determined based on the duration of each network layer determined by multiplying the sixth drift duration and each of the ratios is less than the expected accuracy.

[0115] In an embodiment of the present application, the chip maintenance device can query two drift durations in the data set based on a binary search method or a gradually increasing search method. The duration of each network layer is determined based on the product of the two drift durations and each of the ratios, and then the drift weight corresponding to each network layer under the duration is determined based on the data drift characteristics. Then, the model simulation test is performed based on the drift weight of each network layer corresponding to the two drift durations to determine the test accuracy corresponding to the model. Until the fifth drift duration and the sixth drift duration are found. Among them, the fifth drift duration satisfies: based on the duration of each network layer determined by the fifth drift duration and each of the ratios, the test accuracy of the model determined is not less than the expected accuracy; the sixth drift duration satisfies: based on the duration of each network layer determined by the sixth drift duration and each of the ratios, the test accuracy of the model determined is less than the expected accuracy.

[0116] In the embodiment of the present application, (t1, t2, t3, ..., tN) is used to represent the weight update period of an AI model with N layers of weight data. The update period of the first weight layer is t1, the update period of the second weight layer is t2, the update period of the third weight layer is t3, ..., and the update period of the Nth weight layer is tN. p(t1, t2, ..., t N ) indicates that the weight data of an AI model with N layers of weight data drifted by t1, t2, ..., t N The chip maintenance device fixes the ratio of the drift time of each layer of network weight data to T1 / Ti, T2 / Ti..., TN / Ti, and then searches for T (the fifth drift time) in the data set, that is, searches for T such that p(T1 / T i *T, T2 / T i *T,...,T N / T i *T) meets the expected accuracy, p(T1 / T i *(T+1), T2 / T i *(T+1),...,T N / T i *(T+1)) is lower than the expected accuracy, and p0 in formula (1) is the expected accuracy of the model configured by the user.

[0117]

[0118] S503: Determine the initial update period corresponding to each of the network layers based on the product of the fifth drift duration and each of the ratios.

[0119] In the embodiment of the present application, the chip maintenance device determines the initial update period corresponding to each network layer based on multiplying the fifth drift time by the ratio corresponding to each network layer.

[0120] In the embodiment of the present application, the chip maintenance device can also determine the initial update period corresponding to each network layer based on the ratio of the first drift duration to each network layer and multiplying by a preset proportional factor k, where k is a value less than 1 and greater than 0.

[0121] In the embodiment of the present application, since there will be a certain error between the simulation results of the model in the development environment and the actual test results on the chip, in order to ensure the accuracy of model reasoning after the model maintenance on the chip according to the simulation results, a proportional factor k not exceeding 1 can be set, and the model update cycle is set to (T1 / T i *T*k, T2 / T i *T*k,...,T N / T i*T*k, that is, the update period of the first layer network is T1 / T i *T*k, the update period of the layer 2 network is T2 / T i *T*k.......The smaller the k, the higher the required model inference accuracy and the shorter the set model update cycle.

[0122] In the embodiment of the present application, the maximum drift duration is determined in each drift duration, and the ratio of each drift duration to the maximum drift duration is determined; the fifth drift duration and the sixth drift duration are queried in the data set; wherein, the fifth drift duration satisfies: the test accuracy of the determined model is not less than the expected accuracy based on the duration of each network layer determined by the product of the fifth drift duration and each ratio; the sixth drift duration satisfies: the test accuracy of the determined model is less than the expected accuracy based on the duration of each network layer determined by the product of the sixth drift duration and each ratio; the initial update period corresponding to each network layer is determined based on the product of the fifth drift duration and each ratio. In this way, based on the accuracy consideration of all network layers, the initial update period of each network layer determined by updating the determined drift duration again can make the accuracy of the model after updating the preset update period determined based on the initial update period more consistent with the expected accuracy of the model as a whole, thereby ensuring the performance of the model.

[0123] See also Fig.11 , is an optional flow chart of the chip maintenance method provided in the embodiment of the present application, Figure 3 S203 shown in FIG. 1 can also be implemented by S601 to S603, and the combined steps are described as follows:

[0124] S601. Determine a first average update rate corresponding to a first group of update cycles; wherein the first group of update cycles is composed of each of the initial update cycles.

[0125] In the embodiment of the present application, the chip maintenance device can combine the initial update cycles corresponding to each network layer to obtain a first group of update cycles, and calculate the first average update rate for the initial update cycles in the first group of update cycles.

[0126] S602: Perform mutation update on the first group of update cycles to determine multiple groups of second group update cycles.

[0127] In the embodiment of the present application, a variation update is performed for each initial update cycle, a sub-cycle corresponding to each initial update cycle is determined, and a plurality of second update cycles are formed based on the sub-cycles corresponding to each initial update cycle.

[0128] In the embodiment of the present application, the chip maintenance device randomly increases, decreases or retains the original value for each initial update cycle to determine the corresponding multiple first sub-cycles. Based on the combination of the multiple first sub-cycles corresponding to each initial update cycle, multiple groups of second group update cycles are determined. Each group of second group update cycles includes the first sub-cycle corresponding to each initial update cycle.

[0129] In the embodiment of the present application, each initial update cycle is randomly increased, decreased, or retained based on the first group of update cycles, and X of them are selected as a second group of update cycles. The increase or decrease value can be adjusted according to the size of the update cycle, such as 1 day or 1 week; the selection ratio can also be adjusted according to the situation. When the number of network layers is small, all solutions can be selected as the sub-solution set. When the number of network layers is large, the selection ratio can be reduced accordingly.

[0130] S603. If the first average update rate is greater than the second average update rate corresponding to each group of the second group update periods, a mutation update is performed on the second group update periods with the lowest average update rate to determine multiple groups of third group update periods, and the process continues until it is determined that the N+1th average update rate is greater than the Nth average update rate, and the update period in the Nth group update period is determined to be the preset update period corresponding to each of the network layers.

[0131] In the embodiment of the present application, the chip maintenance device calculates and determines the second average update rate corresponding to the second group of update cycles. The first average update rate and the second average update rate are compared. If the first average update rate is greater than the second average update rate corresponding to each group of the second group of update cycles, the second group of update cycles with the lowest average update rate is used as a new parent cycle for mutation update to determine multiple groups of third group update cycles and their corresponding third average update rates, and each third average update rate is compared with the second average update rate corresponding to the second group of update cycles with the lowest average update rate, until it is determined that the N+1th average update rate is greater than the Nth average update rate, and the update cycle in the Nth group of update cycles is determined to be the preset update cycle corresponding to each of the network layers.

[0132] In an embodiment of the present application, the chip maintenance device can perform simulation testing on the model based on a set of drift weights corresponding to each group of second-group update cycles, determine the test accuracy of the model, and determine the second-group update cycle that meets the expected accuracy among multiple groups of second-group update cycles; and determine the second-group update cycle with the lowest average update rate among the second-group update cycles that meet the expected accuracy.

[0133] In the embodiment of the present application, the first average update rate corresponding to the first group of update cycles is determined, and a mutation update is performed on the first group of update cycles to determine multiple groups of second group update cycles; if the first average update rate is greater than the second average update rate corresponding to each group of second group update cycles, a mutation update is performed on the second group of update cycles with the lowest average update rate to determine multiple groups of third group update cycles, and the process stops when it is determined that the N+1th average update rate is greater than the Nth average update rate, and the update cycle in the Nth group of update cycles is determined to be the preset update cycle corresponding to each network layer. In this way, based on the update rate considerations for all network layers, the preset update cycle of each network layer is determined by performing a mutation iterative update again for the determined initial update cycle length, so that the update rate of the network layer can meet the minimum requirements, thereby reducing the energy consumption of model weight updates.

[0134] See also Fig.12 , is an optional flow chart of the chip maintenance method provided in the embodiment of the present application, and the combined steps are described as follows:

[0135] S11, select a chip to write data.

[0136] In the embodiment of the present application, a third-party device selects a sample chip of the same type as the storage-computing integrated chip, then performs a data drift characteristic test on the selected sample chip, and writes the first test data into the chip.

[0137] S12. Record the data changes of each storage and computing unit.

[0138] In the embodiment of the present application, the third-party device records the change of the data volume of the first test data in each storage and computing unit of the sample chip over time to determine the data drift characteristics of the sample chip.

[0139] S13. Count and store data change characteristics.

[0140] In the embodiment of the present application, the third-party device sends the determined data drift characteristics to the chip maintenance device.

[0141] S14. Set the expected value of network reasoning accuracy and test data set.

[0142] In an embodiment of the present application, the chip maintenance device obtains second test data and true results for the model to be tested, as well as the expected accuracy corresponding to the model.

[0143] S15. Compile the model to determine the deployment location of the network weight storage array.

[0144] In an embodiment of the present application, the chip maintenance device compiles the model on the sample chip and determines the deployment location of each network layer weight.

[0145] S16, simulate and obtain the model weight update cycle.

[0146] In an embodiment of the present application, a weight drift simulation test is performed on each deployed network layer based on the second test data to determine a preset update period corresponding to each network layer.

[0147] S17. Deploy model weights and configure the network according to the orchestration location.

[0148] S18: Storage model deployment time and update cycle.

[0149] In an embodiment of the present application, the model weight data is deployed on a storage and computing integrated chip according to the weight deployment location given by the compiler, and the model reasoning control flow is configured, and then the model weight deployment location, preset update cycle and deployment time are stored.

[0150] S19. The model runs normally.

[0151] S20. Periodically (eg, every day) determine whether the system has a model that needs to be updated.

[0152] S21. Update the model weight data and record the update time.

[0153] In an embodiment of the present application, during the operation of the model, it is periodically determined whether the last deployment or update time of each layer of the network of the model deployed by the system has reached the update period from the current time, and weight deployment is performed on the model network layer whose deployment time has reached the update period, and the update time of the network layer of the model is updated.

[0154] Compared with the prior art solution one (hardware update solution), the embodiment of the present application can simplify the complexity of hardware design, reduce system power consumption, and extend the service life of the chip. Compared with the prior art solution two (software test update solution), the embodiment of the present application advances the model weight update cycle test from the actual operating environment to the development environment, and updates the weight by layer, so that the update rate of the network key layer that has a greater impact on the model calculation accuracy is greater than that of the ordinary layer. First, it can save the power consumption of the model in the actual environment due to testing, and second, it can avoid the model service interruption caused by model testing, reduce the service interruption duration and corresponding power consumption caused by the model weight update, and third, avoid occupying storage space in the actual environment to store the model test data set. Compared with the prior art solution three (software fixed period update solution), this solution simulates the actual model according to the set reasoning accuracy requirements to obtain the model update cycle, which can avoid the situation where the model reasoning accuracy is far lower than expected, as well as the power consumption and service interruption costs caused by unnecessary model maintenance.

[0155] See also Fig.13 , is an optional flow chart of the chip maintenance method provided in the embodiment of the present application, and the combined steps are described as follows:

[0156] S22. Obtain the longest drift duration allowed for the single-layer network weight data (assuming that the weights of other layers remain unchanged).

[0157] In an embodiment of the present application, based on the acquired chip data drift characteristics, each network layer is selected in turn, and assuming that the weight data of other layers are fixed, a drift simulation test is performed on the selected network layer data to find the longest duration of drift of the layer data under the expected accuracy requirement.

[0158] When the chip data drift characteristic belongs to ordered directional drift, that is, the data drifts in a directional manner, the data of the i-th layer weight data of the model after drifting M days and M+1 days can be obtained by querying the table; when the chip data drift characteristic belongs to normal distribution drift, that is, the data is randomly normally distributed, the i-th layer weight data is randomly generated according to the data distribution after the data drifts M days and M+1 days. Then, the inference calculation is performed through the test data set until the drift duration M is found, so that the model calculation accuracy is higher than the expected value when the drift is M days, and the model calculation accuracy is lower than the expected value when the drift is M+1 days. Then the longest drift duration of the single layer of weight data of this layer is M days. For the second case, since the data is randomly normally distributed, the calculation results of the randomly generated weight data may be greatly different. The accuracy can be improved by taking the average value through multiple calculations.

[0159] S23. Calculate the ratio of the drift duration of the network weights of each layer.

[0160] S24. Keep the ratio of the drift duration of each layer of the network unchanged, obtain the longest update duration of the network weight of each layer that meets the expected accuracy, and set it as the initial update period.

[0161] S25. Based on the initial update cycle, each initial update cycle is randomly increased or decreased, and X of them are selected as a group of update cycles for the new generation.

[0162] S26. Calculate the model accuracy corresponding to each group of update cycles and select solutions whose accuracy meets the requirements, and calculate the average update rate for the solutions that pass the screening.

[0163] S27. If the update rate of a group of update cycles is lower than the new group of update cycles formed for it, then the group of update cycles is the target solution, otherwise a new group of update cycles with the lowest update rate is selected as the new generation parent solution.

[0164] In the embodiment of the present application, a new set of update cycles with the lowest update rate is selected as the new generation parent solution for iterative evolution. If the update rate of the parent solution is lower than that of all sub-solutions, it means that the parent solution is already the local optimal solution. If the proportion of the selected sub-solution set is high, the parent solution can be directly output. If the proportion of the selected sub-solution set is low, the parent solution can be used as the next generation parent solution again, until no better solution is found after multiple attempts.

[0165] See also Fig.14 , which is a schematic diagram of the structure of the chip maintenance device provided in an embodiment of the present application.

[0166] In the embodiment of the present application, a chip maintenance device 800 is also provided, including: an updating unit 801.

[0167] An updating unit 801 is used to update the weight parameters corresponding to each network layer in the storage-computing integrated chip based on a preset update period corresponding to each network layer in the model during the model operation;

[0168] Among them, the preset update cycle is determined before the model is deployed on the storage and computing integrated chip, and the preset update cycle is determined based on the data drift characteristics of the storage and computing integrated chip, by simulation testing for each network layer; the preset update cycle is used to meet the expected accuracy of the model.

[0169] In the embodiment of the present application, the chip maintenance device 800 is used to perform a simulation test on each network layer of the model based on the acquired data drift characteristics, and determine the drift duration corresponding to each network layer; wherein the drift duration is the maximum duration that meets the expected accuracy condition;

[0170] Determine, based on the data drift characteristic and the drift duration corresponding to each of the network layers, an initial update period corresponding to each of the network layers that satisfies the expected accuracy;

[0171] Perform mutation and iterative update for each of the initial update cycles until a preset condition is met, and then stop to determine the preset update cycle corresponding to each of the network layers.

[0172] In the embodiment of the present application, the data drift characteristic is determined based on how the first test data written in the sample chip changes over time.

[0173] In the embodiment of the present application, the chip maintenance device 800 is used to compile and deploy the model to the sample chip, and record the storage and computing unit of the weight deployment of each network layer in the sample chip;

[0174] Writing the second test data into the sample chip for simulation testing, and performing weight drift simulation on the storage and computing unit corresponding to each of the network layers based on the data drift characteristics, and determining the test result corresponding to each of the network layers; wherein, when performing weight drift simulation on the storage and computing unit corresponding to each of the network layers, the weights of the storage and computing units corresponding to other network layers remain unchanged;

[0175] Based on a comparison result of the test accuracy corresponding to the test result and the expected accuracy, the drift duration with the longest duration under the condition of satisfying the expected accuracy is determined.

[0176] In the embodiment of the present application, the chip maintenance device 800 is used to query the predetermined simulation weight corresponding to the predetermined drift duration in the data set; wherein the data set is determined based on the data drift characteristics, including the correspondence between multiple drift durations and corresponding simulation weights;

[0177] The calculation result of the storage and computing unit corresponding to each network layer is determined based on the predetermined simulation weight, and the calculation result is passed to the next storage and computing unit until the last storage and computing unit outputs the test result.

[0178] In the embodiment of the present application, the predetermined drift duration includes: an adjacent first drift duration and a second drift duration; the second drift duration is greater than the first drift duration; the first drift duration corresponds to a first test result, and the second drift duration corresponds to a second test result; the chip maintenance device 800 is used to determine that the first drift duration is the longest drift duration under the condition of satisfying the expected accuracy if the comparison result indicates that the test accuracy corresponding to the first test result is not less than the expected accuracy, and the test accuracy corresponding to the second test result is less than the expected accuracy;

[0179] If the comparison result indicates that the test accuracy corresponding to the first test result and the second test result is greater than the expected accuracy, then the test accuracy corresponding to the third drift duration is compared with the expected accuracy until the drift duration that meets the expected accuracy is determined; wherein the third drift duration is a duration greater than the second drift duration;

[0180] If the comparison result indicates that the test accuracy corresponding to the first test result and the second test result respectively is less than the expected accuracy, the test accuracy corresponding to the fourth drift duration is compared with the expected accuracy until the drift duration that meets the expected accuracy is determined; wherein the fourth drift duration is a duration that is less than the first drift duration.

[0181] In the embodiment of the present application, the chip maintenance device 800 is used to determine the maximum drift duration in each of the drift durations, and determine the ratio of each of the drift durations to the maximum drift duration;

[0182] A fifth drift duration and a sixth drift duration are queried in the data set; wherein the fifth drift duration satisfies: the test accuracy of the model determined based on the duration of each network layer determined by multiplying the fifth drift duration and each ratio is not less than the expected accuracy; the sixth drift duration satisfies: the test accuracy of the model determined based on the duration of each network layer determined by multiplying the sixth drift duration and each ratio is less than the expected accuracy;

[0183] The initial update period corresponding to each of the network layers is determined based on the product of the fifth drift duration and each of the ratios.

[0184] In the embodiment of the present application, the chip maintenance device 800 is used to determine a first average update rate corresponding to a first group of update cycles; wherein the first group of update cycles is composed of each of the initial update cycles;

[0185] Performing mutation update on the first group of update cycles to determine multiple groups of second group update cycles;

[0186] If the first average update rate is greater than the second average update rate corresponding to each group of the second group update periods, a mutation update is performed on the second group update periods with the lowest average update rate to determine multiple groups of third group update periods, and the process continues until it is determined that the N+1th average update rate is greater than the Nth average update rate, and the update period in the Nth group update period is determined to be the preset update period corresponding to each of the network layers.

[0187] It should be noted that in the embodiments of the present application, if the above-mentioned method for processing item information is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application can be essentially or partly reflected in the form of a software product that contributes to the relevant technology. The computer software product is stored in a storage medium and includes several instructions for enabling an item information processing device (which can be a personal computer, etc.) to execute all or part of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a magnetic disk or an optical disk. In this way, the embodiments of the present application are not limited to any specific combination of hardware and software.

[0188] Correspondingly, an embodiment of the present application provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps in the method on the chip maintenance device 800 side are implemented.

[0189] It should be noted here that the description of the above storage medium and device embodiments is similar to the description of the above method embodiments, and has similar beneficial effects as the method embodiments. For technical details not disclosed in the storage medium and device embodiments of this application, please refer to the description of the method embodiments of this application for understanding.

[0190] It should be noted that Fig.15 A hardware entity diagram of an electronic device provided in an embodiment of the present application, such as Fig.15 As shown, an embodiment of the present application provides an electronic device 900, including a memory 902 and a processor 901, wherein the memory 902 stores a computer program that can be run on the processor 901, and the processor 901 implements the steps in the above method when executing the program, wherein;

[0191] The processor 901 generally controls the overall operation of the electronic device 900 .

[0192] The memory 902 is configured to store instructions and applications executable by the processor 901, and can also cache data to be processed or processed by the processor 901 and various modules in the electronic device 900 (for example, image data, audio data, voice communication data, and video communication data), which can be implemented through flash memory (FLASH) or random access memory (Random Access Memory, RAM).

[0193] Correspondingly, an embodiment of the present application further provides a computer program product, including a computer program, which can be executed by a processor 901 of an electronic device 900 to complete the steps in the method on the chip maintenance device 800 side.

[0194] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the size of the sequence number of the above-mentioned processes does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned sequence numbers of the embodiments of the present application are only for description and do not represent the advantages and disadvantages of the embodiments.

[0195] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0196] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored, or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the device or unit can be electrical, mechanical or other forms.

[0197] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0198] In addition, all functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may be a separate unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0199] A person skilled in the art can understand that all or part of the steps of implementing the above method embodiment can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above method embodiment; and the aforementioned storage medium includes: a mobile storage device, a read-only memory (ROM), a magnetic disk or an optical disk, and other media that can store program codes.

[0200] Alternatively, if the above-mentioned integrated unit of the present application is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application can be essentially or partly embodied in the form of a software product that contributes to the relevant technology. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a mobile storage device, a ROM, a magnetic disk, or an optical disk.

[0201] The above is only an implementation method of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A chip maintenance method, characterized in that: include: During the model operation, based on the preset update period corresponding to each network layer in the model, the weight parameters corresponding to each network layer in the storage and computing integrated chip are updated; Among them, the preset update period is determined before the model is deployed on the storage and computing integrated chip; the preset update period is determined based on the data drift characteristics of the storage and computing integrated chip, and simulation tests are performed on each network layer; the preset update period is used to meet the expected accuracy of the model.

2. The chip maintenance method according to claim 1, characterized in that: During the model operation, based on the preset update period corresponding to each network layer in the model, before updating the corresponding weight parameter of each network layer in the storage-computing integrated chip, the method further includes: Based on the acquired data drift characteristics, a simulation test is performed on each network layer of the model to determine the drift duration corresponding to each network layer; wherein the drift duration is the maximum duration that meets the expected accuracy condition; Determine, based on the data drift characteristic and the drift duration corresponding to each of the network layers, an initial update period corresponding to each of the network layers that satisfies the expected accuracy; Perform mutation and iterative update for each of the initial update cycles until a preset condition is met, and then stop to determine the preset update cycle corresponding to each of the network layers.

3. The chip maintenance method according to claim 2, characterized in that: The data drift characteristic is determined based on the change of the first test data written in the sample chip over time.

4. The chip maintenance method according to claim 2, characterized in that: The step of performing a simulation test on each network layer of the model based on the acquired data drift characteristics to determine the drift duration corresponding to each network layer includes: Compile and deploy the model to a sample chip, and record the storage and computing units where the weights of each network layer are deployed in the sample chip; Writing the second test data into the sample chip for simulation testing, and performing weight drift simulation on the storage and computing unit corresponding to each of the network layers based on the data drift characteristics, and determining the test result corresponding to each of the network layers; wherein, when performing weight drift simulation on the storage and computing unit corresponding to each of the network layers, the weights of the storage and computing units corresponding to other network layers remain unchanged; Based on a comparison result of the test accuracy corresponding to the test result and the expected accuracy, the drift duration with the longest duration under the condition of satisfying the expected accuracy is determined.

5. The chip maintenance method according to claim 4, characterized in that: The performing weight drift simulation on the storage and computing unit corresponding to each of the network layers based on the data drift characteristics to determine the test result corresponding to each of the network layers includes: Querying a predetermined simulation weight corresponding to a predetermined drift duration in a data set; wherein the data set is determined based on the data drift characteristics and includes a correspondence between a plurality of drift durations and corresponding simulation weights; The calculation result of the storage and computing unit corresponding to each network layer is determined based on the predetermined simulation weight, and the calculation result is passed to the next storage and computing unit until the last storage and computing unit outputs the test result.

6. The chip maintenance method according to claim 5, characterized in that: The predetermined drift duration includes: a first drift duration and a second drift duration that are adjacent to each other; the second drift duration is greater than the first drift duration; the first drift duration corresponds to a first test result, and the second drift duration corresponds to a second test result; The determining, based on a comparison result of the test accuracy corresponding to the test result and the expected accuracy, of the drift duration with the longest duration under the condition of satisfying the expected accuracy comprises one of the following: If the comparison result indicates that the test accuracy corresponding to the first test result is not less than the expected accuracy, and the test accuracy corresponding to the second test result is less than the expected accuracy, then determining the first drift duration to be the longest drift duration that satisfies the expected accuracy condition; If the comparison result indicates that the test accuracy corresponding to the first test result and the second test result is greater than the expected accuracy, then the test accuracy corresponding to the third drift duration is compared with the expected accuracy until the drift duration that meets the expected accuracy is determined; wherein the third drift duration is a duration greater than the second drift duration; If the comparison result indicates that the test accuracy corresponding to the first test result and the second test result respectively is less than the expected accuracy, the test accuracy corresponding to the fourth drift duration is compared with the expected accuracy until the drift duration that meets the expected accuracy is determined; wherein the fourth drift duration is a duration that is less than the first drift duration.

7. The chip maintenance method according to claim 2, characterized in that: The determining, based on the data drift characteristic and the drift duration corresponding to each of the network layers, an initial update period corresponding to each of the network layers that satisfies the expected accuracy includes: Determining a maximum drift duration in each of the drift durations, and determining a ratio of each of the drift durations to the maximum drift duration; A fifth drift duration and a sixth drift duration are queried in the data set; wherein the fifth drift duration satisfies: the test accuracy of the model determined based on the duration of each network layer determined by multiplying the fifth drift duration and each ratio is not less than the expected accuracy; the sixth drift duration satisfies: the test accuracy of the model determined based on the duration of each network layer determined by multiplying the sixth drift duration and each ratio is less than the expected accuracy; The initial update period corresponding to each of the network layers is determined based on the product of the fifth drift duration and each of the ratios.

8. The chip maintenance method according to claim 2, characterized in that: The performing mutation and iterative updating for each of the initial update cycles until a preset condition is met and stopping, and determining the preset update cycle corresponding to each of the network layers, comprises: Determine a first average update rate corresponding to a first group of update cycles; wherein the first group of update cycles is composed of each of the initial update cycles; Performing mutation update on the first group of update cycles to determine multiple groups of second group update cycles; If the first average update rate is greater than the second average update rate corresponding to each group of the second group update periods, a mutation update is performed on the second group update periods with the lowest average update rate to determine multiple groups of third group update periods, and the process continues until it is determined that the N+1th average update rate is greater than the Nth average update rate, and the update period in the Nth group update period is determined to be the preset update period corresponding to each of the network layers.

9. A chip maintenance device, characterized in that: include: An updating unit, used to update the weight parameters corresponding to each network layer in the storage-computing integrated chip based on a preset update period corresponding to each network layer in the model during the model operation; Among them, the preset update cycle is determined before the model is deployed on the storage and computing integrated chip, and the preset update cycle is determined based on the data drift characteristics of the storage and computing integrated chip, by simulation testing for each network layer; the preset update cycle is used to meet the expected accuracy of the model.

10. An electronic device, characterized in that: The method comprises a memory and a processor, wherein the memory stores a computer program executable on the processor, and the processor implements the steps of the method according to any one of claims 1 to 8 when executing the computer program.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps in the method according to any one of claims 1 to 8 are implemented.

12. A computer program product, comprising a computer program, characterized in that The computer program implements the steps of the method according to any one of claims 1 to 8 when executed by a processor.

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