Fpga test case logic resource expansion method, device, equipment, medium and product

Abstract

The present application relates to the technical field of FPGA, and discloses a FPGA test case logic resource expansion method, device, equipment, medium and product, the method comprises the following steps: obtaining the original test case corresponding to the FPGA chip to be tested; copying the original test case, obtaining a plurality of copy test cases, and taking the original test case and the plurality of copy test cases as initial test cases; based on the initial test case, a target test case after expansion is generated. The present application does not need to use the transplantation mode, and can realize the expansion of the test case on the basis of the original original test case, so that the test case resource formed is several times, even dozens or hundreds of times of the original test case, and the pin is almost the same as the original test case. Thus, the problem of insufficient resources caused by the synchronous increase of the number of pins is solved, thereby realizing the significant increase of the logic resource capacity of the test case.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of FPGA, and particularly relates to an FPGA test case logic resource expansion method, device, equipment, medium and product. BACKGROUND

[0002] FPGA (Field Programmable Gate Array, FPGA for short) is an integrated circuit that can be programmed at any time, and the effective use of the FPGA chip is based on the maturity, ease of use and stability of its development tools. At present, the commonly used development tool for developing FPGA chips is EDA (Electronic design automation, EDA for short) software. The EDA software can convert the user's design idea into the actual function of the chip, and can assist in designing, simulating and optimizing the digital logic circuit in the FPGA.

[0003] However, as the testing requirements of the FPGA chip are increasing, the testing process of the EDA software is no longer limited to unit testing. Test engineers generally accumulate a large number of different types of test cases, and hope that these test cases can be applied to the testing process of the FPGA chip being developed to more comprehensively verify the functions of the FPGA chip.

[0004] However, the transplantation process of the test case is usually limited by the capacity, memory block, DSP (Digital Signal Processor, DSP for short, which is an operation unit inside the FPGA) block, packaging pin and other resources of the FPGA. As long as one of the resources exceeds the limit of the target device, it means that the transplantation process fails. Among these resource limits, the most common one is the limitation of the pin resources, which directly leads to the fact that the logic resources in the test case cannot be fully used, resulting in that the functions of the FPGA chip cannot be fully tested. SUMMARY

[0005] Therefore, the present application provides an FPGA test case logic resource expansion method, device, equipment, medium and product to solve the problem that the expansion of the test case is limited by the pin resources in the prior art.

[0006] In a first aspect, the present application provides an FPGA test case logic resource expansion method, which comprises the following steps:

[0007] Obtaining a native test case corresponding to a to-be-tested FPGA chip;

[0008] Copying the native test case to obtain a plurality of copied test cases, and taking the native test case and the plurality of copied test cases together as an initial test case;

[0009] Based on the initial test cases, generate the expanded target test cases.

[0010] In the embodiment, without using the transplantation mode, i.e. without transplanting the test cases of other different types and devices to the FPGA chip to be tested for testing the FPGA chip to be tested, the expansion of the test cases can be realized based on the original native test cases, the test case resources formed in this way are several times, even tens or hundreds of times of the native test cases, and the pins are almost the same as the native test cases, thus solving the problem of the simultaneous increase of the number of pins and the shortage of resources, and realizing the significant increase of the logical resource capacity of the test cases.

[0011] In an alternative embodiment, based on the initial test cases, the expanded target test cases are generated, including:

[0012] Cascade all the initial test cases in sequence to obtain the target test cases.

[0013] In the embodiment, the input and output signal cascading is implemented for the multiple instantiations of the native test cases, the logical resources of the test cases are increased without increasing or as little as possible the device pins, the test cases with high complexity are formed, more FPGA logic and resources can be activated, and the test efficiency of the FPGA logical resources and the EDA tool is effectively improved.

[0014] In an alternative embodiment, based on the initial test cases, the expanded target test cases are generated, including:

[0015] Add a linear feedback shift register and a wrapper to each initial test case to generate an intermediate test case corresponding to the initial test case;

[0016] Parallel all the intermediate test cases to obtain the target test cases.

[0017] In the embodiment, the wire delay between the source register and the destination register is effectively shortened, and the timing is greatly optimized.

[0018] In an alternative embodiment, the input data is copied by using the linear feedback shift register, and is sequentially transmitted to the input end of each initial test case through the shift operation; the output of each initial test case is sequentially transmitted to the wrapper, and finally the highest bit in the wrapper is taken as the output of the target test case.

[0019] In the embodiment, the expansion of the test case resources is realized, the condition of the basically unchanged IO resources is met, and the timing is optimized.

[0020] In an alternative embodiment, all initial test cases are sequentially concatenated to obtain target test cases, including:

[0021] A constraint mark is added between the initial test case and the initial test case connection, and the constraint mark is used to prevent the signal node from being optimized.

[0022] The constraint mark in the embodiment ensures that these signal nodes will be retained and not optimized during the synthesis link, thereby facilitating comprehensive testing of the FPGA.

[0023] In an alternative embodiment, the native test case is expanded to two-dimensional data when the native test case is one-dimensional data.

[0024] Such expansion can make data management clearer, thereby ensuring correct execution of multi-level concatenation.

[0025] In a second aspect, the present application provides a FPGA test case logic resource expansion device, which comprises:

[0026] An acquisition module is configured to acquire a native test case corresponding to a to-be-tested FPGA chip;

[0027] A replication module is configured to replicate the native test case to obtain a plurality of replicated test cases, and use the native test case and the plurality of replicated test cases as initial test cases;

[0028] An expansion module is configured to generate an expanded target test case based on the initial test case.

[0029] In a third aspect, the present application provides a computer device, which comprises a memory and a processor, the memory and the processor are in communication connection with each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the FPGA test case logic resource expansion method of the first aspect or any of the corresponding embodiments thereof.

[0030] In a fourth aspect, the present application provides a computer readable storage medium, which stores computer instructions, and the computer instructions are used to make a computer execute the FPGA test case logic resource expansion method of the first aspect or any of the corresponding embodiments thereof.

[0031] In a fifth aspect, the present application provides a computer program product, which comprises computer instructions, and the computer instructions are used to make a computer execute the FPGA test case logic resource expansion method of the first aspect or any of the corresponding embodiments thereof.

[0032] It should be noted that the FPGA test case logic resource expansion device, the computer device and the computer readable storage medium provided by the present application correspond to the FPGA test case logic resource expansion method described above. Therefore, the beneficial effects of the FPGA test case logic resource expansion device, the computer device and the computer readable storage medium are described in the corresponding beneficial effects of the FPGA test case logic resource expansion method described above, and will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0033] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the drawings needed in the specific embodiments or prior art description will be briefly introduced below. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0034] Figure 1 It is a flowchart of the FPGA test case logic resource expansion method according to the embodiment of the present application;

[0035] Figure 2 It is a code diagram of a certain case implementation fragment according to the embodiment of the present application;

[0036] Figure 3 It is a schematic diagram of one of the expansion methods according to the embodiment of the present application;

[0037] Figure 4 It is a schematic diagram of another expansion method according to the embodiment of the present application;

[0038] Figure 5 It is a code diagram implemented by shift operation according to the embodiment of the present application;

[0039] Figure 6 It is another code diagram implemented by shift operation according to the embodiment of the present application;

[0040] Figure 7 It is a code diagram of the overall framework according to the embodiment of the present application;

[0041] Figure 8 It is a structure block diagram of the FPGA test case logic resource expansion device according to the embodiment of the present application;

[0042] Figure 9 It is a hardware structure diagram of the computer device of the embodiment of the present application. DETAILED DESCRIPTION

[0043] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0044] An FPGA chip vendor typically possesses a rich set of test cases, and many websites also offer test benchmarks for use. However, these test cases share the common characteristic of consuming relatively few logic resources. The conventional method to increase the resource usage of test cases is to duplicate them multiple times and then expand them in parallel, resulting in a test case with several times the original design resources. Clearly, this parallel resource expansion method is limited by the number of device pins, meaning that after all pins are used, only a fraction, or even a fraction of, of the logic resources are utilized. Therefore, the pin count limitation is significant and prominent in expanding FPGA test cases. For example, if an FPGA chip has 100 available pins, and a test case requires more than 100 pins, the test case will fail during routing. Simply removing a few pins, on the other hand, affects the functionality and other resource requirements of the test case, thus reducing its quality.

[0045] Therefore, in current related technologies, it is difficult to guarantee that resources can be expanded based on the original test cases while ensuring successful layout and routing. This is a major problem that EDA software testing work must face.

[0046] In view of this, according to an embodiment of the present invention, an embodiment of a method for expanding the logic resources of FPGA test cases is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0047] This embodiment provides a method for expanding the logic resources of FPGA test cases, which can be executed by devices such as servers, terminals, and mobile terminals. Figure 1 This is a flowchart of an FPGA test case logic resource expansion method according to an embodiment of the present invention, such as... Figure 1 As shown, the process includes the following steps:

[0048] Step S101: Obtain the native test cases corresponding to the FPGA chip under test. These native test cases can be the test cases that were provided with the FPGA chip at the factory.

[0049] Step S102: Copy the original test cases to obtain multiple copied test cases, and use the original test cases and multiple copied test cases together as the initial test cases.

[0050] Step S103: Based on the initial test cases, generate expanded target test cases. Specifically, the expansion can be achieved by cascading all initial test cases sequentially to obtain the cascaded target test cases, thus expanding the test cases; or by adding shift registers before and after each initial test case, using linear feedback shift registers to "copy" the data input, and then sequentially passing it to the input of each initial test case through shift operations, thereby expanding the test cases.

[0051] In this embodiment, there is no need for porting, i.e., there is no need to port test cases of other different types or devices to the FPGA chip under test for testing. Test cases can be expanded simply by using the original native test cases. The resulting test case resources are several times, or even tens or hundreds of times, greater than those of the original test cases, while the number of pins is almost the same. This solves the problem of insufficient resources when the number of pins increases simultaneously, thus achieving a significant increase in the logic resource capacity of the test cases.

[0052] The approach of this invention fully follows the basic functions and logical requirements of the original design. The logical resource capacity of the generated use cases is approximately the original resource amount multiplied by the number of consecutive connections. Therefore, under normal circumstances, use cases with hundreds of kilobytes or even several megabytes of logical resources can be obtained, making the logical resources very abundant.

[0053] In addition, in FPGA chip design, it is necessary to distinguish the cascaded signals and to cascade resources with obvious diffusion of logic and data. Simply cascading a set of signals may not increase the logic resources.

[0054] For the output signals of the initial test cases, they can either be cascaded or output to independent signals (not participating in the cascade). In other words, it is not necessary to cascade all the output signals to achieve the original functional coverage and logic resource multiplication.

[0055] While this invention can be used to obtain a large number of test cases, it is not effective for all native test cases. It is primarily effective for test cases in OpenCores used for data transformation, such as data encryption and decryption. For example, some industrial control test cases, due to their lack of significant logical diffusion, cannot be used to multiply logical resources. Previously, there were almost no particularly effective methods to implement test cases with more than 50K logical resources. Although this invention is clear in its concept, simple and convenient to implement, it is extremely practical.

[0056] Its input and output cascading concept is reflected in Figure 2 The box shown, Figure 2 This demonstrates a snippet of the implementation of a particular use case.

[0057] In some optional implementations, expanded target test cases are generated based on the initial test cases, including:

[0058] Cascade all initial test cases sequentially to obtain the target test cases.

[0059] In other words, the original test cases are copied multiple times and arranged sequentially, i.e., serial expansion, as shown in the reference. Figure 3 As shown, the output of the previous initialization test case is connected to the input of the next initialization test case, forming a connection between multiple test cases.

[0060] By instantiating multiple copies of the original test cases and cascading input and output signals, the logic resources of the test cases can be increased without adding or with minimal addition of device pins. This results in test cases with higher complexity that can activate more FPGA logic and resources, thereby effectively improving the testing efficiency of FPGA logic resources and EDA tools. It can also effectively generate large-capacity or even extra-large-capacity test cases without being limited by the number of FPGA chip pins, making it possible to generate test cases with specific logic resource capacities (typically several hundred KB LUTs) when testing and verifying EDA software.

[0061] In some optional implementations, expanded target test cases are generated based on the initial test cases, including:

[0062] Add a linear feedback shift register and a wrapper to each initial test case to generate intermediate test cases that correspond one-to-one with the initial test cases.

[0063] Connect all intermediate test cases in parallel to obtain the target test cases.

[0064] The previous implementation expanded use case resources while addressing the insufficient pin resources. However, as the number of cascades increases, routing delays may also increase, hindering timing analysis. To optimize timing, this embodiment refers to... Figure 4 As shown, a linear feedback shift register is added to the front end of each initial test case, and a wrapper (containing a shift register) is added to the back end of each initial test case. This effectively shortens the routing delay between the source register and the destination register and greatly optimizes the timing.

[0065] In some optional implementations, a linear feedback shift register is used to copy the input data, which is then sequentially passed to the input of each initial test case via a shift operation. The output of each initial test case is sequentially passed to a wrapper, and finally, the most significant bit in the wrapper is used as the output of the target test case. The input data is the test data used to input the FPGA chip under test.

[0066] The specific implementation method is as follows: A linear feedback shift register is used to "copy" the data input, and the data is then sequentially passed to the input of each initial test case through shift operations. For details, please refer to [link / reference]. Figure 5 As shown.

[0067] Simultaneously, the outputs of each initial test case are sequentially passed to the shift register in the wrapper, and finally the most significant bit is sent out. For the specific implementation process, please refer to [link / reference needed]. Figure 6 As shown. The implementation method for the overall framework connection is as follows: Figure 7 As shown.

[0068] Compared with the cascading implementation, this embodiment not only expands the use case resources, but also satisfies the condition that the IO resources remain basically unchanged, and optimizes the timing.

[0069] In some optional implementations, all initial test cases are cascaded sequentially to obtain the target test cases, including:

[0070] Add constraint markers between the initial test cases and the initial test case connections. Constraint markers are used to prevent signal nodes from being optimized.

[0071] When expanding test cases using a cascading approach, the key operation is "connecting the output of the previous test case to the input of the next test case." For EDA tools, based on the fundamental principle of conserving chip logic resources, completely identical repetitive modules are highly likely to be optimized away during the FPGA design synthesis phase, thus failing to meet the resource expansion requirements. This is why parallel expansion is commonly used in this field. Therefore, it is necessary to establish a non-optimizable node group, making it a "link" between preceding and subsequent test cases. To address this, for general EDA tools, a constraint instruction for a "keep" node is provided for each initial test case, which is the constraint marker in this embodiment. This ensures that these signal nodes are retained and not optimized during the synthesis phase, thereby facilitating comprehensive FPGA testing. Based on this method, a single test case with only simple complexity can be transformed into a complex test case with extremely high complexity, capable of activating a large amount of FPGA logic and various resources, thereby improving the testing efficiency of FPGA logic resources and EDA tools.

[0072] In some alternative implementations, when the original test cases are one-dimensional data, they are expanded to two-dimensional data.

[0073] The generated target test cases are essentially multi-level cascades of the original test cases, so it's necessary to add a dimension to some arrays within the original test cases. The original one-dimensional arrays need to be expanded into two-dimensional arrays; this added dimension is used to store data between the original test cases. This expansion makes data management clearer, thereby ensuring the correct execution of the multi-level cascade.

[0074] This embodiment also provides an FPGA test case logic resource expansion device, which is used to implement the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0075] This embodiment provides an FPGA test case logic resource expansion device, such as... Figure 8 As shown, the device includes:

[0076] The acquisition module 201 is used to acquire the native test cases corresponding to the FPGA chip under test.

[0077] The copy module 202 is used to copy the original test cases, obtain multiple copied test cases, and use the original test cases and multiple copied test cases together as the initial test cases;

[0078] The expansion module 203 is used to generate expanded target test cases based on the initial test cases.

[0079] In some alternative implementations, the expansion module 203 includes:

[0080] The first expansion unit is used to cascade all initial test cases sequentially to obtain the target test cases.

[0081] The second expansion unit is used to add a linear feedback shift register and a wrapper to each initial test case, generating intermediate test cases that correspond one-to-one with the initial test cases; and to connect all intermediate test cases in parallel to obtain the target test case. It is also used to copy the input data using the linear feedback shift register and pass it sequentially to the input of each initial test case through a shift operation; the output of each initial test case is sequentially passed to the wrapper, and finally, the highest bit in the wrapper is used as the output of the target test case.

[0082] The marking unit is used to add constraint markings between initial test cases and initial test case connections. Constraint markings are used to prevent signal nodes from being optimized.

[0083] The third expansion unit is used to expand the original test cases into two-dimensional data when the original test cases are one-dimensional data.

[0084] In this embodiment, the FPGA test case logic resource expansion device is presented in the form of a functional unit. Here, a unit refers to an ASIC circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0085] Further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0086] This invention also provides a computer device having the above-described features. Figure 8 The FPGA test case shown is a logic resource expansion device.

[0087] Please see Figure 9 , Figure 9 This is a schematic diagram of the structure of a computer device provided in an optional embodiment of the present invention, such as... Figure 9 As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 9 Take a processor 10 as an example.

[0088] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0089] The memory 20 stores instructions executable by at least one processor 10 to cause the at least one processor 10 to perform the method shown in the above embodiments.

[0090] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0091] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0092] The computer device also includes a communication interface 30 for communicating with other devices or communication networks.

[0093] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.

[0094] A portion of this invention can be applied as a computer program product, such as computer program instructions, which, when executed by a computer, can invoke or provide the methods and / or technical solutions according to the invention through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, installation package files, etc. Correspondingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions, or the computer compiling the instructions and then executing the corresponding compiled program, or the computer reading and executing the instructions, or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0095] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A method for expanding the logic resources of FPGA test cases, characterized in that, The method includes: Obtain the native test cases corresponding to the FPGA chip under test; the native test cases are the test cases used for data transformation in OpenCores; Copy the original test case to obtain multiple copied test cases, and use the original test case and the multiple copied test cases together as the initial test case; Based on the initial test cases, expanded target test cases are generated, including: A linear feedback shift register and a wrapper are added to each initial test case to generate intermediate test cases that correspond one-to-one with the initial test cases; all intermediate test cases are connected in parallel to obtain the target test case; wherein, the input data is copied using the linear feedback shift register and passed to the input of each initial test case in sequence through a shift operation; the output of each initial test case is passed to the wrapper in sequence, and finally the highest bit in the wrapper is used as the output of the target test case.

2. The method according to claim 1, characterized in that, The process of generating expanded target test cases based on the initial test cases further includes: All the initial test cases are cascaded sequentially to obtain the target test cases.

3. The method according to claim 1, characterized in that, The step of cascading all the initial test cases sequentially to obtain the target test cases includes: A constraint marker is added between the initial test case and the connection of the initial test case. The constraint marker is used to prevent the signal node from being optimized.

4. The method according to claim 1, characterized in that, If the original test cases are one-dimensional data, the original test cases will be expanded to two-dimensional data.

5. An FPGA test case logic resource expansion device, characterized in that, The device includes: The acquisition module is used to acquire the native test cases corresponding to the FPGA chip under test; the native test cases are test cases used for data transformation in OpenCores. The copying module is used to copy the original test cases to obtain multiple copied test cases, and to use the original test cases and the multiple copied test cases together as the initial test cases. An expansion module is used to generate expanded target test cases based on the initial test cases. This includes: adding a linear feedback shift register and a wrapper to each initial test case to generate intermediate test cases corresponding one-to-one with the initial test cases; connecting all the intermediate test cases in parallel to obtain the target test cases; wherein the linear feedback shift register is used to copy the input data and then sequentially passes it to the input of each initial test case through a shift operation; the output of each initial test case is sequentially passed to the wrapper, and finally, the highest bit in the wrapper is used as the output of the target test case.

6. A computer device, characterized in that, include: The system includes a memory and a processor, which are interconnected. The memory stores computer instructions, and the processor executes the computer instructions to perform the FPGA test case logic resource expansion method according to any one of claims 1-4.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing the computer to execute the FPGA test case logic resource expansion method according to any one of claims 1-4.

8. A computer program product, characterized in that, Includes computer instructions, said computer instructions being used to cause a computer to execute the FPGA test case logic resource expansion method according to any one of claims 1-4.

Images