NOR Flash memory with multi-mode SPI (Serial Peripheral Interface) with CRC (Cyclic Redundancy Check)

Abstract

The invention discloses a NOR Flash memory with a multi-mode SPI (Serial Peripheral Interface) with CRC (Cyclic Redundancy Check), which can select different SPI modes according to different instructions received from the SPI through the cooperation of an input / output control module and an instruction decoding module, thereby realizing the compatibility of multiple SPI modes, simultaneously realizing the high-speed transmission of data and realizing the high-speed data transmission. Particularly, when a DTR four-wire SPI mode is selected, the mode can output data through four bidirectional data ports at the rising edge and the falling edge of an external clock signal SCLK, and the maximum throughput rate of the output data can reach 8 times of that of the SCLK under the condition that the clock frequency is not changed; according to the invention, the CRC data verification module is integrated, error detection and verification are carried out on code data stored in NOR FLASH and a data transmission process through cooperative work of the CRC data verification module and a data path, and integrity and reliability of data in a multi-mode transmission process are ensured.

Description

Technical Field

[0001] The invention relates to the field of NOR Flash memory, and in particular to a NOR Flash memory with a multi-mode SPI interface having a CRC check. Background Art

[0002] As a high-performance non-volatile memory, NOR Flash is widely used in system startup and firmware storage. The SPI serial interface has become a common communication method between NOR Flash and processors due to its simplicity and low pin count. At present, the commonly used SPI interface circuits mostly use multi-line transmission to meet the requirements of high-speed transmission, mainly including single-line, dual-line or four-line mode. Some designs may also use the DTR (Double Transfer Rate) mode of double-edge triggered data transmission. However, many designs fail to effectively combine these technologies, resulting in insufficient performance and compatibility. And with the continuous improvement of the Internet of Things and embedded systems' requirements for data transmission mode, transmission rate and reliability, the traditional SPI interface shows shortcomings and limitations in these aspects.

[0003] Chinese patent application number 202011604951.1, the patent name is a FLASH memory with an SPI interface for high-speed data reading, which proposes a method of combining multiple units such as an input rising edge synchronization unit, an input falling edge synchronization unit, a combination unit, and a synchronization unit to achieve double data output without changing the clock frequency. However, this method still has limitations on the transmission rate of data output, cannot give full play to the potential of high-performance FLASH devices, and lacks verification of the integrity and reliability of the data transmission process.

[0004] Chinese patent application number 202211035244.4, the patent name is a method for designing a four-wire serial peripheral interface communication protocol. Aiming at the problem of slow throughput of single-wire and dual-wire SPI, a four-wire serial peripheral interface communication protocol method for the field of vehicle-mounted SOC communication technology is proposed. The throughput rate of this method can reach about 40Mbps, which is 4 times that of single-wire SPI and 2 times that of dual-wire SPI. However, this method abandons the compatibility with multiple SPI mode transmissions, has certain limitations, and also lacks verification of the integrity and reliability of the data transmission process. Summary of the invention

[0005] In order to overcome the shortcomings and deficiencies of the prior art, a NOR Flash memory with a multi-mode SPI interface and CRC check is proposed.

[0006] A NOR Flash memory with a multi-mode SPI interface and CRC check, the NOR Flash memory includes the following modules:

[0007] A signal interface module, used for receiving an external input clock signal SCLK, a bit selection signal CS of NOR FLASH, and four bidirectional data signals IOXs;

[0008] The signal processing module includes a clock divider submodule, which is used as the working clock signal of the NOR FLASH device; a data receiver submodule, which is used to collect the data signal input to the NOR FLASH; and a data transmitter submodule, which is used to output the data read from the NOR FLASH.

[0009] The input and output control module contains a serial-to-parallel conversion control submodule, which is used to convert the input and output data signals into serial and parallel signals; a multi-mode SPI selection submodule, which can interact with the instruction decoding module and select the mode according to the decoded register file; an input and output direction control submodule, which is used to control the direction of the four data ports of the SPI interface, and the default direction is input;

[0010] A decoding module, which decodes the input instruction signal after serial conversion through the instruction decoding module to form a register file, wherein the register file includes a command register, an address register and a status register. The command register stores a command byte obtained from instruction decoding, which is used to operate the corresponding function of NOR FLASH. The address register stores two address bytes obtained from instruction decoding, which are used to store the starting address of the NOR FLASH memory unit operated under the instruction. The status register stores a status byte that changes internally in real time, which is used to reflect the real-time status of the NORFLASH function control.

[0011] A data buffer module, which includes a write data FIFO and a read data FIFO. The read data FIFO and the write data FIFO are used to buffer the read and write data, and are both connected to the input and output control module and the NOR FLASH function control module;

[0012] NOR FLASH function controller module, which contains a timing configuration submodule for storing the timing parameters of each control signal of NORFLASH; a state machine submodule for executing the timing changes of NOR FLASH control signals under different functions according to different commands and addresses from the register file; and a NOR FLASH interface module for outputting corresponding control signals;

[0013] CRC data check module, which contains a data check submodule based on IEEE802.3 CRC-32 and a 32-bit CRC check value register. The function of the check submodule is to perform cyclic redundancy check on the data read from NOR FLASH and calculate the corresponding check code; the CRC check value register stores four data bytes from the check module, that is, the check value after cyclic redundancy check.

[0014] Furthermore, the IEEE802.3 CRC-32 is a cyclic redundancy check algorithm, whose data width is 32 bits, the initial value is 0XFFFFFFFF, the result XOR value is 0X00000000, the input and output values ​​are not flipped, and the polynomial formula is:

[0015] X 32 +X 26 +X 23 +X 22 +X 16 +X 12 +X 11 +X 10 +X 8 +X 7 +X 5 +X 4 +X 2 +X+1, where X represents the shift operation of a binary number.

[0016] Furthermore, the basic format of the instruction protocol of the NOR FLASH memory is: command+address+dummy+data, each instruction sequence starts with a one-byte command code, and the other three have different combinations depending on the instructions. The command is the command sending stage, the address is the address sending stage, the dummy is the invalid byte sending stage, and the data is the data sending or receiving stage.

[0017] Furthermore, the multi-mode SPI includes single-wire SPI, dual-wire SPI, four-wire SPI and four-wire SPI in DTR mode.

[0018] Further, the read operation of the single-line SPI, dual-line SPI, four-line SPI and four-line SPI in DTR mode on NOR FLASH includes the following steps:

[0019] Step 1, the signal interface first receives the bit selection enable signal from the outside, then divides the clock signal SCLK to obtain the NOR FALSH working clock, and receives the data signal IOXs;

[0020] Step 2, input stage, the received command and address signals are converted into serial and parallel signals by the input and output control module, and then sent to the decoding module. The decoding module analyzes the corresponding input configuration information according to the instruction format. For the read operation, the input configuration information includes: read operation command, starting address and invalid bytes, and writes these input configuration information into the corresponding register file;

[0021] Step 3, according to the command register and address register values ​​in the register file, the input and output control module selects the corresponding SPI mode;

[0022] Step 4, according to the command register and address register values ​​in the register file, the NOR FLASH function controller module performs different functions according to different commands, thereby outputting corresponding control signals to operate the NOR FLASH. For the read operation, the function controller module performs a read operation on the NOR FLASH, reads the program in the memory, and writes it into the read FIFO of the data buffer module;

[0023] Step 5, the invalid byte stage, is a unique process for the read operation, which is used to execute the delay time of step 4 and wait for the data to be read out from the NOR FLASH;

[0024] Step 6, output stage, after two invalid bytes, the input and output control module outputs the data in the read FIFO through the SPI interface according to the selected SPI mode.

[0025] Furthermore, the verification step of the CRC data verification module includes:

[0026] Step 1, the 32-bit data stored in the read FIFO of the data buffer module is the data read from the NOR FLASH and needs to be verified, which serves as the data stream source of the verification process;

[0027] Step 2, the check submodule of the CRC data check module includes a 32-bit input register, an initial value register, an output register, and a CRC calculation submodule. The initial value of the initial value register is 0XFFFFFFFF;

[0028] Step 3, the CRC check value register of the CRC data check module stores the check code obtained after CRC calculation of all the data in the read FIFO;

[0029] Step 4, the input register reads 32-bit data from the read FIFO, performs CRC calculation with the initial value register, and writes the result to the output register. Then, it is determined whether the data stream from the read FIFO has been read out in full. If not, the value of the output register is used as the value of the initial value register for the next CRC calculation, and the CRC calculation is performed again with the updated input register value. This cycle continues until the data stream is fully read out. At this time, the value of the output register is written to the CRC check value register. The CRC calculation is completed and the process ends.

[0030] Beneficial effects:

[0031] The invention proposes a NOR FLASH memory with a multi-mode SPI interface with CRC check. The memory can select different SPI modes, such as single-line SPI, dual-line SPI, four-line SPI and DTR SPI, according to different instructions received from the SPI interface through the cooperation of an input / output control module and an instruction decoding module, so as to achieve compatibility with multiple SPI modes and high-speed data transmission. In particular, when the DTR four-line SPI mode is selected, data can be output through four bidirectional data ports at the rising edge and the falling edge of an external clock signal SCLK respectively. Under the condition of not changing the clock frequency, the maximum throughput rate of the output data can reach 8 times of SCLK. The invention integrates a CRC data check module. Through the cooperation of the module and a data path, error detection and check can be achieved for code data stored in the NOR FLASH and a data transmission process, so as to ensure the integrity and reliability of data in the multi-mode transmission process. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a schematic diagram of a specific implementation of an internal design structure of a NOR FLASH memory with a multi-mode SPI interface with CRC check provided by the present invention;

[0033] Figure 2 It is an operation example diagram of a NOR FLASH memory with a multi-mode SPI interface with CRC check in the present invention being used for single-line SPI reading of NOR FLASH;

[0034] Figure 3 It is an operation example diagram of a NOR FLASH memory with a multi-mode SPI interface with CRC check in the present invention being used for dual-line SPI reading of NOR FLASH;

[0035] Figure 4 It is an operation example diagram of a NOR FLASH memory with a multi-mode SPI interface with CRC check in the present invention being used for four-wire SPI reading of NOR FLASH;

[0036] Figure 5 It is an operation example diagram of a NOR FLASH memory with a multi-mode SPI interface with CRC check in the present invention being used for four-wire SPI reading NOR FLASH in DTR mode;

[0037] Figure 6 Schematic diagram of the verification process of the CRC data verification module in an embodiment of the present invention;

[0038] Figure 7 It is an operation example diagram of a NOR FLASH memory with a multi-mode SPI interface with CRC check for CRC data check of the present invention;

[0039] Figure 8 It is a basic format diagram of the instruction protocol in the embodiment of the present invention. DETAILED DESCRIPTION

[0040] The technical solutions in the embodiments of the present invention will be further described in detail and completely below in conjunction with the drawings in the embodiments of the present invention. It is obvious that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0041] like Figure 1 As shown, the embodiment of the present invention discloses a NOR FLASH memory with a multi-mode SPI interface with CRC check, comprising:

[0042] The signal interface module 1 is used to receive an external input clock signal SCLK, a bit selection signal CS of NOR FLASH and four bidirectional data signals IOXs;

[0043] The signal processing module 2 includes a clock divider submodule 3 for serving as a working clock signal of the NOR FLASH device; a data receiver submodule 4 for collecting data signals input to the NOR FLASH; and a data transmitter submodule 5 for outputting data read from the NOR FLASH.

[0044] An input / output control module 6, which includes a serial-to-parallel conversion control submodule 7 for performing serial-to-parallel conversion on input / output data signals; a multi-mode SPI selection submodule 8, which can interact with a decoding module 10 and perform mode selection according to a decoded register file 12; an input / output direction control submodule 9, which is used to control the directions of the four data ports of the SPI interface, with the default direction being input;

[0045] A decoding module 10 decodes the input instruction signal after serial conversion through an instruction decoding module 11 to form a register file 12. The register file 12 includes a command register 13, an address register 14, and a status register 15. Further, the command register 13 stores a command byte obtained from instruction decoding, which is used to operate the corresponding function of NOR FLASH. The address register 14 stores two address bytes obtained from instruction decoding, which are used to store the starting address of the NOR FLASH memory unit operated under the instruction. The status register 15 stores a status byte that changes internally in real time, which is used to reflect the real-time status of the NOR FLASH function control.

[0046] A data buffer module 16, which includes a write data FIFO 17 and a read data FIFO 18. The read data FIFO 18 and the write data FIFO 17 are used to buffer the read and write data, and are both connected to the input and output control module 6 and the NORFLASH function control module 19;

[0047] NOR FLASH function controller module 19, which includes a timing configuration submodule 21 for storing the timing parameters of each control signal of NOR FLASH; a state machine submodule 20 for executing the timing changes of NOR FLASH control signals under different functions according to different commands and addresses from the register file; and a NOR FLASH interface module 22 for outputting corresponding control signals;

[0048] Specifically, the present invention provides an operation example for reading NOR FLASH in single-line SPI, dual-line SPI, four-line SPI and four-line SPI in DTR mode, such as Figures 2 to 5 As shown, in these examples, it is a read operation of NOR FLASH, which specifically includes the following steps:

[0049] Step 1, the signal interface first receives the bit select enable signal (CS is pulled low) from the outside, then divides the clock signal SCLK to obtain the NOR FALSH working clock, and receives the data signal IOXs;

[0050] Step 2, input stage, the received command and address signals are converted from serial to parallel by the input / output control module and then sent to the decoding module. The decoding module analyzes the corresponding input configuration information according to the instruction format. For the read operation, the input configuration information includes: a certain read operation command (1 byte), the starting address (2 bytes) and the invalid byte (2 bytes), and writes these input configuration information into the corresponding register file;

[0051] Step 3: According to the command register and address register values ​​in the register file, the input and output control module can select the corresponding SPI mode, such as Figure 2 As shown, the single-wire SPI mode is selected. Figure 3 As shown, the dual-wire SPI mode is selected. Figure 4 As shown, the four-wire SPI mode is selected. Figure 5 As shown, the four-wire SPI mode in DTR mode is selected;

[0052] Step 4, according to the command register and address register values ​​in the register file, the NOR FLASH function controller module performs different functions according to different commands, thereby outputting corresponding control signals to operate the NOR FLASH. For the read operation, the function controller module performs a read operation on the NOR FLASH, thereby reading out the program in the memory and writing it into the read FIFO of the data buffer module.

[0053] Step 5, the invalid byte stage, is a unique process for the read operation, which is mainly used to execute the delay time of step 4, waiting for the data to be read out from the NOR FLASH;

[0054] Step 6, output stage, after two invalid bytes, the input and output control module outputs the data in the read FIFO through the SPI interface according to the selected SPI mode.

[0055] Specifically, for different SPI modes, such as Figure 2 As shown in the figure, the single-line SPI mode triggers the output on the falling edge of the external clock SCLK. A 32-bit data output requires 32 clock cycles, such as Figure 3 As shown, the dual-wire SPI mode also triggers the output on the falling edge, and a 32-bit data output only requires 16 clock cycles, such as Figure 4 As shown, the four-wire SPI mode also triggers the output on the falling edge, and a 32-bit data output only requires 8 clock cycles, such as Figure 5 As shown in the figure, the four-wire SPI mode in DTR mode can trigger the output on both the rising and falling edges of the external clock. A 32-bit data output only requires 4 clock cycles.

[0056] CRC data check module 23, which internally includes a data check submodule 24 based on IEEE802.3 CRC-32 and a 32-bit CRC check value register 25. The function of the check submodule is to perform cyclic redundancy check on the data read from NOR FLASH and calculate the corresponding check code; the CRC check value register stores four data bytes from the check module, that is, the check value after cyclic redundancy check.

[0057] Furthermore, the IEEE802.3 CRC-32 is a cyclic redundancy check algorithm, whose data width is 32 bits, the initial value is 0XFFFFFFFF, the result XOR value is 0X00000000, the input and output values ​​are not flipped, and the polynomial formula is:

[0058] X 32 +X 26 +X 23 +X 22 +X 16 +X 12 +X 11 +X 10 +X 8 +X 7 +X 5 +X 4

[0059] +X 2 +X+1

[0060] The schematic diagram of the verification process of the CRC data verification module in the embodiment of the present invention is as follows: Figure 6 The specific process is explained as follows:

[0061] Step 1, the 32-bit data stored in the read FIFO of the data buffer module is the data read from the NOR FLASH and needs to be verified, which serves as the data stream source of the verification process;

[0062] Step 2, the check submodule of the CRC data check module includes a 32-bit input register, an initial value register, an output register, and a CRC calculation submodule. Based on the CRC-32 cyclic redundancy check algorithm, the initial value of the initial value register is 0XFFFFFFFF;

[0063] Step 3, the CRC check value register of the CRC data check module stores the check code obtained after CRC calculation of all the data in the read FIFO.

[0064] Step 4, specifically, the input register reads 32-bit data from the read FIFO, performs CRC calculation with the initial value register (bit shift + XOR operation), and writes the result to the output register. Then, it is determined whether the data stream from the read FIFO has been read out completely. If not, the value of the output register is used as the value of the initial value register for the next CRC calculation, and the CRC calculation is performed again with the updated input register value. This cycle is repeated until the data stream is completely read out, at which time the value of the output register is written into the CRC check value register. Thus, the CRC calculation is completed and the process ends.

[0065] Furthermore, after the CRC calculation is performed on the read data, the check code needs to be read out. Figure 7 As shown, the present invention provides an operation example of a NOR FLASH memory with a multi-mode SPI interface with CRC check for CRC data check, which specifically includes the following steps:

[0066] Step 1, the signal interface first receives the bit select enable signal (CS is pulled low) from the outside, then divides the clock signal SCLK to obtain the NOR FALSH working clock, and receives the data signal IOXs;

[0067] Step 2, input stage, the received command and address signals are converted into serial and parallel signals by the input and output control module, and then sent to the decoding module. The decoding module analyzes the corresponding input configuration information according to the instruction format. For the CRC check operation, the input configuration information includes: CRC check operation command, starting address, and writes these input configuration information into the corresponding register file;

[0068] Step 3, according to the command register value in the register file, execute the function of the corresponding command. For the CRC check operation, first read the data stored in the NOR FLASH starting from the starting address, then calculate the check code through the CRC check module and write it into the CRC check register.

[0069] Step 4, output stage, the input-output controller outputs the value of the CRC check register through the SPI interface.

[0070] In this embodiment, if Figure 8 As shown, the basic format of the instruction protocol is as follows:

[0071] command+address+dummy+data

[0072] Each instruction sequence starts with a one-byte command code, and the other three have different combinations depending on the instructions. Furthermore, the command is a 1-byte command stage, the address is a 2-byte address stage, the dummy is an invalid byte stage of 0, 1 or 2 bytes, and the data is an N-byte data stage.

[0073] According to the instruction encoding method in the above embodiment, the following is a common instruction sequence:

[0074] 1. Single-byte instruction: Command[7:0]

[0075] 2. Read status register command: Command[7:0], Data[7:0]

[0076] 3. Single-line SPI read data command (sector): Command[7:0], Address[16:0], Dummy[16:0], Data[(8*128-1:0)]

[0077] 4. Dual-line SPI read data command (sector): Command[7:0], Address[16:0], Dummy[16:0], Data[(8*128-1:0)]

[0078] 5. Four-wire SPI read data command (sector): Command[7:0], Address[16:0], Dummy[16:0], Data[(8*128-1:0)]

[0079] 6. Four-wire read data command (sector) in DTR mode: Command[7:0], Address[16:0], Dummy[16:0], Data[(8*128-1:0)]

[0080] 7.CRC check instruction: Command[7:0], Address[16:0], Data[31:0]

[0081] The present invention provides a NOR FLASH memory with a multi-mode SPI interface with a CRC check function, and describes the specific implementation methods in detail. These embodiments are only for explaining the specific application of the present invention, and do not limit the protection scope of the present invention. The protection scope of the present invention not only includes the above-mentioned embodiments, but also covers the equivalent replacement or improvement made by any technician based on the technical solution of the present invention and its inventive concept in the technical field of the present invention. Therefore, any equivalent changes or adjustments that conform to the technical content of the present invention should be regarded as within the protection scope of the present invention.

Claims

1. A NOR Flash memory with a multi-mode SPI interface with CRC check, characterized in that: The NOR Flash memory includes the following modules: A signal interface module, used for receiving an external input clock signal SCLK, a bit selection signal CS of NOR FLASH, and four bidirectional data signals IOXs; A signal processing module, which includes a clock divider submodule and is used as a working clock signal of the NOR FLASH device; The data receiver submodule is used to collect the data signal input to the NOR FLASH; the data transmitter submodule is used to output the data read from the NOR FLASH; An input / output control module, which contains a serial-to-parallel conversion control submodule for performing serial-to-parallel conversion on input / output data signals; The multi-mode SPI selection submodule can interact with the instruction decoding module and select the mode according to the decoded register file; the input and output direction control submodule is used to control the direction of the four data ports of the SPI interface, and the default direction is input; A decoding module, which decodes the input instruction signal after serial conversion through the instruction decoding module to form a register file, wherein the register file includes a command register, an address register and a status register. The command register stores a command byte obtained from instruction decoding, which is used to operate the corresponding function of NOR FLASH. The address register stores two address bytes obtained from instruction decoding, which are used to store the starting address of the NOR FLASH memory unit operated under the instruction. The status register stores a status byte that changes internally in real time, which is used to reflect the real-time status of the NOR FLASH function control. A data buffer module, which includes a write data FIFO and a read data FIFO. The read data FIFO and the write data FIFO are used to buffer the read and write data, and are both connected to the input and output control module and the NOR FLASH function control module; NOR FLASH function controller module, which contains a timing configuration submodule for storing the timing parameters of each NOR FLASH control signal; a state machine submodule for executing the timing changes of NOR FLASH control signals under different functions according to different commands and addresses from the register file; and a NOR FLASH interface module for outputting corresponding control signals; CRC data check module, which contains a data check submodule based on IEEE802.3 CRC-32 and a 32-bit CRC check value register. The function of the check submodule is to perform cyclic redundancy check on the data read from NOR FLASH and calculate the corresponding check code; The CRC check value register stores four data bytes from the check module, that is, the check value after the cyclic redundancy check.

2. A NOR Flash memory with a multi-mode SPI interface with CRC check as claimed in claim 1, characterized in that: The IEEE802.3 CRC-32 is a cyclic redundancy check algorithm with a data width of 32 bits, an initial value of 0XFFFFFFFF, a result XOR value of 0X00000000, and input and output values ​​are not flipped. The polynomial formula is: X 32 +X 26 +X 23 +X 22 +X 16 +X 12 +X 11 +X 10 +X 8 +X 7 +X 5 +X 4 +X 2 +X+1, where X represents the shift operation of a binary number.

3. A NOR Flash memory with a multi-mode SPI interface with CRC check as claimed in claim 1, characterized in that: The basic format of the instruction protocol of the NOR FLASH memory is: command+address+dummy+data, each instruction sequence starts with a one-byte command code, and the other three have different combinations depending on the instructions. The command is the command sending stage, the address is the address sending stage, the dummy is the invalid byte sending stage, and the data is the data sending or receiving stage.

4. A NOR Flash memory with a multi-mode SPI interface with CRC check as claimed in claim 1, characterized in that: Multi-mode SPI includes single-wire SPI, dual-wire SPI, four-wire SPI and four-wire SPI in DTR mode.

5. A NOR Flash memory with a multi-mode SPI interface with CRC check as claimed in claim 4, characterized in that: The read operation of the single-line SPI, the dual-line SPI, the four-line SPI and the four-line SPI in the DTR mode on the NOR FLASH comprises the following steps: Step 1, the signal interface first receives the bit selection enable signal from the outside, then divides the clock signal SCLK to obtain the NOR FALSH working clock, and receives the data signal IOXs; Step 2, input stage, the received command and address signals are converted into serial and parallel signals by the input and output control module, and then sent to the decoding module. The decoding module analyzes the corresponding input configuration information according to the instruction format. For the read operation, the input configuration information includes: read operation command, starting address and invalid bytes, and writes these input configuration information into the corresponding register file; Step 3, according to the command register and address register values ​​in the register file, the input and output control module selects the corresponding SPI mode; Step 4, according to the command register and address register values ​​in the register file, the NOR FLASH function controller module performs different functions according to different commands, thereby outputting corresponding control signals to operate the NOR FLASH. For the read operation, the function controller module performs a read operation on the NOR FLASH, reads the program in the memory, and writes it into the read FIFO of the data buffer module; Step 5, the invalid byte stage, is a unique process for the read operation, which is used to execute the delay time of step 4 and wait for the data to be read out from the NOR FLASH; Step 6, output stage, after two invalid bytes, the input and output control module outputs the data in the read FIFO through the SPI interface according to the selected SPI mode.

6. A NOR Flash memory with a multi-mode SPI interface with CRC check as claimed in claim 1, characterized in that: The verification step of the CRC data verification module includes: Step 1, the 32-bit data stored in the read FIFO of the data buffer module is the data read from the NOR FLASH and needs to be verified, which serves as the data stream source of the verification process; Step 2, the check submodule of the CRC data check module includes a 32-bit input register, an initial value register, an output register, and a CRC calculation submodule. The initial value of the initial value register is 0XFFFFFFFF; Step 3, the CRC check value register of the CRC data check module stores the check code obtained after CRC calculation of all the data in the read FIFO; Step 4, the input register reads 32-bit data from the read FIFO, performs CRC calculation with the initial value register, and writes the result to the output register. Then, it is determined whether the data stream from the read FIFO has been read out in full. If not, the value of the output register is used as the value of the initial value register for the next CRC calculation, and the CRC calculation is performed again with the updated input register value. This cycle continues until the data stream is fully read out. At this time, the value of the output register is written to the CRC check value register. The CRC calculation is completed and the process ends.

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