Integrated circuit capable of withstanding voltage greater than nominal voltage and corresponding method thereof

Abstract

Embodiments of the present disclosure relate to an integrated circuit capable of withstanding a voltage greater than a rated voltage and a corresponding method thereof. There is provided an integrated circuit comprising: a terminal designed to receive a signal at a rated voltage level that can rise to a maximum voltage level; an output circuit including a first transistor and a second transistor coupled in series between the terminal and the output stage; and a protection circuit designed to generate a first voltage controlling the first transistor and a second voltage controlling the second transistor. In the active state, the first voltage and the second voltage are obtained by dividing the voltage level of the terminal. In a deactivated state, the first voltage is obtained by a voltage level of the terminal, and the second voltage is obtained by subtracting a level of a threshold voltage of the protection transistor from the control voltage.

Description

Technical Field

[0001] Embodiments and implementations relate to integrated circuits, particularly with respect to circuit design for operation at maximum voltages greater than rated voltages and tolerance constraints, such as in USB-C port I / O device circuits. Background Art

[0002] In particular, USB-C provides a "power delivery" mode, commonly referred to as "PD", which uses channel CC1 to negotiate the supply of power between connected devices. In this context, there is a detection solution for voltage levels that requires a divide-by-three solution for the channel CC1 pins. A small divider circuit must be able to guarantee operation at and withstand a maximum voltage of 5V (volts).

[0003] Operable at 5V means that, when the USB-C port I / O circuit is activated, the circuit connected to the external terminal CC can operate correctly when the voltage is increased to 5V.

[0004] Being 5 V tolerant means that, when the USB-C port I / O circuit is disabled, the circuit connected to the external terminal CC can withstand a voltage increase of up to 5 V.

[0005] In a simple circuit of the traditional voltage divider type, there is at least one transistor that must have an absolute maximum rating of 5V to ensure functionality and ability of the circuit to withstand 5V.

[0006] However, there are technology sectors that do not provide for manufacturing transistors with a maximum absolute rating of 5V, where in order to benefit from USB-C port I / O circuits, it is still desirable to be able to meet operation and tolerance constraints at 5V. Summary of the invention

[0007] Embodiments and implementations provide a circuit that is capable of operating at and withstanding a maximum voltage (e.g., 5V) greater than a rated voltage (e.g., 3.3V) utilizing only transistors having maximum absolute ratings that are lower than the maximum voltage (e.g., substantially the same as the rated voltage).

[0008] According to one aspect, in this regard, a method for protecting an output circuit in an integrated circuit is proposed, the output circuit comprising a first transistor and a second transistor, the first transistor and the second transistor being coupled in series between a terminal and an output stage, the terminal receiving a signal at a rated voltage level, the rated voltage level being able to rise to a maximum voltage level, the method comprising: the protection circuit generating a first voltage to control the first transistor, and generating a second voltage to control the second transistor, wherein:

[0009] In an active state, the first voltage and the second voltage are obtained by dividing the voltage levels of the terminals; and

[0010] In the deactivated state, the first voltage is obtained by the voltage level of the terminal, and the second voltage is obtained by the level of the control voltage minus the threshold voltage of the protection transistor.

[0011] In other words, the second voltage is upper bounded by a level equal to the control voltage minus the threshold voltage, which level is obtained, for example, by means of a "cascode" type circuit of transistors which may have a maximum absolute rating lower than the maximum voltage but which are arranged to operate at and withstand the maximum voltage.

[0012] Therefore, a circuit such as a voltage divider that operates at and tolerates 5V can be built using only transistors with an absolute maximum rating of 3.3V, i.e., no "high voltage" transistors with an absolute maximum rating of 5V or more.

[0013] According to one implementation:

[0014] In an activated state, the protection circuit and the output circuit are capable of passing current between the terminal and the ground terminal; and

[0015] In the disabled state, the protection circuit and the output circuit cannot pass current between the terminal and the ground terminal.

[0016] According to one embodiment, the first voltage is obtained via a drain voltage of a protection transistor and the second voltage is obtained via a source voltage of the protection transistor, the protection transistor being coupled between a first resistance element and a second resistance element of the voltage divider bridge.

[0017] According to another aspect, an integrated circuit is provided, the integrated circuit comprising:

[0018] Terminals designed to receive signals at a rated voltage level that can rise to a maximum voltage level;

[0019] an output circuit comprising a first transistor and a second transistor coupled in series between the terminal and the output stage; and

[0020] A protection circuit is designed to generate a first voltage to control the first transistor and a second voltage to control the second transistor so that:

[0021] In an active state, the first voltage and the second voltage are obtained by dividing the voltage levels of the terminals; and

[0022] In the deactivated state, the first voltage is obtained by the voltage level of the terminal, and the second voltage is obtained by the level of the control voltage minus the threshold voltage of the protection transistor.

[0023] According to one embodiment:

[0024] In an activated state, the protection circuit and the output circuit are capable of passing current between the terminal and the ground terminal; and

[0025] In the disabled state, the protection circuit and the output circuit cannot pass current between the terminal and the ground terminal.

[0026] According to one embodiment, the protection circuit comprises a resistor divider bridge including a protection transistor coupled in series between a first resistor element and a second resistor element and designed to be controlled by a control voltage on its gate, the gate of the first transistor being coupled to the drain of the protection transistor and the gate of the second transistor being coupled to the source of the protection transistor.

[0027] According to one embodiment, the first resistive element is coupled between the protection terminal and the drain of the transistor, and the second resistive element is coupled between the source of the protection transistor and the ground terminal.

[0028] According to one embodiment, the protection transistor, the first transistor of the output circuit, and the second transistor of the output circuit have maximum absolute ratings that are lower than the maximum voltage level.

[0029] According to one embodiment, the nominal voltage is between 3.0V and 3.6V, and the maximum voltage is between 4.7V and 5.0V.

[0030] According to another aspect, a system on chip is also proposed, comprising an integrated circuit as defined above, the integrated circuit being in an input-output device of a USB-C port. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Other advantages and features of the present disclosure will become apparent upon examination of the detailed description of non-limiting embodiments and implementations and in light of the accompanying drawings, in which:

[0032] Figure 1 An exemplary circuit is shown;

[0033] Figure 2 Shown is a reference Figure 1 The described circuit is in the active state, and the voltage at the terminals is the rated value;

[0034] Figure 3 Shown is a reference Figure 1 The circuit described is in an active state, with the voltage at the terminals at maximum value;

[0035] Figure 4 Shown is a reference Figure 1 The voltage at the terminals of the described circuit in the inactive state is the rated value;

[0036] Figure 5 Shown is a reference Figure 1 The circuit described is in the deactivated state, with the voltage at the terminals at the maximum value;

[0037] Figure 6 A system on a chip with a network of input-output terminals and functional blocks is schematically shown. DETAILED DESCRIPTION

[0038] Figure 1 An exemplary DIV circuit (such as a voltage divider) is shown that is operable and able to withstand a maximum voltage (eg, 5V), the DIV circuit including transistors all having maximum absolute ratings less than 5V (eg, substantially 3.3V).

[0039] The absolute maximum rating is the voltage value above which the transistor risks breaking down when a voltage greater than this voltage value is applied between its two terminals.

[0040] For the transistors in the DIV circuit, we assume that the gate breakdown voltage (i.e., the maximum absolute rating between the gate terminal and the source / drain terminals) is the same as the junction breakdown voltage (i.e., the maximum absolute rating between the source terminal and the drain terminal).

[0041] The output circuit CRC_out of the voltage divider DIV comprises an output stage Ra-Nout-Rb which is able to divide the voltage V_CC present at the input terminal. The output stage Ra-Nout-Rb is called a "bridge voltage divider".

[0042] This terminal is designed to be at the rated voltage level Vnml( Figure 2 and Figure 4 ) receives the signal V_CC, the rated voltage level can rise to the maximum voltage level Vmax ( Figure 3 and Figure 5 ).

[0043] Voltage division is obtained, for example, with the aid of a series of resistor elements Ra, Rb so that a divided voltage V_CC_div is supplied at the output node Nout, whose level is equal to the ratio B / (A+B) of the voltage level of the input signal V_CC (where A is the value of resistor Ra and B is the value of resistor Rb).

[0044] For example, the values ​​A and B may be chosen such that the ratio B / (A+B) is equal to 1 / 3, in particular in detector applications on USB-C channels CC1 / 2 in power delivery mode, typically "USB PD CC". That is, the ratio of the resistors Ra, Rb that implement the voltage division at the output Nout may be chosen to be any value without affecting the functionality and the ability of the DIV circuit to withstand the maximum voltage.

[0045] The voltage of the input signal V_CC is transmitted to the voltage divider bridge Ra, Rb via a first transistor TPcd and a second transistor TPcs coupled in series between the terminal V_CC and the resistor Ra of the output stage.

[0046] The first transistor TPcd and the second transistor TPcs are PMOS transistors (an abbreviation commonly used for “P-type metal oxide semiconductor”).

[0047] The first transistor TPcd is controlled at its gate by a first so-called "cascode" voltage V_CASCd, and the second transistor TPcs is controlled at its gate by a second voltage (also "cascode") V_CASCs.

[0048] The first cascode voltage V_CASCd and the second cascode voltage V_CASCs are generated by the protection circuit CRC_prot, in particular, as a function of the voltage V_CC of the input signal at the terminal.

[0049] The protection circuit CRC_prot comprises a resistor divider bridge R1 -TNc-R2 including a protection transistor TNc coupled in series between a first resistive element R1 and a second resistive element R2 .

[0050] For example, the first resistance element R1 is coupled between the terminal and the drain of the protection transistor TNc, and the second resistance element R2 is coupled between the source of the protection transistor TNc and the ground terminal GND.

[0051] In one example suitable for a nominal voltage of substantially 3.3 V (eg between 3.0 V and 3.6 V) and a maximum voltage of substantially 5 V (eg between 4.7 V and 5.3 V), a ratio substantially equal to 1 / 3 will be chosen in the voltage divider of the protection circuit CRC_prot.

[0052] The protection transistor TNc is, for example, an NMOS transistor (an abbreviation generally used for “N-type metal oxide semiconductor”).

[0053] The protection transistor TNc is designed to be controlled by a control voltage V_CASC (also called “cascode voltage”) at its gate.

[0054] "Cascode voltage" means a control voltage (eg, a static voltage) that places a transistor in a state that is substantially unchanged with respect to the implementation of the functionality of the circuit to which it belongs.

[0055] In particular, here, using the common source control voltage V_CASC at the gate of the protection transistor TNc, the level at the source voltage "Vs" may have an upper limit relative to the drain voltage "Vd", and the functionality of the circuit including the transistor is able to divide the terminal voltage V_CC.

[0056] In practice, the upper limit of the source voltage Vs of the protection transistor TNc is the level of the gate voltage “Vg” (Vg=V_CASC) minus the threshold “Vt” of the protection transistor TNc.

[0057] In other words: Vs≤Vg-Vt=V_CASC-Vt.

[0058] The threshold voltage Vt of the protection transistor TNc is, for example, between 0.6V and 0.8V.

[0059] The cascode control voltage V_CASC is generated, for example, by an “external” power supply circuit PWR_IO (eg a power supply circuit of an integrated circuit including the voltage divider DIV).

[0060] The cascode control voltage V_CASC is generated, for example, at a nominal voltage level, independent of the actual voltage level V_CC at the terminals.

[0061] The first cascode voltage V_CASCd of the first transistor TPcd of the control output circuit CRC_out is taken from the drain of the protection transistor TNc.

[0062] Accordingly, the second cascode voltage V_CASCs of the second transistor TPcs of the control output circuit CRC_out is taken from the source of the protection transistor TNc.

[0063] For example, in this regard, the gate (V_CASCd) of the first transistor TPcd is coupled to the drain of the protection transistor TNc; and the gate (V_CASCs) of the second transistor TPcs is coupled to the source of the protection transistor TNc.

[0064] Finally, NMOS, TNsw1, TNsw2, Tnsw3 transistors acting as activation / deactivation switches in the voltage divider circuit DIV are arranged between the ground reference terminal GND and the protection circuit CRC_prot, the output circuit CRC_out and the output node Nout.

[0065] The first switch TNsw1 controlled by the activation signal V_EN may, for example, be coupled between the ground GND and the second resistance element R2 of the protection circuit CRC_prot.

[0066] The second switch TNsw2 controlled by the activation signal V_EN may, for example, be coupled between the ground GND and the resistance element Rb of the output circuit CRC_out.

[0067] The third switch TNsw3 controlled by the inversion of the activation signal V_EN may be coupled, for example, between the ground GND and the output node Nout of the output circuit CRC_out.

[0068] In this way, the activation signal V_EN and its inverse V_nEN make the DIV circuit in the activation state ON ( Figure 2 and Figure 3 ), or in the disabled state OFF( Figure 4 and Figure 5 ).

[0069] In the activation state ON, the switches TNsw1 and TNsw2 are controlled to be ON by the activation signal V_EN, and the third switch TNsw3 is controlled to be OFF by the inversion of the activation signal V_nEN.

[0070] Therefore, in the activation state ON, the protection circuit CRC_prot and the output circuit CRC_out can pass current between the terminal and the ground terminal GND.

[0071] In the deactivated state OFF, the switches TNsw1 and TNsw2 are controlled to be OFF by the activation signal V_EN, and the third switch TNsw3 is controlled to be ON by the inversion of the activation signal V_nEN.

[0072] Therefore, in the deactivated state OFF, the protection circuit CRC_prot and the output circuit CRC_out cannot pass current between the terminal and the ground terminal GND. In addition, the output node Nout is “short-circuited” to the ground GND.

[0073] The exemplary protection circuit CRC_prot thus enables the realization of this dual functional condition:

[0074] In the active state ON, the first cascode voltage V_CASCd and the second cascode voltage V_CASCs of the control output circuit CRC_out are obtained by dividing the voltage level V_CC of the terminal (factor N / (N+2N)=1 / 3). In this regard, refer to the following description Figure 2 and Figure 3 .and:

[0075] In the deactivated state OFF, the first cascode voltage V_CASCd of the control output circuit CRC_out is obtained by dividing the voltage level V_CC of the terminal; and the upper limit of the second cascode voltage V_CASCs of the control output circuit CRC_out is the level of the cascode control voltage V_CASC minus the threshold voltage Vt of the protection transistor TNc. In this regard, refer to the following description Figure 4 and Figure 5 .

[0076] Figure 2 The above reference Figure 1 In the described DIV circuit in the active state ON, the voltage V_CC at the terminal is the rated value Vnml.

[0077] The rated voltage Vnml may be between 3.0 V and 3.6 V, for example, 3.3 V. The activation signal V_EN is set to 3.3 V, and its inverse V_nEN is set to 0V.

[0078] In this case, the control voltage V_CASC at 3.3V controls the protection transistor TNc (NMOS type) to be in a conducting state with respect to its source voltage.

[0079] Since the protection circuit CRC_prot is capable of passing current, the drain voltage V_CASCd of the transistor TNc is equal to the voltage divided by 3 of the voltage level V_CC at the terminal, ie, 1.1V.

[0080] The source voltage V_CASCs of the transistor TNc is equal to the drain voltage V_CASCd, which is 1.1V.

[0081] The first voltage V_CASCd at 1.1V controls the first transistor TPcd (PMOS type) of the output circuit CRC_out to be in the on state; and similarly, the second voltage V_CASCs at 1.1V controls the second transistor TPcs (PMOS type) of the output circuit CRC_out to be in the on state.

[0082] The voltage V_CC at 3.3 V is therefore transmitted to the output stage Ra-Nout-Rb, and the voltage division function of V_CC is realized at the voltage V_CC_div at the output node Nout, here also because the output circuit CRC_out is able to deliver current.

[0083] Figure 3 The above reference Figure 1 In the described DIV circuit in the active state ON, the voltage V_CC at the terminal is the maximum value Vmax.

[0084] The maximum voltage Vmax may be between 4.7V and 5.3V, for example 5.0V.

[0085] In this case, the control voltage V_CASC at 3.3V controls the protection transistor TNc (NMOS type) to be in a conducting state with respect to its source voltage.

[0086] The drain voltage V_CASCd of the transistor TNc is equal to the voltage level V_CC at the terminal divided by 3, ie substantially 1.7 V, since the protection circuit CRC_prot is able to pass current.

[0087] The source voltage V_CASCs of the transistor TNc is equal to the drain voltage V_CASCd, which is 1.7V.

[0088] The first voltage V_CASCd at 1.7V controls the first transistor TPcd (PMOS type) of the output circuit CRC_out to be in the on state relative to its source voltage; and similarly, the second voltage V_CASCs at 1.7V controls the second transistor TPcs (PMOS type) of the output circuit CRC_out to be in the on state relative to its source voltage.

[0089] Therefore, the voltage V_CC at 5V is transmitted to the output stage Ra-Nout-Rb, and the voltage division function of V_CC is realized on the voltage V_CC_div at the output node Nout, because the protection circuit CRC_prot can pass current.

[0090] Therefore, the DIV circuit operates at the maximum voltage value V_CC.

[0091] Figure 4 The above reference shows Figure 1 The DIV circuit is in the disabled state OFF, and the voltage V_CC at the terminal is the rated value Vnml, for example, 3.3V.

[0092] In this case, since the protection circuit CRC_prot cannot pass current, the terminal voltage V_CC at 3.3 V is transmitted to the conduction terminal (drain / source) of the protection transistor TNc through resistance coupling.

[0093] The control voltage V_CASC at 3.3V thus controls the protection transistor TNc (NMOS type) in a linear (or "ohmic") state with respect to its source voltage, ie in a self-regulating manner so that the source-gate voltage Vs-Vg is equal to the threshold voltage Vt of the transistor TNc.

[0094] The drain voltage V_CASCd of the transistor TNc is equal to the level V_CC at the terminal, ie, 3.3V.

[0095] The upper limit of the source voltage V_CASCs of the transistor TNc is the level of the cascode control voltage V_CASC minus the threshold voltage Vt of the protection transistor TNc, ie, substantially 2.5V.

[0096] The first voltage V_CASCd at 3.3V controls the first transistor TPcd (PMOS type) of the output circuit CRC_out to be in a conducting state.

[0097] The second voltage V_CASCs at 2.5V controls the second transistor TPcs (PMOS type) of the output circuit CRC_out to be in a linear state, that is, the source-gate voltage Vs-Vg is made equal to the threshold voltage Vtp of the second transistor TPcs in a self-regulating manner. The threshold voltage Vtp of the P-type transistor has a negative sign, for example, Vtp=-0.7V.

[0098] The upper limit of the source voltage V_INT1 of the second transistor TPcs of the output circuit CRC_out may therefore be the second voltage V_CASCs minus the threshold voltage Vtp of the P-type transistor TPcs, ie, substantially 3.3V=2.5V−(−0.7V) (or between 3.0V and 3.3V in practice).

[0099] The output node Nout is connected to the ground, and the voltage V_CC_div=0V is transmitted to the drain of the second transistor PMOS TPcs by resistance coupling via the resistor Ra.

[0100] Figure 5 The above reference shows Figure 1 The DIV circuit is in the disabled state OFF, and the voltage V_CC at the terminal is at a maximum value Vmax, for example, 5V.

[0101] In this case, since the protection circuit CRC_prot cannot pass current, the terminal voltage V_CC at 5 V is transmitted to the conduction terminal (drain / source) of the protection transistor TNc through resistance coupling.

[0102] The control voltage V_CASC at 3.3V thus controls the protection transistor TNc (NMOS type) in a linear (or "ohmic") state with respect to its source voltage, ie in a self-regulating manner so that the source-gate voltage Vs-Vg is equal to the threshold voltage Vt of the transistor TNc.

[0103] The drain voltage V_CASCd of the transistor TNc is equal to the level V_CC at the terminal, ie, 5V.

[0104] The upper limit of the source voltage V_CASCs of the transistor TNc is the level of the cascode control voltage V_CASC minus the threshold voltage Vt of the protection transistor TNc, ie, substantially 2.5V=3.3V-0.7V.

[0105] The first voltage V_CASCd at 5V controls the first transistor TPcd (PMOS type) of the output circuit CRC_out to be in a conducting state.

[0106] The second voltage V_CASCs at 2.5V controls the second transistor TPcs (PMOS type) of the output circuit CRC_out to be in a linear state, that is, the source-gate voltage Vs-Vg is made equal to the threshold voltage Vtp of the second transistor TPcs in a self-regulating manner. The threshold voltage Vtp of the P-type transistor has a negative sign, for example, Vtp=-0.7V.

[0107] The upper limit of the source voltage V_INT1 of the second transistor TPcs of the output circuit CRC_out may therefore be the second voltage V_CASCs minus the threshold voltage Vtp of the P-type transistor TPcs, ie, substantially 3.3V=2.5V-(-0.7V) (or between 3.3V and 3.5V in practice).

[0108] The output node Nout is connected to the ground, and the voltage V_CC_div=0V is transmitted to the drain of the second transistor PMOS TPcs by resistance coupling via the resistor Ra.

[0109] Thus, in this case, none of the transistors of the DIV circuit is biased with a voltage greater than the breakdown voltage between its respective terminals.

[0110] In particular, the protection transistor, the first switch TNsw1 and the two transistors TPcd, TPcs of the output circuit CRC_out are not biased with a voltage greater than a breakdown voltage between their conduction terminals or between their gate terminals and conduction terminals, such as 3.3V (or even 3.5V).

[0111] Therefore, the DIV circuit can withstand the maximum voltage value V_CC.

[0112] Figure 6 A system on chip SOC is schematically shown, which may include a network of input-output terminals IO_RNG and various functional blocks.

[0113] The functional block may include a digital circuit DIG, for example a core or a processor; a memory circuit MEM, for example a volatile memory of the "SRAM" type and possibly a non-volatile memory of the "EEPROM" or "Flash" type; an analog circuit ANL, for example for wireless communication or having functionality for analog detection of physical quantities; a power supply circuit SUP, for example capable of supplying a regulated voltage and which may include a previously referenced Figure 1 Mentioned power supply PWR_IO.

[0114] The network of input-output terminals IO_RNG includes in particular an input-output device IO_CC_CIRC capable of controlling the terminals IO_CC_PIN of the ports CC1 / CC2 of the USB-C connection.

[0115] The input-output device IO_CC_CIRC comprises in particular detection means DET for a voltage level which requires a divide-by-three solution for the voltage level V_CC at the terminal IO_CC_PIN.

[0116] The detection means DET incorporates in particular a voltage divider circuit DIV, as described above with reference to Figures 1 to 5 As described, this enables an operation that is able to operate at and withstand a maximum voltage of 5 V (for a nominal voltage of 3.3 V) to be guaranteed.

[0117] Furthermore, the input-output device IO_CC_CIRC comprises an internal terminal INTRN_PIN for communicating with a functional block DIG-SUP of the system on chip SOC, for example according to a conventional protocol I2C, AHB or AXI.

[0118] Therefore, the operation and tolerance constraints at 5 V imposed by the USB PD CC standard on the input-output device IO_CC_CIRC do not prevent the creation of a system-on-chip SOC in a technology field that does not provide for the manufacture of transistors with a maximum absolute rating greater than or equal to 5 V. This is particularly advantageous in terms of production costs and optimized manufacturing processes.

[0119] A method for protecting an output circuit in an integrated circuit is provided, the output circuit comprising a first transistor and a second transistor, the first transistor and the second transistor being coupled in series between a terminal (IO_CC_PIN) and an output stage (Ra, Rb, Nout), the terminal (IO_CC_PIN) receiving a signal (V_CC) at a rated voltage level (Vnml), the rated voltage level (Vnml) being able to rise to a maximum voltage level (Vmax), the method being summarized as comprising: a protection circuit generating a first voltage (V_CAS) controlling the first transistor Cd), and generates a second voltage (V_CASCs) for controlling the second transistor, wherein: in an activated state (ON), the first voltage (V_CASCd) and the second voltage (V_CASCs) are obtained by dividing the voltage level (V_CC) of the terminal; in a deactivated state (OFF), the first voltage (V_CASCd) is obtained by the voltage level (V_CC) of the terminal, and the second voltage (V_CASCs) is obtained by subtracting the level of the threshold voltage of the protection transistor (TNc) from the control voltage (V_CASC).

[0120] In an activated state (ON), the protection circuit and the output circuit may be able to pass current between the terminal and the ground terminal; and in a deactivated state (OFF), the protection circuit and the output circuit may not be able to pass current between the terminal and the ground terminal.

[0121] The first voltage (V_CASCd) can be obtained by the drain voltage of the protection transistor (TNc), and the second voltage (V_CASCs) can be obtained by the source voltage of the protection transistor (TNc), and the protection transistor (TNc) is coupled between the first resistance element (R1) and the second resistance element (R2) of the voltage divider bridge (RDIV).

[0122] The integrated circuit can be summarized as comprising: a terminal (IO_CC_PIN) designed to receive a signal (V_CC) at a rated voltage level (Vnml) that can rise to a maximum voltage level (Vmax); an output circuit comprising a first transistor (TPcd) and a second transistor (TPcs), the first transistor (TPcd) and the second transistor (TPcs) being coupled in series between the terminal (IO_CC_PIN) and an output stage (Ra, Rb, Nout); and a protection circuit designed to generate a voltage that controls the first transistor The first voltage (V_CASCd) of the first transistor and the second voltage (V_CASCs) of the second transistor are controlled, so that: in the activated state (ON), the first voltage (V_CASCd) and the second voltage (V_CASCs) are obtained by dividing the voltage level (V_CC) of the terminal; in the deactivated state (OFF), the first voltage (V_CASCd) is obtained by the voltage level (V_CC) of the terminal, and the second voltage (V_CASCs) is obtained by subtracting the level of the threshold voltage of the protection transistor (TNc) from the control voltage (V_CASC).

[0123] In an activated state (ON), the protection circuit and the output circuit may be able to pass current between the terminal and the ground terminal; and in a deactivated state (OFF), the protection circuit and the output circuit may not be able to pass current between the terminal and the ground terminal.

[0124] The protection circuit may include a resistor divider bridge (RDIV), which includes a protection transistor (TNc), which is coupled in series between a first resistor element (R1) and a second resistor element (R2) and is designed to be controlled by a control voltage (V_CASC) on its gate, the gate of the first transistor (V_CASCd) being coupled to the drain of the protection transistor, and the gate of the second transistor (V_CASCs) being coupled to the source of the protection transistor.

[0125] The first resistance element (R1) may be coupled between the terminal (IO_CC_PIN) and the drain of the protection transistor (TNc), and the second resistance element (R2) may be coupled between the source of the protection transistor (TNc) and the ground terminal (GND).

[0126] The protection transistor (TNc), the first transistor (TPcd) of the output circuit, and the second transistor (TPcs) of the output circuit may have a maximum absolute rating lower than the maximum voltage level.

[0127] The nominal voltage may be between 3.0V and 3.6V, and the maximum voltage may be between 4.7V and 5.3V.

[0128] The system on chip (SOC) may include an integrated circuit in an input-output device (IO_CC_CIRC) of a terminal (IO_CC_PIN) of the USB-C port.

[0129] The various embodiments described above can be combined to provide additional embodiments. According to the above detailed description, these and other changes can be made to the embodiments. In general, in the appended claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted as including all possible embodiments and the full range of equivalents enjoyed by these claims. Therefore, the claims are not limited by this disclosure.

Claims

1. A method for protecting an output circuit by an integrated circuit, wherein the output circuit includes a first transistor and a second transistor, the first transistor and the second transistor are coupled in series between a terminal and an output stage, the terminal being configured to receive a signal at a rated voltage level, the rated voltage level being able to increase to a maximum voltage level, and The method comprises: A first voltage is generated by a protection circuit, wherein the first voltage controls the first transistor; as well as A second voltage is generated by the protection circuit, and the second voltage controls the second transistor, wherein: In an active state, both the first voltage and the second voltage are generated by dividing a voltage level of the signal; and In a deactivated state, the first voltage is generated to be the same as the voltage level of the signal, and the second voltage is generated to be a level of a control voltage minus a threshold voltage of a protection transistor. 2 . The method of claim 1 , wherein in the activated state, the protection circuit and the output circuit pass current between the terminal and a ground terminal. 3 . The method of claim 1 , wherein in the disabled state, the protection circuit and the output circuit are unable to pass current between the terminal and a ground terminal. 4 . The method according to claim 1 , wherein the first voltage is obtained as a drain voltage of the protection transistor, and the second voltage is obtained as a source voltage of the protection transistor. 5 . The method of claim 4 , wherein the protection transistor is coupled between a first resistive element and a second resistive element of a voltage divider bridge.

6. An integrated circuit comprising: a terminal configured to receive a signal at a voltage level that is capable of increasing to a maximum voltage level; an output circuit comprising a first transistor and a second transistor, the first transistor and the second transistor being coupled in series between the terminal and an output stage; as well as A protection circuit, the protection circuit being configured to generate a first voltage and a second voltage, the first voltage controlling the first transistor, the second voltage controlling the second transistor, wherein: In an active state, both the first voltage and the second voltage are generated by dividing the voltage level of the signal; and In a deactivated state, the first voltage is generated to be the same as the voltage level of the terminal, and the second voltage is generated to be a level of a control voltage minus a threshold voltage of a protection transistor.

7. The integrated circuit of claim 6, wherein in the activated state, the protection circuit and the output circuit are capable of passing current between the terminal and a ground terminal.

8. The integrated circuit of claim 6, wherein in the disabled state, the protection circuit and the output circuit are unable to pass current between the terminal and a ground terminal.

9. The integrated circuit of claim 6 , wherein the protection circuit comprises a resistor divider bridge, the resistor divider bridge comprising the protection transistor, the protection transistor being coupled in series between a first resistor element and a second resistor element, and wherein the protection transistor is configured to be controlled by the control voltage at a gate of the protection transistor.

10. The integrated circuit of claim 9, wherein a gate of the first transistor is coupled to a drain of the protection transistor, and a gate of the second transistor is coupled to a source of the protection transistor.

11. The integrated circuit of claim 9, wherein the first resistive element is coupled between the terminal and a drain of the protection transistor, and the second resistive element is coupled between a source of the protection transistor and a ground terminal.

12. The integrated circuit of claim 6, wherein the protection transistor, the first transistor of the output circuit, and the second transistor of the output circuit have maximum absolute ratings, the maximum absolute ratings being lower than the maximum voltage level.

13. The integrated circuit of claim 6, wherein a nominal voltage of the signal is between 3.0V and 3.6V, and the maximum voltage is between 4.7V and 5.3V.

14. A system on chip, comprising: USB-C port terminal input-output device; as well as An integrated circuit, the integrated circuit comprising: a terminal configured to receive a signal at a voltage level that is capable of increasing to a maximum voltage level; an output circuit comprising a first transistor and a second transistor, the first transistor and the second transistor being coupled in series between the terminal and an output stage; and A protection circuit, the protection circuit being configured to generate a first voltage and a second voltage, the first voltage controlling the first transistor, the second voltage controlling the second transistor, wherein: In an active state, both the first voltage and the second voltage are generated by dividing the voltage level of the signal; and In a deactivated state, the first voltage is generated to be the same as the voltage level of the terminal, and the second voltage is generated to be a level of a control voltage minus a threshold voltage of a protection transistor.

15. The system on chip of claim 14, wherein in the activated state, the protection circuit and the output circuit are capable of passing current between the terminal and a ground terminal. 16 . The system on chip of claim 14 , wherein in the disabled state, the protection circuit and the output circuit are unable to pass current between the terminal and a ground terminal.

17. The system on chip of claim 14, wherein the protection circuit comprises a resistor divider bridge, the resistor divider bridge comprising the protection transistor, the protection transistor being coupled in series between a first resistor element and a second resistor element, and wherein the protection transistor is configured to be controlled by the control voltage at a gate of the protection transistor. 18 . The system on chip of claim 17 , wherein a gate of the first transistor is coupled to a drain of the protection transistor, and a gate of the second transistor is coupled to a source of the protection transistor.

19. The system on chip of claim 17, wherein the first resistive element is coupled between the terminal and a drain of the protection transistor, and the second resistive element is coupled between a source of the protection transistor and a ground terminal.

20. The system on chip of claim 14, wherein the protection transistor, the first transistor of the output circuit, and the second transistor of the output circuit have maximum absolute ratings, the maximum absolute ratings being lower than the maximum voltage level.

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