A 10T1C-SRAM in-memory computing unit and memory computing circuit

Abstract

The present invention relates to the technical field of integrated circuit design, and more specifically, to a 10T1C-SRAM in-memory computing unit and a memory computing circuit. The present invention adds 4 NMOS transistors N4~N7 and 1 capacitor C on the basis of the classic 6T-SRAM, and designs a new 10T1C-SRAM in-memory computing unit, which inherits the data storage and read-write functions of the 6T-SRAM, and can use N4, N5, N6, N7 and C to form a computing unit to realize in-memory AND calculation and in-memory XNOR calculation. The present invention also constructs an in-memory computing circuit based on the newly designed 10T1C-SRAM in-memory computing unit, and can also perform in-memory 1b-AND MAC calculation and in-memory BNN calculation, which has strong functionality and great flexibility.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and more specifically, to: 1. a 10T1C-SRAM in-memory computing unit, and 2. a memory computing circuit constructed based on the 10T1C-SRAM in-memory computing unit. Background Art

[0002] With the rapid development of artificial intelligence, machine learning, and the Internet of Things, deep neural network computing is gradually penetrating into various application scenarios. When performing neural network calculations, the traditional von Neumann computing architecture requires a lot of data movement and frequent memory access. However, due to the gradual decline of the process, the speed gap between the memory and the processing unit is getting bigger and bigger, which brings unnecessary energy loss and computing delay to memory access and data movement. This is also known as the "memory wall" bottleneck problem. Recently, the computing-in-memory (CIM) architecture has been proposed to provide a feasible solution to the energy efficiency problem of edge AI devices.

[0003] Currently, many in-memory computing units can only implement a certain computing mode, such as only AND, or only XNOR, etc. Similarly, the types of computing that can be implemented by the memory computing circuits built based on the existing in-memory computing units are also relatively small. Summary of the invention

[0004] Based on this, it is necessary to provide a 10T1C-SRAM in-memory computing unit and a memory computing circuit to address the problem that some existing in-memory computing units can only implement a certain computing mode.

[0005] The present invention is implemented by the following technical solutions:

[0006] In a first aspect, the present invention provides a 10T1C-SRAM in-memory computing unit, comprising: a 6T-SRAM portion and a computing portion.

[0007] The 6T-SRAM portion is provided with storage nodes Q and QB for reading, writing, and maintaining storage weight data Weight.

[0008] The calculation part includes: 4 NMOS tubes N4~N7 and 1 capacitor C. The gate of N4 is connected to Q, the source is connected to the input signal IN, and the drain is connected to the first end of C; the gate of N5 is connected to the control signal INN_E, the source is connected to QB, and the drain is connected to the first end of C; the gate of N6 is connected to IN, the source is connected to Q, and the drain is connected to the first end of C; the gate of N7 is connected to the control signal INN_EN, the source is grounded to VSS, and the drain is connected to the first end of C; the second end of C is connected to the calculation bit line CBL. Among them, IN represents input data Input.

[0009] The 10T1C-SRAM in-memory computing unit provides three working modes, including: data storage mode, in-memory AND computing mode, and in-memory XNOR computing mode.

[0010] The implementation of the 10T1C-SRAM in-memory computing unit is based on the method or process of an embodiment of the present disclosure.

[0011] In a second aspect, the present invention discloses a storage and calculation circuit constructed based on a 10T1C-SRAM in-memory calculation unit, including: a storage and calculation array and a peripheral control circuit.

[0012] The storage and computing array includes: M 10T1C-SRAM in-memory computing units as disclosed in the first aspect are distributed in an array. The 10T1C-SRAM in-memory computing units in the same row share the same word line WL and the same CTRL module; the 10T1C-SRAM in-memory computing units in the same column share the same bit line BL, the same bit line BLB, and the same computing bit line CBL.

[0013] In the storage and calculation circuit, there are M CTRL modules and M CBLs; the M Es of the M CTRL modules are all global control signals CE, and the M INs are independently controlled; the M CBLs are connected to VSS through M reset NMOS tubes; and the control ends of the M reset NMOS tubes are all connected to the reset signal Reset.

[0014] The peripheral control circuit is used to control the operation of the storage and calculation circuit.

[0015] The memory computing circuit constructed based on the 10T1C-SRAM in-memory computing unit provides five working modes, including: data storage mode, in-memory AND computing mode, in-memory XNOR computing mode, in-memory 1b-AND MAC computing mode, and in-memory BNN computing mode.

[0016] The implementation of the storage-computation circuit constructed based on the 10T1C-SRAM in-memory computing unit is based on the method or process of an embodiment of the present disclosure.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] 1. Based on the classic 6T-SRAM, the present invention adds 4 NMOS transistors N4~N7 and 1 capacitor C to design a new 10T1C-SRAM in-memory computing unit, which inherits the data storage and read-write functions of 6T-SRAM, and can use N4, N5, N6, N7 and C to form a computing unit to realize in-memory AND calculation and in-memory XNOR calculation.

[0019] 2. The present invention is based on the newly designed 10T1C-SRAM in-memory computing unit to construct an in-memory computing circuit, which can not only realize data storage and reading and writing, in-memory AND computing, in-memory XNOR computing, but also in-memory 1b-AND MAC computing and in-memory BNN computing, with strong functionality and great flexibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0021] Figure 1 A circuit diagram of a 10T1C-SRAM in-memory computing unit provided in Embodiment 1 of the present invention;

[0022] Figure 2 A circuit diagram of the CTRL module provided in Embodiment 1 of the present invention;

[0023] Figure 3 for Figure 1 Schematic diagram of the computing unit in the 10T1C-SRAM memory in the data storage mode;

[0024] Figure 4 for Figure 1 The schematic diagram of the calculation part of the 10T1C-SRAM in-memory calculation unit in the in-memory AND calculation mode;

[0025] Figure 5 for Figure 1 Schematic diagram of the calculation part of the 10T1C-SRAM in-memory calculation unit in the in-memory XNOR calculation mode;

[0026] Figure 6 A circuit diagram of a storage and calculation circuit constructed based on a 10T1C-SRAM in-memory calculation unit provided in Embodiment 2 of the present invention;

[0027] Figure 7 for Figure 6 Schematic diagram of in-memory computing circuit for in-memory 1b-AND MAC computing;

[0028] Figure 8 for Figure 6 A signal timing diagram of the in-memory computing circuit performing in-memory 1b-AND MAC computing;

[0029] Fig. 9 for Figure 6 Schematic diagram of in-memory BNN calculations performed by an in-memory computing circuit;

[0030] Fig.10 for Figure 6 Signal timing diagram of the in-memory computing circuit performing in-memory BNN calculation. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] It should be noted that when a component is referred to as being "mounted on" another component, it may be directly on the other component or there may be a central component. When a component is considered to be "set on" another component, it may be directly set on the other component or there may be a central component at the same time. When a component is considered to be "fixed to" another component, it may be directly fixed on the other component or there may be a central component at the same time.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "or / and" used herein includes any and all combinations of one or more of the related listed items.

[0034] Example 1

[0035] See also Figure 1 , is a circuit structure diagram of the 10T1C-SRAM in-memory computing unit provided in this embodiment 1.

[0036] In terms of components, the 10T1C-SRAM memory computing unit includes: 2 PMOS tubes P0~P1, 8 NMOS tubes N0~N7, and 1 capacitor C.

[0037] According to the functional division, the 10T1C-SRAM in-memory computing unit includes: 6T-SRAM part and computing part.

[0038] 1. The 6T-SRAM part is a classic 6T-SRAM, which is provided with storage nodes Q and QB for reading, writing, and maintaining storage weight data Weight.

[0039] Specifically, the 6T-SRAM unit includes: 2 PMOS transistors P0~P1, 4 NMOS transistors N0~N3. P0 and N0 form an inverter, P1 and N1 form another inverter, and the two inverters are cross-coupled to form storage nodes Q and QB. Q is connected to the bit line BL through N2, and QB is connected to the bit line BLB through N3; the gates of N2 and N3 are connected to the word line WL; the sources of P0 and P1 are connected to the power supply VDD; the sources of N0 and N1 are connected to the ground VSS.

[0040] 2. The calculation part includes: 4 NMOS tubes N4~N7 and 1 capacitor C.

[0041] The gate of N4 is connected to Q, the source is connected to the input signal IN, and the drain is connected to the first end of C; the gate of N5 is connected to the control signal INN_E, the source is connected to QB, and the drain is connected to the first end of C; the gate of N6 is connected to IN, the source is connected to Q, and the drain is connected to the first end of C; the gate of N7 is connected to the control signal INN_EN, the source is grounded VSS, and the drain is connected to the first end of C; the second end of C is connected to the calculation bit line CBL.

[0042] Among them, IN represents input data Input.

[0043] The 10T1C-SRAM in-memory computing unit based on the above design provides three working modes, including: ① data storage mode, ② in-memory AND computing mode, and ③ in-memory XNOR computing mode.

[0044] It should be noted that if Figure 1 As shown, the 4 NMOS transistors of the calculation part are controlled by Q, INN_E, IN, and INN_EN respectively. Referring to the above record, Q represents the Weight stored in the 6T-SRAM part; IN represents Input.

[0045] In order to realize the above three working modes, INN_E and INN_EN need to follow certain timing control: INN_E and INN_EN can be independently controlled, or circuit design can be used to realize the associated control of IN, INN_E, and INN_EN.

[0046] In this embodiment 1, the IN, INN_E, and INN_EN association control method is adopted: INN_E and INN_EN are provided by the CTRL module. Figure 2 , the CTRL module includes: 2 inverters INV0~INV1, 2 AND gates AND0~AND1.

[0047] Specifically, the input terminal of INV0 is connected to IN, and the output terminal is connected to the control signal INN; the input terminal of INV1 is connected to the control signal E, and the output terminal is connected to the control signal EN; the input terminal 1 of AND0 is connected to INN, the input terminal 2 is connected to E, and the output terminal is connected to INN_E; the input terminal 1 of AND1 is connected to INN, the input terminal 2 is connected to EN, and the output terminal is connected to INN_EN. In this way, IN, E are associated with INN_E, INN_EN through the CTRL module.

[0048] Then, in this embodiment 1:

[0049] ① In data storage mode:

[0050] See also Figure 3 , IN=0 (N6 is off), E=0, so as to avoid input floating; INN_E=0 (N5 is off), INN_EN=1 (N7 is on), Q, QB are disconnected from the calculation part, the calculation part does not perform calculation and will not affect the 6T-SRAM part; the 6T-SRAM part performs data storage, which is exactly the same as the working mode of the classic 6T-SRAM storage unit, and will not be repeated here.

[0051] ② In the in-memory AND calculation mode:

[0052] It should be noted that IN=1 means Input=1, IN=0 means Input=0, Q=1 means Weight=1, and Q=0 means Weight=0.

[0053] Before performing the AND calculation in memory, a reset is required: E=0, IN=0 (N6 is off), so that INN_E=0 (N5 is off), INN_EN=1 (N7 is on), the first end of C is connected to VSS through N7, and the first end of C is reset to VSS; of course, Q and QB keep the values ​​stored in the last calculation, which may be Q=1, QB=0, or Q=0, QB=1: when Q=1, QB=0, N4 is on, and the first end of C is also connected to IN through N4 (0 at this time), which also has a pull-down effect; when Q=0, QB=1, N4 is off, and the first end of C is reset to VSS through N7.

[0054] When performing in-memory AND calculation, keep E=0; if IN=1 and Q=1, the first end of C is charged and the AND calculation result is 1; if IN=0 or Q=0, the first end of C is not charged and remains at VSS, and the AND calculation result is 0.

[0055] Specific:

[0056] like Figure 4 As shown, when performing in-memory AND calculation, E=0;

[0057] See also Figure 4 In area (a), when Input=1, Weight=1, IN=1, Q=1, INN=0, QB=0, INN_E=0, INN_EN=0, N4 is on, N5 is off, N6 is on, N7 is off, and the first end of C is charged to VDD' through N4 and N6 (due to threshold loss when NMOS tube transmits high level, VDD' is slightly lower than the power supply voltage VDD, but since the calculation part is composed of NMOS tube, it will not affect the calculation result), and the AND calculation result is 1;

[0058] See also Figure 4 In the (b) area, when Input=1, Weight=0, IN=1, Q=0, INN=0, QB=1, INN_E=0, INN_EN=0, N4 is off, N5 is off, N6 is on, N7 is off, the first end of C maintains VSS, and the AND calculation result is 0;

[0059] See also Figure 4 In the (c) area, when Input=0, Weight=1, IN=0, Q=1, INN=1, QB=0, INN_E=0, INN_EN=1, N4 is on, N5 is off, N6 is off, N7 is on, the first end of C maintains VSS, and the AND calculation result is 0;

[0060] See also Figure 4 In the (d) area, when Input=0, Weight=0, IN=0, Q=0, INN=1, QB=1, INN_E=0, INN_EN=1, N4 is off, N5 is off, N6 is off, N7 is on, the first end of C maintains VSS, and the AND calculation result is 0.

[0061] The truth table corresponding to the above in-memory AND calculation is shown in Table 1:

[0062] Table 1 Truth table of the in-memory AND calculation performed by the in-memory calculation unit of 10T1C-SRAM

[0063]

[0064] ③ In the in-memory XNOR calculation mode:

[0065] It should be noted that IN=1 means Input=1, IN=0 means Input=-1, Q=1 means Weight=1, and Q=0 means Weight=-1.

[0066] Similar to the in-memory AND calculation mode, a reset is required before performing the in-memory XNOR calculation: E=0, IN=0 (N6 is off), so that INN_E=0 (N5 is off), INN_EN=1 (N7 is on), the first end of C is connected to VSS through N7, and the first end of C is reset to VSS; of course, Q and QB keep the values ​​stored in the last calculation, which may be Q=1, QB=0, or Q=0, QB=1: when Q=1, QB=0, N4 is on, and the first end of C is also connected to IN through N4 (0 at this time), which is also a pull-down effect; when Q=0, QB=1, N4 is off, and the first end of C is reset to VSS through N7.

[0067] When performing an in-memory XNOR calculation, E=1; if IN=Q, the first end of C is charged and the XNOR calculation result is 1; if IN≠Q, the first end of C is not charged and remains at VSS, and the XNOR calculation result is -1.

[0068] Specifically,

[0069] like Figure 5 As shown, when performing in-memory XNOR calculation, E=1;

[0070] See also Figure 5 In area (a), when Input=1, Weight=1, IN=1, Q=1, INN=0, QB=0, INN_E=0, INN_EN=0, N4 is on, N5 is off, N6 is on, N7 is off, and the first end of C is charged to VDD' through N4 and N6 (due to threshold loss when NMOS tube transmits high level, VDD' is slightly lower than the power supply voltage VDD, but since the calculation part is composed of NMOS tubes, it will not affect the calculation result), and the XNOR calculation result is 1;

[0071] See also Figure 5 In the (b) area, when Input=1, Weight=-1, IN=1, Q=0, INN=0, QB=1, INN_E=0, INN_EN=0, N4 is off, N5 is off, N6 is on, N7 is off, the first end of C maintains VSS, and the XNOR calculation result is -1;

[0072] See also Figure 5 In the (c) area, when Input=-1, Weight=1, IN=0, Q=1, INN=1, QB=0, INN_E=1, INN_EN=0, N4 is on, N5 is on, N6 is off, N7 is off, the first end of C maintains VSS, and the XNOR calculation result is -1;

[0073] See also Figure 5In area (d), when Input=-1, Weight=-1, IN=0, Q=0, INN=1, QB=1, INN_E=1, INN_EN=0, N4 is off, N5 is on, N6 is off, N7 is off, the first end of C is charged to VDD' through N5, and the XNOR calculation result is 1.

[0074] It should be noted that in the above XNOR calculation results: 1 represents true, and -1 represents false.

[0075] The truth table corresponding to the above in-memory XNOR calculation is shown in Table 2:

[0076] Table 2 Truth table of the in-memory XNOR calculation performed by the in-memory calculation unit of 10T1C-SRAM

[0077]

[0078] Example 2

[0079] This embodiment 2 discloses a storage and calculation circuit constructed based on the 10T1C-SRAM in-memory calculation unit disclosed in embodiment 1.

[0080] like Figure 6 As shown, the storage and computing circuit constructed based on the 10T1C-SRAM in-memory computing unit includes: a storage and computing array and a peripheral control circuit.

[0081] The storage and computing array includes: M 10T1C-SRAM in-memory computing units as disclosed in Example 1 are distributed in an array.

[0082] The 10T1C-SRAM in-memory computing units in the same row share the same word line WL and the same CTRL module; the 10T1C-SRAM in-memory computing units in the same column share the same bit line BL, the same bit line BLB, and the same computing bit line CBL.

[0083] In the storage and calculation circuit, there are M CTRL modules and M CBLs; the M Es of the M CTRL modules are all global control signals CE, and the M INs are independently controlled; the M CBLs are connected to VSS through M reset NMOS tubes; the control ends of the M reset NMOS tubes are all connected to the reset signal Reset;

[0084] For details, see Figure 6 , the 10T1C-SRAM memory computing units in the mth row share the word line WL <m>, CTRL moduleCtrl m ;Ctrl m E is E <m>, which is connected to the global control signal CE; Ctrl m IN is IN <m>.

[0085] The computing units in the 10T1C-SRAM memory of the mth column share the bit line BL <m>, bit line BLB <m>, calculate the bit line CBL <m>。CBL <m>Through the mth reset NMOS tube Res m Connect to VSS. m The connection method is: Res m The gate is connected to Reset and the drain is connected to CBL <m>, the source is connected to VSS.

[0086] The peripheral control circuit is used to control the operation of the storage and calculation circuit. In this embodiment 2, the peripheral control circuit can be designed to include: a row decoder, a word line driver, a precharge circuit, a column selector, a sensitive amplifier, an analog-to-digital converter, and a timing controller. The row decoder is used to provide decoding results; the word line driver is used to control the opening or closing of each word line according to the decoding result; the precharge circuit is used to precharge the storage circuit; the column selector is used to cooperate with the word line drive to select any 10T1C-SRAM memory calculation unit in the storage and calculation array; the sensitive amplifier is used to read the weight data Weight stored in the selected 10T1C-SRAM memory calculation unit; the analog-to-digital converter is used to read the voltage of the mth CBL; the timing controller is used to perform timing control on various control signals. Of course, the peripheral control circuit can also be designed in other ways, but it should ensure that the present invention works normally.

[0087] Based on the above structure, the memory calculation circuit built on the 10T1C-SRAM memory calculation unit provides five working modes:

[0088] ① Data storage mode, ② In-memory AND computing mode, ③ In-memory XNOR computing mode, ④ In-memory 1b-AND MAC computing mode, ⑤ In-memory BNN computing mode.

[0089] In ① data storage mode, ② in-memory AND calculation mode, and ③ in-memory XNOR calculation mode, it is necessary to first use the peripheral control circuit to select any 10T1C-SRAM in-memory calculation unit in the storage and calculation array, and eliminate the interference of the 10T1C-SRAM in-memory calculation units in the same column. The subsequent control method refers to Example 1 and will not be repeated here.

[0090] ④ In the in-memory 1b-AND MAC calculation mode:

[0091] Before performing the in-memory 1b-AND MAC calculation, CE=0, M INs are all 0, the first end of C of all 10T1C-SRAM in-memory calculation units is reset to VSS, Reset=1, M reset NMOS tubes are turned on, and the second end of C of all 10T1C-SRAM in-memory calculation units is reset to VSS;

[0092] When performing in-memory 1b-AND MAC calculation, CE=0, the 10T1C-SRAM in-memory calculation unit is in the in-memory AND calculation mode, Reset=0, and the voltage of the mth CBL represents the 1b-AND MAC calculation result of the mth column 10T1C-SRAM in-memory calculation unit.

[0093] That is to say, if for a column of M 10T1C-SRAM in-memory computing units, the in-memory AND calculation results of n 10T1C-SRAM in-memory computing units are 1, then according to the capacitance coupling principle, the voltage of the CBL corresponding to the column is:

[0094] ;

[0095] That is, the calculation result of the in-memory 1b-AND MAC of the in-memory calculation unit of the column 10T1C-SRAM is n.

[0096] In order to more clearly show the calculation process of the in-memory 1b-AND MAC calculation mode, the following takes M=4 as a structural example, and takes one column and the four 10T1C-SRAM in-memory calculation units (CELL1~CELL4) of the column have been pre-stored with 1, 1, 0, 0 respectively, that is, the values ​​of Q1 (Q in CELL1), Q2 (Q in CELL2), Q3 (Q in CELL3), and Q4 (Q in CELL4) are 1, 1, 0, 0 respectively; the input IN of the four CTRL modules (Ctrl1~Ctrl4) corresponding to CELL1~CELL4 <1> , IN <2> , IN <3> , IN <4> 1, 0, 1, 0 respectively:

[0097] Before performing the in-memory 1b-AND MAC calculation, the circuit needs to be reset. At this time, CE=0, IN <1> =0,IN <2> =0,IN <3> =0,IN <4> =0, Reset=1, the first and second ends of the four capacitors C (C1~C4) in CELL1~CELL4 are reset to VSS, and the CBL of this column is pulled down to VSS to eliminate the influence of the last calculation.

[0098] like Figure 7 , Figure 8 As shown, when performing the in-memory 1b-AND MAC calculation, CELL1~CELL4 perform the in-memory AND calculation, and at this time Reset=0, CE=0;

[0099] In CELL1, Q1=1, that is, Weight=1, IN <1> =1, that is, Input=1, C1 is charged, the first end of C1 is VDD', that is, the AND calculation result in the memory of CELL1 is 1;

[0100] In CELL2, Q2=1, that is, Weight=1, IN <2> =0, that is, Input=0, C2 has no charging path, the first end of C2 maintains VSS, that is, the AND calculation result in the memory of CELL2 is 0;

[0101] In CELL3, Q3=0, that is, Weight=0, IN <3> =1, that is, Input=1, C3 has no charging path, the first end of C3 maintains VSS, that is, the AND calculation result in the memory of CELL3 is 0;

[0102] In CELL4, Q4=0, that is, Weight=0, IN <4> =0, that is, Input=0, C4 has no charging path, the first end of C4 maintains VSS, that is, the AND calculation result in the memory of CELL4 is 0;

[0103] According to the capacitive coupling between the four rows, the voltage of the column CBL is VDD' / 4, that is, the calculation result of the 1b-AND MAC in the column memory is 1.

[0104] In general, when M=4:

[0105] If the voltage of the CBL column is 0, the calculation result of the 1b-AND MAC in the column memory is 0;

[0106] If the voltage of the CBL column is VDD' / 4, the calculation result of the 1b-AND MAC in the column memory is 1;

[0107] If the voltage of the CBL column is VDD' / 2, the result of the 1b-AND MAC calculation in the column memory is 2;

[0108] If the voltage of the CBL column is 3VDD' / 4, the calculation result of the 1b-AND MAC in the column memory is 3;

[0109] If the voltage of the CBL column is VDD', the calculation result of the 1b-AND MAC in the column memory is 4.

[0110] Then, when M takes other values, the calculation process is similar and will not be repeated here.

[0111] ⑤ In the in-memory BNN computing mode:

[0112] Before performing in-memory BNN calculation, CE=0, M INs are all 0, the first terminals of C of all 10T1C-SRAM in-memory calculation units are reset to VSS, Reset=1, M reset NMOS tubes are turned on, and the second terminals of C of all 10T1C-SRAM in-memory calculation units are reset to VSS;

[0113] When performing in-memory BNN calculation, CE=1, the 10T1C-SRAM in-memory calculation unit is in the in-memory XNOR calculation mode, Reset=0, and the voltage of the mth CBL represents the in-memory BNN calculation result of the mth column 10T1C-SRAM in-memory calculation unit.

[0114] That is to say, if for a column of M 10T1C-SRAM in-memory computing units, the in-memory XNOR calculation results of n 10T1C-SRAM in-memory computing units are 1, then according to the capacitance coupling principle, the voltage of the CBL corresponding to the column is:

[0115] ;

[0116] That is, the in-memory BNN calculation result of the in-memory calculation unit of this column 10T1C-SRAM is n-(Mn).

[0117] In order to more clearly show the calculation process of the in-memory BNN calculation mode, the following takes M=4 as a structural example, and takes one column and the four 10T1C-SRAM in-memory calculation units (CELL1~CELL4) of the column have been pre-stored with 1, 1, 0, 0 respectively, that is, the values ​​of Q1 (Q in CELL1), Q2 (Q in CELL2), Q3 (Q in CELL3), and Q4 (Q in CELL4) are 1, 1, 0, 0 respectively; the input IN of the four CTRL modules (Ctrl1~Ctrl4) corresponding to CELL1~CELL4 <1> , IN <2> , IN <3> , IN <4> 1, 0, 1, 0 respectively:

[0118] Before performing the in-memory BNN calculation, the circuit needs to be reset. At this time, CE=0, IN <1> =0,IN <2> =0,IN <3> =0,IN <4> =0, Reset=1, the first and second ends of the four capacitors C (C1~C4) in CELL1~CELL4 are reset to VSS, and the CBL of this column is pulled down to VSS to eliminate the influence of the last calculation.

[0119] like Fig. 9 , Fig.10 As shown, when performing the in-memory BNN calculation, CELL1~CELL4 perform in-memory XNOR calculation, at this time Reset=0, CE=1;

[0120] In CELL1, Q1=1, that is, Weight=1, IN <1> =1, that is, Input=1, C1 is charged, the first end of C1 is VDD', that is, the XNOR calculation result in the memory of CELL1 is 1;

[0121] In CELL2, Q2=1, that is, Weight=1, IN <2> =0, that is, Input=-1, C2 has no charging path, the first end of C2 maintains VSS, that is, the XNOR calculation result in the memory of CELL2 is -1;

[0122] In CELL3, Q3=0, that is, Weight=-1, IN <3> =1, that is, Input=1, C3 has no charging path, the first end of C3 maintains VSS, that is, the XNOR calculation result in the memory of CELL3 is -1;

[0123] In CELL4, Q4=0, that is, Weight=-1, IN <4> =0, that is, Input=-1, C4 is charged, the first end of C4 is VDD', that is, the XNOR calculation result in the memory of CELL4 is 1;

[0124] According to the capacitive coupling between the four rows, the voltage of the column CBL is VDD' / 2, that is, the calculation result of the BNN in the column memory is 0.

[0125] In general, when M=4:

[0126] If the voltage of the CBL column is 0, the BNN calculation result in the column memory is -4;

[0127] If the voltage of the CBL column is VDD' / 4, the calculation result of the BNN in the column memory is -2;

[0128] If the voltage of the CBL column is VDD' / 2, the calculation result of the BNN in the column memory is 0;

[0129] If the voltage of the CBL column is 3VDD' / 4, the calculation result of the BNN in the column memory is 2;

[0130] If the voltage of the CBL column is VDD', the calculation result of the BNN in the column memory is 4.

[0131] Then, when M takes other values, the calculation process is similar and will not be repeated here.

[0132] Example 3

[0133] This embodiment 3 discloses an in-memory computing module based on 10T1C-SRAM, which adopts the layout of the memory computing circuit constructed based on the in-memory computing unit of 10T1C-SRAM as disclosed in embodiment 2. The mode of packaging into a module makes it easier to promote and apply the above circuit.

[0134] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0135] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.< / m> < / m> < / m> < / m> < / m> < / m> < / m> < / m>

Claims

1. A 10T1C-SRAM in-memory computing unit, characterized in that: include: 6T-SRAM part, which is provided with storage nodes Q and QB for reading, writing and maintaining storage weight data Weight; The calculation part includes: 4 NMOS tubes N4~N7, and 1 capacitor C; the gate of N4 is connected to Q, the source is connected to the input signal IN, and the drain is connected to the first end of C; the gate of N5 is connected to the control signal INN_E, the source is connected to QB, and the drain is connected to the first end of C; the gate of N6 is connected to IN, the source is connected to Q, and the drain is connected to the first end of C; the gate of N7 is connected to the control signal INN_EN, the source is grounded VSS, and the drain is connected to the first end of C; the second end of C is connected to the calculation bit line CBL; IN represents input data Input; The 10T1C-SRAM in-memory computing unit provides three working modes, including: data storage mode, in-memory AND computing mode, and in-memory XNOR computing mode; In the in-memory AND calculation mode: IN=1 means Input=1, IN=0 means Input=0, Q=1 means Weight=1, Q=0 means Weight=0; If IN=1 and Q=1, QB=0, INN_E=0, INN_EN=0, then the AND calculation result is 1; If IN=1 and Q=0, QB=1, INN_E=0, INN_EN=0, then the AND calculation result is 0; If IN=0 and Q=1, QB=0, INN_E=0, INN_EN=1, then the AND calculation result is 0; If IN=0 and Q=0, QB=1, INN_E=0, INN_EN=1, the AND calculation result is 0.

2. The 10T1C-SRAM in-memory computing unit according to claim 1, characterized in that: 6T-SRAM includes: 2 PMOS tubes P0~P1, 4 NMOS tubes N0~N3; P0 and N0 form an inverter, P1 and N1 form another inverter, and the two inverters are cross-coupled to form storage nodes Q and QB; Q is connected to the bit line BL through N2, and QB is connected to the bit line BLB through N3; the gates of N2 and N3 are connected to the word line WL; the sources of P0 and P1 are connected to the power supply VDD; and the sources of N0 and N1 are connected to the ground VSS.

3. The 10T1C-SRAM in-memory computing unit according to claim 2, characterized in that: INN_E and INN_EN are provided by the CTRL module; The CTRL module includes: 2 inverters INV0~INV1, 2 AND gates AND0~AND1; The input end of INV0 is connected to IN, and the output end is connected to the control signal INN; The input end of INV1 is connected to the control signal E, and the output end is connected to the control signal EN; The input terminal 1 of AND0 is connected to INN, the input terminal 2 is connected to E, and the output terminal is connected to INN_E; Input terminal 1 of AND1 is connected to INN, input terminal 2 is connected to EN, and output terminal is connected to INN_EN.

4. The 10T1C-SRAM in-memory computing unit according to claim 3, characterized in that: In data storage mode: IN=0, E=0, INN_E=0, INN_EN=1, the calculation unit does not perform calculations, and the 6T-SRAM unit stores data.

5. The 10T1C-SRAM in-memory computing unit according to claim 3, characterized in that: Before performing the AND calculation in memory, E=0, IN=0, and the first end of C is reset to VSS; When performing in-memory AND calculation, keep E=0; if IN=1 and Q=1, the first end of C is charged and the AND calculation result is 1; if IN=0 or Q=0, the first end of C is not charged and remains at VSS, and the AND calculation result is 0.

6. The 10T1C-SRAM in-memory computing unit according to claim 3, characterized in that: In in-memory XNOR calculation mode: IN=1 means Input=1, IN=0 means Input=-1, Q=1 means Weight=1, Q=0 means Weight=-1; Before performing the in-memory XNOR calculation, E=0, IN=0, and the first terminal of C is reset to VSS; When performing an in-memory XNOR calculation, E=1; if IN=Q, the first end of C is charged and the XNOR calculation result is 1; if IN≠Q, the first end of C is not charged and remains at VSS, and the XNOR calculation result is -1.

7. A storage and calculation circuit constructed based on a 10T1C-SRAM in-memory calculation unit, characterized in that: include: A storage and computing array, comprising: M*M 10T1C-SRAM in-memory computing units as described in any one of claims 1 to 6, distributed in an array; The 10T1C-SRAM memory computing units in the same row share the same word line WL and the same CTRL module; the 10T1C-SRAM memory computing units in the same column share the same bit line BL, the same bit line BLB, and the same computing bit line CBL; In the storage and calculation circuit, there are M CTRL modules and M CBLs; the M Es of the M CTRL modules are all global control signals CE, and the M INs are independently controlled; the M CBLs are connected to VSS through M reset NMOS tubes; the control ends of the M reset NMOS tubes are all connected to the reset signal Reset; as well as A peripheral control circuit, which is used to control the operation of the storage and calculation circuit; The memory computing circuit constructed based on the 10T1C-SRAM in-memory computing unit provides five working modes, including: data storage mode, in-memory AND computing mode, in-memory XNOR computing mode, in-memory 1b-AND MAC computing mode, and in-memory BNN computing mode.

8. The storage and calculation circuit constructed based on the 10T1C-SRAM in-memory calculation unit according to claim 7, characterized in that: In the in-memory 1b-AND MAC calculation mode: Before performing the in-memory 1b-AND MAC calculation, CE=0, M INs are all 0, the first end of C of all 10T1C-SRAM in-memory calculation units is reset to VSS, Reset=1, M reset NMOS tubes are turned on, and the second end of C of all 10T1C-SRAM in-memory calculation units is reset to VSS; When performing in-memory 1b-AND MAC calculation, CE=0, the 10T1C-SRAM in-memory calculation unit is in the in-memory AND calculation mode, Reset=0, and the voltage of the mth CBL represents the 1b-AND MAC calculation result of the mth column 10T1C-SRAM in-memory calculation unit.

9. The storage and calculation circuit constructed based on the 10T1C-SRAM in-memory calculation unit according to claim 7, characterized in that: In the in-memory BNN computing mode: Before performing in-memory BNN calculation, CE=0, M INs are all 0, the first terminals of C of all 10T1C-SRAM in-memory calculation units are reset to VSS, Reset=1, M reset NMOS tubes are turned on, and the second terminals of C of all 10T1C-SRAM in-memory calculation units are reset to VSS; When performing in-memory BNN calculation, CE=1, the 10T1C-SRAM in-memory calculation unit is in the in-memory XNOR calculation mode, Reset=0, and the voltage of the mth CBL represents the in-memory BNN calculation result of the mth column 10T1C-SRAM in-memory calculation unit.

10. The storage and calculation circuit constructed based on the 10T1C-SRAM in-memory calculation unit according to claim 7, characterized in that: The peripheral control circuit comprises: A row decoder, which is used to provide a decoding result; A word line driver, which is used to control the opening or closing of each word line according to the decoding result; A pre-charging circuit, used for pre-charging the storage circuit; A column selector, which is used to cooperate with the word line driver to select any 10T1C-SRAM in-memory computing unit in the memory computing array; A sensitive amplifier, which is used to read the weight data Weight stored in the selected 10T1C-SRAM memory calculation unit; an analog-to-digital converter, which is used to read the voltage of the mth CBL; as well as The timing controller is used to perform timing control on various control signals.

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