Chip storage module design verification method and non-transient computer readable storage medium

Abstract

A chip storage module design verification method and a non-transitory computer-readable storage medium can improve the voltage depression problem of a chip in the early stage of a chip process and are suitable for a chip storage module design including multiple storage units. The chip storage module design verification method includes: (a) generating a netlist based on multiple storage units; (b) performing a built-in self-test on the netlist to classify the multiple storage units into multiple built-in self-test groups; (c) performing a power analysis on the built-in self-test groups to obtain power values ​​corresponding to the built-in self-test groups under a process voltage temperature angle; (d) setting a conversion time and calculating multiple current values ​​based on the power value and the conversion time; (e) in response to at least one of the multiple current values ​​being greater than a current threshold value related to the chip storage module design, adjusting the logic design of the netlist and executing step (a) again; and (f) in response to the multiple current values ​​being equal to or less than the current threshold value, outputting the chip storage module design.

Description

Technical Field

[0001] The present application document relates to verification technology during chip memory module design, and more particularly to a chip memory module design verification method and a non-transitory computer-readable storage medium that can verify the chip memory module in the early stage of design. Background Art

[0002] With the development of high-performance computing and ultra-large integrated circuits, multiple chips may operate simultaneously in an electronic system to handle huge amounts of computing. However, when the system load changes rapidly (for example, multiple chips are started at the same time), the chip's operating voltage may undershoot, causing the chip to fail. In order to improve this phenomenon, the analysis of the chip's dynamic / static voltage drop (IR drop) has become one of the key acceptance items in the back-end of the chip process.

[0003] However, since the analysis of the dynamic / static voltage drop of the chip in traditional technology is performed at the back end of the chip process, even if the problem is found, the process has already been carried out to the later stage. In addition to the late discovery time, adjusting the physical design of the chip and repeating the chip process will also lead to low analysis efficiency. In addition, traditional technology also makes it difficult to analyze the dynamic / static voltage drop of multiple chips at the same time. Therefore, how to efficiently analyze multiple chips to overcome the problem of voltage undershoot is one of the topics in this field. Summary of the invention

[0004] The present application document provides a chip memory module (memory block) design verification method, which is applicable to the chip memory module design including multiple memory units (memory macros). The chip memory module design verification method comprises the following steps: (a) generating a netlist based on a plurality of memory cells by a computing circuit, wherein the netlist indicates the logic design of the plurality of memory cells; (b) performing a built-in self-test on the netlist by a computing circuit to classify the plurality of memory cells into a plurality of built-in self-test groups; (c) performing a power analysis on the plurality of built-in self-test groups by a computing circuit to obtain a plurality of power values ​​respectively corresponding to the plurality of built-in self-test groups under a process voltage temperature angle; (d) setting a conversion time by a computing circuit, and calculating a plurality of current values ​​according to the plurality of power values ​​and the conversion time; (e) in response to at least one of the plurality of current values ​​of the plurality of built-in self-test groups being greater than a current threshold, adjusting the logic design of the netlist by a computing circuit, and performing step (a) again, wherein the current threshold is related to the chip memory module design; and (f) in response to the plurality of current values ​​of the plurality of built-in self-test groups being equal to or less than the current threshold, outputting the chip memory module design by a computing circuit.

[0005] In some embodiments of the chip storage module design verification method, the chip storage module design verification method further includes the following steps: (g) in response to at least one of the multiple current values ​​of the multiple built-in self-test groups being greater than the current threshold, adjusting the physical design of the multiple memory cells.

[0006] In some embodiments of the chip memory module design verification method, the multiple current values ​​are multiple average current values ​​or multiple instantaneous current peak values ​​corresponding to multiple built-in self-test groups under process voltage and temperature angles and within a conversion time.

[0007] In some embodiments of the chip memory module design verification method, the step of classifying multiple memory cells into multiple built-in self-test groups includes: analyzing the respective functional frequencies of the multiple memory cells; and classifying multiple memory cells with the same functional frequency into one of the multiple built-in self-test groups.

[0008] In some embodiments of the chip memory module design verification method, in response to the one of the plurality of built-in self-test groups including more than one memory cell, the step of classifying the plurality of memory cells into the plurality of built-in self-test groups further includes: analyzing the respective test times and memory sizes of the plurality of memory cells in the one of the plurality of built-in self-test groups; and classifying the plurality of memory cells in the one of the plurality of built-in self-test groups into a plurality of built-in self-test sub-groups. The sum of the test times of at least one memory cell in each of the plurality of built-in self-test sub-groups is equal to each other, or the sum of the memory sizes of at least one memory cell in each of the plurality of built-in self-test sub-groups is equal to each other.

[0009] The present application document provides a non-transitory computer-readable storage medium storing a plurality of computer-readable instructions. When the plurality of computer-readable instructions are executed by one or more processors to verify a chip memory module design of a plurality of memory cells, the one or more processors are used to perform the following operations: (a) generate a netlist based on the plurality of memory cells through a computing circuit, wherein the netlist indicates a logic design of the plurality of memory cells; (b) perform a built-in self-test on the netlist through a computing circuit to classify the plurality of memory cells into a plurality of built-in self-test groups; (c) perform a power analysis on the plurality of built-in self-test groups through a computing circuit to obtain a plurality of power values ​​respectively corresponding to the plurality of built-in self-test groups under a process voltage temperature angle; (d) set a conversion time through a computing circuit, and calculate a plurality of current values ​​according to the plurality of power values ​​and the conversion time; (e) in response to at least one of the plurality of current values ​​of the plurality of built-in self-test groups being greater than a current threshold, adjust the logic design of the netlist through the computing circuit, and perform operation (a) again, wherein the current threshold is related to the chip memory module design; and (f) in response to the plurality of current values ​​of the plurality of built-in self-test groups being equal to or less than the current threshold, output the chip memory module design through the computing circuit.

[0010] In some embodiments of the non-transitory computer readable storage medium, the one or more processors are further configured to perform the following operations: (g) in response to at least one of the multiple current values ​​of the multiple built-in self-test groups being greater than a current threshold, adjusting the physical design of the multiple memory cells.

[0011] In some embodiments of the non-transitory computer readable storage medium, the multiple current values ​​are multiple average current values ​​or multiple instantaneous current peak values ​​respectively corresponding to multiple built-in self-test groups under process voltage temperature angles and within a conversion time.

[0012] In some embodiments of a non-transitory computer-readable storage medium, the operation of one or more processors to classify multiple memory cells into multiple built-in self-test groups includes: analyzing respective functional frequencies of the multiple memory cells; and classifying multiple memory cells having the same functional frequency into one of the multiple built-in self-test groups.

[0013] In some embodiments of the non-transitory computer-readable storage medium, in response to more than one memory cell included in the one of the plurality of built-in self-test groups, the one or more processors classifying the plurality of memory cells into the plurality of built-in self-test groups further comprises: analyzing respective test times and memory sizes of the plurality of memory cells in the one of the plurality of built-in self-test groups; and classifying the plurality of memory cells in the one of the plurality of built-in self-test groups into a plurality of built-in self-test sub-groups. The sum of the test times of at least one memory cell in each of the plurality of built-in self-test sub-groups is equal to each other, or the sum of the memory sizes of at least one memory cell in each of the plurality of built-in self-test sub-groups is equal to each other.

[0014] Through the chip storage module design verification method and non-transitory computer-readable storage medium of this application document, multiple chips can be grouped and analyzed at the same time, and the chip storage module design can be adjusted in the early stage of the chip process, thereby improving the chip voltage undershoot problem and improving the verification efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to make the above and other objects, features, advantages and embodiments of the present disclosure more clearly understood, the accompanying drawings are described as follows:

[0016] Figure 1 A flowchart of a chip storage module design verification method according to some embodiments of the present application document;

[0017] Figure 2A A schematic diagram of classifying a plurality of storage units according to some embodiments of the present application document;

[0018] Figure 2B A schematic diagram of classifying a plurality of storage units according to some other embodiments of the present application document;

[0019] Figure 2C A schematic diagram of classifying a plurality of storage units according to yet other embodiments of the present application document;

[0020] Figure 3 FIG. 4 is a schematic diagram of analyzing whether a built-in self-test group has a voltage undershoot risk according to some embodiments of the present application.

[0021]

Explanation of symbols

[0022] 100: Chip storage module design verification method

[0023] S110,S120,S130,S140 : Steps

[0024] S150,S160,S170 : Steps

[0025] M1~M7: Storage unit

[0026] G1~G3: Built-in self-test group

[0027] G1'~G3': Built-in self-test subgroup DETAILED DESCRIPTION

[0028] The embodiments of the present application document will be described below with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals represent the same or similar elements or method flows.

[0029] In this application document, when an element is referred to as "connected", it may refer to "electrical connection" or "optical connection", and when an element is referred to as "coupled", it may refer to "electrical coupling" or "optical coupling". "Connected" or "coupled" can also be used to indicate the coordinated operation or interaction between two or more elements. Unless the article is specifically limited in the text, "one" and "the" may refer to a single or multiple. It will be further understood that the "comprising", "including", "having" and similar words used in this document specify the features, regions, integers, steps, operations, elements and / or components recorded therein, but do not exclude the one or more other features, regions, integers, steps, operations, elements, components and / or groups thereof described or additional thereto.

[0030] Figure 1 The flowchart of a chip memory block design verification method 100 is shown according to some embodiments of the present application document. The chip memory block design verification method 100 is applicable to a chip memory module design, wherein the chip memory module design includes a plurality of memory macros. In some embodiments, the chip memory module design verification method 100 includes steps S110, S120, S130, S140, S150, S160, and S170.

[0031] In step S110, a netlist is generated based on a plurality of storage cells by a computing circuit (or computing device). The netlist indicates the logic design of the plurality of storage cells (eg, the connection relationship between the plurality of storage cells). After step S110 is completed, step S120 is executed.

[0032] In step S120, a built-in self-test (BIST) is performed on the netlist by a computing circuit to classify the plurality of memory cells into a plurality of BIST groups. The detailed operation of classifying the plurality of memory cells in step S120 will be described in detail in the following paragraphs.

[0033] Figure 2A FIG. 1 is a schematic diagram of classifying the storage units M1 to M7 in step S120 according to some embodiments of the present application document. Figure 2A In an embodiment of the present invention, the memory cells are classified according to their respective functional frequencies. Specifically, first, the functional frequency of each memory cell is analyzed. Then, the memory cells with the same functional frequency are classified into the same built-in self-test group.

[0034] by Figure 2A As an example, first, after analysis, the functional frequency of the storage units M1 to M7 (in Figure 2A Then, the memory cells M1, M3, and M6 with a functional frequency of 1000 are classified into the built-in self-test group G1, the memory cells M2 and M7 with a functional frequency of 1500 are classified into the built-in self-test group G2, and the memory cells M4 and M5 with a functional frequency of 3000 are classified into the built-in self-test group G3.

[0035] In some embodiments, memory cells with the same functional frequency in a BIST group are further classified. Figure 2B FIG. 1 is a schematic diagram of classifying the storage units M1 to M7 in step S120 according to some other embodiments of the present application document. Figure 2B In the embodiment of the present invention, the memory cells M1 to M7 have the same functional frequency, and therefore are further classified according to their respective test times. Specifically, first, the test time of each memory cell is analyzed. Then, the sum of all test times is calculated, and the average test time allocated to each built-in self-test subgroup is calculated based on the number of built-in self-test subgroups used in the built-in self-test group. Finally, the memory cells are classified into built-in self-test subgroups in the same built-in self-test group based on the average test time, so that the sum of the test time of the memory cells in each built-in self-test subgroup is close to the average test time. In other words, the sum of the test time of the memory cells in each built-in self-test subgroup will be close to each other. In some embodiments, the memory cells classified into the same built-in self-test subgroup are close to each other in physical position to improve the robustness of the operating voltage, thereby avoiding the problem of undershoot of the operating voltage.

[0036] by Figure 2B As an example, the memory cells M1 to M7 have the same functional frequency. First, after analysis, the test time of the memory cells M1 to M7 (in Figure 2BThe test time of all memory cells is 5ms. Figure 2B In the embodiment, since the memory cells M1-M7 are divided into three BIST subgroups, it can be known that the average test time of each BIST subgroup should be the total test time divided by three (i.e., about 1.67ms). Then, the memory cells M1 and M2 are classified into the BIST subgroup G1', so that the total test time of the BIST subgroup G1' is 1.67ms; the memory cells M3 and M7 are classified into the BIST subgroup G2', so that the total test time of the BIST subgroup G2' is 1.67ms; and the memory cells M4, M5, and M6 are classified into the BIST subgroup G3', so that the total test time of the BIST subgroup G3' is about 1.67ms.

[0037] As mentioned above, in some embodiments, memory cells with the same functional frequency in a BIST group are further classified. Figure 2C FIG. 1 is a schematic diagram of classifying the storage units M1 to M7 in step S120 according to yet other embodiments of the present application document. Figure 2C In an embodiment, the memory cells M1-M7 have the same functional frequency, and thus are further classified according to their respective memory sizes. Specifically, first, the memory size of each memory cell is analyzed. Then, the memory cells are classified into built-in self-test subgroups in the same built-in self-test group according to the memory size, so that the sum of the memory sizes of the memory cells in each built-in self-test subgroup is approximately the same. In some embodiments, the memory cells classified into the same built-in self-test subgroup are physically close to each other to improve the robustness of the operating voltage, thereby avoiding the problem of undershoot of the operating voltage.

[0038] by Figure 2CFor example, the memory cells M1-M7 have the same functional frequency. First, after analysis, the memory sizes of the memory cells M1-M7 are 10 units, 8 units, 5 units, 9 units, 15 units, 8 units, and 20 units, respectively, where "unit" is "K byte". Then, the memory cells M1 and M5 are classified into the built-in self-test subgroup G1', so that the total memory size of the built-in self-test subgroup G1' is 25 units; the memory cells M2, M4, and M6 are classified into the built-in self-test subgroup G2', so that the total memory size of the built-in self-test subgroup G2' is 25 units; and the memory cells M3 and M7 are classified into the built-in self-test subgroup G3', so that the total memory size of the built-in self-test subgroup G3' is about 25 units. In this way, the total memory sizes of the built-in self-test subgroups G1', G2', and G3' are equal to each other.

[0039] It should be noted that FIG. 2A to FIG. 2C The number of memory cells, built-in self-test groups, and built-in self-test subgroups is only an example and is not intended to limit the present application. Other numbers of memory cells, built-in self-test groups, and built-in self-test subgroups are within the scope of the present application. In some embodiments, a chip memory module design may include more than seven or less than seven memory cells, and these memory cells may be configured as follows: FIG. 2A to FIG. 2C The described functional frequencies, test times, or memory sizes are categorized into more than three or less than three built-in self-test groups, or more than three or less than three built-in self-test sub-groups.

[0040] Please refer again Figure 1 After step S120 is completed, step S130 is executed. In step S130, the operation circuit performs power analysis on the multiple built-in self-test groups classified in step S120 to obtain multiple power values ​​corresponding to the built-in self-test groups at different process voltage temperature corners (PVT corners, PVT corners) (for example, WC corner, TT corner, ML corner, etc.). After step S130 is completed, step S140 is executed.

[0041] In step S140, the operation circuit sets a switching time, and calculates a plurality of corresponding current values ​​according to the plurality of power values ​​and the switching time calculated in step S130. Specifically, the "current value" described above may represent an average current value of the built-in self-test group during the switching time, or may represent an instantaneous current peak value reached by the built-in self-test group during the switching time.

[0042] Specifically, the instantaneous current value can be obtained from the following formula:

[0043] dI(t) / dt=Ipeak*w*cos(wt)

[0044] Where dI(t) / dt is the instantaneous current value, Ipeakt is the instantaneous current peak value, and w is the angular velocity.

[0045] When cos(wt) is equal to 1, the maximum instantaneous current value can be obtained as: (dI(t) / dt)max=Ipeak*w=Ipeak*(2Л / T), where T is the conversion time.

[0046] Next, the average current value (Irms) and the instantaneous current peak value (Ipeak) can be calculated according to the following formula:

[0047] P=V * Irms

[0048] Irms=Ipeak / √2

[0049] P=V * (Ipeak / √2)

[0050] Ipeak=(P * √2) / V

[0051] Where P is the power value and V is the operating voltage.

[0052] When the multiple current values ​​calculated in step S140 are all equal to or less than a current threshold, step S150 is then executed. In step S150, the operation circuit determines that all the classified built-in self-test groups are not risky (i.e., the average current value and the instantaneous current peak value generally do not exceed the current threshold), and thus outputs the chip memory module design of the multiple memory cells.

[0053] In some embodiments, the magnitude of the current threshold can be set by the arithmetic circuit described above according to the design specifications of the chip memory module.

[0054] On the other hand, when at least one of the multiple current values ​​calculated in step S140 is greater than the current threshold, the operation circuit determines that there is a risk in the built-in self-test group (that is, the average current value and the instantaneous current peak value will exceed the current threshold under certain circumstances), and therefore the chip storage module design needs to be adjusted to avoid voltage undershoot.

[0055] Figure 3 FIG. 1 is a schematic diagram of analyzing whether the built-in self-test group G1 has a voltage undershoot risk according to some embodiments of the present application document. Figure 3In the embodiment, through the steps S130 and S140 of the chip memory module design verification method 100, the power value and instantaneous current peak value of the built-in self-test group G1 at different PVT angles (i.e., the WC angle, the TT angle, and the ML angle in the figure) can be calculated. Since the instantaneous current peak value (5.039 amperes) of the built-in self-test group G1 at the ML angle is greater than the set current threshold (5 amperes), the built-in self-test group G1 is judged to have a risk.

[0056] It should be noted that Figure 3 The number and type of PVT angles in the present application are only examples and are not intended to limit the present application. Other numbers and other types of PVT angles are within the scope of the present application. In addition, the types and technical contents of "PVT angles" in the present application are obvious to those with ordinary knowledge in the art, so the technical contents will not be repeated in the present application.

[0057] Please refer again Figure 1 As described above, when at least one of the multiple current values ​​calculated in step S140 is greater than the current threshold, the operation circuit determines that the chip memory module design needs to be adjusted. At this time, step S160 or step S170 will be executed according to the adjustment method of the chip memory module design.

[0058] In step S160, the operation circuit determines the logic design of the adjusted netlist. Since the adjustment of the logic design of the netlist is implemented in the early stage of the chip process, the adjusted netlist can be verified again. Therefore, after step S160 is completed, step S110 will be executed again to verify whether the adjusted chip memory module design meets the requirements.

[0059] On the other hand, in step S170, the operation circuit determines to adjust the physical design of the memory cell, and this physical design will be adjusted in the later stage of the chip process. Through steps S160 and S170, the chip memory module design verification method 100 can realize two ways of adjusting the chip memory module design in the early stage or the later stage of the chip process.

[0060] It should be noted that the number and order of the steps in the chip memory module design verification method 100 of the present application document are only examples and are not intended to limit the present application document. The number and order of other steps are within the scope of the present application document. In some embodiments, step S170 can be omitted, so when at least one of the multiple current values ​​calculated in step S140 is greater than the current threshold, step S160 will be directly executed.

[0061] The present application document provides a non-transitory computer-readable storage medium storing a plurality of computer-readable instructions. When the computer-readable instructions are executed by one or more processors, the one or more processors are used to execute the chip storage module design verification method 100 described above. In some embodiments, the non-transitory computer-readable storage medium may be an electronic, magnetic, optical, electromagnetic, infrared and / or semiconductor system (or device or apparatus). For example, the non-transitory computer-readable storage medium includes a semiconductor or solid-state memory, a magnetic tape, a disk, a random access memory (RAM), a read-only memory (ROM), a hard disk and / or an optical disk. In some embodiments using optical disks, the non-transitory computer-readable storage medium includes a read-only optical disk (Compact Disk-Read Only Memory, CD-ROM), a read-write optical disk (Compact Disk-Read / Write, CD-R / W) and / or a digital video disc (Digital Video Disc, DVD).

[0062] Through the chip storage module design verification method 100 and the non-transitory computer readable storage medium of the present application document, multiple chips in the electronic system can be grouped and current analyzed at the same time to prevent the chip from having voltage undershoot problems. In addition, since the chip storage module design verification method 100 of the present application document adjusts the chip storage module design in the early stage of the chip process, the efficiency of verification and adjustment can also be improved.

[0063] The above are only preferred embodiments of the present application. Without departing from the scope or spirit of the present application, the structure of the present application can be modified and equivalently changed. In summary, all modifications and equivalent changes made to the present application within the scope of the following claims are within the scope of the present application.

Claims

1. A chip storage module design verification method, characterized in that: The present invention is applicable to the design of a chip memory module including a plurality of memory cells. The chip memory module design verification method comprises the following steps: (a) generating a netlist based on the plurality of memory cells by a computing circuit, wherein the netlist indicates a logic design of the plurality of memory cells; (b) performing a built-in self-test on the netlist by the operation circuit to classify the plurality of memory cells into a plurality of built-in self-test groups; (c) performing a power analysis on the plurality of built-in self-test groups by the computing circuit to obtain a plurality of power values ​​respectively corresponding to the plurality of built-in self-test groups at a process voltage temperature angle; (d) setting a conversion time by the calculation circuit, and calculating a plurality of current values ​​according to the plurality of power values ​​and the conversion time; (e) in response to at least one of the plurality of current values ​​of the plurality of built-in self-test groups being greater than a current threshold, adjusting the logic design of the netlist by the operation circuit, and performing step (a) again, wherein the current threshold is related to the chip memory module design; as well as (f) In response to the multiple current values ​​of the multiple built-in self-test groups being equal to or less than the current threshold, outputting the chip memory module design through the operation circuit.

2. The chip storage module design verification method according to claim 1, characterized in that: Further comprising the following steps: (g) In response to at least one of the plurality of current values ​​of the plurality of built-in self-test groups being greater than the current threshold, adjusting a physical design of the plurality of memory cells.

3. The chip storage module design verification method according to claim 1, characterized in that: The multiple current values ​​are multiple average current values ​​or multiple instantaneous current peak values ​​respectively corresponding to the multiple built-in self-test groups at the process voltage temperature angle and within the conversion time.

4. The chip storage module design verification method according to claim 1, characterized in that: The step of classifying the plurality of storage units into the plurality of built-in self-test groups comprises: analyzing a functional frequency of each of the plurality of memory cells; and The plurality of memory cells having the same functional frequency are classified into one of the plurality of built-in self-test groups.

5. The chip storage module design verification method according to claim 4, characterized in that: In response to the one of the plurality of built-in self-test groups including more than one memory cell, the step of classifying the plurality of memory cells into the plurality of built-in self-test groups further comprises: analyzing a test time and a memory size of each of the plurality of memory cells in the one of the plurality of built-in self-test groups; and classifying the plurality of memory cells in the one of the plurality of built-in self-test groups into a plurality of built-in self-test sub-groups, A sum of the test time of at least one memory cell in each of the plurality of BIST subgroups is equal to one another, or a sum of the memory size of at least one memory cell in each of the plurality of BIST subgroups is equal to one another.

6. A non-transitory computer-readable storage medium, characterized in that: A plurality of computer-readable instructions are stored. When the plurality of computer-readable instructions are executed by one or more processors to verify a chip memory module design of a plurality of memory cells, the one or more processors are used to perform the following operations: (a) generating a netlist based on the plurality of memory cells, wherein the netlist indicates a logical design of the plurality of memory cells; (b) performing a built-in self-test on the netlist to classify the plurality of memory cells into a plurality of built-in self-test groups; (c) performing a power analysis on the plurality of built-in self-test groups to obtain a plurality of power values ​​respectively corresponding to the plurality of built-in self-test groups at a process voltage-temperature angle; (d) setting a conversion time, and calculating a plurality of current values ​​according to the plurality of power values ​​and the conversion time; (e) in response to at least one of the plurality of current values ​​of the plurality of built-in self-test groups being greater than a current threshold, adjusting the logic design of the netlist and performing operation (a) again, wherein the current threshold is related to the chip memory module design; as well as (f) In response to the multiple current values ​​of the multiple built-in self-test groups being equal to or less than the current threshold, outputting the chip memory module design.

7. The non-transitory computer-readable storage medium of claim 6, wherein: The one or more processors are further configured to perform the following operations: (g) In response to at least one of the plurality of current values ​​of the plurality of built-in self-test groups being greater than the current threshold, adjusting a physical design of the plurality of memory cells.

8. The non-transitory computer-readable storage medium of claim 6, wherein: The multiple current values ​​are multiple average current values ​​or multiple instantaneous current peak values ​​respectively corresponding to the multiple built-in self-test groups at the process voltage temperature angle and within the conversion time.

9. The non-transitory computer-readable storage medium of claim 6, wherein: The operation of the one or more processors classifying the plurality of storage units into the plurality of built-in self-test groups includes: analyzing a functional frequency of each of the plurality of memory cells; and The plurality of memory cells having the same functional frequency are classified into one of the plurality of built-in self-test groups.

10. The non-transitory computer-readable storage medium of claim 9, wherein: In response to the one of the plurality of built-in self-test groups including more than one storage unit, the one or more processors classify the plurality of storage units into the plurality of built-in self-test groups further comprising: analyzing a test time and a memory size of each of the plurality of memory cells in the one of the plurality of built-in self-test groups; and classifying the plurality of memory cells in the one of the plurality of built-in self-test groups into a plurality of built-in self-test sub-groups, A sum of the test time of at least one memory cell in each of the plurality of BIST subgroups is equal to one another, or a sum of the memory size of at least one memory cell in each of the plurality of BIST subgroups is equal to one another.

Images