Post-simulation time sequence check file generation method
Through the collaborative work of the post-simulation timing violation inspection system and the mail system, the standard post-simulation timing inspection file is generated, which solves the problem of slow and inaccurate generation of post-simulation timing inspection files, and improves the iteration speed and the efficiency of result confirmation.
Patent Information
- Application Number
- CN202411360551.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-27
- Publication Date
- 2025-01-14
AI Technical Summary
The post-simulation timing check file generation speed is slow and inaccurate, resulting in low efficiency in manual confirmation and writing timing check file, affecting the iteration speed and result accuracy.
The simulation log file is generated through simulation software, and the simulation timing violation check system is checked after loading, the timing violation information is counted, the time interval and keyword matching is configured, the excel file is generated, the mail system is marked and merged, and the standard simulation timing inspection file is finally generated.
It significantly accelerates the convergence speed of timing check file generation, shortens the confirmation time of post-simulation results, and improves chip development efficiency.
Smart Images
Figure CN119312746A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of digital integrated circuit verification, and in particular relates to a method for generating a post-simulation timing check file. Background Art
[0002] As the scale of digital chips continues to increase, chip verification is becoming increasingly important in the entire chip development process. Faced with the increasing pressure to go to market, the project team is faced with how to shorten the verification time and improve the verification efficiency. Digital chip verification includes two parts: pre-simulation and post-simulation. Pre-simulation is mainly used to verify the correctness of circuit design, and only considers the circuit logic relationship and signal transmission. Post-simulation verification is an important part of digital chip verification. Its main purpose is to perform software simulation on the actual performance of the chip after the physical layout of the chip. Post-simulation focuses on the actual performance of the chip under specific processes and layouts, including timing, power consumption, temperature, etc. Post-simulation can simulate the behavior of the chip under actual working conditions using comprehensive back-gate-level simulation, providing a basis for chip optimization and debugging. Post-simulation needs to consider the impact of physical factors on chip performance, so it is relatively slower than pre-simulation.
[0003] However, the results of post-simulation have added timing violation check information compared to pre-simulation, so the log files generated during the post-simulation iteration are generally very large. It is not only time-consuming and laborious for verification engineers to confirm and analyze each timing violation and write timing check files, but omissions often occur. Chip verification engineers and design engineers need to jointly confirm and communicate the results of each post-simulation timing violation, and there is currently no unified annotation file format. In addition, the inefficiency of manually merging timing check files will also affect the speed of each post-simulation iteration. Summary of the invention
[0004] The purpose of the present invention is to provide a method for generating a post-simulation timing check file, which solves the problem of slow and inaccurate generation of the post-simulation timing check file in the prior art.
[0005] The technical solution adopted by the present invention is a method for generating a post-simulation timing check file, which specifically comprises the following steps:
[0006] Step 1, use simulation software to generate a simulation log file, and load the simulation log file into a post-simulation timing violation check system;
[0007] Step 2, the target information of the type and total number of timing violations in the post-simulation timing violation check system statistical log file is sent to the filter;
[0008] Step 3: Configure the time interval, simulation time accuracy and target keyword in the filter. The filter performs keyword matching. After matching, the timing paths are merged, and the effective target information of the final violation types and total number is counted. The effective target information is delivered to the mail system in the specified Excel file format for processing.
[0009] Step 4: The mail system annotates the Excel file, and loads the annotated Excel file into the standard merge unit for processing and post-simulation iteration to generate a standard post-simulation timing check file.
[0010] The present invention is also characterized in that:
[0011] The target information in step 2 includes the timing violation setup time, hold time, width time, glitch time, and recrem time.
[0012] In step 3, the time interval configured is arbitrarily selected from 0 to the end time of the simulation; the simulation time accuracy includes fs, ps, ns and us.
[0013] The keyword matching in step 3 includes matching relevant module keywords and eliminating irrelevant module keywords.
[0014] The excel file format in step 3 includes the project name, code version information, violation information list and violation information confirmation column.
[0015] The specific process of step 3 is: configure the time interval, simulation time accuracy and target keyword in the filter, the filter performs keyword matching, and the information of the violation type and total number after the matching is completed is sent to the filter merging unit. After receiving the information, the filter merging unit merges and classifies the timing violation register paths, and counts the valid target information of the final violation type and total number after the merger, and delivers the valid target information to the mail system for processing in the specified Excel file format.
[0016] The specific process of step 4 is: the mail system marks the Excel file, and loads the marked Excel file into the standard merging unit for processing, generates a standard check file for subsequent post-simulation iterations, and merges the standard check files generated by different batches of post-simulation to generate a post-simulation timing check file.
[0017] The beneficial effects of the present invention are:
[0018] The post-simulation timing check file generation method provided by the present invention solves the problems of slow speed and easy omissions in manually checking post-simulation timing violations and manually writing check files. The iterative process of timing check file generation can be traced through the email system, and the convergence speed of the final version of the timing check file generation is significantly accelerated, which greatly shortens the confirmation time of the post-simulation results and the post-simulation time, and effectively reduces the chip development process. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] Figure 1 It is a flow chart of the method for generating a post-simulation timing check file of the present invention. DETAILED DESCRIPTION
[0020] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments.
[0021] Example 1
[0022] The post-simulation timing check file generation method proposed in this embodiment is as follows: Figure 1 As shown, the specific steps include:
[0023] Step 1, use simulation software to generate a simulation log file, and load the simulation log file into a post-simulation timing violation check system;
[0024] Step 2, the target information of the type and total number of timing violations in the post-simulation timing violation check system statistical log file is sent to the filter;
[0025] Step 3: Configure the time interval, simulation time accuracy and target keyword in the filter. The filter performs keyword matching. After matching, the timing paths are merged, and the effective target information of the final violation types and total number is counted. The effective target information is delivered to the mail system in the specified Excel file format for processing.
[0026] Step 4: The mail system annotates the Excel file, and loads the annotated Excel file into the standard merge unit for processing and post-simulation iteration to generate a standard post-simulation timing check file.
[0027] Example 2
[0028] The post-simulation timing check file generation method proposed in this embodiment is as follows: Figure 1 As shown, the specific steps include:
[0029] Step 1, use simulation software to generate a simulation log file, and load the simulation log file into a post-simulation timing violation check system;
[0030] Step 2, the target information of the type and total number of timing violations in the post-simulation timing violation check system statistical log file is sent to the filter;
[0031] The target information includes timing violation setup time, hold time, width time, glitch time and recrem time;
[0032] Step 3: Configure the time interval, simulation time accuracy and target keyword in the filter. The filter performs keyword matching. After matching, the timing paths are merged, and the effective target information of the final violation types and total number is counted. The effective target information is delivered to the mail system in the specified Excel file format for processing.
[0033] The configuration time interval can be arbitrarily selected from 0 to the end of the simulation; the simulation time accuracy includes fs, ps, ns and us;
[0034] Keyword matching includes matching relevant module keywords and eliminating irrelevant module keywords;
[0035] The excel file format includes the project name, code version information, violation information list and violation information confirmation column;
[0036] Step 4: The mail system annotates the Excel file, and loads the annotated Excel file into the standard merge unit for processing and post-simulation iteration to generate a standard post-simulation timing check file.
[0037] Example 3
[0038] The post-simulation timing check file generation method proposed in this embodiment is as follows: Figure 1 As shown, the specific steps include:
[0039] Step 1, use simulation software to generate a simulation log file, and load the simulation log file into a post-simulation timing violation check system;
[0040] Step 2, the target information of the type and total number of timing violations in the post-simulation timing violation check system statistical log file is sent to the filter;
[0041] The target information includes timing violation setup time, hold time, width time, glitch time and recrem time;
[0042] Step 3: Configure the time interval, simulation time accuracy and target keyword in the filter. The filter performs keyword matching. After matching, the timing paths are merged, and the effective target information of the final violation types and total number is counted. The effective target information is delivered to the mail system in the specified Excel file format for processing.
[0043] The configuration time interval can be arbitrarily selected from 0 to the end of the simulation; the simulation time accuracy includes fs, ps, ns and us;
[0044] Keyword matching includes matching relevant module keywords and eliminating irrelevant module keywords;
[0045] The excel file format includes the project name, code version information, violation information list and violation information confirmation column;
[0046] The specific process of step 3 is as follows: configure the time interval, simulation time accuracy and target keyword in the filter, the filter performs keyword matching, and the information of the violation type and total number after matching is sent to the filter merging unit. After receiving the information, the filter merging unit merges and classifies the timing violation register paths, and counts the valid target information of the final violation type and total number after merging, and delivers the valid target information to the mail system for processing in the specified Excel file format;
[0047] Step 4: The mail system annotates the Excel file, and loads the annotated Excel file into the standard merge unit for processing and post-simulation iteration to generate a standard post-simulation timing check file.
[0048] Example 4
[0049] The post-simulation timing check file generation method proposed in this embodiment is as follows: Figure 1 As shown, the specific steps include:
[0050] Step 1, use simulation software to generate a simulation log file, and load the simulation log file into a post-simulation timing violation check system;
[0051] Step 2, the target information of the type and total number of timing violations in the post-simulation timing violation check system statistical log file is sent to the filter;
[0052] The target information includes timing violation setup time, hold time, width time, glitch time and recrem time;
[0053] Step 3: Configure the time interval, simulation time accuracy and target keyword in the filter. The filter performs keyword matching. After matching, the timing paths are merged, and the effective target information of the final violation types and total number is counted. The effective target information is delivered to the mail system in the specified Excel file format for processing.
[0054] The configuration time interval can be arbitrarily selected from 0 to the end of the simulation; the simulation time accuracy includes fs, ps, ns and us;
[0055] Keyword matching includes matching relevant module keywords and eliminating irrelevant module keywords;
[0056] The excel file format includes the project name, code version information, violation information list and violation information confirmation column;
[0057] The specific process of step 3 is as follows: configure the time interval, simulation time accuracy and target keyword in the filter, the filter performs keyword matching, and the information of the violation type and total number after matching is sent to the filter merging unit. After receiving the information, the filter merging unit merges and classifies the timing violation register paths, and counts the valid target information of the final violation type and total number after merging, and delivers the valid target information to the mail system for processing in the specified Excel file format;
[0058] Step 4: The mail system annotates the Excel file, and loads the annotated Excel file into the standard merge unit for processing and post-simulation iteration to generate a standard post-simulation timing check file;
[0059] The specific process of step 4 is: the mail system marks the Excel file, and loads the marked Excel file into the standard merging unit for processing, generates a standard check file for subsequent post-simulation iterations, and merges the standard check files generated by different batches of post-simulation to generate a post-simulation timing check file.
[0060] Example 5
[0061] The post-simulation timing check file generation method proposed in this embodiment is as follows: Figure 1 As shown, the specific steps include:
[0062] Step 1: Use mainstream verification simulation software to load the netlist and SDF file for post-simulation, generate a simulation log file, and load the simulation log file into the post-simulation timing violation check system;
[0063] Step 2, a post-simulation timing violation statistics unit is designed in the post-simulation timing violation checking system by using Python language, and the post-simulation timing violation statistics unit retrieves the target information of the timing violation types and total number in the log file and sends it to the filter;
[0064] The target information includes timing violation setup time, hold time, width time, glitch time and recrem time;
[0065] Step 3: Input the time interval, simulation time accuracy and target keywords in the user graphical interface of the filter through the tkinter module of Python. The filter performs keyword matching, matches the valid target information and removes the non-interest target information. After the matching is completed, the information of the violation type and total number is sent to the filter merging unit. After receiving the information, the filter merging unit merges and classifies the timing violation register paths, and counts the valid target information of the final violation type and total number after the merger, and delivers the valid target information to the mail system in the specified Excel file format for processing;
[0066] The configuration time interval can be arbitrarily selected from 0 to the end of the simulation; the simulation time accuracy includes fs, ps, ns and us;
[0067] Keyword matching includes matching relevant module keywords and eliminating irrelevant module keywords;
[0068] The excel file format includes the project name, code version information, violation information list and violation information confirmation column;
[0069] Step 4: The email system sends an Excel file containing violation information to the designated designer for confirmation, which is implemented using the smtplib and email modules in Python;
[0070] The mail system annotates the Excel file and loads the annotated Excel file into the standard merging unit for processing. The standard merging unit is implemented by executing the jar file through the Java virtual machine to generate a standard check file for subsequent post-simulation iterations. The standard check files generated by different batches of post-simulation are merged to generate a post-simulation timing check file; the post-simulation timing check file is a tfile file with the suffix .tcheck. This file is used to inform the simulator of the timing paths that do not need to be checked.
Claims
1. A post-simulation timing check file generation method, characterized in that: The specific steps include: Step 1, use simulation software to generate a simulation log file, and load the simulation log file into a post-simulation timing violation check system; Step 2, the target information of the type and total number of timing violations in the post-simulation timing violation check system statistical log file is sent to the filter; Step 3: Configure the time interval, simulation time accuracy and target keyword in the filter. The filter performs keyword matching. After matching, the timing paths are merged, and the effective target information of the final violation types and total number is counted. The effective target information is delivered to the mail system in the specified Excel file format for processing. Step 4: The mail system annotates the Excel file, and loads the annotated Excel file into the standard merge unit for processing and post-simulation iteration to generate a standard post-simulation timing check file.
2. The post-simulation timing check file generation method according to claim 1, characterized in that: The target information in step 2 includes timing violation setup time, hold time, width time, glitch time and recrem time.
3. The post-simulation timing check file generation method according to claim 1, characterized in that: The configuration time interval in step 3 is arbitrarily selected from 0 to the end of the simulation time; the simulation time accuracy includes fs, ps, ns and us.
4. The post-simulation timing check file generation method according to claim 1, characterized in that: The keyword matching in step 3 includes matching relevant module keywords and eliminating irrelevant module keywords.
5. The post-simulation timing check file generation method according to claim 1, characterized in that: The excel file format described in step 3 includes the project name, code version information, violation information list and violation information confirmation column.
6. The post-simulation timing check file generation method according to claim 1, characterized in that: The specific process of step 3 is: configure the time interval, simulation time accuracy and target keyword in the filter, the filter performs keyword matching, and the information of the violation type and total number after the matching is completed is sent to the filter merging unit. After receiving the information, the filter merging unit merges and classifies the timing violation register paths, and counts the valid target information of the final violation type and total number after the merger, and delivers the valid target information to the mail system for processing in the specified Excel file format.
7. The post-simulation timing check file generation method according to claim 1, characterized in that: The specific process of step 4 is: the mail system marks the Excel file, and loads the marked Excel file into the standard merging unit for processing, generates a standard inspection file for subsequent post-simulation iterations, and merges the standard inspection files generated by different batches of post-simulation to generate a post-simulation timing inspection file.