Pixel circuit for large-amplitude brightness display

Abstract

The invention provides a pixel circuit for large-amplitude brightness display. The pixel circuit comprises a switching transistor, a first driving transistor, a second driving transistor, a first light-emitting control transistor, a second light-emitting control transistor and a light-emitting diode. The first driving transistor is coupled to the switching transistor. The second driving transistor is coupled to the switching transistor. The first light emitting control transistor is coupled to the first driving transistor. The second light emitting control transistor is coupled to the second driving transistor. The light emitting diode is coupled to the first light emitting control transistor and the second light emitting control transistor.

Description

Technical Field

[0001] The invention relates to a pixel circuit, and in particular to a pixel circuit with large brightness and a driving method. Background Art

[0002] The pixel circuit is the circuit that controls the brightness of the pixels on the display. In an active matrix pixel circuit, each pixel has its own transistor. The transistor is used to control the current flowing to the pixel. The transistor is turned on and off by a digital signal. When the transistor is on, current flows through the pixel, making the pixel glow; when the transistor is off, the pixel is off because no current flows through the pixel.

[0003] Pixel drive is a method of controlling the brightness of pixels in a light-emitting diode (LED) display. The most common pixel drive scheme is 2T1C (two transistors, one capacitor), which uses two transistors and a capacitor to control the current flowing through the LED. The first transistor is used to select the pixel, the second transistor is used to transmit the signal from the data line, and the capacitor is used to store the charge used to turn on the LED.

[0004] However, the above pixel circuit and driving scheme cannot meet the demand for large display brightness, that is, high brightness during the day and low brightness at night. For most active matrix LED displays, the brightness is controlled by the driving current of the LED, so the driving circuit needs to generate a large driving current. At present, it is technically difficult to cover such a large driving current with only one driving transistor. Therefore, the brightness level of the display may not be accurate. Summary of the invention

[0005] The object of the present invention is to provide a pixel circuit for large-brightness display.

[0006] The present invention provides a pixel circuit for large-brightness display, which includes a switch transistor, a first drive transistor, a second drive transistor, a first light-emitting control transistor, a second light-emitting control transistor and a light-emitting diode. The first drive transistor is coupled to the switch transistor. The second drive transistor is coupled to the second end of the switch transistor. The first light-emitting control transistor is coupled to the first drive transistor. The second light-emitting control transistor is coupled to the second drive transistor. The light-emitting diode is coupled to the first light-emitting control transistor and the second light-emitting control transistor.

[0007] The present invention further provides another pixel circuit for large-brightness display, which includes a switching transistor, a first driving transistor, a second driving transistor, a first light-emitting control transistor, a second light-emitting control transistor, a capacitor, a light-emitting diode, a first light-emitting control line, and a second light-emitting control line. The first driving transistor is coupled to the second end of the switching transistor. The second driving transistor is coupled to the switching transistor. The first light-emitting control transistor is coupled to the first driving transistor. The second light-emitting control transistor is coupled to the second driving transistor. The capacitor is coupled between the first end of the first light-emitting control transistor and the control end of the first driving transistor. The light-emitting diode is coupled to the first driving transistor and the second driving transistor. The first light-emitting control line is coupled to the first light-emitting control transistor. The second light-emitting control line is coupled to the second light-emitting control transistor. The first light-emitting control line provides a first signal having a first duty cycle to the first light-emitting control transistor, and the second light-emitting control line provides a second signal having a second duty cycle to the second light-emitting control transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 FIG. 4 is a schematic diagram of a display panel according to an embodiment of the present invention.

[0009] Figure 2 for Figure 1 Circuit diagram of the display panel.

[0010] Figure 3 is a pixel circuit diagram in an embodiment of the present invention.

[0011] Figure 4A for Figure 3 A timing diagram of operation signals of a pixel circuit according to an embodiment of a high brightness mode.

[0012] Figure 4B for Figure 3 A timing diagram of operation signals of a pixel circuit according to an embodiment of a low brightness mode.

[0013] Figure 5 FIG. 4 is a pixel circuit diagram of another embodiment.

[0014] Figure 6 FIG. 4 is a pixel circuit diagram of another embodiment.

[0015] Figure 7 FIG. 4 is a pixel circuit diagram of another embodiment.

[0016] Figure 8 FIG. 4 is a pixel circuit diagram of another embodiment.

[0017] Fig. 9A for Figure 8 A timing diagram of operation signals of a pixel circuit according to an embodiment of a high brightness mode.

[0018] Fig. 9B for Figure 8 A timing diagram of operation signals of a pixel circuit according to an embodiment of a low brightness mode.

[0019] Fig.10 FIG. 4 is a pixel circuit diagram of another embodiment.

[0020] Fig.11A for Fig.10 A timing diagram of operation signals of a pixel circuit according to an embodiment of a high brightness mode.

[0021] Fig. 11B for Fig.10 A timing diagram of operation signals of a pixel circuit according to an embodiment of a low brightness mode.

[0022] Fig.12 FIG. 4 is a pixel circuit diagram of another embodiment.

[0023] Fig.13A for Fig.12 A timing diagram of operation signals of a pixel circuit according to an embodiment of a high brightness mode.

[0024] Fig. 13B for Fig.12 A timing diagram of operation signals of a pixel circuit according to an embodiment of a low brightness mode.

[0025] Fig.14 FIG. 4 is a pixel circuit diagram of another embodiment.

[0026] Fig.15A for Fig.14 A timing diagram of operation signals of a pixel circuit according to an embodiment of a high brightness mode.

[0027] Fig. 15B for Fig.14 A timing diagram of operation signals of a pixel circuit according to an embodiment of a low brightness mode.

[0028] Fig.16 This is a brightness mode control system according to an embodiment of the present invention.

[0029] Explanation of reference numerals: 10 ~ display panel; 1 ~ pixel circuit matrix; 2 ~ vertical driver; 3 ~ data driver; P11-PNM ~ pixel; S1-SN ~ scan line; E1-EN ~ light-emitting control line; D1-DM ~ data line; T2 ~ switch transistor; T1a, T1b ~ drive transistor; T3a, T3b, T6a, T6b ~ light-emitting control transistor; C1, C1a, C1b, C2b, C2a ~ capacitor; LED1 ~ light-emitting diode; SCANn ~ scan signal; DATAm ~ data signal; Dm ~ data line; EMAn, EMBn ~ light-emitting control signal; EAn, EBn ~ light-emitting control line; Vg ~ gate voltage; PVDD, PVSS, VRST, VREF ~ voltage; Sn ~scanning line; t0-t5~time; 100, 200, 300, 400, 500, 600, 700, 800~pixel circuit; RSTn~reset signal; Rn~reset line; T4a, T4b, T4~reset transistor; T5a, T5b~compensation transistor; CPAn, CPBn~compensation signal; CAn, CBn~compensation line; T7~reference control transistor; 20~brightness mode control system; 21~ambient light sensor; 22~illumination intensity comparator; 23~display controller; 24~timing controller; 25~display data processor; 26~grayscale controller; 27~high brightness mode lookup table; 28~low brightness mode lookup table; SIG_BM~brightness mode signal; SIG_D~display signal. DETAILED DESCRIPTION

[0030] The present invention can be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that in order to facilitate the reader's understanding and the simplicity of the drawings, the multiple drawings in the present invention only depict a portion of the display device, and certain elements in the drawings are not drawn according to the actual scale. In addition, the number and size of each element in the drawings are only for illustration and are not intended to limit the scope of the present invention.

[0031] Certain words are used throughout the specification and claims to refer to specific components. It should be understood by those skilled in the art that electronic equipment manufacturers may refer to the same components by different names. The present invention is not intended to distinguish between components that have the same function but different names. In the following specification and claims, the words "including" and "comprising" are open-ended words and should be interpreted as "including but not limited to...".

[0032] Directional terms mentioned in the present invention, such as "upper", "lower", "front", "back", "left", "right", etc., are only referenced to the directions of the accompanying drawings. Therefore, the directional terms used are for illustration and not for limiting the present invention. It should be understood that for those of ordinary skill in the art, the specifically described or labeled elements may exist in various forms. In addition, when an element or film layer is referred to as being "on", "disposed on" or "connected to" another element or film layer, it may be directly on or directly connected to this other element or film layer, or there may be an intervening element or film layer between the two (indirect case).

[0033] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used in the embodiments to describe the relative relationship of a labeled element to another element in the drawings. It should be understood that if the labeled device is turned upside down, the element on the "lower" side may be the element on the "upper" side.

[0034] In the present specification and claims, ordinals such as "first", "second", etc. are used to modify elements in the claims. This does not mean that the required element has any of the aforementioned ordinals, and does not represent the order of the required element with another required element or the order in the manufacturing method. The ordinals are only used to distinguish a required element with a certain name from another required element with the same certain name.

[0035] It should be understood that without departing from the spirit of the present invention, the technical features in the different embodiments described below may be replaced with each other, recombined or mixed to form another embodiment.

[0036] The electronic device of the present invention may include a display device, a backlight device, an antenna device, a sensor device, a splicing device or a transparent display device, but is not limited thereto. The electronic device may be a bendable, flexible or rollable electronic device.

[0037] The display device may include a non-self-luminous display device or a self-luminous display device, but is not limited thereto. The display device may include, for example, a liquid crystal, a light-emitting diode, fluorescence, phosphor, a quantum dot (QD), other suitable display media, or a combination thereof. The light-emitting diode may include, for example, an organic light-emitting diode (OLED), a sub-millimeter light-emitting diode (mini LED), a micro LED, or a quantum dot light-emitting diode (quantum dot LED), but is not limited thereto.

[0038] Figure 1 FIG. 1 is a schematic diagram of a display panel 10 according to an embodiment of the present invention. Figure 2 is a circuit diagram of the display panel 10. Figure 1 and Figure 2 As shown, the display panel 10 includes a pixel circuit matrix 1, a vertical driver (V driver) 2 and a data driver 3. The pixel circuit matrix 1 includes a plurality of pixels P11-PNM, which are located in the area where a plurality of scan lines S1-SN and a plurality of light emitting control lines E1-EN intersect with a plurality of data lines D1-DM. The pixel circuit matrix 1 displays an image according to the applied data voltage.

[0039] The vertical driver 2 can generate a scan signal and a light-emitting control signal. In some embodiments, the vertical driver 2 can also generate a compensation signal. After receiving the scan control signal (i.e., the start pulse and the clock signal), the vertical driver 2 sequentially provides the scan signal to the scan lines S1-SN. After receiving the start pulse and the clock signal, the vertical driver 2 also provides the light-emitting control signal to the light-emitting control lines E1-EN. The data driver 3 provides the data voltage corresponding to the RGB (red, green and blue) data to the data lines D1-DM in response to the data control signal.

[0040] Each of the pixels P11-PNM includes R, G, and B pixel circuits. In the pixel circuit matrix 1, the R, G, and B pixel circuits have the same circuit structure and emit R, G, and B light with brightness corresponding to the current supplied to the pixel circuit. Therefore, each of the pixels P11-PNM combines the light emitted from the R, G, and B pixel circuits and displays a specific color according to the combination of the pixel color and the brightness.

[0041] Figure 3Schematic diagram of a pixel circuit 100 in an embodiment of the present invention. The pixel circuit 100 may be a pixel circuit Pnm (1≤m≤M, 1≤n≤N) of one of the pixels P11-PNM, and the pixel circuit 100 may have some changes. The pixel circuit 100 includes a switch transistor T2, a drive transistor T1a, a drive transistor T1b, a light-emitting control transistor T3a, a light-emitting control transistor T3b, a capacitor C1, and a light-emitting diode LED1. The switch transistor T2, the drive transistors T1a and T1b, and the light-emitting control transistors T3a and T3b each include a first end, a second end, and a control end. The control ends of the drive transistor T1a and the drive transistor T1b are both coupled to the second end of the switch transistor T2. The second end of the drive transistor T1a may be coupled to the first end of the light-emitting control transistor T3a. The second end of the drive transistor T1b may be coupled to the first end of the light-emitting control transistor T3b. The light-emitting diode LED1 may be coupled to the second end of the light-emitting control transistor T3a and the second end of the light-emitting control transistor T3b. The capacitor C1 may be coupled between the control terminal of the driving transistor T1a and the voltage PVDD (i.e., DC voltage). The control terminal of the switch transistor T2 may be coupled to the scan line Sn. The first terminal of the switch transistor T2 may be coupled to the data line Dm. The control terminal of the light emitting control transistor T3a may be coupled to the light emitting control line EAn, and the control terminal of the light emitting control transistor T3b may be coupled to another light emitting control line EBn.

[0042] The scan line Sn provides a scan signal SCANn to turn on the switch transistor T2, so that the data line Dm can write the data signal DATAm into the control terminal of the driving transistors T1a and T1b. The driving current is controlled by the driving transistors T1a and T1b according to the data signal DATAm input through the switch transistor T2. The capacitor C1 can store charges for turning on the driving transistors T1a and T1b. The voltage PVDD is provided to the first terminal of the driving transistor T1a and the first terminal of the driving transistor T1b, and the voltage PVSS is provided to the light-emitting diode LED1. In this way, the pixel circuit 100 can establish a voltage difference so that the driving current flows from the voltage PVDD terminal to the voltage PVSS terminal, wherein the voltage PVDD is greater than the voltage PVSS.

[0043] The light emitting control line EAn provides a light emitting control signal EMAn having a first duty cycle to the light emitting control transistor T3a. The light emitting control line EBn provides a light emitting control signal EMBn having a second duty cycle to the light emitting control transistor T3b. In some embodiments, the first duty cycle may be different from the second duty cycle, while in some other embodiments, the first duty cycle may be the same as the second duty cycle. The light emitting period of the light emitting diode LED1 is controlled by the light emitting control transistors T3a and T3b according to the light emitting control signals EMAn and EMBn, respectively. In some other embodiments, only one of the light emitting control signals EMAn and EMBn turns on the light emitting control switch at a specific duty cycle.

[0044] The switch transistor T2, the driving transistors T1a and T1b, and the light emission control transistors T3a and T3b may be p-type transistors. The driving transistor T1a and the driving transistor T1b have different channel width-to-length ratios (W / L).

[0045] In some embodiments, the driving transistor T1a may be a low temperature polysilicon (LTPS) thin film transistor. In some embodiments, the driving transistor T1b may be an oxide thin film transistor. In some embodiments, the driving transistor T1a may have a width-to-length ratio of about 20 μm / 5 μm=4 for relatively large currents. In some embodiments, the driving transistor T1b may have a width-to-length ratio of about 5 μm / 25 μm=0.2 for relatively small currents.

[0046] In the above embodiment, two different types (size or mobility characteristics) of driving transistors T1a and T1b are selectively used for two display brightness modes. The driving unit includes driving transistors T1a and T1b and light-emitting control transistors T3a and T3b, and the driving transistors T1a and T1b are respectively coupled in series to the light-emitting control transistors T3a and T3b. The light-emitting control transistors T3a and T3b are commonly coupled to the light-emitting diode LED1. The control ends of the light-emitting control transistors T3a and T3b are independently controlled by the light-emitting control signals EMAn and EMBn, respectively, to select a suitable driving current according to the high brightness mode or the low brightness mode. It should be noted that the scan signal SCANn and the light-emitting control signals EMAn and EMBn can be provided by the vertical driver 2. The data signal DATAm can be provided by the data driver 3.

[0047] When the switching transistor T2 is turned on, the gate voltage Vg is set to the data voltage of the next display frame period, so that the gate-source voltage (Vgs) of the driving transistor T1a and the driving transistor T1b is updated to generate a current for the subsequent display frame period. At this time, if the light emitting control transistor T3a is turned on by the light emitting control signal EMAn, a large current will flow through the light emitting diode LED1 for the high brightness mode. On the other hand, if the light emitting control transistor T3b is turned on by the light emitting control signal EMBn, a small current will flow through the light emitting diode LED1 for the low brightness mode.

[0048] In some embodiments, more brightness modes can be created by adding more driving transistors and light emission control transistors based on the same principle, respectively, to the pixel circuit 100. The present invention is not limited thereto.

[0049] Please refer to Figure 4A and Figure 4B . Figure 4A 1 is a timing diagram of the operation signals of the pixel circuit 100 according to the embodiment of the high brightness mode. Initially, at time t0, the scan signal SCANn, the light emission control signal EMAn and EMBn are at a high level. Therefore, the initial state of the driving transistors T1a and T1b, the switching transistor T2 and the light emission control transistors T3a and T3b is cut off. The display frame period starts from time t1. Between time t1 and t2, a low pulse appears in the scan signal SCANn, so that the data signal DATAm controls the driving transistors T1a and T1b through the switching transistor T2. Between time t2 and t3, a low pulse appears in the light emission control signal EMAn to turn on the light emission control transistor T3a. The light emission control signal EMBn is maintained at a high level to keep the light emission control transistor T3b cut off. Therefore, during the time period, a large driving current can flow from the voltage PVDD terminal to the voltage PVSS terminal for a long time to drive the light emitting diode LED1 to display in the high brightness mode. At time t4, another display frame period begins. For different display frame periods, the behavior of the operating signal is similar, and for the sake of brevity, it will not be repeated here.

[0050] Figure 4B1 is a timing diagram of the operation signals of the pixel circuit 100 according to the embodiment of the low brightness mode. Initially at time t0, the scan signal SCANn, the light emission control signal EMAn and EMBn are at a high level. Therefore, the initial state of the driving transistors T1a and T1b, the switching transistor T2 and the light emission control transistors T3a and T3b is cut off. The display frame cycle starts from time t1. Between time t1 and t2, a low pulse appears in the scan signal SCANn, so that the data signal DATAm controls the driving transistors T1a and T1b through the switching transistor T2. Between time t2 and t3, a low pulse appears in the light emission control signal EMBn to turn on the light emission control transistor T3b. The light emission control signal EMAn is maintained at a high level to keep the light emission control transistor T3a cut off. In this way, during this period of time, a small driving current can flow from the voltage PVDD terminal to the voltage PVSS terminal in a shorter time to drive the light emitting diode LED1 to display in a low brightness mode. At time t4, another display frame cycle begins. For different display frame periods, the behavior of the operating signal is similar, and for the sake of brevity, it will not be repeated here.

[0051] Figure 5 Schematic diagram of a pixel circuit 200 of another embodiment. The pixel circuit 200 may be a pixel circuit Pnm of one of the pixels P11-PNM, and the pixel circuit 200 may have some changes. The pixel circuit 200 includes a switch transistor T2, a drive transistor T1a, a drive transistor T1b, a light-emitting control transistor T3a, a light-emitting control transistor T3b, a capacitor C1, and a light-emitting diode LED1. The switch transistor T2, the drive transistors T1a and T1b, and the light-emitting control transistors T3a and T3b each include a first end, a second end, and a control end. The control ends of the drive transistor T1a and the drive transistor T1b are both coupled to the second end of the switch transistor T2. The first end of the drive transistor T1a may be coupled to the second end of the light-emitting control transistor T3a. The first end of the drive transistor T1b may be coupled to the second end of the light-emitting control transistor T3b. The light-emitting diode LED1 may be coupled to the first end of the light-emitting control transistor T3a and the first end of the light-emitting control transistor T3b. The capacitor C1 may be coupled between the control end of the drive transistor T1a and the voltage source PVSS. The control end of the switch transistor T2 may be coupled to the scan line Sn. The first end of the switch transistor T2 may be coupled to the data line Dm. The control end of the light emitting control transistor T3a may be coupled to the light emitting control line EAn, and the control end of the light emitting control transistor T3b may be coupled to another light emitting control line EBn.

[0052] The scan line Sn provides a scan signal SCANn to the switch transistor T2, so that the data line Dm writes the data signal DATAm to the control terminal of the driving transistors T1a and T1b. The driving current is controlled by the driving transistors T1a and T1b according to the data signal DATAm input through the switch transistor T2. The voltage PVSS is provided to the second terminal of the driving transistor T1a and the second terminal of the driving transistor T1b, and the voltage PVDD is provided to the light emitting diode LED1. In this way, the pixel circuit 200 can establish a voltage difference so that the driving current flows from the voltage PVDD terminal to the voltage PVSS terminal, wherein the voltage PVDD is greater than the voltage PVSS.

[0053] The light emission control line EAn provides a light emission control signal EMAn having a first duty cycle to the light emission control transistor T3a. The light emission control line EBn provides a light emission control signal EMBn having a second duty cycle to the light emission control transistor T3b. In some embodiments, the first duty cycle may be different from the second duty cycle, while in some other embodiments, the first duty cycle may be the same as the second duty cycle. The light emission period of the light emitting diode LED1 is controlled by the light emission control transistors T3a and T3b according to the light emission control signals EMAn and EMBn, respectively.

[0054] The switch transistor T2, the driving transistors T1a and T1b, and the light emission control transistors T3a and T3b may be n-type transistors. The driving transistor T1a and the driving transistor T1b have different channel width-to-length ratios (W / L).

[0055] In some embodiments, the driving transistor T1a may be a low temperature polysilicon (LTPS) thin film transistor. In some embodiments, the driving transistor T1b may be an oxide thin film transistor. In some embodiments, the driving transistor T1a may have a width-to-length ratio of about 20 μm / 5 μm=4 for relatively large currents. In some embodiments, the driving transistor T1b may have a width-to-length ratio of about 5 μm / 25 μm=0.2 for relatively small currents.

[0056] In the above embodiment, two different types (size or mobility characteristics) of driving transistors T1a and T1b are selectively used for two display brightness modes. The driving unit includes driving transistors T1a and T1b and light-emitting control transistors T3a and T3b, and the driving transistors T1a and T1b are respectively coupled in series with the light-emitting control transistors T3a and T3b. The light-emitting control transistors T3a and T3b are commonly coupled to the light-emitting diode LED1. The control ends of the light-emitting control transistors T3a and T3b are independently controlled by the light-emitting control signals EMAn and EMBn, respectively, to select a suitable driving current according to the high brightness mode or the low brightness mode. It should be noted that the scan signal SCANn and the light-emitting control signals EMAn and EMBn can be provided by the vertical driver 2. The data signal DATAm can be provided by the data driver 3.

[0057] When the switch transistor T2 is turned on, the gate voltage Vg is set to the data voltage of the next display frame period, so that the gate-source voltage (Vgs) of the driving transistor T1a and the driving transistor T1b is updated to generate a current for the subsequent display frame period. At this time, if the light emitting control transistor T3a is turned on by the light emitting control signal EMAn, a large current will flow through the light emitting diode LED for high brightness mode. On the other hand, if the light emitting control transistor T3b is turned on by the light emitting control signal EMBn, a small current will flow through the light emitting diode LED for low brightness mode. The operating signal of the pixel circuit 200 is similar to the operating signal of the pixel circuit 100, and for the sake of brevity, it will not be repeated here.

[0058] In some embodiments, more brightness modes can be created by adding more driving transistors and light emission control transistors based on the same principle to the pixel circuit 200. The present invention is not limited thereto.

[0059] Figure 6Schematic diagram of a pixel circuit 300 of another embodiment. The pixel circuit 300 may be a pixel circuit Pnm (1≤m≤M, 1≤n≤N) of one of the pixels P11-PNM, and the pixel circuit 300 may have some changes. The pixel circuit 300 includes a switch transistor T2, a drive transistor T1a, a drive transistor T1b, a light-emitting control transistor T3a, a light-emitting control transistor T3b, a capacitor C1, and a light-emitting diode LED1. The switch transistor T2, the drive transistors T1a and T1b, and the light-emitting control transistors T3a and T3b each include a first end, a second end, and a control end. The control ends of the drive transistor T1a and the drive transistor T1b are both coupled to the second end of the switch transistor T2. The second end of the light-emitting control transistor T3a may be coupled to the first end of the drive transistor T1a. The second end of the light-emitting control transistor T3b may be coupled to the first end of the drive transistor T1b. The light-emitting diode LED1 may be coupled to the second end of the drive transistor T1a and the second end of the drive transistor T1b. The capacitor C1 may be coupled between the control terminal of the driving transistor T1a and the voltage source PVDD (i.e., DC voltage). The control terminal of the switch transistor T2 may be coupled to the scan line Sn. The first terminal of the switch transistor T2 may be coupled to the data line Dm. The control terminal of the light emitting control transistor T3a may be coupled to the light emitting control line EAn, and the control terminal of the light emitting control transistor T3b may be coupled to another light emitting control line EBn.

[0060] The scan line Sn provides a scan signal SCANn to the switch transistor T2, so that the data line Dm writes the data signal DATAm to the control terminal of the driving transistors T1a and T1b. The driving current is controlled by the driving transistors T1a and T1b according to the data signal DATAm input through the switch transistor T2. The voltage PVDD is provided to the first terminal of the light emitting control transistor T3a and the first terminal of the light emitting control transistor T3b, and the voltage PVSS is provided to the light emitting diode LED1. In this way, the pixel circuit 300 can establish a voltage difference so that the driving current flows from the voltage PVDD terminal to the voltage PVSS terminal, wherein the voltage PVDD is greater than the voltage PVSS.

[0061] The light emission control line EAn provides a light emission control signal EMAn having a first duty cycle to the light emission control transistor T3a. The light emission control line EBn provides a light emission control signal EMBn having a second duty cycle to the light emission control transistor T3b. In some embodiments, the first duty cycle may be different from the second duty cycle, while in some other embodiments, the first duty cycle may be the same as the second duty cycle. The light emission period of the light emitting diode LED1 is controlled by the light emission control transistors T3a and T3b according to the light emission control signals EMAn and EMBn, respectively.

[0062] The switch transistor T2, the driving transistors T1a and T1b, and the light emission control transistors T3a and T3b may be p-type transistors. The driving transistor T1a and the driving transistor T1b have different channel width-to-length ratios (W / L).

[0063] In some embodiments, the driving transistor T1a may be a low temperature polysilicon (LTPS) thin film transistor. In some embodiments, the driving transistor T1b may be an oxide thin film transistor. In some embodiments, the driving transistor T1a may have a width-to-length ratio of about 20 μm / 5 μm=4 for relatively large currents. In some embodiments, the driving transistor T1b may have a width-to-length ratio of about 5 μm / 25 μm=0.2 for relatively small currents.

[0064] In the above embodiment, two different types (size or mobility characteristics) of driving transistors T1a and T1b are selectively used for two display brightness modes. The driving unit includes driving transistors T1a and T1b and light-emitting control transistors T3a and T3b respectively coupled in series. The driving transistors T1a and T1b are commonly coupled to the light-emitting diode LED1. The control ends of the light-emitting control transistors T3a and T3b are independently controlled by light-emitting control signals EMAn and EMBn, respectively, to select a suitable driving current according to the high brightness mode or the low brightness mode. It should be noted that the scan signal SCANn and the light-emitting control signals EMAn and EMBn can be provided by the vertical driver 2. The data signal DATAm can be provided by the data driver 3.

[0065] The operation signal of the pixel circuit 300 is similar to the operation signal of the pixel circuit 100 , and for the sake of brevity, a repeated description is not given here.

[0066] Figure 7Schematic diagram of a pixel circuit 400 of another embodiment. The pixel circuit 400 may be a pixel circuit Pnm (1≤m≤M, 1≤n≤N) of one of the pixels P11-PNM, and the pixel circuit 400 may have some changes. The pixel circuit 400 includes a switch transistor T2, a drive transistor T1a, a drive transistor T1b, a light-emitting control transistor T3a, a light-emitting control transistor T3b, a capacitor C1, and a light-emitting diode LED1. The switch transistor T2, the drive transistors T1a and T1b, and the light-emitting control transistors T3a and T3b each include a first end, a second end, and a control end. The control ends of the drive transistor T1a and the drive transistor T1b are both coupled to the second end of the switch transistor T2. The second end of the drive transistor T1a may be coupled to the first end of the light-emitting control transistor T3a. The second end of the drive transistor T1b may be coupled to the first end of the light-emitting control transistor T3b. The light-emitting diode LED1 may be coupled to the first ends of the drive transistors T1a and T1b. The capacitor C1 may be coupled between the control terminal of the driving transistor T1a and the voltage source PVSS. The control terminal of the switch transistor T2 may be coupled to the scan line Sn. The first terminal of the switch transistor T2 may be coupled to the data line Dm. The control terminal of the light emitting control transistor T3a may be coupled to the light emitting control line EAn, and the control terminal of the light emitting control transistor T3b may be coupled to another light emitting control line EBn.

[0067] The scan line Sn provides a scan signal SCANn to the switch transistor T2, so that the data line Dm writes the data signal DATAm to the control terminal of the driving transistors T1a and T1b. The driving current is controlled by the driving transistors T1a and T1b according to the data signal DATAm input through the switch transistor T2. The voltage PVSS is provided to the second terminal of the light emitting control transistor T3a and the second terminal of the light emitting control transistor T3b, and the voltage PVDD is provided to the light emitting diode LED1. In this way, the pixel circuit 400 can establish a voltage difference so that the driving current flows from the voltage PVDD terminal to the voltage PVSS terminal, wherein the voltage PVDD is greater than the voltage PVSS.

[0068] The light emission control line EAn provides a light emission control signal EMAn having a first duty cycle to the light emission control transistor T3a. The light emission control line EBn provides a light emission control signal EMBn having a second duty cycle to the light emission control transistor T3b. In some embodiments, the first duty cycle may be different from the second duty cycle, while in some other embodiments, the first duty cycle may be the same as the second duty cycle. The light emission period of the light emitting diode LED1 is controlled by the light emission control transistors T3a and T3b according to the light emission control signals EMAn and EMBn, respectively.

[0069] The switch transistor T2, the driving transistors T1a and T1b, and the light emission control transistors T3a and T3b may be n-type transistors. The driving transistor T1a and the driving transistor T1b have different channel width-to-length ratios (W / L).

[0070] In some embodiments, the driving transistor T1a may be a low temperature polysilicon (LTPS) thin film transistor. In some embodiments, the driving transistor T1b may be an oxide thin film transistor. In some embodiments, the driving transistor T1a may have a width-to-length ratio of about 20 μm / 5 μm=4 for relatively large currents. In some embodiments, the driving transistor T1b may have a width-to-length ratio of about 5 μm / 25 μm=0.2 for relatively small currents.

[0071] In the above embodiment, two different types (size or mobility characteristics) of driving transistors T1a and T1b are selectively used for two display brightness modes. The driving unit includes driving transistors T1a and T1b and light-emitting control transistors T3a and T3b, and the driving transistors T1a and T1b are coupled in series with the light-emitting control transistors T3a and T3b respectively. The driving transistors T1a and T1b are commonly coupled to the light-emitting diode LED1. The control ends of the light-emitting control transistors T3a and T3b are independently controlled by the light-emitting control signals EMAn and EMBn, respectively, to select a suitable driving current according to the high brightness mode or the low brightness mode. It should be noted that the scan signal SCANn and the light-emitting control signals EMAn and EMBn can be provided by the vertical driver 2. The data signal DATAm can be provided by the data driver 3.

[0072] The operation signals of the pixel circuit 400 are similar to the operation signals of the pixel circuit 100 , and for the sake of brevity, they are not described again here.

[0073] Figure 8 Schematic diagram of a pixel circuit 500 of another embodiment. The pixel circuit 500 may be a pixel circuit Pnm (1≤m≤M, 1≤n≤N) of one of the pixels P11-PNM, and the pixel circuit 500 may have some changes. The pixel circuit 500 includes a switch transistor T2, drive transistors T1a and T1b, light emission control transistors T3a, T3b, T6a and T6b, reset transistors T4a and T4b, compensation transistors T5a and T5b, capacitors C1a and C1b, and a light emitting diode LED1. The switch transistor T2, the drive transistors T1a and T1b, the light emission control transistors T3a, T3b, T6a and T6b, the reset transistors T4a and T4b, and the compensation transistors T5a and T5b each include a first terminal, a second terminal, and a control terminal.

[0074] The control end of the driving transistor T1a may be coupled to the second end of the reset transistor T4a. The control end of the driving transistor T1b may be coupled to the second end of the reset transistor T4b. The second end of the driving transistor T1a may be coupled to the first end of the light emitting control transistor T3a. The second end of the driving transistor T1b may be coupled to the first end of the light emitting control transistor T3b. The light emitting diode LED1 may be coupled to the second end of the light emitting control transistor T3a and the second end of the light emitting control transistor T3b. The control ends of the reset transistors T4a and T4b are both coupled to the reset line Rn. The control ends of the compensation transistors T5a and T5b are both coupled to the scan line Sn. The capacitor C1a may be coupled between the control end of the driving transistor T1a and the voltage source PVDD. The capacitor C1b may be coupled between the control end of the driving transistor T1b and the voltage source PVDD. The second end of the compensation transistor T5a may be coupled to the control end of the driving transistor T1a, and the first end of the compensation transistor T5a may be coupled to the second end of the driving transistor T1a. The second end of the compensation transistor T5b may be coupled to the control end of the driving transistor T1b, and the first end of the compensation transistor T5b may be coupled to the second end of the driving transistor T1b. The control end of the switch transistor T2 may be coupled to the scan line Sn. The first end of the switch transistor T2 may be coupled to the data line Dm. The second end of the switch transistor T2 may be coupled to the first ends of the driving transistors T1a and T1b. The control ends of the light emitting control transistors T3a and T6a may be coupled to the light emitting control line EAn, and the control ends of the light emitting control transistors T3b and T6b may be coupled to another light emitting control line EBn. The second ends of the light emitting control transistors T6a and T6b are respectively coupled to the first ends of the driving transistors T1a and T1b.

[0075] The scan line Sn provides a scan signal SCANn to the switch transistor T2 and the compensation transistors T5a and T5b, so that the data line Dm writes the data signal DATAm to the control terminal of the driving transistors T1a and T1b. The driving current is controlled by the driving transistors T1a and T1b according to the data signal DATAm input through the switch transistor T2. The capacitors C1a and C1b can store charges for turning on the driving transistors T1a and T1b, respectively. The voltage PVDD is provided to the first terminal of the driving transistor T6a and the first terminal of the driving transistor T6b, and the voltage PVSS is provided to the light-emitting diode LED1. In this way, the pixel circuit 500 can establish a voltage difference so that the driving current flows from the voltage PVDD terminal to the voltage PVSS terminal, wherein the voltage PVDD is greater than the voltage PVSS.

[0076] The reset line Rn provides a reset signal RSTn to the reset transistors T4a and T4b. The voltage VRST is provided to the first terminals of the reset transistors T4a and T4b. The reset transistors T4a and T4b function to set the drive transistors T1a and T1b to receive the data signal DATAm of the next display frame period.

[0077] The light emitting control line EAn provides a light emitting control signal EMAn having a first duty cycle to the light emitting control transistors T3a and T6a. The light emitting control line EBn provides a light emitting control signal EMBn having a second duty cycle to the light emitting control transistors T3b and T6b. In some embodiments, the first duty cycle may be different from the second duty cycle, while in some other embodiments, the first duty cycle may be the same as the second duty cycle. The light emitting period of the light emitting diode LED1 is controlled by the light emitting control transistors T3a, T6a and T3b, T6b according to the light emitting control signals EMAn and EMBn, respectively.

[0078] The switch transistor T2, the driving transistors T1a and T1b, the light emission control transistors T3a, T3b, T6a and T6b, the reset transistors T4a and T4b, and the compensation transistors T5a and T5b may be p-type transistors. The driving transistors T1a and T1b have different channel width-to-length ratios (W / L).

[0079] In some embodiments, the driving transistor T1a may be a low temperature polysilicon (LTPS) thin film transistor. In some embodiments, the driving transistor T1b may be an oxide thin film transistor. In some embodiments, the driving transistor T1a may have a width-to-length ratio of about 20 μm / 5 μm=4 for relatively large currents. In some embodiments, the driving transistor T1b may have a width-to-length ratio of about 5 μm / 25 μm=0.2 for relatively small currents.

[0080] Please refer to Fig. 9A and Fig. 9B . Fig. 9A1 is a timing diagram of the operation signals of the pixel circuit 500 according to the embodiment of the high brightness mode. Initially at time t0, the reset signal RSTn, the scan signal SCANn, the light emission control signals EMAn and EMBn are at a high level. Therefore, the initial state of the switch transistor T2, the light emission control transistors T3a, T3b, T6a and T6b, the reset transistors T4a and T4b, and the compensation transistors T5a and T5b is cut off. Between time t1 and t2, a low pulse appears in the reset signal RSTn to turn on the reset transistors T4a and T4b, thereby allowing the voltage VRST to reset the drive transistors T1a and T1b. This mechanism ensures that the drive transistors T1a and T1b can be turned on during the next display frame period. The display frame period starts from time t2. Between time t2 and t3, a low pulse appears in the scan signal SCANn, allowing the data signal DATAm to reach the first end of each of the drive transistors T1a and T1b through the switch transistor T2, while turning on the compensation transistors T5a and T5b. When the compensation transistors T5a and T5b are turned on, the data signal DATAm can be transmitted to the corresponding control terminals of the driving transistors T1a and T1b through the corresponding compensation transistors T5a and T5b, thereby determining the control voltage of the driving transistors T1a and T1b. Between time t3 and t4, a low pulse appears in the light emitting control signal EMAn to turn on the light emitting control transistors T3a and T6a. The light emitting control signal EMBn is maintained at a high level to keep the light emitting control transistors T3b and T6b turned off. In this way, during this period, a large driving current can flow from the voltage PVDD terminal to the voltage PVSS terminal to drive the light emitting diode LED1 to display in a high brightness mode. At time t5, another display frame period begins. For different display frame periods, the behavior of the operating signal is similar, and for the sake of brevity, it will not be repeated here.

[0081] Fig. 9B1 is a timing diagram of the operation signals of the pixel circuit 500 according to the embodiment of the low brightness mode. Initially at time t0, the reset signal RSTn, the scan signal SCANn, the light emission control signal EMAn and EMBn are at a high level. Therefore, the initial state of the switch transistor T2, the light emission control transistor T3a, T3b, T6a and T6b, the reset transistor T4a and T4b, and the compensation transistor T5a and T5b is cut off. Between time t1 and t2, a low pulse appears in the reset signal RSTn to turn on the reset transistors T4a and T4b, thereby allowing the voltage VRST to reset the drive transistors T1a and T1b. This mechanism ensures that the drive transistors T1a and T1b can be turned on during the next display frame period. The display frame period starts from time t2. Between time t2 and t3, a low pulse appears in the scan signal SCANn, allowing the data signal DATAm to reach the first end of each of the drive transistors T1a and T1b through the switch transistor T2. When the compensation transistors T5a and T5b are turned on, the data signal DATAm can be transmitted to the corresponding control terminals of the driving transistors T1a and T1b through the corresponding compensation transistors T5a and T5b, thereby determining the control voltage of the driving transistors T1a and T1b. Between time t3 and t4, a low pulse appears in the light emitting control signal EMBn to turn on the light emitting control transistors T3b and T6b. The light emitting control signal EMAn is maintained at a high level to keep the light emitting control transistors T3a and T6a turned off. In this way, during the time period, a small driving current can flow from the voltage PVDD terminal to the voltage PVSS terminal to drive the light emitting diode LED1 to display in a low brightness mode. At time t5, another display frame period begins. For different display frame periods, the behavior of the operating signal is similar, and for the sake of brevity, it will not be repeated here.

[0082] Fig.10 Schematic diagram of a pixel circuit 600 of another embodiment. The pixel circuit 600 may be a pixel circuit Pnm (1≤m≤M, 1≤n≤N) of one of the pixels P11-PNM, and the pixel circuit 600 may have some changes. The pixel circuit 600 includes a switch transistor T2, a drive transistor T1a and T1b, a light emitting control transistor T3a, T3b, T6a and T6b, a reset transistor T4, a compensation transistor T5a and T5b, a capacitor C1, and a light emitting diode LED1. The switch transistor T2, the drive transistor T1a and T1b, the light emitting control transistor T3a, T3b, T6a and T6b, the reset transistor T4, and the compensation transistor T5a and T5b each include a first terminal, a second terminal, and a control terminal.

[0083] The control terminal of the driving transistor T1a may be coupled to the second terminal of the reset transistor T4. The control terminal of the driving transistor T1b may be coupled to the second terminal of the reset transistor T4. The first terminal of the light emitting control transistor T3a may be coupled to the second terminal of the driving transistor T1a. The first terminal of the light emitting control transistor T3b may be coupled to the second terminal of the driving transistor T1b. The light emitting diode LED1 may be coupled to the second terminal of the light emitting control transistor T3a and the second terminal of the light emitting control transistor T3b. The control terminal of the reset transistor T4 may be coupled to the reset line Rn. The control terminal of the compensation transistor T5a may be coupled to the compensation line CAn, and the control terminal of the compensation transistor T5b may be coupled to another compensation line CBn. The capacitor C1 may be coupled between the control terminal of the driving transistor T1a and the voltage source PVDD. The second terminal of the compensation transistor T5a may be coupled to the control terminal of the driving transistor T1a, and the first terminal of the compensation transistor T5a may be coupled to the second terminal of the driving transistor T1a. The second end of the compensation transistor T5b may be coupled to the control end of the driving transistor T1b, and the second end of the compensation transistor T5b may be coupled to the second end of the driving transistor T1b. The control end of the switch transistor T2 may be coupled to the scan line Sn. The first end of the switch transistor T2 may be coupled to the data line Dm. The second end of the switch transistor T2 may be coupled to the first ends of the driving transistors T1a and T1b. The control terminals of the light emitting control transistors T3a and T6a may be coupled to the light emitting control line EAn, and the control terminals of the light emitting control transistors T3b and T6b may be coupled to another light emitting control line EBn. The second ends of the light emitting control transistors T6a and T6b are coupled to the first ends of the driving transistors T1a and T1b, respectively.

[0084] The scan line Sn provides a scan signal SCANn to the switch transistor T2 and the compensation transistors T5a and T5b, so that the data line Dm writes the data signal DATAm to the control terminals of the driving transistors T1a and T1b. The driving current is controlled by the driving transistors T1a and T1b according to the data signal DATAm input through the switch transistor T2. The voltage PVDD is provided to the first terminal of the driving transistor T6a and the first terminal of the driving transistor T6b, and the voltage PVSS is provided to the light emitting diode LED1. In this way, the pixel circuit 600 can establish a voltage difference so that the driving current flows from the voltage PVDD terminal to the voltage PVSS terminal, wherein the voltage PVDD is greater than the voltage PVSS.

[0085] The reset line Rn provides a reset signal RSTn to the reset transistor T4. The voltage VRST is provided to the first terminal of the reset transistor T4. The function of the reset transistor T4 is to set the drive transistors T1a and T1b to receive the data signal DATAm of the next display frame period. The compensation lines CAn and CBn provide compensation signals CPAn and CPBn respectively to independently control the compensation transistors T5a and T5b.

[0086] The light emitting control line EAn provides a light emitting control signal EMAn having a first duty cycle to the light emitting control transistors T3a and T6a. The light emitting control line EBn provides a light emitting control signal EMBn having a second duty cycle to the light emitting control transistors T3b and T6b. In some embodiments, the first duty cycle may be different from the second duty cycle, while in some other embodiments, the first duty cycle may be the same as the second duty cycle. The light emitting period of the light emitting diode LED1 is controlled by the light emitting control transistors T3a, T6a and T3b, T6b according to the light emitting control signals EMAn and EMBn, respectively. It should be noted that the scan signal SCANn, the compensation signals CPAn and CPBn, and the light emitting control signals EMAn and EMBn may be provided by the vertical driver 2. The data signal DATAm may be provided by the data driver 3.

[0087] The switch transistor T2, the driving transistors T1a and T1b, the light emission control transistors T3a, T3b, T6a and T6b, the reset transistor T4, and the compensation transistors T5a and T5b may be p-type transistors. The driving transistors T1a and T1b have different channel width-to-length ratios (W / L).

[0088] In some embodiments, the driving transistor T1a may be a low temperature polysilicon (LTPS) thin film transistor. In some embodiments, the driving transistor T1b may be an oxide thin film transistor. In some embodiments, the driving transistor T1a may have a width-to-length ratio of about 20 μm / 5 μm=4 for relatively large currents. In some embodiments, the driving transistor T1b may have a width-to-length ratio of about 5 μm / 25 μm=0.2 for relatively small currents.

[0089] Please refer to Fig.11A and Fig. 11B . Fig.11A1 is a timing diagram of the operation signals of the pixel circuit 600 according to the embodiment of the high brightness mode. Initially, at time t0, the reset signal RSTn, the scan signal SCANn, the light emission control signals EMAn and EMBn, and the compensation signals CPAn and CPBn are at a high level. Therefore, the initial state of the switch transistor T2, the light emission control transistors T3a, T3b, T6a and T6b, and the reset transistor T4, the compensation transistors T5a and T5b is cut off. Between time t1 and t2, a low pulse appears in the reset signal RSTn to turn on the reset transistor T4, thereby allowing the voltage VRST to reset the drive transistors T1a and T1b. This mechanism ensures that the drive transistors T1a and T1b can be turned on during the next display frame period. The display frame period starts from time t2. Between time t2 and t3, a low pulse appears in the scan signal SCANn, allowing the data signal DATAm to reach the first end of each of the drive transistors T1a and T1b through the switch transistor T2. At the same time, a low pulse appears in the compensation signal CPAn to turn on the compensation transistor T5a. When the compensation transistor T5a is turned on, the data signal DATAm can be transmitted to the control terminal of the driving transistor T1a through the compensation transistor T5a, thereby determining the control voltage of the driving transistor T1a. The compensation signal CPBn is maintained at a high level. Between time t3 and t4, a low pulse appears in the light emitting control signal EMAn to turn on the light emitting control transistors T3a and T6a. The light emitting control signal EMBn is maintained at a high level to keep the light emitting control transistors T3b and T6b turned off. In this way, during this period, a large driving current can flow from the voltage PVDD terminal to the voltage PVSS terminal to drive the light emitting diode LED1 to display in a high brightness mode. At time t5, another display frame cycle begins. For different display frame cycles, the behavior of the operating signal is similar, and for the sake of brevity, it will not be repeated here.

[0090] Fig. 11B1 is a timing diagram of the operation signals of the pixel circuit 600 according to the embodiment of the low brightness mode. Initially, at time t0, the reset signal RSTn, the scan signal SCANn, the light emission control signals EMAn and EMBn, and the compensation signals CPAn and CPBn are at a high level. Therefore, the initial state of the switch transistor T2, the light emission control transistors T3a, T3b, T6a and T6b, and the reset transistor T4, the compensation transistors T5a and T5b is cut off. Between time t1 and t2, a low pulse appears in the reset signal RSTn to turn on the reset transistor T4, thereby allowing the voltage VRST to reset the drive transistors T1a and T1b. This mechanism ensures that the drive transistors T1a and T1b can be turned on during the next display frame period. The display frame period starts from time t2. Between time t2 and t3, a low pulse appears in the scan signal SCANn, allowing the data signal DATAm to reach the first end of each of the drive transistors T1a and T1b through the switch transistor T2. At the same time, a low pulse appears in the compensation signal CPBn to turn on the compensation transistor T5b. When the compensation transistor T5b is turned on, the data signal DATAm can be transmitted to the control terminal of the driving transistor T1b through the compensation transistor T5b, thereby determining the control voltage of the driving transistor T1b. The compensation signal CPAn is maintained at a high level. Between time t3 and t4, a low pulse appears in the light emitting control signal EMBn to turn on the light emitting control transistors T3b and T6b. The light emitting control signal EMAn is maintained at a high level to keep the light emitting control transistors T3a and T6a turned off. In this way, during the time period, a small driving current can flow from the voltage PVDD terminal to the voltage PVSS terminal to drive the light emitting diode LED1 to display in a low brightness mode. At time t5, another display frame period begins. For different display frame periods, the behavior of the operating signal is similar, and for the sake of brevity, it will not be repeated here.

[0091] Fig.12 Schematic diagram of a pixel circuit 700 of another embodiment. The pixel circuit 700 may be a pixel circuit Pnm (1≤m≤M, 1≤n≤N) of one of the pixels P11-PNM, and the pixel circuit 700 may have some changes. The pixel circuit 700 includes a switch transistor T2, a drive transistor T1a and T1b, a light emission control transistor T3a and T3b, a reset transistor T4a and T4b, a compensation transistor T5a and T5b, a reference control transistor T7, capacitors C1a, C1b, C2a and C2b, and a light emitting diode LED1. The switch transistor T2, the drive transistor T1a and T1b, the light emission control transistor T3a and T3b, the reset transistor T4a and T4b, the compensation transistor T5a and T5b, and the reference control transistor T7 each include a first terminal, a second terminal, and a control terminal.

[0092] The control end of the driving transistor T1a may be coupled to the second end of the reset transistor T4a. The control end of the driving transistor T1b may be coupled to the second end of the reset transistor T4b. The second end of the driving transistor T1a may be coupled to the first end of the light emitting control transistor T3a. The second end of the driving transistor T1b may be coupled to the first end of the light emitting control transistor T3b. The light emitting diode LED1 may be coupled to the second end of the light emitting control transistor T3a and the second end of the light emitting control transistor T3b. The control ends of the reset transistors T4a and T4b are both coupled to the reset line Rn. The control ends of the compensation transistors T5a and T5b are both coupled to the scanning line Sn. The capacitor C1a may be coupled between the control end of the driving transistor T1a and the voltage source PVDD. The capacitor C1b may be coupled between the control end of the driving transistor T1b and the voltage source PVDD. The capacitor C2a may be coupled between the second end of the switch transistor T2 and the control end of the driving transistor T1a. The capacitor C2b may be coupled between the second end of the switch transistor T2 and the control end of the driving transistor T1b. The second end of the compensation transistor T5a may be coupled to the control end of the driving transistor T1a, and the first end of the compensation transistor T5a may be coupled to the second end of the driving transistor T1a. The second end of the compensation transistor T5b may be coupled to the control end of the driving transistor T1b, and the first end of the compensation transistor T5b may be coupled to the second end of the driving transistor T1b. The control end of the switch transistor T2 may be coupled to the scan line Sn. The first terminal of the switch transistor T2 may be coupled to the data line Dm. The control end of the light emitting control transistor T3a may be coupled to the light emitting control line EAn, and the control end of the light emitting control transistor T3b may be coupled to another light emitting control line EBn. The control end of the reference control transistor T7 may be coupled to the scan line Sn. The second end of the reference control transistor T7 may be coupled to the second end of the switch transistor T2.

[0093] The scan line Sn provides a scan signal SCANn to the switch transistor T2, the compensation transistors T5a and T5b, and the reference control transistor T7, so that the data line Dm writes the data signal DATAm to the control terminal of the driving transistors T1a and T1b. The voltage VREF is provided to the first terminal of the reference control transistor T7 to provide a coupling voltage for the capacitors C2a and C2b. The driving transistors T1a and T1b control the driving current according to the data signal DATAm coupled through the capacitors C2a and C2b, respectively. The capacitors C2a and C2b can be used to drive the driving transistors T1a and T1b, respectively. As the level of the data signal DATAm is higher, a higher driving current can be generated through the driving transistor T1a or T1b. The voltage PVDD is provided to the first terminal of the driving transistor T1a and the first terminal of the driving transistor T1b, and the voltage PVSS is provided to the light emitting diode LED1. In this way, the pixel circuit 700 can establish a voltage difference so that the driving current flows from the voltage PVDD terminal to the voltage PVSS terminal, wherein the voltage PVDD is greater than the voltage PVSS.

[0094] The reset line Rn provides a reset signal RSTn to the reset transistors T4a and T4b. The voltage VRST is provided to the first terminals of the reset transistors T4a and T4b. The reset transistors T4a and T4b function to set the drive transistors T1a and T1b to receive the data signal DATAm of the next display frame period.

[0095] The light emission control line EAn provides a light emission control signal EMAn having a first duty cycle to the light emission control transistor T3a. The light emission control line EBn provides a light emission control signal EMBn having a second duty cycle to the light emission control transistor T3b. In some embodiments, the first duty cycle may be different from the second duty cycle, while in some other embodiments, the first duty cycle may be the same as the second duty cycle. The light emission period of the light emitting diode LED1 is controlled by the light emission control transistors T3a and T3b according to the light emission control signals EMAn and EMBn, respectively.

[0096] The switch transistor T2, the driving transistors T1a and T1b, the light emission control transistors T3a and T3b, the reset transistors T4a and T4b, and the compensation transistors T5a and T5b may be p-type transistors. The reference control transistor T7 may be an n-type transistor. The driving transistors T1a and T1b have different channel width-to-length ratios (W / L).

[0097] In some embodiments, the driving transistor T1a may be a low temperature polysilicon (LTPS) thin film transistor. In some embodiments, the driving transistor T1b may be an oxide thin film transistor. In some embodiments, the driving transistor T1a may have a width-to-length ratio of about 20 μm / 5 μm=4 for relatively large currents. In some embodiments, the driving transistor T1b may have a width-to-length ratio of about 5 μm / 25 μm=0.2 for relatively small currents.

[0098] Please refer to Fig.13A and Fig. 13B . Fig.13A is a timing diagram of the operation signals of the pixel circuit 700 according to the embodiment of the high brightness mode. Initially, at time t0, the reset signal RSTn, the scan signal SCANn, the light emission control signals EMAn and EMBn are at a high level. Therefore, the initial state of the switching transistor T2, the light emission control transistors T3a and T3b, the reset transistors T4a and T4b, and the compensation transistors T5a and T5b is cut off, and the initial state of the reference control transistor T7 is turned on. Between time t1 and t2, a low pulse appears in the reset signal RSTn to turn on the reset transistors T4a and T4b, thereby allowing the voltage VRST to reset the drive transistors T1a and T1b. This mechanism ensures that the drive transistors T1a and T1b can be turned on during the next display frame period. The display frame period starts at time t2. Between time t2 and t3, a low pulse appears in the scan signal SCANn to turn on the switch transistor T2 and the compensation transistors T5a and T5b and turn off the reference transistor T7, allowing the data signal DATAm to pass through the switch transistor T2 and couple to the respective capacitors C2a and C2b, thereby controlling the drive transistors T1a and T1b. Between time t3 and t4, a low pulse appears in the light-emitting control signal EMAn to turn on the light-emitting control transistor T3a. The light-emitting control signal EMBn is maintained at a high level to keep the light-emitting control transistor T3b turned off. In this way, during the time period, a large drive current can flow from the voltage PVDD terminal to the voltage PVSS terminal to drive the light-emitting diode LED1 to display in a high-brightness mode. At time t5, another display frame period begins. For different display frame periods, the behavior of the operating signal is similar, and for the sake of brevity, it will not be repeated here.

[0099] Fig. 13Bis a timing diagram of the operation signals of the pixel circuit 700 according to the embodiment of the low brightness mode. Initially, at time t0, the reset signal RSTn, the scan signal SCANn, the light emission control signals EMAn and EMBn are at a high level. Therefore, the initial state of the switching transistor T2, the light emission control transistors T3a and T3b, the reset transistors T4a and T4b, and the compensation transistors T5a and T5b is cut off, and the initial state of the reference control transistor T7 is turned on. Between time t1 and t2, a low pulse appears in the reset signal RSTn to turn on the reset transistors T4a and T4b, thereby allowing the voltage VRST to reset the drive transistors T1a and T1b. This mechanism ensures that the drive transistors T1a and T1b can be turned on during the next display frame period. The display frame period starts from time t2. Between time t2 and t3, a low pulse appears in the scan signal SCANn to turn on the switch transistor T2 and the compensation transistors T5a and T5b and turn off the reference transistor T7, allowing the data signal DATAm to pass through the switch transistor T2 and couple to the respective capacitors C2a and C2b, thereby controlling the drive transistors T1a and T1b. Between time t3 and t4, a low pulse appears in the light emitting control signal EMBn to turn on the light emitting control transistor T3b. The light emitting control signal EMAn is maintained at a high level to keep the light emitting control transistor T3a turned off. In this way, during the time period, a small drive current can flow from the voltage PVDD terminal to the voltage PVSS terminal to drive the light emitting diode LED1 to display in a low brightness mode. At time t5, another display frame period begins. For different display frame periods, the behavior of the operating signal is similar, and for the sake of brevity, it will not be repeated here.

[0100] Fig.14 Schematic diagram of a pixel circuit 800 of another embodiment. The pixel circuit 800 may be a pixel circuit Pnm (1≤m≤M, 1≤n≤N) of one of the pixels P11-PNM, and the pixel circuit 800 may have some changes. The pixel circuit 800 includes a switch transistor T2, a drive transistor T1a and T1b, a light emission control transistor T3a and T3b, a reset transistor T4, a compensation transistor T5a and T5b, a reference control transistor T7, capacitors C1, C2, and a light emitting diode LED1. The switch transistor T2, the drive transistor T1a and T1b, the light emission control transistor T3a and T3b, the reset transistor T4, the compensation transistor T5a and T5b, and the reference control transistor T7 each include a first terminal, a second terminal, and a control terminal.

[0101] The control terminals of the driving transistors T1a and T1b may be coupled to the second terminal of the reset transistor T4. The second terminal of the driving transistor T1a may be coupled to the first terminal of the light emitting control transistor T3a. The second terminal of the driving transistor T1b may be coupled to the first terminal of the light emitting control transistor T3b. The light emitting diode LED1 may be coupled to the second terminal of the light emitting control transistor T3a and the second terminal of the light emitting control transistor T3b. The control terminal of the reset transistor T4 may be coupled to the reset line Rn. The control terminal of the compensation transistor T5a may be coupled to the compensation line CAn, and the control terminal of the compensation transistor T5b may be coupled to another compensation line CBn. The capacitor C1 may be coupled between the control terminal of the driving transistor T1a and the voltage source PVDD. The capacitor C2 may be coupled between the second terminal of the switch transistor T2 and the control terminal of the driving transistor T1a. The second terminal of the compensation transistor T5a may be coupled to the control terminal of the driving transistor T1a, and the first terminal of the compensation transistor T5a may be coupled to the second terminal of the driving transistor T1a. The second end of the compensation transistor T5b may be coupled to the control end of the driving transistor T1b, and the first end of the compensation transistor T5b may be coupled to the second end of the driving transistor T1b. The control end of the switch transistor T2 may be coupled to the scan line Sn. The first end of the switch transistor T2 may be coupled to the data line Dm. The control end of the light emitting control transistor T3a may be coupled to the light emitting control line EAn, and the control end of the light emitting control transistor T3b may be coupled to another light emitting control line EBn. The control end of the reference control transistor T7 may be coupled to the scan line Sn. The second end of the reference control transistor T7 may be coupled to the second end of the switch transistor T2.

[0102] The scan line Sn provides a scan signal SCANn to the switch transistor T2 and the reference control transistor T7, so that the data line Dm writes the data signal DATAm to the control terminal of the driving transistors T1a and T1b. The voltage VREF is provided to the first terminal of the reference control transistor T7 to provide a coupling voltage for the capacitor C2. The driving transistors T1a and T1b control the driving current according to the data signal DATAm coupled by the capacitor C2. The capacitor C2 can be used to drive the driving transistors T1a and T1b. As the level of the data signal DATAm is higher, a higher driving current can be generated through the driving transistor T1a or T1b. The voltage PVDD is provided to the first terminal of the driving transistor T1a and the first terminal of the driving transistor T1b, and the voltage PVSS is provided to the light emitting diode LED1. In this way, the pixel circuit 800 can establish a voltage difference so that the driving current flows from the voltage PVDD terminal to the voltage PVSS terminal, wherein the voltage PVDD is greater than the voltage PVSS.

[0103] The reset line Rn provides a reset signal RSTn to the reset transistor T4. The voltage VRST is provided to the first terminal of the reset transistor T4. The reset transistor T4 is used to set the driving transistors T1a and T1b to receive the data signal DATAm in the next display frame period. The compensation lines CAn and CBn provide compensation signals CPAn and CPBn respectively to independently control the compensation transistors T5a and T5b.

[0104] The light emission control line EAn provides a light emission control signal EMAn having a first duty cycle to the light emission control transistor T3a. The light emission control line EBn provides a light emission control signal EMBn having a second duty cycle to the light emission control transistor T3b. In some embodiments, the first duty cycle may be different from the second duty cycle, while in some other embodiments, the first duty cycle may be the same as the second duty cycle. The light emission period of the light emitting diode LED1 is controlled by the light emission control transistors T3a and T3b according to the light emission control signals EMAn and EMBn, respectively.

[0105] The switch transistor T2, the driving transistors T1a and T1b, the light emission control transistors T3a and T3b, the reset transistor T4, the compensation transistors T5a and T5b may be p-type transistors. The reference control transistor T7 may be an n-type transistor. The driving transistors T1a and T1b have different channel width-to-length ratios (W / L).

[0106] In some embodiments, the driving transistor T1a may be a low temperature polysilicon (LTPS) thin film transistor. In some embodiments, the driving transistor T1b may be an oxide thin film transistor. In some embodiments, the driving transistor T1a may have a width-to-length ratio of about 20 μm / 5 μm=4 for relatively large currents. In some embodiments, the driving transistor T1b may have a width-to-length ratio of about 5 μm / 25 μm=0.2 for relatively small currents.

[0107] Please refer to Fig.15A and Fig. 15B . Fig.15A8 is a timing diagram of the operation signals of the pixel circuit 800 according to the embodiment of the high brightness mode. Initially, at time t0, the reset signal RSTn, the scan signal SCANn, the light emission control signals EMAn and EMBn, and the compensation signals CPAn and CPBn are at a high level. Therefore, the initial state of the switching transistor T2, the light emission control transistors T3a and T3b, the reset transistor T4, and the compensation transistors T5a and T5b is cut off, and the initial state of the reference control transistor T7 is turned on. Between time t1 and t2, a low pulse appears in the reset signal RSTn to turn on the reset transistor T4, thereby allowing the voltage VRST to reset the drive transistors T1a and T1b. This mechanism ensures that the drive transistors T1a and T1b can be turned on during the next display frame period. The display frame period starts at time t2. Between time t2 and t3, a low pulse appears in the scan signal SCANn to turn on the switch transistor T2 and turn off the reference transistor T7, allowing the data signal DATAm to pass through the switch transistor T2 and couple to the capacitor C2, thereby controlling the drive transistors T1a and T1b. At the same time, a low pulse appears in the compensation signal CPAn to turn on the compensation transistor T5a. The compensation signal CPBn is maintained at a high level. Between time t3 and t4, a low pulse appears in the light-emitting control signal EMAn to turn on the light-emitting control transistor T3a. The light-emitting control signal EMBn is maintained at a high level to keep the light-emitting control transistor T3b turned off. In this way, during the time period, a large drive current can flow from the voltage PVDD terminal to the voltage PVSS terminal to drive the light-emitting diode LED1 to display in a high-brightness mode. At time t5, another display frame period begins. For different display frame periods, the behavior of the operating signal is similar, and for the sake of brevity, it is not repeated here.

[0108] Fig. 15B8 is a timing diagram of the operation signals of the pixel circuit 800 according to the embodiment of the low brightness mode. Initially, at time t0, the reset signal RSTn, the scan signal SCANn, the light emission control signals EMAn and EMBn, and the compensation signals CPAn and CPBn are at a high level. Therefore, the initial state of the driving transistors T1a and T1b, the switching transistor T2, the light emission control transistors T3a and T3b, the reset transistor T4, and the compensation transistors T5a and T5b is cut off, and the initial state of the reference control transistor T7 is turned on. Between time t1 and t2, a low pulse appears in the reset signal RSTn to turn on the reset transistor T4, thereby allowing the voltage VRST to reset the driving transistors T1a and T1b. This mechanism ensures that the driving transistors T1a and T1b can be turned on during the next display frame period. The display frame period starts from time t2. Between time t2 and t3, a low pulse appears in the scan signal SCANn to turn on the switch transistor T2 and turn off the reference transistor T7, so that the data signal DATAm passes through the switch transistor T2 and is coupled to the capacitor C2, thereby controlling the driving transistors T1a and T1b. At the same time, a low pulse appears in the compensation signal CPBn to turn on the compensation transistor T5b. The compensation signal CPAn is maintained at a high level. Between time t3 and t4, a low pulse appears in the light-emitting control signal EMBn to turn on the light-emitting control transistor T3b. The light-emitting control signal EMAn is maintained at a high level to keep the light-emitting control transistor T3a turned off. In this way, during the time period, a small driving current can flow from the voltage PVDD terminal to the voltage PVSS terminal to drive the light-emitting diode LED1 to display in a low brightness mode. At time t5, another display frame period begins. For different display frame periods, the behavior of the operating signal is similar, and for the sake of brevity, it is not repeated here.

[0109] In the above embodiments, the control terminal of the transistor may be a gate; the first terminal of the transistor may be a source; and the second terminal of the transistor may be a drain. According to the implementation, the source and the drain may be reversed.

[0110] Fig.16 The brightness mode control system 20 of the embodiment of the present invention is shown in FIG. The brightness mode control system 20 may be coupled to the display panel 10 and includes an ambient light sensor 21, an illumination intensity comparator 22 coupled to the ambient light sensor 21, and a display controller 23 coupled to the illumination intensity comparator 22. The display controller 23 has a timing controller 24, a display data processor 25, and a grayscale controller 26. The grayscale controller 26 has a high brightness mode lookup table (look-up table, LUT) 27 and a low brightness mode lookup table (look-up table, LUT) 28.

[0111] The ambient light sensor 21 can detect the intensity of ambient light. The illumination intensity comparator 22 can decide whether to turn on the high brightness mode or the low brightness mode according to the intensity of the ambient light, and generate a brightness mode signal SIG_BM. The timing controller 24 cooperates with the display processor 25 to generate a control signal (e.g., a scan signal, a light control signal, a reset signal, and a compensation signal) for the vertical driver 2 according to the brightness mode signal SIG_BM and the display signal SIG_D. The grayscale controller 26 can generate a control signal (e.g., a data signal and a gamma voltage) for the data driver 3 according to the brightness mode signal SIG_BM and the display signal SIG_D. In addition, if the illumination intensity comparator 22 determines to enable the high brightness mode, the high brightness mode lookup table 27 will be used to generate the data driver control signal. On the other hand, if the illumination intensity comparator 22 determines to enable the low brightness mode, the low brightness mode lookup table 28 will be used to generate the data driver control signal.

[0112] In each of the embodiments provided above, a wide range of display brightness modes can be achieved, and the accuracy of grayscale can be improved, especially in low brightness mode.

[0113] The above description is only an embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A pixel circuit for large brightness display, characterized in that: Include: a switching transistor; a first driving transistor coupled to the switch transistor; a second driving transistor coupled to the switch transistor; a first light emitting control transistor, coupled to the first driving transistor; a second light emitting control transistor, coupled to the second driving transistor; and A light emitting diode is coupled to the first light emitting control transistor and the second light emitting control transistor.

2. The pixel circuit according to claim 1, wherein: The device also includes a capacitor coupled to a control terminal of the first driving transistor.

3. The pixel circuit according to claim 1, wherein: The first driving transistor and the second driving transistor include different semiconductor materials.

4. The pixel circuit according to claim 3, characterized in that: The first driving transistor is a low temperature polysilicon thin film transistor.

5. The pixel circuit according to claim 3, characterized in that: The second driving transistor is an oxide thin film transistor.

6. The pixel circuit according to claim 1, wherein: The first driving transistor and the second driving transistor have different channel width-to-length ratios.

7. The pixel circuit according to claim 1, wherein: The first driving transistor, the second driving transistor, the first light emission control transistor, and the second light emission control transistor are n-type transistors.

8. The pixel circuit according to claim 1, wherein: The first driving transistor, the second driving transistor, the first light emission control transistor, and the second light emission control transistor are p-type transistors.

9. The pixel circuit according to claim 1, wherein: Also includes: a first light emitting control line, coupled to the first light emitting control transistor; and a second light emitting control line, coupled to the second light emitting control transistor; The first light emitting control line provides a first signal having a first duty cycle to the first light emitting control transistor, and the second light emitting control line provides a second signal having a second duty cycle to the second light emitting control transistor.

10. The pixel circuit according to claim 1, wherein: Also includes: a first reset transistor coupled to a control terminal of the first driving transistor; a second reset transistor coupled to a control terminal of the second driving transistor; a first compensation transistor coupled to a second terminal of the first driving transistor; a second compensation transistor coupled to a second terminal of the second driving transistor; a third light emitting control transistor, coupled to a first terminal of the first driving transistor; a fourth light emitting control transistor, coupled to a first terminal of the second driving transistor; a first capacitor coupled to the control terminal of the first driving transistor; and A second capacitor is coupled to the control terminal of the second driving transistor.

11. The pixel circuit according to claim 10, characterized in that: Also includes: a reset line coupled to a control terminal of the first reset transistor and a control terminal of the second reset transistor; a scan line coupled to a control terminal of the switch transistor, a control terminal of the first compensation transistor, and a control terminal of the second compensation transistor; a first light emitting control line coupled to a control terminal of the first light emitting control transistor and a control terminal of the third light emitting control transistor; and a second light emitting control line coupled to a control terminal of the second light emitting control transistor and a control terminal of the fourth light emitting control transistor; in: The first light emission control line provides a first signal having a first duty ratio to the first light emission control transistor and the third light emission control transistor, and the second light emission control line provides a second signal having a second duty ratio to the second light emission control transistor and the fourth light emission control transistor; and The reset line provides a reset signal to the first reset transistor and the second reset transistor.

12. The pixel circuit according to claim 10, wherein: The first reset transistor, the second reset transistor, the first compensation transistor, the second compensation transistor, the third light emission control transistor, and the fourth light emission control transistor are p-type transistors.

13. The pixel circuit according to claim 1, wherein: Also includes: a first reset transistor coupled to a control terminal of the first driving transistor; a first compensation transistor coupled to a second terminal of the first driving transistor; a second compensation transistor coupled to a second terminal of the second driving transistor; a third light emitting control transistor, coupled to a first terminal of the first driving transistor; a fourth light emitting control transistor, coupled to a first terminal of the second driving transistor; and A first capacitor is coupled to the control terminal of the first driving transistor and a control terminal of the second driving transistor.

14. The pixel circuit according to claim 13, characterized in that: Also includes: a reset line coupled to a control terminal of the first reset transistor; A scan line coupled to a control terminal of the switch transistor; a first light emitting control line coupled to a control terminal of the first light emitting control transistor and a control terminal of the third light emitting control transistor; a second light emitting control line coupled to a control terminal of the second light emitting control transistor and a control terminal of the fourth light emitting control transistor; a first compensation line coupled to a control terminal of the first compensation transistor; and a second compensation line coupled to a control terminal of the second compensation transistor; in: The first light emission control line provides a first signal having a first duty ratio to the first light emission control transistor and the third light emission control transistor, and the second light emission control line provides a second signal having a second duty ratio to the second light emission control transistor and the fourth light emission control transistor; The reset line provides a reset signal to the first reset transistor; and The first compensation line provides a first compensation signal to the first compensation transistor, and the second compensation line provides a second compensation signal to the second compensation transistor.

15. The pixel circuit according to claim 1, wherein: Also includes: a first reset transistor coupled to a control terminal of the first driving transistor; a second reset transistor coupled to a control terminal of the second driving transistor; a first compensation transistor coupled to a second terminal of the first driving transistor; a second compensation transistor coupled to a second terminal of the second driving transistor; a reference control transistor coupled to a second terminal of the switch transistor; a first capacitor coupled to a control terminal of the first driving transistor; a second capacitor coupled to a control terminal of the second driving transistor; a third capacitor coupled between a second terminal of the reference control transistor and a control terminal of the first driving transistor; and A fourth capacitor is coupled between the second terminal of the reference control transistor and a control terminal of the second driving transistor.

16. The pixel circuit according to claim 15, characterized in that: Also includes: a reset line coupled to a control terminal of the first reset transistor and a control terminal of the second reset transistor; a scan line coupled to a control terminal of the switch transistor, a control terminal of the first compensation transistor, and a control terminal of the second compensation transistor; a first light emitting control line coupled to a control terminal of the first light emitting control transistor; and a second light emitting control line coupled to a control terminal of the second light emitting control transistor; in: The first light emission control line provides a first signal having a first duty cycle to the first light emission control transistor, and the second light emission control line provides a second signal having a second duty cycle to the second light emission control transistor; and The reset line provides a reset signal to the first reset transistor and the second reset transistor.

17. The pixel circuit according to claim 1, wherein: Also includes: a first reset transistor coupled to a control terminal of the first driving transistor; a first compensation transistor coupled to a second terminal of the first driving transistor; a second compensation transistor coupled to a second terminal of the second driving transistor; a reference control transistor coupled to a second terminal of the switch transistor; a first capacitor coupled to a control terminal of the first driving transistor; and A third capacitor is coupled between a second terminal of the reference control transistor and the control terminal of the first driving transistor.

18. The pixel circuit according to claim 17, wherein: Also includes: a reset line coupled to a control terminal of the first reset transistor; A scan line coupled to a control terminal of the switch transistor; a first light emitting control line coupled to a control terminal of the first light emitting control transistor; a second light emitting control line coupled to a control terminal of the second light emitting control transistor; a first compensation line coupled to a control terminal of the first compensation transistor; and a second compensation line coupled to a control terminal of the second compensation transistor; in: The first light emission control line provides a first signal having a first duty ratio to the first light emission control transistor and the third light emission control transistor, and the second light emission control line provides a second signal having a second duty ratio to the second light emission control transistor and the fourth light emission control transistor; The reset line provides a reset signal to the first reset transistor; and The first compensation line provides a first compensation signal to the first compensation transistor, and the second compensation line provides a second compensation signal to the second compensation transistor.

19. A pixel circuit for large brightness display, characterized in that: Include: a switching transistor; a first driving transistor coupled to the switch transistor; a second driving transistor coupled to the switch transistor; a first light emitting control transistor, coupled to the first driving transistor; a second light emitting control transistor, coupled to the second driving transistor; a capacitor coupled to a control terminal of the first driving transistor; and A light emitting diode is coupled to the first light emitting control transistor and the second light emitting control transistor.

20. The pixel circuit according to claim 19, characterized in that: Also includes: a first light emitting control line, coupled to the first light emitting control transistor; and a second light emitting control line, coupled to the second light emitting control transistor; The first light emitting control line provides a first signal having a first duty cycle to the first light emitting control transistor, and the second light emitting control line provides a second signal having a second duty cycle to the second light emitting control transistor.

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