Low dielectric absorption low mismatch precision linear MIM capacitor and integration technology

Abstract

The invention discloses a low-dielectric-absorption low-mismatch precision linear MIM capacitor and an integration technology. The integration technology comprises the following steps: 1) forming an active region and an isolation field oxygen region; and 2) forming a thick gate oxide layer and a thin gate oxide layer. And 3) depositing a polysilicon layer, and constructing a polysilicon gate of the MOS tube. And 4) completing photoetching injection of the source electrode and the drain electrode of the multi-mode gate oxide high-low voltage BiCMOS / CMOS. And 5) improving the flatness of the lower surface area of the metal film resistor through chemical mechanical planarization. And (6) sputtering a high-resistivity microcrystalline titanium film on the lower electrode of the metal MIM capacitor by a PVD (Physical Vapor Deposition) method. And (7) depositing PECVD (plasma enhanced chemical vapor deposition) silicon nitride (Si < x > N < y > Hz) on a metal MIM capacitor dielectric layer. And (8) sputtering a high-resistivity microcrystalline titanium film on the upper electrode of the metal MIM capacitor by a PVD (Physical Vapor Deposition) method. And 9) sputtering an aluminum-copper film layer and completing the etching processing of a metal connecting wire. According to the invention, the precision matching problem of the metal MIM capacitor is optimized, the packaging function density and the device density of the integrated circuit are improved, and the miniaturization and the light weight of the high-performance integrated circuit are promoted.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuits, in particular to low dielectric absorption and low mismatch precision linear MIM capacitors and integration technology. Background Art

[0002] In the field of high-performance analog signal or mixed-signal integrated circuit manufacturing, the accuracy of integrated capacitors used in AD / DA data converters, smart sensors, and other signal processing circuits directly limits the accuracy and performance of these integrated circuits. Metal MIM capacitors have excellent electrical characteristics such as ideal parasitic substrate capacitance noise self-limitation and no depletion effect of capacitor plates. At the same time, metal MIM capacitors are also easy to integrate with standard analog integrated circuit metal interconnection processes. The mismatch of metal MIM capacitors calibrated by nonlinear processes can be controlled within ±0.001%, so integrating metal MIM capacitors with almost ideal linearity into high-performance integrated circuits has become an important task in the research and development of BiCMOS / CMOS / Bipolar special processes.

[0003] In order to meet the needs of miniaturization and lightweight of integrated circuits, it is necessary to use capacitor dielectric materials such as SiN or TaN with higher dielectric constants than SiO2 to increase the unit capacitance of metal MIM capacitors. Due to the limitations of the thermal budget of the applicable process of the metal interconnect film layer, the defects such as microcracks and pinholes in the dielectric film layer of the MIM capacitor will be higher than those of materials with the same chemical ratio in high-temperature processes. Therefore, factors such as the body trap density of the dielectric film layer of the metal MIM capacitor, the dielectric-metal interface state, and the stress mismatch between the capacitor dielectric and the metal film layer have become the main sources affecting the performance of metal capacitors.

[0004] On the other hand, the capacitance of metal MIM capacitors will shift with the operating frequency and bias voltage, which will cause analog signal distortion. This capacitance shift will even be transmitted to a higher operating frequency state, eventually forming positive feedback and causing circuit failure. Therefore, using process calibration technology to improve dielectric strength and reduce dielectric absorption coefficient to improve hysteresis, mismatch, and nonlinear effects of metal MIM capacitors has always been a hot and difficult issue in academic research and technological innovation. Summary of the invention

[0005] The object of the present invention is to provide a low dielectric absorption low mismatch precision linear MIM capacitor and integration technology, comprising the following steps:

[0006] 1) forming a well on the surface of the substrate, forming an active area on the surface of the well, and forming an isolation oxide layer in the area outside the active area;

[0007] 2) Selecting the metal film resistor area, the high voltage device active area, the medium voltage device active area and the low voltage device active area that require a low temperature coefficient;

[0008] 3) forming a thick gate oxide layer in the active region of the high voltage device and the active region of the medium voltage device respectively; forming a thin gate oxide layer in the active region of the low voltage device;

[0009] 4) Forming the polysilicon gate of the MOS tube and selecting the doped source and drain regions of the MOS tube;

[0010] 5) Complete the photolithography implantation of the dual-gate oxide high-low voltage CMOS source and drain in the doped source and drain regions of the MOS tube, and activate the doped impurities by rapid annealing process;

[0011] 6) Depositing a silicon nitride layer and a BPSG low dielectric constant filling film layer;

[0012] 7) Complete the film flattening process and device contact hole processing;

[0013] 8) Complete the tungsten plug filling process of the device contact hole; sputter the aluminum silicon copper film layer, which is recorded as the first layer of metal, and complete the first layer of metal wiring etching process;

[0014] 9) Repeat steps 6) to 8) according to the circuit design requirements until the next top metal layer is sputtered, which is recorded as the (n-1)th metal layer;

[0015] 10) After the argon atom sputtering cleaning is completed, a h1 angstrom titanium film layer is sputtered, and then a h2 angstrom amorphous silicon nitride SixNyHz film layer is deposited;

[0016] 11) After the argon atom sputtering cleaning is completed, a h3 angstrom microcrystalline titanium film is sputtered on the silicon nitride film layer;

[0017] 12) depositing h4 angstrom semicrystalline titanium / h5 angstrom titanium nitride in an integrated magnetron sputtering chamber;

[0018] 13) Using PVD method to sputter aluminum alloy film and anti-reflective titanium nitride film layer suitable for planarization process integration;

[0019] 14) According to the mask layout, the titanium / titanium nitride / aluminum silicon copper / titanium nitride upper plate of the MIM capacitor is exposed, developed, and dry-etched to form an integrated metal-silicon nitride-metal capacitor;

[0020] The formed integrated metal-silicon nitride-metal capacitor has a dielectric absorption coefficient DA ≤ 30ppm, a second-order voltage coefficient abs (QVC) ≤ 3ppm / V2, and a linear voltage coefficient abs (LVC) ≤ 1.5ppm / V;

[0021] 15) Deposition of low dielectric constant filling film layer USG film, CMP planarization of metal interlayer, through hole etching, chemical mechanical planarization of tungsten plug,

[0022] 16) Sputtering the top metal layer, recorded as the nth metal layer, and completing the nth metal wiring etching process to form the metal interconnection of the circuit components;

[0023] 17) The passivation composite dielectric layer is deposited by PECVD, and the passivation protective layer is exposed, developed, and etched.

[0024] Furthermore, in step 4), the steps of forming the polysilicon gate of the MOS tube include: depositing a gate polysilicon layer on the surface, doping the polysilicon layer, and then etching the gate polycrystalline structure, so that the gate oxide layer and the polysilicon on the surface of the gate oxide layer constitute the polysilicon gate of the MOS tube.

[0025] Further, in step 6), a silicon nitride layer is deposited by low pressure chemical vapor deposition; a BPSG low dielectric constant filling film layer is deposited by PECVD;

[0026] In step 7), a chemical mechanical polishing (CMP) process is used to planarize the film layer; a dry etching process is used to process the device contact holes;

[0027] In step 8), a tungsten sputtering process and a tungsten chemical mechanical planarization process are used to complete the device contact hole tungsten plug filling process;

[0028] In step 10), a h1 angstrom titanium film layer is sputtered by magnetron plasma physical vapor phase PVD method; and a h2 angstrom amorphous silicon nitride SixNyHz film layer is deposited by plasma enhanced chemical vapor phase PECVD;

[0029] In step 11), a h3 angstrom microcrystalline titanium film is sputtered by a magnetron plasma physical vapor phase PVD method;

[0030] In step 12), h4 angstrom semi-crystalline titanium / h5 angstrom titanium nitride is deposited by PVD in situ by surface chemical reaction;

[0031] In step 15), a low dielectric constant filling film layer USG film is deposited by PECVD method;

[0032] Further, in step 9), the interconnect structure film layer of the (n-1)th metal layer is tungsten / titanium / aluminum silicon copper / titanium nitride;

[0033] In step 16), the circuit components include MOS devices and MIM capacitors.

[0034] Further, n≥2; h1=50 ～ 300 angstroms; h2 ≥ 180 angstroms; h3 = 150 ～ 300 angstroms; h4 = 50 ～ 100 angstroms; h5 = 100 ～300 angstrom; DA≤30ppm; abs(QVC)≤3ppm / V2; abs(LVC)≤1.5ppm / V.

[0035] Furthermore, the impurities are P-type impurities or N-type impurities.

[0036] Furthermore, a chemical mechanical planarization process is used to planarize the (n-1)-layer intermetallic dielectric layer to form a global planarized dielectric layer and a tungsten plug structure.

[0037] Furthermore, a high dielectric constant silicon-rich silicon nitride film deposited by PECVD is used as the dielectric layer of the metal MIM capacitor.

[0038] Furthermore, a high selectivity tungsten-silicon dioxide chemical mechanical planarization process is used to complete the processing of the tungsten plug structure.

[0039] The metal MIM capacitor module obtained by using the low dielectric absorption low mismatch precision linear MIM capacitor and integration technology mainly includes a substrate, a well, a field oxide layer, a dielectric layer, a thick gate oxide layer, a thin gate oxide layer, a polysilicon gate and a metal film layer;

[0040] The substrate is located at the bottom; the well is formed on the surface of the substrate;

[0041] The field oxide layer is formed outside the active area;

[0042] The active area includes a high voltage device area, a medium voltage device area and a low voltage device area;

[0043] A thick gate oxide layer is provided in the high voltage device region and the medium voltage device region;

[0044] A thin gate oxide layer in the low voltage device area;

[0045] The metal MIM capacitor is formed in the middle of the dielectric layer between the (n-1)th metal layer and the nth metal layer;

[0046] The polysilicon gate of the MOS tube is constructed on a thick gate oxide layer and a thin gate oxide layer.

[0047] The technical effect of the present invention is unquestionable. The present invention solves the problem of nonlinear process calibration of metal MIM capacitors, the problem of reducing the dielectric absorption coefficient of metal MIM capacitors, and the problem of precise matching of metal MIM capacitors.

[0048] The present invention generates a metal MIM capacitor on the middle area between the sub-top metal and the top metal dielectric film layer of the multi-mode gate oxide high-low voltage compatible BiCMOS / CMOS process, thereby reducing the parasitic substrate capacitance crosstalk noise of the metal MIM capacitor and improving the packaging function density of the integrated circuit.

[0049] The present invention solves the problem of accurately controlling the non-planarity of metal film MIM capacitors by chemically and mechanically flattening the lower surface area of ​​metal MIM capacitors, reduces the steps of metal MIM capacitor film layers and the stress between film layers, and improves the long-term stability of matching metal MIM capacitors.

[0050] The present invention improves the interface trap density between the metal electrode film layer and the capacitor medium of the metal MIM capacitor, thereby improving the polarization and depolarization performance of the metal MIM capacitor medium, improving the capacitance value deviation performance of the metal MIM capacitor caused by changes in operating frequency and bias voltage, and optimizing the nonlinear mismatch problem of the metal MIM capacitor.

[0051] The present invention improves the metal capacitor electrode film system by sputtering a microcrystalline titanium film of suitable thickness by magnetron plasma PVD method. It reduces the compressive stress of the aluminum alloy film layer of the lower electrode of the metal MIM capacitor, improves the surface unevenness such as Hilllock defect of the metal film layer, and provides a dielectric layer PECVD silicon nitride Si x N y H z It provides an excellent film-forming environment, reduces the probability of inter-layer pinhole defects, and further improves the silicon nitride Si x N y H z Dielectric strength and capacitor operating voltage range.

[0052] The present invention uses in-situ PVD deposition of semi-crystalline titanium / titanium nitride composite film layer in an integrated magnetron sputtering chamber to improve the metal film layer and dielectric silicon nitride Si x N y H z The dry etching selectivity ratio can not only ensure the process control accuracy of the geometric dimensions of the electrode on the metal MIM capacitor, but also avoid problems such as metal capacitor short circuit. More importantly, it can also reduce the thickness of the dielectric film layer between capacitors and increase the unit capacitance of the capacitor, thereby increasing the device density of the integrated circuit and promoting the miniaturization and lightweight of the integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 A cross-sectional view of the shield oxide layer grown after completing conventional CMOS processes such as well implantation, annealing, and field oxidation;

[0054] Figure 2 Cross-sectional view after the thick gate oxide layer is grown to complete the high voltage device;

[0055] Figure 3 A cross-sectional view of growing a thin gate oxide layer after stripping off the thick gate oxide layer;

[0056] Figure 4A cross-sectional view of a MOS tube after light doping implantation in the source and drain regions and etching of the gate polycrystalline sidewalls to form a gate polycrystalline sidewall protection structure;

[0057] Figure 5 To complete the global planarization of the silicon-metal inter-dielectric filling layer, the tungsten plug structure, and the cross-sectional view after the first metal layer is etched;

[0058] Figure 6 The cross-sectional view of the global planarization and tungsten plug structure after the sputtering deposition of the second top metal layer (denoted as the (n-1)th layer);

[0059] Figure 7 , a cross-sectional view after the magnetron plasma physical vapor phase PVD microcrystalline titanium metal film deposition is completed on the second top metal layer (denoted as the (n-1)th layer);

[0060] Figure 8 It is a cross-sectional view of a microcrystalline titanium metal film after the deposition of a silicon-rich silicon nitride film by plasma enhanced chemical vapor phase PECVD is completed on the second top metal layer (denoted as the (n-1)th layer);

[0061] Fig. 9 It is a cross-sectional view of the metal MIM capacitor dielectric silicon nitride film layer after the magnetron plasma physical vapor phase PVD microcrystalline titanium metal film deposition is completed;

[0062] Fig.10 The cross-sectional view after sputtering deposition of the metal film layer system (semi-crystalline titanium / titanium nitride / aluminum silicon copper / titanium nitride) of the upper electrode of the metal MIM capacitor;

[0063] Fig.11 A cross-sectional view of the metal MIM capacitor structure after completing the exposure, etching, dielectric filling, tungsten plug filling, and planarization process steps;

[0064] Fig.12 It is a schematic diagram of the integration of the metal MIM capacitor module and the multi-mode gate oxide high and low voltage compatible BiCMOS / CMOS process platform;

[0065] In the figure, 101, the sub-top metal; 102, the high-resistivity microcrystalline titanium film (preferred) of the lower electrode of the metal MIM capacitor; 103, the PECVD silicon-rich silicon nitride film layer of the metal MIM capacitor dielectric; 104, the high-resistivity microcrystalline titanium film (preferred) of the upper electrode of the metal MIM capacitor; 105, the tungsten plug interconnecting the top metal and the sub-top metal; 201, the tungsten plug interconnecting the lower electrode of the metal MIM capacitor and the top metal; 202, the top metal system; 203, the metal system of the upper electrode of the metal MIM capacitor; 204, the low-resistivity semi-crystalline titanium film layer of the upper electrode of the metal MIM capacitor; 205, the titanium nitride film layer of the barrier layer of the upper electrode of the metal MIM capacitor. DETAILED DESCRIPTION

[0066] The present invention is further described below in conjunction with the embodiments, but it should not be understood that the above subject matter of the present invention is limited to the following embodiments. Without departing from the above technical ideas of the present invention, various substitutions and changes are made according to the common technical knowledge and customary means in the art, which should all be included in the protection scope of the present invention.

[0067] Embodiment 1:

[0068] See also Figure 1-Figure 12 , a low dielectric absorption and low mismatch precision linear MIM capacitor integration method, comprising the following steps:

[0069] 1) forming a well on the surface of the substrate, forming an active area on the surface of the well, and forming an isolation oxide layer in the area outside the active area;

[0070] 2) Selecting the metal film resistor area, the high voltage device active area, the medium voltage device active area and the low voltage device active area that require a low temperature coefficient;

[0071] 3) forming a thick gate oxide layer in the active region of the high voltage device and the active region of the medium voltage device respectively; forming a thin gate oxide layer in the active region of the low voltage device;

[0072] 4) Forming the polysilicon gate of the MOS tube and selecting the doped source and drain regions of the MOS tube;

[0073] 5) Complete the photolithography implantation of the dual-gate oxide high-low voltage CMOS source and drain in the doped source and drain regions of the MOS tube, and activate the doped impurities by rapid annealing process;

[0074] 6) Depositing a silicon nitride layer and a BPSG low dielectric constant filling film layer;

[0075] 7) Complete the film flattening process and device contact hole processing;

[0076] 8) Complete the tungsten plug filling process of the device contact hole; sputter the aluminum silicon copper film layer, which is recorded as the first layer of metal, and complete the first layer of metal wiring etching process;

[0077] 9) Repeat steps 6) to 8) according to the circuit design requirements until the next top metal layer is sputtered, which is recorded as the (n-1)th metal layer;

[0078] 10) After the argon atom sputtering cleaning is completed, a h1 angstrom titanium film layer is sputtered, and then a h2 angstrom amorphous silicon nitride SixNyHz film layer is deposited;

[0079] 11) After the argon atom sputtering cleaning is completed, a h3 angstrom microcrystalline titanium film is sputtered on the silicon nitride film layer;

[0080] 12) depositing h4 angstrom semicrystalline titanium / h5 angstrom titanium nitride in an integrated magnetron sputtering chamber;

[0081] 13) Using PVD method to sputter aluminum alloy film and anti-reflective titanium nitride film layer suitable for planarization process integration;

[0082] 14) According to the mask layout, the titanium / titanium nitride / aluminum silicon copper / titanium nitride upper plate of the MIM capacitor is exposed, developed, and dry-etched to form an integrated metal-silicon nitride-metal capacitor;

[0083] The formed integrated metal-silicon nitride-metal capacitor has a dielectric absorption coefficient DA ≤ 30ppm, a second-order voltage coefficient abs (QVC) ≤ 3ppm / V2, and a linear voltage coefficient abs (LVC) ≤ 1.5ppm / V;

[0084] 15) Deposition of low dielectric constant filling film layer USG film, CMP planarization of metal interlayer, through hole etching, chemical mechanical planarization of tungsten plug,

[0085] 16) Sputtering the top metal layer, recorded as the nth metal layer, and completing the nth metal wiring etching process to form the metal interconnection of the circuit components;

[0086] 17) The passivation composite dielectric layer is deposited by PECVD, and the passivation protective layer is exposed, developed, and etched.

[0087] In step 4), the steps of forming the polysilicon gate of the MOS tube are: depositing a gate polysilicon layer on the surface, doping the polysilicon layer, and then completing etching of the gate polycrystalline structure, so that the gate oxide layer and the polysilicon on the surface of the gate oxide layer constitute the polysilicon gate of the MOS tube.

[0088] In step 6), a silicon nitride layer is deposited by low pressure chemical vapor deposition; a BPSG low dielectric constant filling film layer is deposited by PECVD;

[0089] In step 7), a chemical mechanical polishing (CMP) process is used to planarize the film layer; a dry etching process is used to process the device contact holes;

[0090] In step 8), a tungsten sputtering process and a tungsten chemical mechanical planarization process are used to complete the device contact hole tungsten plug filling process;

[0091] In step 10), a h1 angstrom titanium film layer is sputtered by magnetron plasma physical vapor phase PVD method; and a h2 angstrom amorphous silicon nitride SixNyHz film layer is deposited by plasma enhanced chemical vapor phase PECVD;

[0092] In step 11), a h3 angstrom microcrystalline titanium film is sputtered by a magnetron plasma physical vapor phase PVD method;

[0093] In step 12), h4 angstrom semi-crystalline titanium / h5 angstrom titanium nitride is deposited by PVD in situ by surface chemical reaction;

[0094] In step 15), a low dielectric constant filling film layer USG film is deposited by PECVD method;

[0095] In step 9), the interconnect structure film layer of the (n-1)th metal layer is tungsten / titanium / aluminum silicon copper / titanium nitride;

[0096] In step 16), the circuit components include MOS devices and MIM capacitors.

[0097] n≥2; h1=50 ～ 300 angstroms; h2 ≥ 180 angstroms; h3 = 150 ～ 300 angstroms; h4 = 50 ～ 100 angstroms; h5 = 100 ～ 300 angstrom; DA≤30ppm; abs(QVC)≤3ppm / V2; abs(LVC)≤1.5ppm / V.

[0098] The impurities are P-type impurities or N-type impurities.

[0099] The (n-1)-layer intermetallic dielectric layer is planarized by a chemical mechanical planarization process to form a global planarized dielectric layer and a tungsten plug structure.

[0100] : High dielectric constant silicon-rich silicon nitride film deposited by PECVD is used as the dielectric layer of the metal MIM capacitor.

[0101] The tungsten plug structure is processed using a high selectivity tungsten-silicon dioxide chemical mechanical planarization process.

[0102] Embodiment 2:

[0103] A method for integrating a low dielectric absorption and low mismatch precision linear MIM capacitor comprises the following steps:

[0104] 1) growing a 300-500mm thick pad oxide film layer on the substrate, and depositing a silicon nitride and silicon dioxide composite film layer using an LPCVD process;

[0105] 2) using exposure and dry etching process to form isolation groove pattern, and then stripping the photoresist;

[0106] 3) using a silicon dioxide-silicon nitride-silicon dioxide hard mask and adopting a silicon etching dry process to form an isolation trench;

[0107] 4) Using a chlorine atmosphere oxidation process to generate a sidewall oxide film layer, and then filling the isolation medium;

[0108] 5) Using a planarization process to remove excess slot filling medium, using an oxidation process to form a rounded structure at the corner of the isolation slot, and finally forming a complete isolation slot structure;

[0109] Other technical contents are the same as those in Example 1.

[0110] In step 1), the substrate may be a SOI structural material sheet;

[0111] In step 3), the isolation trench may be a STI shallow trench isolation structure or a DTI deep trench isolation structure;

[0112] In step 4), the trench filling material can be a silicon dioxide-silicon nitride composite medium or an amorphous polysilicon medium.

[0113] In step 5), the trench filling medium planarization may adopt a CMP chemical mechanical global planarization process or a thermal oxidation planarization process;

[0114] Embodiment 3:

[0115] The low dielectric absorption and low mismatch precision linear MIM capacitor integration method has the same technical content as any one of embodiments 1-2. Further, in step 4), the step of forming the polysilicon gate of the MOS tube is: depositing a gate polysilicon layer on the surface, doping the polysilicon layer, and then completing the etching of the gate polycrystalline structure. Thus, the gate oxide layer and the polysilicon on the surface of the gate oxide layer constitute the polysilicon gate of the MOS tube.

[0116] Embodiment 4:

[0117] A method for integrating a low dielectric absorption and low mismatch precision linear MIM capacitor, the technical content of which is the same as any one of embodiments 1-3, further, in step 6), a silicon nitride layer is deposited by low pressure chemical vapor deposition; a BPSG low dielectric constant filling film layer is deposited by PECVD;

[0118] In step 7), a chemical mechanical polishing (CMP) process is used to planarize the film layer; a dry etching process is used to process the device contact holes;

[0119] In step 8), a tungsten sputtering process and a tungsten chemical mechanical planarization process are used to complete the device contact hole tungsten plug filling process;

[0120] In step 10), a h1 angstrom titanium film layer is sputtered by magnetron plasma physical vapor phase PVD method; and a h2 angstrom amorphous silicon nitride SixNyHz film layer is deposited by plasma enhanced chemical vapor phase PECVD;

[0121] In step 11), a h3 angstrom microcrystalline titanium film is sputtered by a magnetron plasma physical vapor phase PVD method;

[0122] In step 12), h4 angstrom semi-crystalline titanium / h5 angstrom titanium nitride is deposited by PVD in situ by surface chemical reaction;

[0123] In step 15), a low dielectric constant filling film layer USG film is deposited by PECVD method; Example 5:

[0124] A method for integrating a low dielectric absorption and low mismatch precision linear MIM capacitor, the technical content of which is the same as any one of embodiments 1-4, further, in step 9), the interconnect structure film layer of the (n-1)th metal layer is tungsten / titanium / aluminum silicon copper / titanium nitride;

[0125] In step 16), the circuit components include MOS devices and MIM capacitors.

[0126] Embodiment 6:

[0127] Low dielectric absorption and low mismatch precision linear MIM capacitor integration method, the technical content is the same as any one of embodiments 1-5, further, n≥2; h1=50 ～ 300 angstroms; h2 ≥ 180 angstroms; h3 = 150 ～ 300 angstroms; h4 = 50 ～ 100 angstroms; h5 = 100 ～ 300 angstrom; DA≤30ppm; abs(QVC)≤3ppm / V2; abs(LVC)≤1.5ppm / V.

[0128] Embodiment 7:

[0129] A method for integrating a low dielectric absorption and low mismatch precision linear MIM capacitor, the technical content of which is the same as any one of Examples 1-6, and further, the impurities are P-type impurities or N-type impurities.

[0130] Embodiment 8:

[0131] A method for integrating a low dielectric absorption and low mismatch precision linear MIM capacitor, the technical content of which is the same as any one of Examples 1-7, and further, a chemical mechanical planarization process is used to planarize the (n-1)-layer intermetallic dielectric layer to form a global planarized dielectric layer and a tungsten plug structure.

[0132] Embodiment 9:

[0133] A method for integrating a low dielectric absorption and low mismatch precision linear MIM capacitor, the technical content of which is the same as any one of Examples 1-3, and further, a high dielectric constant silicon-rich silicon nitride film deposited by PECVD is used as the dielectric layer of the metal MIM capacitor.

[0134] Embodiment 10:

[0135] A method for integrating a low dielectric absorption and low mismatch precision linear MIM capacitor, the technical content of which is the same as any one of Examples 1-9, and further, a high selectivity tungsten-silicon dioxide chemical mechanical planarization process is used to complete the tungsten plug structure processing.

[0136] Embodiment 11:

[0137] The metal MIM capacitor module obtained by using the low dielectric absorption low mismatch precision linear MIM capacitor and integration technology described in any one of embodiments 1-10 mainly includes a substrate, a well, a field oxide layer, a dielectric layer, a thick gate oxide layer, a thin gate oxide layer, a polysilicon gate and a metal film layer;

[0138] The substrate is located at the bottom; the well is formed on the surface of the substrate;

[0139] The field oxide layer is formed outside the active area;

[0140] The active area includes a high voltage device area, a medium voltage device area and a low voltage device area;

[0141] A thick gate oxide layer is provided in the high voltage device region and the medium voltage device region;

[0142] A thin gate oxide layer in the low voltage device area;

[0143] The metal MIM capacitor is formed in the middle of the dielectric layer between the (n-1)th metal layer and the nth metal layer;

[0144] The polysilicon gate of the MOS tube is constructed on a thick gate oxide layer and a thin gate oxide layer.

[0145] Embodiment 12:

[0146] The low dielectric absorption low mismatch precision linear MIM capacitor and integration technology integrated with multi-layer metal wiring multi-mode gate oxide high and low voltage compatible BiCMOS / CMOS process mainly includes the following steps:

[0147] 1) A well is formed on the surface of the substrate, an active region is formed on the surface of the well, and an isolation field is formed in the region outside the active region. A shielding protection layer is formed on the surface of the active region and the field oxide layer, wherein the shielding protection layer can be a thermal oxide layer.

[0148] MOS tubes can be divided into NMOS tubes and PMOS tubes, so the structure in the embodiment of the present invention can include the integration of metal film resistors with NMOS tubes, metal film resistors with PMOS tubes, or metal film resistors with both NMOS tubes and PMOS tubes. When the metal film resistor is integrated with the NMOS tube, the well in this step refers to the P well. When the metal film resistor is integrated with the PMOS tube, the well in this step refers to the N well. When the metal film resistor is integrated with the NMOS tube and the PMOS tube at the same time, the well in this step is the general term for the N well and the P well.

[0149] 2) Complete the pre-lithography implantation process of the dual-gate oxide high and low voltage CMOS source and drain, and select the areas requiring metal film resistors, high voltage device active areas, medium voltage device active areas, and low voltage device active areas.

[0150] 3) forming a thick gate oxide layer in the high voltage device active area and the medium voltage device active area respectively. forming a thin gate oxide layer after forming a stripped gate oxide layer in the low voltage device area not covered by the selected field oxide layer

[0151] An LPCVD polysilicon layer is deposited on the surface of the thick gate oxide layer and the thin gate oxide layer, so that the polysilicon formed on the surface of the gate oxide layer and the gate oxide layer constitute a polysilicon gate of a MOS tube.

[0152] The polysilicon layer is etched by using photolithography and etching processes such as dry polysilicon etcher. Except for the polysilicon in the selected area, the polysilicon on the surface of other positions is etched away. The polysilicon remaining on the surface of the gate oxide layer and the gate oxide layer constitute the polysilicon gate of the MOS tube. The gate polycrystalline etching adopts endpoint detection. During the over-etching process of the oxide layer, the etching gas increases the oxygen concentration to improve the selectivity of the polysilicon and the gate oxide layer. This can avoid excessive damage to the silicon in the source and drain areas of the MOS tube.

[0153] 4) Complete the photolithography implantation of dual-gate oxide high-low voltage CMOS source and drain in the doped source and drain regions of the MOS tube.

[0154] The impurities are P-type impurities or N-type impurities.

[0155] First, lightly doped source and drain regions are formed by photolithography and ion implantation. Figure 4 , the “-” in the figure indicates that the ion content is low, and then two thin films with the same material as the first dielectric layer and the second dielectric layer are deposited, and the two dielectric films are anisotropically etched to form side walls on both sides of the polysilicon gate.

[0156] See also Figure 5 , using photolithography and ion implantation to form heavily doped source and drain regions of the PMOS tube. In the figure, the "+" in the logo indicates that the ion content is high, and then a rapid annealing process is performed to form the doped source and drain regions of the PMOS tube.

[0157] See also Figure 5First, a low-pressure chemical vapor deposition growth process is used to deposit the third dielectric layer, and then a global chemical mechanical process is used to flatten the third dielectric layer, and the third dielectric layer is etched using a photolithography and etching process to form a contact hole for depositing metal, and then tungsten metal is deposited in the contact hole. After the completion of the chemical mechanical platforming of metal tungsten, aluminum silicon copper is sputtered, and then a photolithography and etching process is used to form metal connections in the required area.

[0158] After the third dielectric layer is planarized by chemical mechanical process, the depth of the contact hole for metal deposition ranges from thousands of angstroms to more than ten kiloangstroms. If the third dielectric layer is planarized by conventional reflow process, the subsequent contact hole lithography exposure process window will be relatively small, which will eventually lead to fluctuations in device performance.

[0159] 5) Deposit a silicon nitride oxide layer using low pressure chemical vapor deposition and deposit a BPSG low dielectric constant filling film layer using PECVD.

[0160] 6) The film layer is flattened using a chemical mechanical polishing (CMP) process, and then the device contact hole processing is completed using a dry etching process.

[0161] 7) Use tungsten sputtering process and tungsten chemical mechanical planarization process to complete the device contact hole filling process. Sputter the aluminum silicon copper film layer and complete the first layer of metal connection etching process.

[0162] 8) According to the circuit design requirements, repeat the metal interconnection process steps such as PECVD low-k filling film layer USG deposition, intermetallic dielectric layer CMP planarization, through-hole etching, tungsten plug chemical mechanical planarization, interconnection aluminum silicon copper metal sputtering etching, etc. until the second top metal is sputtered, recorded as the (n-2)th layer of metal, and the (n-2)th layer of metal wiring etching is completed.

[0163] Currently, analog integrated circuits are developing towards high integration and thin volume. High-performance analog integrated circuits require more than 3 layers of metal wiring. Therefore, intermetallic dielectric CMP planarization and tungsten plug structure have become basic process requirements.

[0164] 9) Depositing a low dielectric constant filling film layer USG, and using a chemical mechanical polishing (CMP) process to complete the planarization of the intermetallic dielectric film layer, forming an m1 angstrom USG dielectric layer on the (n-2)th layer.

[0165] The chemical mechanical planarization of the dielectric ensures the flatness DOP of the lower surface area of ​​the metal MIM capacitor to be manufactured later, effectively controls the non-planarity problem of the metal MIM capacitor, and improves the process processing accuracy and device stability of the metal MIM capacitor.

[0166] 10) According to the circuit design requirements, repeat the metal interconnection process steps such as PECVD low-k filling film layer USG deposition, intermetallic dielectric layer CMP planarization, through-hole etching, tungsten plug chemical mechanical planarization, interconnect aluminum silicon copper metal sputtering etching, etc. until the second top metal is sputtered, recorded as the (n-1)th metal layer, see Figure 6 , the metal interconnect structure film layer is tungsten / titanium / aluminum silicon copper / titanium nitride;

[0167] 11) After the argon atom sputtering cleaning is completed, a h1 angstrom titanium film layer is sputtered by a magnetron plasma physical vapor phase PVD method, see Figure 7 Next, plasma enhanced chemical vapor deposition (PECVD) was used to deposit h2 angstrom amorphous silicon nitride Si x N y H z Film, see Figure 8 ;

[0168] Preferably, the metal film layer system of the lower electrode of the metal capacitor can be effectively optimized by sputtering a microcrystalline titanium film with a thickness of h1 angstrom by magnetron plasma PVD method;

[0169] Preferably, sputtering a microcrystalline titanium film with a thickness of h1 angstroms can reduce the compressive stress of the aluminum alloy film layer of the lower electrode of the metal MIM capacitor and improve the surface unevenness such as Hilllock defects of the metal film layer;

[0170] Sputtering h1 angstrom thick microcrystalline titanium film as the dielectric layer PECVD silicon nitride Si x N y H z It provides an excellent film-forming environment, reduces the density of interface traps between film layers, and thus further improves the Si x N y H z Dielectric strength and capacitor operating voltage range.

[0171] 12) After the argon atomic sputtering cleaning is completed, a h3 angstrom microcrystalline titanium film is sputtered on the silicon nitride film layer by a magnetron plasma physical vapor phase PVD method, see Fig. 9 ;

[0172] The use of magnetron plasma PVD sputtering of h3 angstrom thick microcrystalline titanium film on the silicon nitride film layer can effectively optimize and reduce the PECVD silicon nitride Si of the metal MIM capacitor dielectric film layer. x N y H z stress;

[0173] The use of magnetron plasma PVD method to sputter a microcrystalline titanium film with a thickness of h3 angstroms on the silicon nitride film layer can reduce the probability of pinhole defects in the capacitor dielectric film layer, provide an excellent film-forming environment, reduce the probability of pinhole defects between film layers, and further improve the silicon nitride Si x N y H z Dielectric strength and capacitor operating voltage range.

[0174] 13) In-situ PVD deposition of h4 angstrom semicrystalline titanium / h5 angstrom titanium nitride in an integrated magnetron sputtering chamber using surface chemical reaction;

[0175] The adhesion performance of the metal MIM capacitor dielectric film layer and the metal alloy system of the metal MIM capacitor upper electrode can be improved by using integrated magnetron sputtering surface chemical reaction in-situ PVD deposition of low resistivity semi-crystalline titanium / titanium nitride on high resistivity microcrystalline titanium film.

[0176] The low resistivity semi-crystalline titanium / titanium nitride is deposited on the high resistivity microcrystalline titanium film by integrated magnetron sputtering surface chemical reaction in-situ PVD, which acts as a barrier layer and ensures the excellent conductive performance of the metal alloy system of the metal MIM capacitor upper electrode.

[0177] 14) Using PVD method to sputter aluminum alloy film and anti-reflective titanium nitride film layer suitable for planarization process integration, see Fig.10 ;

[0178] 15) Expose, develop, and dry-etch the MIM capacitor upper plate titanium / titanium nitride / aluminum silicon copper / titanium nitride according to the mask pattern;

[0179] 16) completing exposure, development, and dry etching of the lower electrode of the MIM capacitor and the (n-1)th layer of metal interconnection wiring according to the mask pattern;

[0180] 17) The integrated metal-silicon nitride-metal capacitor formed has the characteristics of dielectric absorption coefficient DA, second-order voltage coefficient QVC, linear voltage coefficient LVC, etc., see Fig.11 ;

[0181] Fig.11Among them, 101, the sub-top metal; 102, the high resistivity microcrystalline titanium film (preferred) of the lower electrode of the metal MIM capacitor; 103, the PECVD silicon-rich silicon nitride film layer of the metal MIM capacitor dielectric; 104, the high resistivity microcrystalline titanium film (preferred) of the upper electrode of the metal MIM capacitor; 105, the tungsten plug interconnecting the top metal and the sub-top metal; 201, the tungsten plug interconnecting the lower electrode of the metal MIM capacitor and the top metal; 202, the top metal system; 203, the metal system of the upper electrode of the metal MIM capacitor; 204, the low resistivity semi-crystalline titanium film layer of the upper electrode of the metal MIM capacitor; 205, the titanium nitride film layer of the barrier layer of the upper electrode of the metal MIM capacitor.

[0182] 18) Use PECVD to deposit low dielectric constant filling film layer USG film, CMP planarization of metal interlayer, through hole etching, chemical mechanical planarization of tungsten plug,

[0183] The tungsten plug structure is processed by adopting a high selectivity tungsten-silicon dioxide chemical mechanical planarization process, which can not only control the steps on the lower surface of the top metal, but also ensure the consistency of the thickness of the dielectric layer above the metal MIM capacitor within and between chips, effectively improving the quality factor of the metal MIM capacitor and improving the consistency and yield of the metal MIM capacitor.

[0184] 19) Sputtering the top metal layer, recorded as the nth metal layer, and completing the nth metal wiring etching process to form the metal interconnection of the MIM capacitor and other circuit components;

[0185] 20) Use PECVD to deposit the passivation composite dielectric layer, and complete the passivation protective layer exposure, development, and etching processing, see Fig.12 .

Claims

1. Low dielectric absorption low mismatch precision linear MIM capacitors and integration technology, characterized by, The following steps are involved: 1) A well is formed on the surface of the substrate, an active area is formed on the surface of the well, and an isolation oxide layer is formed in the area outside the active area. 2) Select the metal film resistor area, high voltage device active area, medium voltage device active area and low voltage device active area that require a low temperature coefficient. 3) forming a thick gate oxide layer in the active region of the high voltage device and the active region of the medium voltage device respectively; forming a thin gate oxide layer in the active region of the low voltage device; 4) Forming the polysilicon gate of the MOS tube and selecting the doped source and drain regions of the MOS tube; 5) Complete the photolithography implantation of the dual-gate oxide high-low voltage CMOS source and drain in the doped source and drain regions of the MOS tube, and activate the doped impurities by rapid annealing process; 6) Depositing a silicon nitride layer and a BPSG low dielectric constant filling film layer; 7) Complete the film flattening process and device contact hole processing; 8) Complete the tungsten plug filling process of the device contact hole; sputter the aluminum silicon copper film layer, which is recorded as the first layer of metal, and complete the first layer of metal wiring etching process; 9) Repeat steps 6) to 8) according to the circuit design requirements until the next top metal layer is sputtered, which is recorded as the (n-1)th metal layer; 10) After the argon atom sputtering cleaning is completed, a h1 angstrom titanium film layer is sputtered, and then a h2 angstrom amorphous silicon nitride SixNyHz film layer is deposited; 11) After the argon atom sputtering cleaning is completed, a h3 angstrom microcrystalline titanium film is sputtered on the silicon nitride film layer; 12) depositing h4 angstrom semicrystalline titanium / h5 angstrom titanium nitride in an integrated magnetron sputtering chamber; 13) Using PVD method to sputter aluminum alloy film and anti-reflective titanium nitride film layer suitable for planarization process integration; 14) According to the mask layout, the titanium / titanium nitride / aluminum silicon copper / titanium nitride upper plate of the MIM capacitor is exposed, developed, and dry-etched to form an integrated metal-silicon nitride-metal capacitor; The formed integrated metal-silicon nitride-metal capacitor has a dielectric absorption coefficient DA ≤ 30ppm, a second-order voltage coefficient abs (QVC) ≤ 3ppm / V2, and a linear voltage coefficient abs (LVC) ≤ 1.5ppm / V; 15) Deposition of low dielectric constant filling film layer USG film, CMP planarization of metal interlayer, through hole etching, chemical mechanical planarization of tungsten plug, 16) Sputtering the top metal layer, recorded as the nth metal layer, and completing the nth metal wiring etching process to form the metal interconnection of the circuit components; 17) The passivation composite dielectric layer is deposited by PECVD, and the passivation protective layer is exposed, developed, and etched.

2. The low dielectric absorption low mismatch precision linear MIM capacitor and integration technology according to claim 1, characterized in that: In step 4), the steps of forming the polysilicon gate of the MOS tube are: depositing a gate polysilicon layer on the surface, doping the polysilicon layer, and then etching the gate polycrystalline structure, so that the gate oxide layer and the polysilicon on the surface of the gate oxide layer constitute the polysilicon gate of the MOS tube.

3. The low dielectric absorption low mismatch precision linear MIM capacitor and integration technology according to claim 1, characterized in that: In step 6), a silicon nitride layer is deposited by low pressure chemical vapor deposition; a BPSG low dielectric constant filling film layer is deposited by PECVD; In step 7), a chemical mechanical polishing (CMP) process is used to planarize the film layer; a dry etching process is used to process the device contact holes; In step 8), a tungsten sputtering process and a tungsten chemical mechanical planarization process are used to complete the device contact hole tungsten plug filling process; In step 10), a h1 angstrom titanium film layer is sputtered by magnetron plasma physical vapor phase PVD method; and a h2 angstrom amorphous silicon nitride SixNyHz film layer is deposited by plasma enhanced chemical vapor phase PECVD; In step 11), a h3 angstrom microcrystalline titanium film is sputtered by a magnetron plasma physical vapor phase PVD method; In step 12), h4 angstrom semi-crystalline titanium / h5 angstrom titanium nitride is deposited by PVD in situ by surface chemical reaction; In step 15), a low dielectric constant filling film layer USG film is deposited by PECVD method.

4. The low dielectric absorption low mismatch precision linear MIM capacitor and integration technology according to claim 1, characterized in that: In step 9), the interconnect structure film layer of the (n-1)th metal layer is tungsten / titanium / aluminum silicon copper / titanium nitride; In step 16), the circuit components include MOS devices and MIM capacitors.

5. The low dielectric absorption low mismatch precision linear MIM capacitor and integration technology according to claim 1, characterized in that: n≥2; h1=50 ～ 300 angstroms; h2 ≥ 180 angstroms; h3 = 150 ～ 300 angstroms; h4 = 50 ～ 100 angstroms; h5 = 100 ～ 300 angstrom; DA≤30ppm; abs(QVC)≤3ppm / V2; abs(LVC)≤1.5ppm / V.

6. The low dielectric absorption low mismatch precision linear MIM capacitor and integration technology according to claim 1, characterized in that: The impurities are P-type impurities or N-type impurities.

7. The low dielectric absorption low mismatch precision linear MIM capacitor and integration technology according to claim 1, characterized in that: The (n-1)-layer intermetallic dielectric layer is planarized by a chemical mechanical planarization process to form a global planarized dielectric layer and a tungsten plug structure.

8. The low dielectric absorption low mismatch precision linear MIM capacitor and integration technology according to claim 1, characterized in that: A high dielectric constant silicon-rich silicon nitride film deposited by PECVD is used as the dielectric layer of the metal MIM capacitor.

9. The low dielectric absorption low mismatch precision linear MIM capacitor and integration technology according to claim 1, characterized in that: The tungsten plug structure is processed using a high selectivity tungsten-silicon dioxide chemical mechanical planarization process.

10. A metal MIM capacitor module obtained by using the low dielectric absorption, low mismatch, precision linear MIM capacitor and integration technology as claimed in any one of claims 1 to 9, characterized in that: It mainly includes substrate, well, field oxide layer, dielectric layer, thick gate oxide layer, thin gate oxide layer, polysilicon gate and metal film layer; The substrate is located at the bottom; the well is formed on the surface of the substrate; The field oxide layer is formed outside the active area; The active area includes a high voltage device area, a medium voltage device area and a low voltage device area; A thick gate oxide layer is provided in the high voltage device region and the medium voltage device region; A thin gate oxide layer in the low voltage device area; The metal MIM capacitor is formed in the middle of the dielectric layer between the (n-1)th metal layer and the nth metal layer; The polysilicon gate of the MOS tube is constructed on a thick gate oxide layer and a thin gate oxide layer.

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