Adaptive backplane for high speed, high density electrical connectors

Abstract

A printed circuit board includes: a plurality of layers including an attachment layer and a wiring layer; and via patterns formed in one or more of the plurality of layers, each via pattern including: a first signal via and a second signal via configured to receive a contact tail of a signal conductor of a connector; a ground via configured to receive a contact tail of a ground conductor of the connector; a ground black shadow via in position adjacent to each of the first signal via and the second signal via; and a non-plated via between each of the ground black shadow vias and the signal via. Different layers of the plurality of layers may have different isolation pad configurations.

Description

Technical Field

[0001] The present application relates generally to interconnection systems for interconnecting electronic components, such as interconnection systems including electrical connectors. Background Art

[0002] Electrical connectors are used in many electronic systems. It is often easier and more cost-effective to manufacture the system as separate electronic components, such as printed circuit boards (PCBs), which can be connected together using electrical connectors. One known arrangement for connecting several printed circuit boards is to use one printed circuit board as a backplane. Other printed circuit boards (called "daughter boards" or "daughter cards") can then be connected through the backplane.

[0003] A known backplane has the form of a printed circuit board on which many connectors can be mounted. Conductive traces in the backplane can be electrically connected to signal conductors in the connectors so that signals can be transmitted between the connectors. Daughter cards can also have connectors mounted thereon. The connectors mounted on the daughter cards can be plugged into connectors mounted on the backplane. In this way, signals can be transmitted between daughter cards through the backplane. The daughter cards can be plugged into the backplane at right angles. Therefore, connectors for these applications can include right-angle bends and are often referred to as "right-angle connectors." Other known connectors include, but are not limited to, orthogonal midplane connectors and midplaneless direct-attachment orthogonal connectors.

[0004] Connectors can also be used in other configurations for interconnecting printed circuit boards, and for interconnecting other types of devices such as cables to printed circuit boards. Sometimes, one or more smaller printed circuit boards can be connected to another larger printed circuit board. In such a configuration, the larger printed circuit board can be referred to as a "motherboard," and the printed circuit board connected thereto can be referred to as a daughterboard. In addition, boards of the same or similar size can sometimes be arranged in parallel. Connectors used in these applications are often referred to as "stacking connectors" or "mezzanine connectors."

[0005] Regardless of the exact application, the design of electrical connectors has adapted to reflect trends in the electronics industry. Electronic systems have generally become smaller, faster, and more complex in function. As a result of these trends, the number of circuits in a given area in an electronic system, as well as the frequency with which the circuits operate, has grown significantly in recent years. Current systems transmit more data between printed circuit boards, and require electrical connectors that are electrically capable of handling more data at faster speeds than connectors available only a few years ago.

[0006] In high-density, high-speed connectors, electrical connectors may be very close to each other so that there may be electrical interference between adjacent signal conductors. In order to reduce interference and also to provide the desired electrical properties, shielding members are usually provided between or around adjacent signal conductors. The shielding member may prevent the signal carried on one conductor from generating "crosstalk" on another conductor. The shielding member may also affect the impedance of each conductor, which may further affect the electrical properties.

[0007] Other techniques can be used to control the performance of the connector. For example, transmitting signals in a differential manner can reduce crosstalk. A differential signal is carried on a pair of conductive paths called a "differential pair". The voltage difference between the conductive paths represents the signal. In general, the differential pair is designed to have preferential coupling between the paired conductive paths. For example, the two conductive paths of the differential pair can be arranged to extend closer to each other than the adjacent signal paths in the connector. Shielding is not required between the paired conductive paths, but shielding can be used between the differential pairs. Electrical connectors can be designed for differential signals as well as single-ended signals.

[0008] In an interconnect system, such a connector is attached to a printed circuit board, one of which can act as a backplane for transmitting signals between electrical connectors and for providing a reference plane for a reference conductor in the connector that can be grounded. Typically, the backplane is formed as a multilayer assembly made of a stack of dielectric sheets (sometimes referred to as "prepregs"). Some or all of the dielectric sheets may have a conductive film on one or both sides of the surface. Some conductive films may be patterned using photolithography techniques to form conductive traces for interconnecting between circuit boards, circuits, and / or circuit elements. Other conductive films may remain essentially unchanged and may act as a ground plane or power plane for supplying a reference potential. The dielectric sheets may be formed into an integral board structure, such as by pressing the stacked dielectric sheets together under pressure.

[0009] In order to form electrical connections to conductive traces or ground / power planes, holes may be drilled through the printed circuit board. These holes (or "vias") may be filled or plated with metal so that the vias are electrically connected to one or more of the conductive traces or planes through which they pass.

[0010] To attach the connector to a printed circuit board, the contact pins or contact "tails" of the connector may be inserted into vias, with or without the use of solder. The vias are sized to receive the contact tails of the connector.

[0011] The vias on the printed circuit board can be arranged in a via pattern that matches the arrangement of the contact tails on the connector. For example, the via pattern can include a signal via that receives the signal contact tail of the connector and a ground via that receives the ground contact tail of the connector. The arrangement of the via pattern on the printed circuit board, typically referred to as a "connector footprint", can include a pattern of vias in columns and / or rows. Examples of connector footprints are disclosed in U.S. Patents Nos. 10,034,366, 10,455,689, 9,730,313, 9,775,231, and 10,187,972. Summary of the invention

[0012] The electrical performance of a printed circuit board attached to a connector depends at least in part on the structure of the printed circuit board, including conductor traces, ground planes, vias, and other structures. Electrical performance issues become more severe as the signal conductor density and operating frequency of the connector increase. Such electrical performance issues may include, but are not limited to, crosstalk between densely spaced signal conductors and impedance variations along the signal conductors. As a result, improvements in the construction of connector footprints are needed to improve impedance at high signal conductor densities and / or high operating frequencies.

[0013] In some embodiments, a printed circuit board includes: a plurality of layers, including an attachment layer and a routing layer; and a via pattern formed in one or more of the plurality of layers, each of the via patterns including: a first signal via and a second signal via configured to receive a contact tail of a signal conductor of a connector; a ground via configured to receive a contact tail of a ground conductor of the connector; a ground shadow via positioned adjacent to each of the first signal via and the second signal via; and a non-plated hole positioned between each of the ground shadow via and the signal via.

[0014] In some embodiments, the non-plated vias extend to a predetermined depth in the plurality of layers.

[0015] In some embodiments, the predetermined depth is the depth of a boundary between an attachment layer and a routing layer.

[0016] In some embodiments, the predetermined depth is equal to or greater than the length of the contact tails of the signal conductors of the connector.

[0017] In some embodiments, each of the first signal via and the second signal via is configured to have a first section having a first diameter and a second section having a second diameter smaller than the first diameter.

[0018] In some embodiments, the first signal via and the second signal via are plated with a conductive material from a top surface of the printed circuit board to at least a wiring layer of the wiring layer.

[0019] In some embodiments, the first signal via and the second signal via are not plated with conductive material under the wiring layer.

[0020] In some embodiments, each of the ground shadow vias is configured to have a third segment having a third diameter and a fourth segment having a fourth diameter greater than the third diameter.

[0021] In some embodiments, each of the ground shadow vias extends through multiple layers and is plated with a conductive material through the multiple layers.

[0022] In some embodiments, each of the ground vias extends through multiple layers and is plated with a conductive material through the multiple layers.

[0023] In some embodiments, the attachment layer includes a top layer having a first isolating pad surrounding the first signal via, a second isolating pad surrounding the second signal via, and a conductive strip separating the first isolating pad and the second isolating pad.

[0024] In some embodiments, the routing layer includes a wiring layer having a third isolation pad surrounding the first signal via, a fourth isolation pad surrounding the second signal via, and a conductive strip separating the third isolation pad and the fourth isolation pad.

[0025] In some embodiments, each of the wiring layer immediately above the wiring layer and the wiring layer immediately below the wiring layer includes a fifth isolation pad surrounding the first signal via, a sixth isolation pad surrounding the second signal via, and a conductive strip separating the fifth isolation pad and the sixth isolation pad.

[0026] In some embodiments, each of the attachment layers except the top layer includes a seventh isolation pad surrounding both the first signal via and the second signal via.

[0027] In some embodiments, each of the wiring layers except the wiring layer, and the wiring layer immediately above the wiring layer and the wiring layer immediately below the wiring layer includes an eighth isolation pad surrounding both the first signal via and the second signal via.

[0028] In some embodiments, a center of each of the non-plated vias is equally spaced from respective centers of the signal via and the ground shadow via.

[0029] In another embodiment, a printed circuit board includes: multiple layers, including an attachment layer and a routing layer; and a via pattern formed in one or more of the multiple layers, each of the via patterns including: a first signal via and a second signal via, configured to receive a contact tail of a signal conductor of a connector, wherein each of the first signal via and the second signal via is configured to have a first section with a first diameter in the attachment layer, and a second section with a second diameter smaller than the first diameter in the routing layer; a ground via, configured to receive a contact tail of a ground conductor of the connector; a ground shadow via, positioned adjacent to each of the first signal via and the second signal via, wherein each of the ground shadow via is configured to have a first section with a third diameter in the attachment layer, and a second section with a fourth diameter larger than the third diameter in the routing layer; and a non-plated hole, located between each of the ground shadow vias and the signal via in the attachment layer.

[0030] In some embodiments, a first diameter of the first signal via and the second signal via is greater than a third diameter of the ground shadow via.

[0031] In some embodiments, the second diameters of the first signal via and the second signal via are greater than the fourth diameter of the ground shadow via.

[0032] In some embodiments, the diameter of the non-plated hole is equal to the third diameter of the ground shadow via.

[0033] In some embodiments, a center of each of the non-plated vias is equally spaced from respective centers of the signal via and the ground shadow via.

[0034] In some embodiments, the attachment layer includes a top layer having a first isolating pad surrounding the first signal via, a second isolating pad surrounding the second signal via, and a conductive strip separating the first isolating pad and the second isolating pad.

[0035] In some embodiments, the routing layer includes a wiring layer having a third isolation pad surrounding the first signal via, a fourth isolation pad surrounding the second signal via, and a conductive strip separating the third isolation pad and the fourth isolation pad.

[0036] In some embodiments, each of the wiring layer immediately above the wiring layer and the wiring layer immediately below the wiring layer includes a fifth isolation pad surrounding the first signal via, a sixth isolation pad surrounding the second signal via, and a conductive strip separating the fifth isolation pad and the sixth isolation pad.

[0037] In some embodiments, each of the attachment layers except the top layer includes a seventh isolation pad surrounding both the first signal via and the second signal via.

[0038] In some embodiments, each of the wiring layers except the wiring layer, and the wiring layer immediately above the wiring layer and the wiring layer immediately below the wiring layer includes an eighth isolation pad surrounding both the first signal via and the second signal via.

[0039] In some embodiments, the third, fourth, fifth, and sixth isolating disks have equal widths.

[0040] In some embodiments, the first and second isolating disks have a greater width than the third and fourth isolating disks.

[0041] In some embodiments, the seventh isolating disc has a greater width than the eighth isolating disc.

[0042] In another embodiment, a method of manufacturing a via pattern in a printed circuit board including a plurality of layers is provided. The method includes: forming a first signal via and a second signal via to receive a contact tail of a signal conductor of a connector; forming a ground via to receive a contact tail of a ground conductor of the connector; forming a ground shadow via positioned adjacent to each of the first signal via and the second signal via; and forming a non-plated hole between each of the ground shadow via and the signal via. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] For a better understanding of the disclosed technology, reference is made to the accompanying drawings, which are incorporated herein by reference, wherein:

[0044] Figure 1 is an exploded view of a high-speed, high-density electrical connector, backplane, and daughterboard;

[0045] Figure 2 Pictured Figure 1 A portion of the electrical connector that mates with the backplane;

[0046] Figure 3 Pictured Figure 2 A pin module of an electrical connector;

[0047] Figure 4 is a partial top view of a backplane having an array of differential pair connectors;

[0048] Figure 5 is a simplified cross section of the back plate;

[0049] Figure 6 is a partial top view of a top layer of a printed circuit board according to an embodiment;

[0050] Figure 7 yes Figure 6 A simplified cross-sectional view of a printed circuit board;

[0051] Figure 8 yes Figure 6 and Figure 7 A partial top view of a wiring layer in a printed circuit board;

[0052] Fig. 9 yes Figure 6 and Figure 7 A partial top view of a wiring layer immediately above a wiring layer in a printed circuit board;

[0053] Fig.10 yes Figure 6 and Figure 7 A partial top view of an attachment layer below a top layer in a printed circuit board; and

[0054] Fig.11 yes Figure 6 and Figure 7 A partial top view of a wiring layer in a printed circuit board, which wiring layer is not the wiring layer and the wiring layer immediately above the wiring layer and the wiring layer immediately below the wiring layer. DETAILED DESCRIPTION

[0055] The inventors have recognized and appreciated that, while efforts have been made to provide improved electrical connectors in order to improve the performance of interconnect systems, significant performance improvements can be achieved at certain very high frequencies through creative design of printed circuit boards. According to some embodiments, improvements can be achieved by introducing structures in the connector footprint that change the electrical properties of the printed circuit board. The structures shown and described herein can be employed in any type of printed circuit board, including but not limited to backplanes, motherboards, daughterboards, orthogonally mated daughtercards with or without mating midplanes, and daughtercards mated to cables.

[0056] Those structures may include, for example, conductive structures extending vertically through the board in an attachment layer of the board to short together the edges of the ground plane that might otherwise float freely due to ground clearance formed around the signal conductors. In some embodiments, the structure may be a via that extends through only a portion of a layer of the board, such as an attachment layer of the board, where the via has a larger diameter to accommodate a flexible pin or other contact tail of a connector or other component mounted on the surface of the board. In some embodiments, the structure may be a via that is plated or filled with conductive material that passes through some or all layers of the printed circuit board. In some embodiments, the via is not plated or filled with conductive material that passes through some or all layers of the printed circuit board, thereby forming an air hole in the printed circuit board.

[0057] Figure 1 An example of an electrical interconnect system of a form that can be used in an electronic system is illustrated. In this example, the electrical interconnect system includes a right angle connector and can be used, for example, to electrically connect a daughter card to a backplane. Figure 11 and 2 illustrate two mating connectors. In this example, the backplane connector 100 is designed to be attached to the backplane 110, and the daughter card connector 120 is designed to be attached to the daughter card 130. The backplane 110 is also referred to as a "printed circuit board" herein. The daughter card connector 120 includes a contact tail 132 designed to be attached to the daughter card 130, and the backplane connector 100 includes a contact tail 140 designed to be attached to the backplane 110. These contact tails form one end of the conductive element passing through the interconnection system. When the connectors are mounted to their respective circuit boards, the contact tails are electrically connected to conductive structures in the printed circuit board that carry signals or are connected to a reference potential.

[0058] Each connector also has a mating engagement portion where the connector can mate with or detach from the other connector. The daughter card connector 120 includes a mating engagement portion 140. The backplane connector 100 includes a mating engagement portion 142. Figure 1 It is not fully visible in the figure, but the mating contact portion of the conductive element is exposed at the mating joint.

[0059] exist Figure 2 Provided in Figure 1 Further details of the construction of the interconnect system are shown with the backplane connector 100 partially removed. Figure 2 In the embodiment of FIG. 1 , the front wall of the housing 210 is removed to reveal the interior portion of the mating engagement portion 142. Figure 2 In the embodiment of the present invention, the backplane connector 100 has a modular structure. A plurality of pin modules 220 are organized to form an array of conductive elements. Each pin module 220 can be designed to cooperate with a module of the daughter card connector 120.

[0060] In the illustrated embodiment, four rows and eight columns of pin modules 220 are shown. With each pin module having two signal conductors, the four rows 230A, 230B, 230C, and 230D of pin modules generate a total of four pairs or eight columns of signal conductors. However, it should be understood that the number of signal conductors per row or column is not limiting. More or fewer rows of pin modules 220 may be included in the housing 210. Similarly, more or fewer columns of pin modules 220 may be included in the housing 210. Alternatively or in addition, the housing 210 may be considered a module of a backplane connector, and multiple such modules may be arranged side by side, thereby extending the length of the backplane connector.

[0061] exist Figure 2In an embodiment of the present invention, each pin module 220 includes conductive elements that function as signal conductors. Those signal conductors are held within an insulating member that may serve as a portion of the housing 210. The insulating portion of the pin module 220 may be positioned to separate the signal conductors from the rest of the housing 210. In this configuration, the rest of the housing 210 may be conductive or partially conductive. Lossy or conductive members may be positioned adjacent to the rows 230A, 230B, 230C, and 230D of the pin modules 220. Figure 2 In the embodiment of FIG. 5 , spacers 240A, 240B, and 240C are provided between adjacent rows of pin modules.

[0062] Figure 3 The pin modules 220 are illustrated in greater detail. Each pin module 220 includes a pair of conductive elements that serve as signal conductors 314A and 314B. Each signal conductor has a mating engagement portion shaped as a pin. Opposite ends of the signal conductors have contact tails 316A and 316B for making electrical connections with vias in a printed circuit board such as backplane 110. In this embodiment, the contact tails are shaped as press-fit flexible sections. The middle portion of the signal conductor passes through the pin module 220.

[0063] Conductive elements serving as reference conductors 342A and 342B are attached at opposing outer surfaces of the pin module 220. Each reference conductor has a contact tail 350 shaped for making electrical connection with a via in a printed circuit board such as the backplane 110. The reference conductors also have a mating contact portion.

[0064] refer to Figure 4 Embodiments of a printed circuit board are described. Figure 4 1 shows a partial top view of the backplane 110, which shows the connector footprint 410 of the vias for mating with the contact tails of the backplane connector 100. The backplane 110 can be implemented as a printed circuit board as described below. As shown, the connector footprint 410 includes an array of rows and columns of via patterns 420. Each via pattern 420 corresponds to a differential pair of signal conductors and an associated reference conductor, and Figure 4 As shown, each via pattern 420 includes a first signal via 430 and a second signal via 432 that form a differential signal pair, and ground vias 440, 442, 444, and 446 associated with each pair of signal vias 430, 432. It should be understood that each via pattern 420 and Figure 31 and described above match the pattern of contact tails 316A, 316B, and 350 of the pin module 220 shown in FIG. 1 and described above. In addition, the array of via patterns 420 in the backplane 110 matches the array of pin modules 220 in the backplane connector 100. It should be understood that the parameters of the connector footprint 410 may vary, including the number and arrangement of via patterns 420 and the configuration of each via pattern 420, as long as the connector footprint 410 matches the pattern of contact tails in the backplane connector 100. In some embodiments, the arrays of via patterns may be offset in the vertical direction relative to each other.

[0065] refer to Figure 5 Additional embodiments of printed circuit boards are described. Figure 5 A simplified cross-sectional view of a portion of a backplane 110 in accordance with an embodiment is shown in FIG. The portion shown may represent a signal via in a connector footprint. Figure 5 The layer structure of the backplane 110 and the signal via 550 are shown for illustration purposes. It should be understood that the actual backplane 110 includes a plurality of vias densely spaced apart in a specific pattern as described below. The backplane 110 may be implemented as a printed circuit board.

[0066] like Figure 5 As further shown, the backplane 110 includes a plurality of layers. Each of the plurality of layers of the backplane 110 may include a conductive layer and a dielectric sheet, such that the backplane 110 includes an alternating arrangement of conductive layers and dielectric sheets. Each conductive layer may act as a ground plane, or may be patterned to form conductive traces, or may include ground planes and conductive traces in different regions. During assembly, these layers may be formed by stacking multiple sheets of patterned copper sheets and prepregs, and then pressing them under heat to melt all the sheets. The patterned copper may generate traces and other conductive structures within the printed circuit board. As a result of the melting, these layers may be structurally inseparable in the finished backplane. However, despite this, the layers may be identified in the melted structure based on the location of the conductive structures.

[0067] These layers can be assigned different functions and thus can have different structural features. In some embodiments, the first portion of the layers closest to the surface can have vias wide enough to accommodate the contact tails of the components mounted to the surface. These layers can be referred to as "attachment layers". The second portion of the layers can have narrower vias for generating wider wiring trenches. These layers can be referred to as "wiring layers".

[0068] In the illustrated embodiment, the backplane 110 includes attachment layers 560, 562, etc. and wiring layers 570, 572, etc. The attachment layers are located on the upper portion of the backplane 110, and the wiring layers are located below the attachment layers. The attachment layers 560, 562, etc. and the wiring layers 570, 572, etc. are adhered together to form a single structure in the form of a printed circuit board. The number of attachment layers and the number of wiring layers in a specific backplane may vary depending on the application.

[0069] like Figure 5 As shown, the backplane 110 may include a ground plane 540 between dielectric layers of the structure, and may include signal traces 542 in or between routing layers. The signal traces 544 are shown connected to signal vias 550.

[0070] The signal via 550 includes plating 552 in the attachment layer and in one or more routing layers. The signal via 550 can be backdrilled in the lower area 554 of the backplane 110 to remove the plating. A ground clearance 556 is provided between the signal via 550 and the ground plane 540.

[0071] like Figure 5 As further shown, the via 550 has a first diameter 580 in the attachment layer and a second diameter 582 in the routing layer. The first diameter 580 is larger than the second diameter 582. In particular, the first diameter 580 is selected to receive the contact tails of the backplane connector 100, and the second diameter 582 is selected based on the typical via diameters of the printed circuit board. Because the via 550 has a relatively large first diameter 580, and because the vias are densely spaced to match the high-density backplane connector 100, very little area is reserved in the attachment layer 560, 562, etc. for signal routing. In the routing layer 570, 572, etc. located below the via in the attachment layer, there is additional area available for signal routing.

[0072] In some embodiments, the vias may have the same diameter in the attachment layer and the routing layer.For example, the contact elements of the connector may be attached to pads on the surface of the backplane 110 in a surface mount configuration.

[0073] In some embodiments, the backplane 110 may include a conductive surface layer 590 on its top surface. The conductive surface layer 590 is patterned to provide an antipad 592 or non-conductive area around each signal via. The conductive surface layer 590 may be connected to some or all of the ground vias and may provide a contact portion, such as a conductive pad or conductive finger, for the connector ground.

[0074] refer to Figure 6-11Embodiments of printed circuit boards are described. It should be appreciated that Figure 6-11 The top view of the printed circuit board is partially schematic because not all of the illustrated structures are visible in all embodiments when the top of the printed circuit board is viewed with the naked eye. The board may be provided with coatings that obscure some of the structures. In addition, some structures may be formed on layers below the surface of the board. Nevertheless, those layers may still be shown in the top view so that the relative positions of the structures in the layers can be understood. For example, a signal trace and a ground plane may not be visible at the same time in the same view of the board because they are on different vertical planes within the printed circuit board. However, because the relative positioning of the signal and ground structures may be important to the performance of the printed circuit board, both may be shown in the so-called top view.

[0075] Figure 6 A partial top view of an embodiment of an attachment layer is shown in FIG. Figure 6 A via pattern 600 of the connector footprint 410 of the backplane 110 is shown.

[0076] The via pattern 600 may be formed in a top attachment layer 602 of the backplane 110, and the top attachment layer 602 may include a ground plane 604 of a conductive material formed on a dielectric sheet 606. The via pattern 600 includes a first signal via 610 and a second signal via 612 that may form a differential signal pair, the signal vias 610 and 612 extending vertically through the attachment layer and having contact tails 316A, 316B (selected to receive the backplane connector 100) in the attachment layer 560. Figure 3 ) In some embodiments, as described below, the signal vias 610 and 612 may have different diameters in the attachment layer and in the routing layer.

[0077] The via pattern 600 also includes ground vias 630, 632, 634, and 636 associated with the signal vias 610 and 612. Figure 6 In the embodiment of the present invention, the ground vias 630 and 632 can be located at one end of the via pattern 600 adjacent to the signal via 610, and the ground vias 634 and 636 can be located at the opposite end of the via pattern 420 adjacent to the signal via 612. The ground vias 630, 632, 634, and 636 are sized to receive the corresponding contact tails 350 ( Figure 3 ). The ground vias interconnect the ground planes of some or all layers of the backplane 110. The ground vias may extend through all layers of the backplane 110 and may be plated with a conductive material.

[0078] The via pattern 600 also includes ground shadow vias 640, 642, 644, and 646. The ground shadow vias 640 and 642 are located on opposite sides of the signal via 610, and the ground shadow vias 644 and 646 are located on opposite sides of the signal via 612. The ground shadow vias 640, 642, 644, and 646 extend through the backplane 110 and may be plated with a conductive material. In some embodiments, as described below, the ground shadow vias 640, 642, 644, and 646 may have different sizes in the attachment layer and in the routing layer.

[0079] The via pattern 600 also includes non-plated vias 650, 652, 654, and 656. Non-plated vias 650 and 652 are located on opposite sides of the signal via 610, and non-plated vias 654 and 656 are located on opposite sides of the signal via 612. In addition, non-plated vias 650, 652, 654, and 656 are located between respective ground shadow vias and signal vias. Thus, non-plated via 650 is located between shadow via 640 and signal via 610; non-plated via 652 is located between shadow via 642 and signal via 610; non-plated via 654 is located between shadow via 644 and signal via 612; and non-plated via 656 is located between shadow via 646 and signal via 612. Non-plated vias 650, 652, 654, and 656 extend through the attachment layer, but do not extend through the routing layer. Non-plated holes are not plated with conductive material and effectively act as air holes.

[0080] exist Figure 6 In the embodiment of FIG. 1 , the ground shadow vias 640 and 642 and the non-plated vias 650 and 652 may be positioned along a virtual line 660 passing through the signal via 610. In addition, the ground shadow vias 644 and 646 and the non-plated vias 654 and 656 may be positioned along a virtual line 662 passing through the signal via 612. The lines 660 and 662 are perpendicular to the virtual line 664 passing through the signal vias 610 and 612.

[0081] In some embodiments, the centers of the non-plated vias 650, 652, 654, and 656 are equally spaced from the centers of the signal vias 610 and 612, respectively, and from the centers of the ground shadow vias 640, 642, 644, and 646. Thus, for example, the center of the non-plated via 650 is equally spaced from the center of the signal via 610 and from the center of the ground shadow via 640. It should be understood that these locations are not limiting.

[0082] When forming the backplane 110, the ground plane 604 is partially removed, such as by patterning a copper layer on a sheet, to form one or more isolation pads, thereby forming a ground clearance surrounding the signal vias 610 and 612, thereby exposing the dielectric sheet 606 of the attachment layer 602. Figure 6In the embodiment of the present invention, the via pattern 600 of the top layer 602 of the printed circuit board includes a first isolating pad 670 surrounding the signal via 610 and a second isolating pad 672 surrounding the signal via 612. The isolating pads 670 and 672 are separated by a conductive strip 674 between the signal vias 610 and 612. The isolating pads 670 and 672 are sized and shaped to prevent the ground plane 604 from shorting with the signal vias 610 and 612 even if there is some inaccuracy in forming the vias relative to the ground plane 604, and to establish a desired impedance for the signal path formed by the signal vias 610 and 612.

[0083] exist Figure 6 In the embodiment of the present invention, the isolation disks 670 and 672 are rectangular in shape and have a width 676, and the signal vias 610 and 612 are centrally located in the respective isolation disks. However, the isolation disks 670 and 672 can have any suitable shape. In some embodiments, the conductive strip 674 is omitted so that a single isolation disk surrounds both the signal vias 610 and 612.

[0084] As mentioned above, signal vias 610 and 612 are electrically isolated from ground plane 604. Ground vias 630, 632, 634, and 636 and ground shadow vias 640, 642, 644, and 646 are in electrical contact with ground plane 604. Figure 6 In the embodiment of FIG. 6 , non-plated vias 650, 652, 654, and 656 are formed in isolation pads 670 and 672. However, since the non-plated vias do not include conductive material, contact with ground plane 604 is not an issue.

[0085] Figure 7 It is shown along Figure 6 A cross section of the back plate 110 is captured by line 660 . Figure 6 and 7 As shown, signal vias 610 extend through one or more of the attachment layers 602, 712, etc. and the wiring layers 720, 722, etc., and provide a connection to a signal trace on at least one of the wiring layers (referred to as a signal wiring layer). Figure 7 The signal wiring layer 730 is shown in FIG. Figure 8 The contact pad 740 on the signal via 610 of the signal trace 840 is shown in FIG.

[0086] The non-plated holes 650 and 652 are located adjacent to the signal via 610 and are not plated with conductive material. The non-plated holes 650 and 652 extend below the surface of the backplane 110 to a predetermined depth 742. In some embodiments, the predetermined depth 742 may correspond to the length of the contact tails of the connector 100 or may be slightly greater than the length of the contact tails. In some embodiments, the predetermined depth 742 may be the depth of the boundary between the attachment layer and the wiring layer, such that the layer above the predetermined depth is the attachment layer and the layer below the predetermined depth is the wiring layer. In some embodiments, the predetermined depth 742 may be 1 mm.

[0087] Ground shadow vias 640 and 642 are located adjacent to non-plated holes 650 and 652, respectively. Ground shadow vias 640 and 642 extend through the attachment layer of backplane 110 and through the wiring layer and are plated with a conductive material. Figure 7 As shown, the non-plated via 650 is located between the ground shadow via 640 and the signal via 610 in the attachment layer, and the non-plated via 652 is located between the ground shadow via 642 and the signal via 610 in the attachment layer. As mentioned above, the center of the non-plated via 650 can be equally spaced from the center of the signal via 610 and the center of the ground shadow via 640.

[0088] The signal via 610 extends through the attachment layer and through at least one wiring layer of the backplane 110. The signal via 610 is plated with a conductive material from at least the top surface of the backplane 110 to the wiring layer 730. The signal via 610 can be formed by drilling a hole completely through the printed circuit board, plating the hole, and then removing the portion of the plating below the wiring layer 730, typically by back drilling.

[0089] exist Figure 7 In the embodiment of the present invention, the signal via 610 has a first section 750 having a first diameter 752 and a second section 754 having a second diameter 756. The first section 750 can extend through the attachment layer to a predetermined depth 742, and the second section 754 can extend through at least one wiring layer. The first diameter 752 can be larger than the second diameter 756 and can be selected to receive the contact tail 140 ( Figure 1 ). The signal via 610 is plated with a conductive material from at least the top layer 602 to the wiring layer 730. The signal via 610 may include a contact pad 758 on the top layer of the backplane 110 and may include a contact pad 740 on the wiring layer 730 to which the signal trace is connected.

[0090] like Figure 7As further shown, the shadow via 640 includes a first section 760 having a third diameter 762 and a second section 764 having a fourth diameter 766. The fourth diameter 766 can be larger than the third diameter 762. The length of the first section 760 of the shadow via 640 can be slightly less than, equal to, or slightly greater than the length of the first section 750 of the signal via 610. The shadow via 640 is provided with a contact pad (not shown) that can be connected to some or all of the ground planes in the attachment layer and the routing layer. The shadow via 642 can have the same construction as the shadow via 640.

[0091] Even if there is a variation in the diameter of the signal via, the third and fourth diameters of the shadow via may be selected to avoid impedance discontinuities along the signal via. A non-limiting example of the dimensions of the signal via and the shadow via is described below. Both the signal via and the shadow via may vary in diameter at or near a predetermined depth corresponding to the length of the contact tail of the connector.

[0092] In one non-limiting example, the first diameter 752 of the first section 750 of the signal via 610 may be a finished hole size of 0.31 mm + / - 0.05 mm, and the second diameter 756 of the second section 754 may be a finished hole size of 0.27 mm + / - 0.05 mm. The third diameter 762 of the first section 760 of the ground shadow via 640 may be a finished hole size of 0.064 mm + / - 0.05 mm, and the fourth diameter 766 of the second section 764 may be a finished hole size of 0.114 mm + / - 0.05 mm. In this example, the non-plated via 650 may have a diameter of 0.150 mm. Also, in this example, the center distance between the signal via 610 and the ground shadow via 640 may be 0.72 mm, and the center distance between the signal via 610 and the non-plated via 650 may be 0.358 mm. It should be understood that these dimensions are not limiting and other dimensions may be used.

[0093] In other embodiments, the signal via 610 and the ground shadow via 640 may have uniform diameters in the layer through the backplane 110. The diameter of the shadow via 640 may be smaller than the diameter of the signal via, but this is not required.

[0094] Figure 8 The wiring layer 730 ( Figure 7 ) is a partial top view of an embodiment of the present invention. Figure 8 8. It should be understood that the via pattern 820 is vertically aligned with the via pattern 600. It should also be understood that the via pattern 820 is not visible in the backplane 110 after the layers of the backplane are pressed together. Figure 77 shows the location of the wiring layer 730 in the layers of the backplane 110. It should be understood that different signal vias within the connector footprint are connected to different wiring layers according to signal wiring requirements.

[0095] The via pattern 820 of the wiring layer 730 includes signal vias 610 and 612 extending vertically through the attachment layer and at least to the wiring layer 730. The signal vias 610 and 612 may have a smaller diameter in the wiring layer than in the attachment layer.

[0096] When forming the backplane 110, the ground plane 830 is partially removed to form a third isolation plate 832 surrounding the signal via 610 and a fourth isolation plate 834 surrounding the signal via 612. The isolation plates 832 and 834 may have a width 836 that is smaller than the width 676 ( Figure 6 ). However, this need not be the case, and in some embodiments, the spacing between the signal vias and the edge of the ground plane may be selected at each layer to provide a desired impedance, or otherwise provide desired electrical properties. Figure 8 In the embodiment of FIG. 8 , the isolation plates 832 and 834 are rectangular in shape and are separated by the conductive strip 838 . In other embodiments, a single isolation plate may surround the signal vias 610 and 612 .

[0097] The via pattern 820 of the wiring layer 730 also includes ground vias 630, 632, 634, and 636, which have the same location and configuration as the corresponding ground vias in the top attach layer 602. Typically, the ground vias interconnect the ground planes in all layers of the backplane 110.

[0098] The via pattern 820 of the wiring layer 730 also includes ground shadow vias 640, 642, 644, and 646 that extend vertically through the attachment layer and the wiring layer. The diameter of the ground shadow via in the wiring layer 730 can be larger than the diameter of the ground shadow via in the attachment layer. Figure 6 ) does not extend to the wiring layer 730 and Figure 8 Not shown.

[0099] The via pattern 820 also includes a signal trace 840 connected to the signal via 610 and a signal trace 842 connected to the signal via 612. The signal traces 840 and 842 provide electrical connections between the respective signal vias 610 and 612 and other electrical components on the printed circuit board. The signal traces 840 and 842 are formed on the dielectric layer ( Figure 8 8 (not shown) and is vertically separated from the ground plane 830 by a dielectric layer.

[0100] like Figure 8As shown, signal traces 840 and 842 enter via pattern 820 in a parallel configuration near a middle portion of via pattern 820 and then diverge toward respective signal vias 610 and 612 near corners of isolation pads 832 and 834. Each signal trace may include a first segment 850 having a first width, a second segment 852 having a second width, and a contact pad 740 surrounding the respective signal via.

[0101] The first width of the first segment 850 may be smaller than the second width of the second segment 852. Figure 8 As can be seen in FIG. 8 , a first segment 850 of the signal trace 840 is routed over the ground plane 830, while a second segment 852 of the signal trace 840 is routed over the isolation plate 832. The first width of the first segment 850 is selected based on the size rules of the printed circuit board. The second width of the second segment 852 is selected to limit impedance changes as the signal trace 840 passes over the isolation plate 832.

[0102] Fig. 9 One embodiment of layer 728 ( Figure 7 ) is a partial top view. Layer 728 is a layer above wiring layer 730. Layer 732 below wiring layer 730 can be connected to Fig. 9 The layer 728 shown in has the same construction. Thus, Fig. 9 Indicates the layers above and below the wiring layer 730. Layer 728 is the wiring layer.

[0103] Fig. 9 900 is shown in FIG. It should be understood that the via pattern 900 is similar to the via pattern 600 ( Figure 6 ) and 820( Figure 8 ) are aligned in the vertical direction. It should also be understood that the via pattern 900 is not visible in the backplane 110 after the layers of the backplane are pressed together.

[0104] The via pattern 900 of layer 728 includes signal vias 610 and 612. Signal vias 610 and 612 may have a smaller diameter in the routing layer than in the attachment layer.

[0105] When forming the backplane 110, the ground plane 930 is partially removed to form a fifth isolation plate 980 surrounding the signal via 610 and a sixth isolation plate 982 surrounding the signal via 612. The isolation plates 980 and 982 may have the same size as the isolation plates 832 and 834 of the wiring layer 730, and may have a smaller size than the isolation plates 670 and 672 of the top layer 602. In particular, the isolation plates 980 and 982 may have a width 936 that is equal to the width 836 ( Figure 8). However, this need not be the case, and in some embodiments, the spacing between the signal vias and the edge of the ground plane may be selected at each layer to provide a desired impedance, or otherwise provide desired electrical properties. Fig. 9 In the embodiment of FIG. 9A , the isolation pads 980 and 982 are rectangular in shape and are separated by the conductive strip 938 . In other embodiments, in the via pattern 900 , a single isolation pad may surround the signal vias 610 and 612 .

[0106] The via pattern 900 of layer 728 also includes ground vias 630, 632, 634, and 636, which have the same location and configuration as the corresponding ground vias in the top attach layer 602. Typically, the ground vias interconnect the ground planes of all layers of the backplane 110.

[0107] The via pattern 900 of layer 728 also includes ground shadow vias 640, 642, 644, and 646 that extend vertically through the attachment layer and the routing layer. The diameter of the ground shadow via in layer 728 can be larger than the diameter of the ground shadow via in the attachment layer. Non-plated holes 650, 652, 654, and 656 ( Figure 6 ) does not extend to layer 728 and in Fig. 9 Not shown.

[0108] Fig.10 One embodiment of layer 712 ( Figure 7 ). Layer 712 is a layer below top layer 602. Layer 712 represents a layer between top layer 602 and layer 718 at a predetermined depth. Layer 712 is an attachment layer.

[0109] Fig.10 1 and 2 show a via pattern 1000. It should be understood that the via pattern 1000 is different from the via pattern 600 ( Figure 6 ) and 820( Figure 8 ) are aligned in the vertical direction. It should also be understood that the via pattern 1000 is not visible in the backplane 110 after the layers of the backplane are pressed together.

[0110] The via pattern 1000 of layer 712 includes signal vias 610 and 612. Signal vias 610 and 612 may have a larger diameter in the attachment layer than in the routing layer.

[0111] When forming the backplane 110, the ground plane 1030 is partially removed to form a seventh isolation plate 1080 surrounding both the signal via 610 and the signal via 612. The isolation plate 1080 may have a width 1082 that is equal to or slightly larger than the isolation plates 670 and 672 in the top layer 602 ( Figure 6). The width 1082 of the isolation disk 1080 is selected based on the diameter of the signal vias 610 and 612 in layer 712. Thus, the width 1082 of the isolation disk 1080 in the attachment layer can be greater than the width of the isolation disk in the routing layer. However, this is not necessarily the case, and in some embodiments, the spacing between the edge of the signal via and the ground plane can be selected at each layer to provide a desired impedance, or otherwise provide a desired electrical property. Fig.10 In the embodiment of the present invention, the isolation disk 1080 is rectangular in shape.

[0112] The via pattern 1000 of layer 712 also includes ground vias 630, 632, 634, and 636, which have the same location and configuration as the corresponding ground vias in top layer 602. Typically, the ground vias interconnect the ground planes in all layers of the backplane 110.

[0113] The via pattern 1000 of layer 712 also includes ground shadow vias 640, 642, 644, and 646 that extend vertically through the attachment layer and the routing layer. The diameter of the ground shadow vias in layer 712 may be smaller than the diameter of the ground shadow vias in the routing layer.

[0114] The via pattern 1000 of layer 712 also includes non-plated holes 650, 652, 654, and 656, which have the same location and configuration as the corresponding non-plated holes in the top attach layer 602. As mentioned above, the non-plated holes extend to a predetermined depth 742.

[0115] Fig.11 Layer 722 ( Figure 7 ). Layer 722 is a layer below the predetermined depth 742. Layer 722 represents the layers between the predetermined depth 742 and the bottom of the backplane 110, except for the wiring layer 730, and the layers 728 and 732 above and below the wiring layer 730, respectively. Layer 722 is a wiring layer.

[0116] Fig.11 1 and 2 show a via pattern 1100. It should be understood that the via pattern 1100 is similar to the via pattern 600 ( Figure 6 ) and 820( Figure 8 ) are aligned in the vertical direction. It should also be understood that the via pattern 1100 is not visible in the backplane 110 after the layers of the backplane are pressed together.

[0117] The via pattern 1100 of layer 722 includes signal vias 610 and 612. Signal vias 610 and 612 may have a smaller diameter in the routing layer than in the attachment layer.

[0118] When forming the back plate 110, the ground plane 1130 is partially removed to form an eighth isolation plate 1180 surrounding both the signal via 610 and the signal via 612. The isolation plate 1180 may have a width 1182 that is smaller than the width 1082 ( Fig.10 ). The width 1182 of the isolation disk 1180 is selected based on the diameter of the signal vias 610 and 612 in the layer 722. Thus, the width 1182 of the isolation disk 1180 in the routing layer can be less than the width of the isolation disk in the attachment layer. However, this is not necessarily the case, and in some embodiments, the spacing between the signal via and the edge of the ground plane can be selected at each layer to provide a desired impedance, or otherwise provide a desired electrical property. Fig.11 In the embodiment, the isolation disk 1180 is rectangular in shape.

[0119] The via pattern 1100 of layer 722 also includes ground vias 630, 632, 634, and 636, which have the same location and configuration as the corresponding ground vias in top layer 602. Typically, the ground vias interconnect the ground planes in all layers of the backplane 110.

[0120] The via pattern 1100 of layer 722 also includes ground shadow vias 640, 642, 644, and 646 that extend vertically through the attachment layer and the routing layer. The diameter of the ground shadow via in layer 722 can be larger than the diameter of the ground shadow via in the attachment layer. Non-plated holes 650, 652, 654, and 656 ( Figure 6 ) does not extend to layer 722 and in Fig.11 Not shown.

[0121] In summary, different layers of the backplane 110 can have different isolation disk configurations to provide desired performance. Some layers can include separate isolation disks around each signal via with conductive tape between the isolation disks. Some layers can include a single isolation disk around both the first signal via and the second signal via. The size of the isolation disk can be based on the diameter of the signal via, with larger isolation disks used with signal vias having larger diameters. The isolation disk can be configured to improve signal transmission on, for example, a signal wiring layer.

[0122] In one non-limiting example corresponding to the via dimensions described above, the width 676 of the first and second isolating discs 670 and 672 is 1.1 mm, the width 836 of the third and fourth isolating discs 830 and 832 is 0.86 mm, the width 936 of the fifth and sixth isolating discs 980 and 982 is 0.86 mm, the width 1082 of the seventh isolating disc 1080 is 1.12 mm, and the width 1182 of the eighth isolating disc 1180 is 0.86 mm. The spacers 674, 838, and 938 may have a width of 0.22 mm. It should be understood that these dimensions are not limiting and other dimensions may be used.

[0123] Many features of a printed circuit board are shown and described herein. It should be understood that these features may be employed alone or in combination in a particular application without departing from the scope of the present disclosure.

[0124] Thus, having described at least one illustrative embodiment of the present invention, various changes, modifications and improvements will readily occur to those skilled in the art. For example, a layer may be described as an upper layer, or "above" or "below" other layers. It should be appreciated that these terms are for ease of description and are not intended to limit the orientation of the layers. In the illustrated embodiment, "upper" refers to the direction toward the surface of the printed circuit board to which the component is attached. In some embodiments, the component may be attached to both sides of the printed circuit board, and the upper and lower portions may depend on the vias currently under consideration. Such changes, modifications and improvements are intended to be part of this disclosure and are intended to fall within the spirit and scope of the present invention. Thus, the foregoing description is intended to be exemplary and not restrictive. The present invention is limited only by the appended claims and their equivalents.

Claims

1. A printed circuit board, comprising: multiple layers, including attachment and routing layers; as well as a via pattern formed in one or more of the plurality of layers, each of the via patterns comprising: a first signal via and a second signal via configured to receive contact tails of signal conductors of the connector; a ground via configured to receive a contact tail of a ground conductor of the connector; a ground shadow via positioned adjacent to each of the first signal via and the second signal via; and A non-plated hole is located between each of the ground shadow vias and the signal via. 2 . The printed circuit board of claim 1 , wherein the non-plated vias extend to a predetermined depth in the plurality of layers. 3 . The printed circuit board according to claim 2 , wherein the predetermined depth is a depth of a boundary between the attachment layer and the wiring layer. 4 . The printed circuit board of claim 2 , wherein the predetermined depth is equal to or greater than a length of the contact tail of the signal conductor of the connector. 5 . The printed circuit board of claim 1 , wherein each of the first signal via and the second signal via is configured to have a first section having a first diameter and a second section having a second diameter smaller than the first diameter. 6 . The printed circuit board of claim 5 , wherein the first signal via and the second signal via are plated with a conductive material from a top surface of the printed circuit board to at least a wiring layer of the wiring layer. 7 . The printed circuit board of claim 6 , wherein the first signal via and the second signal via are not plated with the conductive material under the wiring layer. 8 . The printed circuit board of claim 5 , wherein each of the ground shadow vias is configured to have a third section having a third diameter and a fourth section having a fourth diameter greater than the third diameter.

9. The printed circuit board of claim 1, wherein each of the ground shadow vias extends through the plurality of layers and is plated with a conductive material through the plurality of layers.

10. The printed circuit board of claim 1, wherein each of the ground vias extends through the plurality of layers and is plated with a conductive material through the plurality of layers.

11. The printed circuit board of claim 1, wherein the attachment layer comprises a top layer having a first isolation pad surrounding the first signal via, a second isolation pad surrounding the second signal via, and a conductive strip separating the first isolation pad and the second isolation pad.

12. The printed circuit board according to claim 11, wherein the wiring layer includes a wiring layer having a third isolation pad surrounding the first signal via, a fourth isolation pad surrounding the second signal via, and a conductive strip separating the third isolation pad and the fourth isolation pad.

13. A printed circuit board according to claim 12, wherein each of the wiring layer immediately above the wiring layer and the wiring layer immediately below the wiring layer includes a fifth isolation plate surrounding the first signal via, a sixth isolation plate surrounding the second signal via, and a conductive strip separating the fifth isolation plate and the sixth isolation plate. 14 . The printed circuit board of claim 13 , wherein each of the attachment layers except the top layer comprises a seventh isolation pad surrounding both the first signal via and the second signal via.

15. The printed circuit board according to claim 14, wherein Each of the wiring layers other than the wiring layer, and the wiring layer immediately above the wiring layer and the wiring layer immediately below the wiring layer includes an eighth isolation pad surrounding both the first signal via and the second signal via.

16. The printed circuit board of claim 1, wherein a center of each of the non-plated holes is equally spaced from respective centers of the signal via and the ground shadow via.

17. A printed circuit board comprising: multiple layers, including attachment and routing layers; as well as a via pattern formed in one or more of the plurality of layers, each of the via patterns comprising: a first signal via and a second signal via configured to receive a contact tail of a signal conductor of a connector, wherein each of the first signal via and the second signal via is configured to have a first segment in the attachment layer having a first diameter, and a second segment in the routing layer having a second diameter smaller than the first diameter; a ground via configured to receive a contact tail of a ground conductor of the connector; a ground shadow via positioned adjacent to each of the first signal via and the second signal via, wherein each of the ground shadow vias is configured to have a first section in the attachment layer having a third diameter, and a second section in the routing layer having a fourth diameter greater than the third diameter; and A non-plated hole is located in the attachment layer between each of the ground shadow vias and the signal via. 18 . The printed circuit board of claim 17 , wherein the first diameters of the first signal via and the second signal via are greater than the third diameter of the ground shadow via. 19 . The printed circuit board of claim 18 , wherein the second diameters of the first signal via and the second signal via are greater than the fourth diameter of the ground shadow via.

20. The printed circuit board of claim 17, wherein a diameter of the non-plated hole is equal to the third diameter of the ground shadow via.

21. The printed circuit board of claim 17, wherein a center of each of the non-plated holes is equally spaced from respective centers of the signal via and the ground shadow via.

22. The printed circuit board of claim 17, wherein the attachment layer comprises a top layer having a first isolation pad surrounding the first signal via, a second isolation pad surrounding the second signal via, and a conductive strip separating the first isolation pad and the second isolation pad.

23. The printed circuit board of claim 22, wherein the wiring layer comprises a wiring layer having a third isolation pad surrounding the first signal via, a fourth isolation pad surrounding the second signal via, and a conductive strip separating the third isolation pad and the fourth isolation pad.

24. A printed circuit board according to claim 23, wherein each of the wiring layer immediately above the wiring layer and the wiring layer immediately below the wiring layer includes a fifth isolation plate surrounding the first signal via, a sixth isolation plate surrounding the second signal via, and a conductive strip separating the fifth isolation plate and the sixth isolation plate. 25 . The printed circuit board of claim 24 , wherein each of the attachment layers except the top layer comprises a seventh isolation pad surrounding both the first signal via and the second signal via.

26. The printed circuit board according to claim 25, wherein Each of the wiring layers other than the wiring layer, and the wiring layer immediately above the wiring layer and the wiring layer immediately below the wiring layer includes an eighth isolation pad surrounding both the first signal via and the second signal via. 27 . The printed circuit board of claim 26 , wherein the third, fourth, fifth and sixth separation disks have equal widths.

28. The printed circuit board of claim 27, wherein the first and second separation disks have a greater width than the third and fourth separation disks.

29. The printed circuit board of claim 28, wherein the seventh separation disk has a width greater than that of the eighth separation disk.

30. A method of manufacturing a via pattern in a printed circuit board comprising a plurality of layers, the method comprising: forming a first signal via and a second signal via to receive contact tails of a signal conductor of the connector; forming a ground via to receive a contact tail of a ground conductor of the connector; forming a ground shadow via positioned adjacent to each of the first signal via and the second signal via; as well as A non-plated hole is formed between each of the ground shadow vias and the signal via.

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