A fast phase locking circuit for phase-locked loop recovery from transition mode

Abstract

The present invention discloses a phase fast locking circuit for a phase-locked loop to recover from a transition mode, which belongs to the field of integrated circuits and includes: a frequency detector-charge pump, a voltage-controlled oscillator, a transition circuit, a feedback divider, a switch, a first inverter, a second inverter, a first AND gate, a second AND gate, a NOR gate, a first trigger, and a second trigger. The present invention can use a backup transition circuit to maintain the voltage-controlled oscillator to operate at a stable frequency during the abnormal disconnection of the input reference signal CLK_REF, and use the continuous resetting of the feedback divider to achieve synchronization of the output feedback clock DIVIDER_OUT and the input reference signal CLK_REF when the input reference signal CLK_REF recovers from the abnormal disconnection state, greatly reducing the maximum phase difference between the output feedback clock DIVIDER_OUT and the input reference signal CLK_REF when the input reference signal CLK_REF recovers from the abnormal disconnection state, so that the voltage-controlled oscillator can continue to maintain a stable frequency to maintain the normal operation of the system during the abnormality and recovery of the input reference signal.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuits, and in particular to a phase fast locking circuit for a phase locked loop to recover from a transition mode. Background Art

[0002] A phase locked loop (PLL) is a circuit that uses an external reference signal to control the frequency and phase of an oscillating signal inside the loop, and obtains a dynamically locked output clock signal by responding to the feedback frequency and phase of the output signal.

[0003] The phase-locked loop is usually composed of several main modules, including the phase frequency detector (PFD), charge pump (CP), loop filter (LF), and voltage controlled oscillator (VCO). The function of the phase frequency detector is to detect the frequency and phase difference between the input signal and the output feedback signal, and output the corresponding control signal to the charge pump, so as to further adjust the frequency and phase of the voltage controlled oscillator. When there is a frequency or phase difference between the input signal and the output feedback signal, the PFD and CP will adjust the control voltage VCTRL of the VCO, so as to further adjust the frequency and phase of the VCO output clock VCO_CLK. In a stably operating system, there is usually a need to keep the frequency of the VCO output clock VCO_CLK stable during operation. Summary of the invention

[0004] The object of the present invention is to provide a phase fast locking circuit for a phase locked loop to recover from a transition mode, so as to solve the problems in the background technology.

[0005] In order to solve the above technical problems, the present invention provides a phase fast locking circuit for a phase-locked loop to recover from a transition mode, comprising: a frequency detector-charge pump, a voltage-controlled oscillator, a transition circuit, a feedback frequency divider, a switch, a first inverter, a second inverter, a first AND gate, a second AND gate, a NOR gate, a first trigger and a second trigger;

[0006] CLK_REF and DIVIDER_OUT are the input reference signal and feedback signal of the frequency detector-charge pump detection respectively; the reference signal CLK_REF is connected to the clock end of the first trigger and the clock end of the second trigger at the same time; REF_READY_FLAG represents the indication signal that CLK_REF is normal, and is connected to the D end of the first trigger, the enable end of the first trigger and the enable end of the second trigger at the same time;

[0007] The Q end of the first trigger is connected to the D end of the second trigger and the first input end of the first AND gate at the same time; the Q end of the second trigger is connected to the second input end of the first AND gate through the first inverter; the output end of the first AND gate is connected to the first input end of the second AND gate;

[0008] The positive input end of the transition circuit is connected to the signal value VCTRL_MONITOR monitored when the voltage-controlled oscillator is working stably, and the output end is connected to the negative input end and the output end of the frequency detector-charge pump through a switch; the input end of the voltage-controlled oscillator is connected to the output end of the frequency detector-charge pump and the output end of the transition circuit at the same time, the output end of the voltage-controlled oscillator is connected to the input end of the feedback frequency divider, the first input end of the NOR gate and the input end of the second inverter at the same time, the output end of the second inverter is connected to the second input end of the NOR gate; the output end of the NOR gate is connected to the second input end of the second AND gate;

[0009] The output end of the second AND gate generates a reset signal RESET_DIV of the feedback divider, and the feedback divider outputs a feedback clock DIVIDER_OUT to the frequency detector-charge pump.

[0010] In one embodiment, when the input reference signal CLK_REF works normally, REF_READY_FLAG is pulled high, the control voltage VCTRL standby transition circuit output switch of the voltage controlled oscillator is disconnected, and the control voltage VCTRL is determined by the frequency detector-charge pump;

[0011] When the input reference signal CLK_REF is abnormally disconnected, REF_READY_FLAG is pulled low, the output switch of the standby transition circuit of the control voltage VCTRL of the voltage-controlled oscillator is turned on, and the control voltage VCTRL is determined by the transition circuit. The transition circuit forces the monitored signal value VCTRL_MONITOR when the voltage-controlled oscillator is working stably to be injected into the control voltage VCTRL. When the input reference signal CLK_REF is abnormally disconnected, the voltage-controlled oscillator continues to work at a stable frequency;

[0012] When the abnormal disconnection state of the input reference signal CLK_REF is restored, the output switch of the standby transition circuit of the control voltage VCTRL of the voltage controlled oscillator is disconnected, and the control voltage VCTRL returns to being determined by the frequency detector-charge pump again.

[0013] In one embodiment, the output signal VCO_CLK_FALLING_PULSE of the NOR gate is generated by the output clock VCO_CLK of the voltage-controlled oscillator through the second inverter and the NOR gate, and is manifested as a short pulse generated at the falling edge of VCO_CLK; the first rising edge of the abnormal disconnection state of the input reference signal CLK_REF is recovered as the T1 moment, the abnormal disconnection state of the input reference signal CLK_REF is recovered, and after a short delay, the peripheral circuit will detect the recovery state of CLK_REF and pull up REF_READY_FLAG, and at this time, there is a large phase difference between the input reference signal CLK_REF that has just been recovered and the feedback signal DIVIDER_OUT; the second rising edge of the abnormal disconnection state of the input reference signal CLK_REF is recovered as the T2 moment, and the pulled-up REF_READY_FLAG passes through the trigger at the rising edge of the input reference signal CLK_REF through the logic control of the first trigger, the second trigger, the first inverter, and the first AND gate to pull REF_READY_PULSE. SE is pulled to a high level signal, and the high level signal of REF_READY_PULSE is maintained until the next rising edge of the input reference signal CLK_REF. At time T3, the high level REF_READY_PULSE and VCO_CLK_FALLING_PULSE generate the reset signal RESET_DIV of the feedback divider DIVIDER through the second AND gate, and the feedback divider DIVIDER is reset at each falling edge of VCO_CLK from time T2 to T3; at time T3, REF_READY_PULSE returns to a low level, and no high level pulse of RESET_DIV is generated. The feedback divider DIVIDER will restart the frequency division count at the first rising edge of VCO_CLK after the last high level pulse of the reset signal RESET_DIV, and at this time, the maximum phase difference between the output feedback signal DIVIDER_OUT generated by the feedback divider DIVIDER and the input reference signal CLK_REF is reduced to half a cycle of VCO_CLK.

[0014] The present invention provides a phase fast locking circuit for a phase-locked loop to recover from a transition mode, which effectively solves the frequency drift problem faced by a traditional phase-locked loop when an input reference signal CLK_REF is abnormally disconnected and recovered from the abnormality. The circuit structure proposed by the present invention can use a backup transition circuit to maintain a voltage-controlled oscillator to operate at a stable frequency during the period when the input reference signal CLK_REF is abnormally disconnected, and use continuous resetting of the feedback divider to achieve synchronization of the output feedback clock signal DIVIDER_OUT with the input reference signal CLK_REF when the input reference signal CLK_REF is recovered from the abnormal disconnection state, thereby greatly reducing the maximum phase difference between the output feedback clock signal DIVIDER_OUT and the input reference signal CLK_REF when the input reference signal CLK_REF is recovered from the abnormal disconnection state, so that the voltage-controlled oscillator can continue to maintain a stable frequency to maintain normal operation of the system during the process of abnormality and recovery of the input reference signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 The present invention is a schematic diagram of a phase fast locking circuit structure for a phase-locked loop to recover from a transition mode.

[0016] Figure 2 The present invention is a timing diagram of a phase fast locking circuit for a phase-locked loop to recover from a transition mode. DETAILED DESCRIPTION

[0017] The following is a further detailed description of a phase fast locking circuit for recovering a phase-locked loop from a transition mode proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0018] The present invention proposes a phase fast locking circuit for recovering a phase-locked loop from a transition mode, and its structural block diagram is as follows: Figure 1 As shown, it includes: a phase frequency detector-charge pump (PFD-CP), a voltage controlled oscillator (VCO), a transition circuit (Holdover), a feedback divider (DIVIDER), a switch SW1, an inverter INV1, an inverter INV2, an AND gate AND1, an AND gate AND2, a NOR gate NOR1, a trigger DFF1 and a trigger DFF2.

[0019] The reference signal CLK_REF is connected to the clock end of the trigger DFF1 and the clock end of the trigger DFF2 at the same time; REF_READY_FLAG represents the indication signal that CLK_REF is detected to be normal, and is connected to the D end of the trigger DFF1, the enable end of the trigger DFF1 and the enable end of the trigger DFF2 at the same time; the Q end of the trigger DFF1 is connected to the D end of the trigger DFF2 and the first input end of the AND gate AND1 at the same time; the Q end of the trigger DFF2 is connected to the second input end of the AND gate AND1 through the inverter INV1; the output end of the AND gate AND1 is connected to the first input end of the AND gate AND2;

[0020] The positive input end of the transition circuit is connected to the signal value VCTRL_MONITOR monitored when the voltage-controlled oscillator VCO is working stably, and the output end is connected to the negative input end and the output end of the frequency detector-charge pump through a switch; the input end of the voltage-controlled oscillator VCO is connected to the output end of the frequency detector-charge pump and the output end of the transition circuit at the same time, and the output end of the voltage-controlled oscillator VCO is connected to the input end of the feedback frequency divider, the first input end of the NOR gate NOR1 and the input end of the inverter INV2 at the same time, and the output end of the inverter INV2 is connected to the second input end of the NOR gate NOR1; the output end of the NOR gate NOR1 is connected to the second input end of the AND gate AND2;

[0021] The output end of the AND gate AND2 generates a reset signal RESET_DIV of the feedback divider, and the feedback divider outputs a feedback clock DIVIDER_OUT to the frequency detector-charge pump.

[0022] Among them, CLK_REF and DIVIDER_OUT are respectively the input reference signal and feedback signal detected by the phase frequency detector PFD; REF_READY_FLAG represents the indication signal that CLK_REF is normal; VCTRL_MONITOR represents the real-time monitoring signal for the control voltage VCTRL. When the input reference signal CLK_REF works normally, REF_READY_FLAG is pulled high, the output switch SW1 of the VCTRL standby transition circuit Holdover circuit is disconnected, and the control voltage VCTRL of the voltage-controlled oscillator VCO is determined by the phase frequency detector PFD and the charge pump CP; when the input reference signal CLK_REF is abnormally disconnected, REF_READY_FLAG is pulled low, the output switch SW1 of the VCTRL standby transition circuit Holdover circuit is turned on, and the control voltage VCTRL of the voltage-controlled oscillator VCO is determined by the Holdover circuit. The Holdover circuit forces the monitored signal value VCTRL_MONITOR when the voltage-controlled oscillator VCO is working stably into VCTRL, so that the voltage-controlled oscillator VCO is stable when the input reference signal CLK_REF is abnormally disconnected. The VCO can continue to maintain a stable frequency operation; when the abnormal disconnection state of the input reference signal CLK_REF is restored, the output switch SW1 of the VCTRL standby circuit Holdover circuit is disconnected, and the voltage controlled oscillator VCO control voltage VCTRL returns to being determined by the phase frequency detector PFD and the charge pump CP. However, the phase of the restored input reference signal CLK_REF is usually not consistent with the voltage controlled oscillator VCO output clock VCO_CLK and the output feedback clock DIVIDER_OUT. If there is a phase difference between the input signal CLK_REF and the output feedback clock DIVIDER_OUT, the phase frequency detector PFD and the charge pump CP will adjust the operating frequency of the voltage controlled oscillator VCO. A stable operating system usually hopes that the frequency of the voltage controlled oscillator VCO output clock VCO_CLK remains stable.

[0023] pass Figure 1 The phase fast locking circuit structure recovered from the transition mode shown in the figure can reduce the maximum phase difference between the input reference signal CLK_REF and the output feedback clock DIVIDER_OUT when the input reference signal CLK_REF is recovered from half the period of the input reference signal CLK_REF to half the period of the VCO output clock VCO_CLK. Since the frequency of VCO_CLK is usually tens or even hundreds of times that of CLK_REF, the circuit structure provided by the present invention can greatly reduce the maximum phase difference of the input signal of the phase frequency detector PFD when the input reference signal CLK_REF is recovered from an abnormality, so that the voltage-controlled oscillator VCO can continue to operate at a more stable frequency.

[0024] Figure 2The figure shows the working timing diagram of the phase fast locking circuit for the phase-locked loop to recover from the transition mode, where VCO_CLK_FALLING_PULSE is generated by VCO_CLK through the inverter INV2 and the NOR gate NOR1, and is manifested as a short pulse generated at the falling edge of VCO_CLK. At time T1, i.e., the first rising edge of the abnormal disconnection state of the input reference signal CLK_REF, the abnormal disconnection state of the input reference signal CLK_REF is restored. After a short delay, the peripheral circuit will detect the recovery state of CLK_REF and pull REF_READY_FLAG high. At this time, there is a large phase difference between the input reference signal CLK_REF that has just been restored and the feedback clock DIVIDER_OUT. At time T2, i.e., the second rising edge of the abnormal disconnection state of the input reference signal CLK_REF, the pulled-up REF_READY_FLAG passes through the trigger at the rising edge of the input reference signal CLK_REF through the triggers DFF1, DFF2, the inverter INV1, and the logic control of the AND gate AND1 to pull REF_READY_PULSE to a high level signal, and keep the high level signal of REF_READY_PULSE until the input reference signal CLK At the next rising edge of K_REF (i.e., time T3), the high-level REF_READY_PULSE and VCO_CLK_FALLING_PULSE generate the reset signal RESET_DIV of the feedback divider DIVIDER through the AND gate AND2, and the feedback divider DIVIDER is reset at each falling edge of VCO_CLK from time T2 to T3; at time T3, REF_READY_PULSE returns to a low level and no longer generates a high-level pulse of RESET_DIV. The feedback divider DIVIDER restarts the frequency division count at the first rising edge of VCO_CLK after the last high-level pulse of the reset signal RESET_DIV. At this time, the maximum phase difference between the output feedback clock DIVIDER_OUT generated by the feedback divider DIVIDER and the input reference signal CLK_REF is reduced to half a cycle of VCO_CLK.

[0025] The present invention uses a simple structure to significantly reduce the maximum phase difference between the output feedback clock DIVIDER_OUT and the input reference signal CLK_REF when the input reference signal CLK_REF recovers from an abnormality, thereby further enabling the voltage-controlled oscillator VCO to continue to maintain a more stable frequency during the abnormality and recovery of the input reference signal to maintain normal operation of the system. Figure 1The circuit structure shown continuously resets the feedback divider DIVIDER during the first and second rising edges of the input reference signal CLK_REF after the input reference signal CLK_REF recovers from the abnormal disconnection state, thereby achieving synchronization between the output feedback clock DIVIDER_OUT and the input reference signal CLK_REF, and thereby significantly reducing the initial phase difference.

[0026] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A phase fast locking circuit for a phase-locked loop to recover from a transition mode, characterized in that: include: Frequency detector and phase detector - charge pump, voltage controlled oscillator, transition circuit, feedback frequency divider, switch, first inverter, second inverter, first AND gate, second AND gate, NOR gate, first trigger and second trigger; CLK_REF and DIVIDER_OUT are the input reference signal and feedback signal of the frequency detector-charge pump respectively; the reference signal CLK_REF is connected to the clock end of the first trigger and the clock end of the second trigger at the same time; REF_READY_FLAG represents the indication signal that CLK_REF is normal, and is connected to the D end of the first trigger, the enable end of the first trigger and the enable end of the second trigger at the same time; The Q end of the first trigger is connected to the D end of the second trigger and the first input end of the first AND gate at the same time; the Q end of the second trigger is connected to the second input end of the first AND gate through the first inverter; the output end of the first AND gate is connected to the first input end of the second AND gate; The positive input end of the transition circuit is connected to the signal value VCTRL_MONITOR monitored when the voltage-controlled oscillator is working stably, and the output end is connected to the negative input end and the output end of the frequency detector-charge pump through a switch; the input end of the voltage-controlled oscillator is connected to the output end of the frequency detector-charge pump and the output end of the transition circuit at the same time, the output end of the voltage-controlled oscillator is connected to the input end of the feedback frequency divider, the first input end of the NOR gate and the input end of the second inverter at the same time, the output end of the second inverter is connected to the second input end of the NOR gate; the output end of the NOR gate is connected to the second input end of the second AND gate; The output end of the second AND gate generates a reset signal RESET_DIV of the feedback divider, and the feedback divider outputs a feedback clock DIVIDER_OUT to the frequency detector-charge pump.

2. The phase fast locking circuit for recovering a phase-locked loop from a transition mode according to claim 1, characterized in that: When the input reference signal CLK_REF works normally, REF_READY_FLAG is pulled high, the control voltage VCTRL standby transition circuit output switch of the voltage-controlled oscillator is disconnected, and the control voltage VCTRL is determined by the frequency detector-charge pump; When the input reference signal CLK_REF is abnormally disconnected, REF_READY_FLAG is pulled low, the output switch of the standby transition circuit of the control voltage VCTRL of the voltage-controlled oscillator is turned on, and the control voltage VCTRL is determined by the transition circuit. The transition circuit forces the monitored signal value VCTRL_MONITOR when the voltage-controlled oscillator is working stably to be injected into the control voltage VCTRL. When the input reference signal CLK_REF is abnormally disconnected, the voltage-controlled oscillator continues to work at a stable frequency; When the abnormal disconnection state of the input reference signal CLK_REF is restored, the output switch of the standby transition circuit of the control voltage VCTRL of the voltage controlled oscillator is disconnected, and the control voltage VCTRL returns to being determined by the frequency detector-charge pump again.

3. The phase fast locking circuit for recovering a phase-locked loop from a transition mode as claimed in claim 2, characterized in that: The output signal VCO_CLK_FALLING_PULSE of the NOR gate is generated by the output clock VCO_CLK of the voltage-controlled oscillator through the second inverter and the NOR gate, and is manifested as a short pulse generated at the falling edge of VCO_CLK; the first rising edge of the abnormal disconnection state of the input reference signal CLK_REF is recovered as the T1 moment, and the abnormal disconnection state of the input reference signal CLK_REF is recovered. After a short delay, the peripheral circuit will detect the recovery state of CLK_REF and pull REF_READY_FLAG high. At this time, there is a large phase difference between the input reference signal CLK_REF that has just been recovered and the feedback signal DIVIDER_OUT; the second rising edge of the abnormal disconnection state of the input reference signal CLK_REF is recovered as the T2 moment, and the pulled-up REF_READY_FLAG passes through the trigger and the logic control of the first trigger, the second trigger, the first inverter, and the first AND gate at the rising edge of the input reference signal CLK_REF pulls REF_READY_PULSE to a high level. level signal, and keep the high level signal of REF_READY_PULSE until the next rising edge of the input reference signal CLK_REF. At time T3, the high level REF_READY_PULSE and VCO_CLK_FALLING_PULSE generate the reset signal RESET_DIV of the feedback divider DIVIDER through the second AND gate, and reset the feedback divider DIVIDER at each falling edge of VCO_CLK from time T2 to T3; at time T3, REF_READY_PULSE returns to a low level and no longer generates a high level pulse of RESET_DIV. The feedback divider DIVIDER restarts the frequency division count at the first rising edge of VCO_CLK after the last high level pulse of the reset signal RESET_DIV. At this time, the maximum phase difference between the output feedback signal DIVIDER_OUT generated by the feedback divider DIVIDER and the input reference signal CLK_REF is reduced to half a cycle of VCO_CLK.

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