Differential-based MRAM storage cell and preparation method thereof, MRAM storage cell array, MRAM memory and chip

Abstract

The present disclosure relates to the field of storage technology, and specifically to a differential-based MRAM storage cell and its preparation method, an MRAM storage cell array, an MRAM memory, and a chip. The present disclosure innovatively introduces a dual magnetic tunnel junction comprising a first magnetic tunnel junction and a second magnetic tunnel junction into the MRAM storage cell. The first and second magnetic tunnel junctions are mirror-imaged on both sides of a first metal layer, with their free layers both electrically contacting the first metal layer, and their fixed layers electrically contacting the second and third metal layers, respectively. When a write operation is performed on the MRAM storage cell, data is written by applying write currents in different directions passing through the dual magnetic tunnel junctions. When a read operation is performed on the MRAM storage cell, data is read by determining the difference in magnetic resistance between the first magnetic tunnel junction and the second magnetic tunnel junction. This effectively resists interference from external magnetic fields.

Description

Technical Field

[0001] The present disclosure relates to the field of storage technology, and in particular to a differential-based MRAM storage cell and a preparation method thereof, an MRAM storage cell array, an MRAM memory, and a chip. Background Art

[0002] With the rapid development of electronic information technology, the demand for high-speed, high-density, non-volatile memory is growing. Magnetoresistive random access memory (MRAM), a new type of memory that combines the high-speed read and write capabilities of static random access memory (SRAM) with the high density and non-volatility of dynamic random access memory (DRAM), has attracted widespread attention and research. The basic principle of MRAM is similar to that of hard disk drives, both relying on the magnetization state of magnetic materials to store data. MRAM offers significant advantages in terms of integration, read and write speed, and power consumption.

[0003] The basic storage unit of existing MRAM is primarily composed of a magnetic tunnel junction (MTJ). The MTJ has a unique structure, with its core consisting of two layers of ferromagnetic material (a "free" ferromagnetic layer and a "pinned" ferromagnetic layer) sandwiched by an extremely thin insulating shielding layer (such as magnesium oxide or aluminum oxide). This structure gives the MTJ a bistable tunnel magnetoresistance (TMR) effect. When the spin magnetic states of the "free" and "pinned" ferromagnetic layers are parallel or antiparallel, the MTJ exhibits two stable states: low resistance and high resistance, respectively. These two states can be used to represent the logical data "0" and "1," respectively.

[0004] However, despite MRAM's theoretically near-infinite write cycles and excellent non-volatility, practical applications still face challenges. In particular, MRAM relies on the magnetization state within the MTJ, a state that is susceptible to interference from strong external magnetic fields. When exposed to strong interfering magnetic fields, the "free" ferromagnetic layer within the MTJ can be affected, causing its magnetization direction to change. This can lead to erroneous data flips, severely impacting MRAM's read and write accuracy and data reliability.

[0005] Therefore, developing a new type of MRAM that can effectively resist interference from external magnetic fields has become an important issue that needs to be urgently addressed in the current field of storage technology. Summary of the Invention

[0006] In order to solve the problems in the related art, the embodiments of the present disclosure provide an MRAM memory cell based on a differential form and a preparation method thereof, an MRAM memory cell array, an MRAM memory and a chip.

[0007] In a first aspect, an embodiment of the present disclosure provides a differential MRAM memory cell, the MRAM memory cell comprising: a MOS transistor, a dual magnetic tunnel junction, a first metal layer, a second metal layer, and a third metal layer; wherein the dual magnetic tunnel junction comprises: a first magnetic tunnel junction and a second magnetic tunnel junction; the first magnetic tunnel junction and the second magnetic tunnel junction respectively comprise a fixed layer, a non-magnetic tunnel layer, and a free layer arranged in sequence;

[0008] The first magnetic tunnel junction and the second magnetic tunnel junction are mirror-imaged and arranged on both sides of the first metal layer. The free layer of the first magnetic tunnel junction and the free layer of the second magnetic tunnel junction are respectively in electrical contact with the first metal layer. The fixed layer of the first magnetic tunnel junction is in electrical contact with the second metal layer, and the fixed layer of the second magnetic tunnel junction is in electrical contact with the third metal layer.

[0009] The gate of the MOS transistor is connected to the word line, the source of the MOS transistor is connected to the source line, and the drain of the MOS transistor is connected to the third metal layer;

[0010] When the MRAM storage cell is in a write state, the second metal layer, the word line, and the source line are respectively connected to a data write circuit, and a write current penetrating the dual magnetic tunnel junction is formed between the second metal layer and the drain of the MOS transistor according to write data through the data write circuit, so that the data write circuit writes the write data into the MRAM storage cell through the write current, wherein the direction of the write current corresponds to the write data;

[0011] When the MRAM memory cell is in a read state, the first metal layer is connected to a first input terminal of a data read circuit, and the second metal layer and the third metal layer are respectively connected to a second input terminal of the data read circuit, so that the data read circuit reads data of the MRAM memory cell based on the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction, and the data of the MRAM memory cell is output through the output terminal of the data read circuit; wherein the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction includes a positive magnetoresistance difference and a negative magnetoresistance difference, the positive magnetoresistance difference being formed because the magnetoresistance of the first magnetic tunnel junction is greater than that of the second magnetic tunnel junction, and the negative magnetoresistance difference being formed because the magnetoresistance of the first magnetic tunnel junction is less than that of the second magnetic tunnel junction.

[0012] According to an embodiment of the present disclosure, the direction of the write current includes a first direction and a second direction;

[0013] When the direction of the write current is the first direction, the write current is the first write current;

[0014] When the direction of the write current is the second direction, the write current is the second write current;

[0015] The direction of the write current corresponds to the write data, including:

[0016] The first write current corresponds to the first write data; the second write current corresponds to the second write data;

[0017] The first written data is 0, and the second written data is 1; or the first written data is 1, and the second written data is 0.

[0018] According to an embodiment of the present disclosure, forming a write current penetrating the dual magnetic tunnel junction between the second metal layer and the drain of the MOS transistor according to write data includes:

[0019] When the write data is first write data, a first write current is formed between the second metal layer and the drain of the MOS transistor and penetrates the dual magnetic tunnel junction;

[0020] When the write data is second write data, a second write current penetrating the dual magnetic tunnel junction is formed between the second metal layer and the drain of the MOS transistor.

[0021] According to an embodiment of the present disclosure, forming a first write current between the second metal layer and the drain of the MOS transistor and penetrating the dual magnetic tunnel junction includes:

[0022] When a high level is input to the word line to turn on the MOS transistor, and at the same time a first voltage is applied to the second metal layer and a second voltage is applied to the source line, and the first voltage is greater than the second voltage, a first write current is generated that flows from the second metal layer to the drain of the MOS transistor and penetrates the dual magnetic tunnel junction, and the first write current flows out from the source of the MOS transistor;

[0023] The forming of a second write current penetrating the dual magnetic tunnel junction between the second metal layer and the drain of the MOS transistor includes:

[0024] When a high level is input to the word line to turn on the MOS transistor, and a first voltage is applied to the source line and a second voltage is applied to the second metal layer, and the first voltage is greater than the second voltage, a second write current is generated that flows from the drain of the MOS transistor to the second metal layer and penetrates the dual magnetic tunnel junction, and the second write current flows out from the second metal layer;

[0025] Wherein, turning on the MOS transistor includes: when the MOS transistor is an NMOS transistor, applying a forward bias voltage between the gate and source of the MOS transistor; when the MOS transistor is a PMOS transistor, applying a negative bias voltage between the gate and source of the MOS transistor, so that the MOS transistor is turned on.

[0026] According to an embodiment of the present disclosure, writing the write data into the MRAM storage cell by using the write current includes:

[0027] When the write current is the first write current, then:

[0028] The first write current flows from the fixed layer to the free layer of the first magnetic tunnel junction, causing the magnetization directions of the free layer of the first magnetic tunnel junction and the fixed layer of the first magnetic tunnel junction to be opposite, and the magnetoresistance state of the first magnetic tunnel junction to be a high-resistance state; the first write current flows from the free layer to the fixed layer of the second magnetic tunnel junction, causing the magnetization directions of the free layer of the second magnetic tunnel junction and the fixed layer of the second magnetic tunnel junction to be the same, and the magnetoresistance state of the second magnetic tunnel junction to be a low-resistance state, and the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction to be a positive magnetoresistance difference, thereby writing the first write data;

[0029] When the write current is the second write current, then:

[0030] The second write current flows from the free layer of the first magnetic tunnel junction to the fixed layer, so that the magnetization directions of the free layer of the first magnetic tunnel junction and the fixed layer of the first magnetic tunnel junction are the same, and the magnetoresistance state of the first magnetic tunnel junction is a low resistance state; the second write current flows from the fixed layer of the second magnetic tunnel junction to the free layer, so that the magnetization directions of the free layer of the second magnetic tunnel junction and the fixed layer of the second magnetic tunnel junction are opposite, the magnetoresistance state of the second magnetic tunnel junction is a high resistance state, and the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction is a negative magnetoresistance difference, thereby writing the second write data.

[0031] According to an embodiment of the present disclosure, reading data of the MRAM storage cell according to the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction includes:

[0032] determining a voltage difference between a first input terminal and a second input terminal of the data reading circuit according to a magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction;

[0033] Data of the MRAM storage cell is read according to a voltage difference between the first input terminal and the second input terminal of the data reading circuit.

[0034] According to an embodiment of the present disclosure, determining a voltage difference between a first input terminal and a second input terminal of the data reading circuit according to a magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction includes:

[0035] When the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction is a positive magnetoresistance difference, the voltage at the first input terminal of the data reading circuit is less than the voltage at the second input terminal of the data reading circuit;

[0036] When the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction is a negative magnetoresistance difference, the voltage at the first input terminal of the data reading circuit is greater than the voltage at the second input terminal of the data reading circuit;

[0037] The step of reading data of the MRAM storage cell according to a voltage difference between a first input terminal and a second input terminal of the data reading circuit includes:

[0038] When the voltage at the first input terminal of the data reading circuit is less than the voltage at the second input terminal of the data reading circuit, the data read from the MRAM storage cell is the first write data;

[0039] When the voltage at the first input terminal of the data reading circuit is greater than the voltage at the second input terminal of the data reading circuit, the data read from the MRAM storage cell is the second write data.

[0040] In a second aspect, an embodiment of the present disclosure provides a differential MRAM memory cell, the MRAM memory cell comprising: a MOS transistor, three dual magnetic tunnel junctions, a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, a fifth metal layer, a sixth metal layer, and a seventh metal layer; wherein the three dual magnetic tunnel junctions are: a first dual magnetic tunnel junction, a second dual magnetic tunnel junction, and a third dual magnetic tunnel junction; the dual magnetic tunnel junctions include: a first magnetic tunnel junction and a second magnetic tunnel junction; the first magnetic tunnel junction and the second magnetic tunnel junction respectively include a fixed layer, a non-magnetic tunnel layer, and a free layer arranged in sequence;

[0041] The first magnetic tunnel junction of the first double magnetic tunnel junction and the second magnetic tunnel junction of the first double magnetic tunnel junction are mirror-imaged and arranged on both sides of the first metal layer. The free layer of the first magnetic tunnel junction of the first double magnetic tunnel junction and the free layer of the second magnetic tunnel junction of the first double magnetic tunnel junction are respectively in electrical contact with the first metal layer. The fixed layer of the first magnetic tunnel junction of the first double magnetic tunnel junction is in electrical contact with the second metal layer, and the fixed layer of the second magnetic tunnel junction of the first double magnetic tunnel junction is in electrical contact with the third metal layer.

[0042] The first magnetic tunnel junction of the second double magnetic tunnel junction and the second magnetic tunnel junction of the second double magnetic tunnel junction are mirror-imaged and arranged on both sides of the fourth metal layer. The free layer of the first magnetic tunnel junction of the second double magnetic tunnel junction and the free layer of the second magnetic tunnel junction of the second double magnetic tunnel junction are respectively in electrical contact with the fourth metal layer. The fixed layer of the first magnetic tunnel junction of the second double magnetic tunnel junction is in electrical contact with the third metal layer, and the fixed layer of the second magnetic tunnel junction of the second double magnetic tunnel junction is in electrical contact with the fifth metal layer.

[0043] The first magnetic tunnel junction of the third double magnetic tunnel junction and the second magnetic tunnel junction of the third double magnetic tunnel junction are mirror-imaged and arranged on both sides of the sixth metal layer. The free layer of the first magnetic tunnel junction of the third double magnetic tunnel junction and the free layer of the second magnetic tunnel junction of the third double magnetic tunnel junction are respectively in electrical contact with the sixth metal layer. The pinned layer of the first magnetic tunnel junction of the third double magnetic tunnel junction is in electrical contact with the fifth metal layer, and the pinned layer of the second magnetic tunnel junction of the third double magnetic tunnel junction is in electrical contact with the seventh metal layer.

[0044] The gate of the MOS transistor is connected to the word line, the source of the MOS transistor is connected to the source line, and the drain of the MOS transistor is connected to the seventh metal layer;

[0045] When the MRAM storage cell is in a write state, the second metal layer, the word line, and the source line are respectively connected to a data write circuit, and a write current is formed between the second metal layer and the drain of the MOS transistor according to write data, penetrating the first double magnetic tunnel junction, the second double magnetic tunnel junction, and the third double magnetic tunnel junction, so that the data write circuit writes the write data into the MRAM storage cell through the write current, wherein the direction of the write current corresponds to the write data;

[0046] When the MRAM memory cell is in a read state, the first metal layer, the fourth metal layer, and the sixth metal layer are respectively connected to a first input terminal of a data read circuit, and the second metal layer, the third metal layer, the fifth metal layer, and the seventh metal layer are respectively connected to a second input terminal of the data read circuit, so that the data read circuit reads data of the MRAM memory cell based on a magnetoresistance difference between a first magnetic tunnel junction and a second magnetic tunnel junction of each double magnetic tunnel junction, and the data of the MRAM memory cell is output through an output terminal of the data read circuit. The magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction includes a positive magnetoresistance difference and a negative magnetoresistance difference, wherein the positive magnetoresistance difference is formed because the magnetoresistance of the first magnetic tunnel junction is greater than that of the second magnetic tunnel junction, and the negative magnetoresistance difference is formed because the magnetoresistance of the first magnetic tunnel junction is less than that of the second magnetic tunnel junction.

[0047] According to an embodiment of the present disclosure, the data reading circuit includes: a first data reading circuit, a second data reading circuit, a third data reading circuit, and a logic integration circuit, wherein output terminals of the first data reading circuit, the second data reading circuit, and the third data reading circuit are respectively connected to the logic integration circuit;

[0048] The first metal layer, the fourth metal layer, and the sixth metal layer are respectively connected to a first input terminal of a data reading circuit, and the second metal layer, the third metal layer, the fifth metal layer, and the seventh metal layer are respectively connected to a second input terminal of the data reading circuit, comprising:

[0049] The first metal layer is connected to the first input terminal of the first data reading circuit, the fourth metal layer is connected to the first input terminal of the second data reading circuit, the sixth metal layer is connected to the first input terminal of the third data reading circuit, and the second metal layer, the third metal layer, the fifth metal layer and the seventh metal layer are all connected to the second input terminals of the first data reading circuit, the second data reading circuit and the third data reading circuit.

[0050] According to an embodiment of the present disclosure, the data reading circuit reads data of the MRAM storage cell according to the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction of each double magnetic tunnel junction, including:

[0051] The first data reading circuit determines first read data according to a magnetoresistance difference between a first magnetic tunnel junction and a second magnetic tunnel junction of the first double magnetic tunnel junction, which is recorded as D1;

[0052] The second data reading circuit determines second read data according to a magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction of the second double magnetic tunnel junction, which is recorded as D2;

[0053] The third data reading circuit determines third read data according to the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction of the third double magnetic tunnel junction, which is recorded as D3;

[0054] The logic integration circuit determines the data of the MRAM storage cell according to the first read data, the second read data, and the third read data, and the data of the MRAM storage cell is output through the output terminal of the logic integration circuit;

[0055] The data D of the MRAM storage unit is expressed as follows:

[0056] D=(D1∧D2)∨(D2∧D3)∨(D1∧D3).

[0057] In a third aspect, an embodiment of the present disclosure provides a differential MRAM memory cell array, comprising: N MRAM memory cells according to any one of the first aspect or the second aspect arranged in an array, and N MOS transistors corresponding one-to-one to the N MRAM memory cells, where N is an integer greater than 1;

[0058] The second metal layer of each MRAM storage cell is connected to the source of the MOS tube corresponding to the MRAM storage cell, and the drains of the N MOS tubes are connected to the first source line;

[0059] The sources of the MOS transistors of each MRAM storage cell are connected to each other and then to the second source line; the gates of the MOS transistors corresponding to the MRAM storage cells are connected to the gates of the MOS transistors of the MRAM storage cells and then to the word lines corresponding to the MRAM storage cells;

[0060] The first metal layer of each MRAM storage cell is connected to the first input terminal of the data reading circuit;

[0061] The first source line and the second source line are respectively connected to the second input terminal of the data reading circuit;

[0062] An output terminal of the data reading circuit is connected to a bit line.

[0063] In a fourth aspect, an embodiment of the present disclosure provides a differential MRAM memory, comprising: an MRAM memory cell array cluster, a data writing circuit, and a data reading circuit; the MRAM memory cell array cluster comprises one or more MRAM memory cell arrays according to the third aspect;

[0064] The input end of the data writing circuit is connected to the external IO port for receiving write data;

[0065] The output end of the data writing circuit is connected to the word line of the MRAM memory cell corresponding to the MRAM memory cell array, and the first source line and the second source line of the MRAM memory cell array, for outputting the written data;

[0066] The data write circuit is configured to generate a write current between a second metal layer of an MRAM memory cell in the MRAM memory cell array and a drain of a MOS transistor of the MRAM memory cell in the MRAM memory cell array according to the write data, so as to penetrate a double magnetic tunnel junction of the MRAM memory cell in the MRAM memory cell array, and write the write data into the MRAM memory cell in the MRAM memory cell array through the write current, wherein a direction of the write current corresponds to the write data;

[0067] The data reading circuit is configured to read data of the MRAM memory cell in the MRAM memory cell array based on a magnetoresistance difference between a first magnetic tunnel junction and a second magnetic tunnel junction of the MRAM memory cell, and the data of the MRAM memory cell is output through an output end of the data reading circuit; wherein the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction includes a positive magnetoresistance difference and a negative magnetoresistance difference, the positive magnetoresistance difference being formed because the magnetoresistance of the first magnetic tunnel junction is greater than the magnetoresistance of the second magnetic tunnel junction, and the negative magnetoresistance difference being formed because the magnetoresistance of the first magnetic tunnel junction is less than the magnetoresistance of the second magnetic tunnel junction.

[0068] According to an embodiment of the present disclosure, the direction of the write current includes a first direction and a second direction;

[0069] When the direction of the write current is the first direction, the write current is the first write current;

[0070] When the direction of the write current is the second direction, the write current is the second write current;

[0071] The direction of the write current corresponds to the write data, including:

[0072] The first write current corresponds to the first write data; the second write current corresponds to the second write data;

[0073] The first written data is 0, and the second written data is 1; or the first written data is 1, and the second written data is 0.

[0074] According to an embodiment of the present disclosure, forming a write current penetrating a dual magnetic tunnel junction of the MRAM memory cell in the MRAM memory cell array between a second metal layer of the MRAM memory cell in the MRAM memory cell array and a drain of a MOS transistor of the MRAM memory cell in the MRAM memory cell array according to the write data includes:

[0075] When the write data is first write data, a first write current is formed between the second metal layer and the drain of the MOS transistor and penetrates the dual magnetic tunnel junction;

[0076] When the write data is second write data, a second write current penetrating the dual magnetic tunnel junction is formed between the second metal layer and the drain of the MOS transistor.

[0077] According to an embodiment of the present disclosure, forming a first write current between the second metal layer and the drain of the MOS transistor and penetrating the dual magnetic tunnel junction includes:

[0078] When a high level is input to the word line to turn on the MOS transistor, and at the same time a first voltage is applied to the second metal layer and a second voltage is applied to the source line, and the first voltage is greater than the second voltage, a first write current is generated that flows from the second metal layer to the drain of the MOS transistor and penetrates the dual magnetic tunnel junction, and the first write current flows out from the source of the MOS transistor;

[0079] The forming of a second write current penetrating the dual magnetic tunnel junction between the second metal layer and the drain of the MOS transistor includes:

[0080] When a high level is input to the word line to turn on the MOS transistor, and a first voltage is applied to the source line and a second voltage is applied to the second metal layer, and the first voltage is greater than the second voltage, a second write current is generated that flows from the drain of the MOS transistor to the second metal layer and penetrates the dual magnetic tunnel junction, and the second write current flows out from the second metal layer;

[0081] Wherein, turning on the MOS transistor includes: when the MOS transistor is an NMOS transistor, applying a forward bias voltage between the gate and source of the MOS transistor; when the MOS transistor is a PMOS transistor, applying a negative bias voltage between the gate and source of the MOS transistor, so that the MOS transistor is turned on.

[0082] According to an embodiment of the present disclosure, writing the write data into the MRAM storage cell by using the write current includes:

[0083] When the write current is the first write current, then:

[0084] The first write current flows from the fixed layer to the free layer of the first magnetic tunnel junction, so that the magnetization directions of the free layer of the first magnetic tunnel junction and the fixed layer of the first magnetic tunnel junction are opposite, and the magnetoresistance state of the first magnetic tunnel junction is a high-resistance state; the first write current flows from the free layer to the fixed layer of the second magnetic tunnel junction, so that the magnetization directions of the free layer of the second magnetic tunnel junction and the fixed layer of the second magnetic tunnel junction are the same, and the magnetoresistance state of the second magnetic tunnel junction is a low-resistance state, thereby writing the first write data;

[0085] When the write current is the second write current, then:

[0086] The second write current flows from the free layer of the first magnetic tunnel junction to the fixed layer, so that the magnetization directions of the free layer of the first magnetic tunnel junction and the fixed layer of the first magnetic tunnel junction are the same, and the magnetoresistance state of the first magnetic tunnel junction is a low resistance state; the second write current flows from the fixed layer of the second magnetic tunnel junction to the free layer, so that the magnetization directions of the free layer of the second magnetic tunnel junction and the fixed layer of the second magnetic tunnel junction are opposite, and the magnetoresistance state of the second magnetic tunnel junction is a high resistance state, thereby writing the second write data.

[0087] According to an embodiment of the present disclosure, the method of reading data of the MRAM memory cell in the MRAM memory cell array according to the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction includes:

[0088] determining a voltage difference between a first input terminal and a second input terminal of the data reading circuit according to a magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction;

[0089] Data of the MRAM storage cell is read according to a voltage difference between the first input terminal and the second input terminal of the data reading circuit.

[0090] According to an embodiment of the present disclosure, determining a voltage difference between a first input terminal and a second input terminal of the data reading circuit according to a magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction includes:

[0091] When the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction is a positive magnetoresistance difference, the voltage at the first input terminal of the data reading circuit is less than the voltage at the second input terminal of the data reading circuit;

[0092] When the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction is a negative magnetoresistance difference, the voltage at the first input terminal of the data reading circuit is greater than the voltage at the second input terminal of the data reading circuit;

[0093] The step of reading data of the MRAM storage cell according to a voltage difference between a first input terminal and a second input terminal of the data reading circuit includes:

[0094] When the voltage at the first input terminal of the data reading circuit is less than the voltage at the second input terminal of the data reading circuit, the data read from the MRAM storage cell is the first write data;

[0095] When the voltage at the first input terminal of the data reading circuit is greater than the voltage at the second input terminal of the data reading circuit, the data read from the MRAM storage cell is the second write data.

[0096] In a fifth aspect, an embodiment of the present disclosure provides a method for preparing a differential MRAM memory cell, wherein the MRAM memory cell includes: a MOS transistor, a dual magnetic tunnel junction, a first metal layer, a second metal layer, and a third metal layer; wherein the dual magnetic tunnel junction includes: a first magnetic tunnel junction and a second magnetic tunnel junction, and the preparation method includes:

[0097] forming the MOS transistor, wherein the MOS transistor is located at the bottom of the MRAM storage unit;

[0098] forming the third metal layer on the MOS tube;

[0099] forming a fixed layer, a non-magnetic tunneling layer and a free layer of the second magnetic tunnel junction in sequence on the third metal layer;

[0100] forming the first metal layer on the free layer of the second magnetic tunnel junction;

[0101] forming a free layer, a non-magnetic tunneling layer and a fixed layer of the first magnetic tunnel junction in sequence on the first metal layer;

[0102] The second metal layer is formed on the fixed layer of the first magnetic tunnel junction.

[0103] In a sixth aspect, an embodiment of the present disclosure provides a method for preparing a differential MRAM memory cell, wherein the MRAM memory cell includes: a MOS transistor, a first dual magnetic tunnel junction, a second dual magnetic tunnel junction, a third dual magnetic tunnel junction, a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, a fifth metal layer, a sixth metal layer, and a seventh metal layer; wherein the dual magnetic tunnel junction includes: a first magnetic tunnel junction and a second magnetic tunnel junction, and the preparation method includes:

[0104] forming the MOS transistor, wherein the MOS transistor is located at the bottom of the MRAM storage unit;

[0105] forming the seventh metal layer on the MOS transistor;

[0106] forming a fixed layer, a non-magnetic tunneling layer and a free layer of the second magnetic tunnel junction of the third double magnetic tunnel junction in sequence on the seventh metal layer;

[0107] forming the sixth metal layer on the free layer of the second magnetic tunnel junction of the third double magnetic tunnel junction;

[0108] forming a free layer, a non-magnetic tunneling layer and a fixed layer of a first magnetic tunnel junction of the third double magnetic tunnel junction in sequence on the sixth metal layer;

[0109] forming the fifth metal layer on the fixed layer of the first magnetic tunnel junction of the third double magnetic tunnel junction;

[0110] forming a fixed layer, a non-magnetic tunneling layer and a free layer of the second magnetic tunnel junction of the second double magnetic tunnel junction in sequence on the fifth metal layer;

[0111] forming a fourth metal layer on the free layer of the second magnetic tunnel junction of the second double magnetic tunnel junction;

[0112] forming a free layer, a non-magnetic tunneling layer and a fixed layer of the first magnetic tunnel junction of the second double magnetic tunnel junction in sequence on the fourth metal layer;

[0113] forming a third metal layer on the fixed layer of the second magnetic tunnel junction of the second double magnetic tunnel junction;

[0114] forming a fixed layer, a non-magnetic tunneling layer and a free layer of the second magnetic tunnel junction of the first double magnetic tunnel junction in sequence on the third metal layer;

[0115] forming a first metal layer on the free layer of the second magnetic tunnel junction of the first double magnetic tunnel junction;

[0116] forming a free layer, a non-magnetic tunneling layer and a fixed layer of a first magnetic tunnel junction of the first double magnetic tunnel junction in sequence on the first metal layer;

[0117] A second metal layer is formed on the fixed layer of the first magnetic tunnel junction of the first double magnetic tunnel junction.

[0118] In a seventh aspect, an embodiment of the present disclosure provides an MRAM memory cell based on a differential form, and the MRAM memory cell is prepared according to the preparation method described in any one of the fifth and sixth aspects.

[0119] In an eighth aspect, an embodiment of the present disclosure provides a chip comprising the MRAM storage unit according to any one of the first and second aspects.

[0120] In a ninth aspect, an embodiment of the present disclosure provides a chip comprising the MRAM storage unit according to any one of the seventh aspects.

[0121] In a tenth aspect, an embodiment of the present disclosure provides a chip comprising the MRAM memory described in any one of the third aspects.

[0122] According to the technical solution provided by the embodiments of the present disclosure, a dual magnetic tunnel junction (MTJ) comprising a first magnetic tunnel junction (MTJ) and a second magnetic tunnel junction (MTJ) is innovatively introduced into an MRAM memory cell. The first and second MTJs are mirror-imaged on either side of a first metal layer, with their free layers both electrically contacting the first metal layer and their fixed layers electrically contacting the second and third metal layers, respectively. When writing to the MRAM memory cell, data is written by applying write currents in different directions through the dual magnetic tunnel junctions. When reading from the MRAM memory cell, data is read by determining the difference in magnetoresistance between the first and second MTJs. Because the two MTJs are mirrored, this symmetrical design allows them to be relatively independent in physical location while possessing similar electromagnetic properties. When subjected to strong external magnetic field interference, the two MTJs are affected in roughly the same way, thereby reducing storage errors caused by uneven magnetic fields. Furthermore, under common-mode magnetic field interference, the magnetoresistance of the two MTJs changes synchronously with the external magnetic field, but the difference in magnetoresistance is not easily altered. By identifying the difference in magnetoresistance, stored data can be effectively read, ensuring accurate data reading and effectively resisting external magnetic field interference.

[0123] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0124] Other features, objectives and advantages of the present disclosure will become more apparent through the following detailed description of non-limiting embodiments in conjunction with the accompanying drawings. In the accompanying drawings:

[0125] Figure 1 A schematic structural diagram of a differential MRAM storage cell according to an embodiment of the present disclosure is shown;

[0126] Figure 2 A schematic diagram showing a connection between a differential MRAM storage unit and a data writing circuit according to an embodiment of the present disclosure is shown;

[0127] Figure 3 A schematic diagram showing a connection between a differential MRAM storage cell and a data reading circuit according to an embodiment of the present disclosure is shown;

[0128] Figure 4A schematic diagram showing a connection between a differential MRAM storage unit and a data reading circuit in a specific example of the present disclosure is shown;

[0129] Figure 5 A schematic structural diagram of another differential MRAM storage cell according to an embodiment of the present disclosure is shown;

[0130] Figure 6 A schematic diagram showing the connection between another differential-based MRAM storage unit and a data writing circuit according to an embodiment of the present disclosure is shown;

[0131] Figure 7 A schematic diagram illustrating a connection between another differential-based MRAM storage cell and a data reading circuit according to an embodiment of the present disclosure is shown;

[0132] Figure 8 A schematic diagram showing a connection between another differential-based MRAM storage unit and a data reading circuit in a specific example of the present disclosure is shown;

[0133] Figure 9 A schematic structural diagram of a differential-based MRAM memory cell array in a specific example of the present disclosure is shown;

[0134] Figure 10 A schematic structural diagram of a differential MRAM memory according to an embodiment of the present disclosure is shown;

[0135] Figure 11 A flowchart showing a method for preparing a differential-type MRAM memory cell according to an embodiment of the present disclosure is shown;

[0136] Figure 12 A flow chart illustrating another method for preparing a differential-based MRAM memory cell according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0137] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement them. In addition, for the sake of clarity, parts not related to the description of the exemplary embodiments are omitted in the accompanying drawings.

[0138] In the present disclosure, it should be understood that terms such as "include" or "have" are intended to indicate the presence of features, numbers, steps, actions, components, parts, or combinations thereof disclosed in the present specification, and are not intended to exclude the possibility that one or more other features, numbers, steps, actions, components, parts, or combinations thereof exist or are added.

[0139] It should also be noted that, in the absence of conflict, the embodiments and features of the embodiments of the present disclosure may be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0140] As mentioned above, when the MRAM memory in the prior art is based on traditional MTJ for storage, the magnetization state inside the MTJ is easily disturbed by the strong external magnetic field, which affects the "free" ferromagnetic layer and causes its magnetization direction to change, thereby affecting the read and write accuracy and data reliability of the MRAM.

[0141] To overcome this problem, researchers are constantly exploring ways to improve MRAM's ability to resist interference from external magnetic fields. Currently, there are several approaches:

[0142] 1. By integrating a magnetic shielding layer around or inside the MRAM chip, the impact of the external magnetic field on the MTJ storage unit is reduced. These shielding layers are usually made of high-permeability materials, such as Permalloy. Although they can guide or disperse the external magnetic field, thereby protecting the magnetization state of the MTJ from interference, the high cost of these materials increases the production cost of MRAM. At the same time, the design of the magnetic shielding layer requires precise calculations to ensure that it can effectively guide or disperse the external magnetic field, which increases the complexity of the design. In addition, the introduction of the magnetic shielding layer will increase the size of the MRAM chip, affecting its use in highly integrated applications.

[0143] 2. Magnetic noise suppression technology is used to suppress magnetic noise, including using more accurate reading circuits, optimizing reading algorithms, and introducing error detection and correction mechanisms. Although this can improve the reading stability and accuracy of MRAM to a certain extent, optimizing reading algorithms and introducing error detection and correction mechanisms may increase the computational complexity and power consumption of the system.

[0144] 3. By introducing a multi-layer magnetic material structure into the MTJ, a more complex magnetization state is formed to improve the stability of the MTJ to the external magnetic field. The multi-layer structure can increase the magnetic anisotropy of the MTJ, making its magnetization state more difficult to be flipped by the external magnetic field. However, the design of the multi-layer magnetic material structure requires precise control of the thickness, composition and magnetic properties of each layer. In addition, the multi-layer structure may introduce additional magnetic effects and interactions, which require careful optimization to ensure that the overall performance of the MTJ is not affected, increasing the complexity and difficulty of the design.

[0145] It can be seen that the above-mentioned methods for improving the anti-interference capability of MRAM to external magnetic fields often increase implementation cost and complexity, which limits the widespread application of MRAM.

[0146] How can MRAM be made to effectively resist external magnetic field interference while also being simple to implement, thereby enabling its widespread application? After repeated demonstrations and careful consideration, the inventors of this disclosure have proposed a differential MRAM memory cell. Specifically, traditional MRAM memory cells typically employ a single magnetic tunnel junction (MTJ) structure, while this disclosure innovatively introduces a dual magnetic tunnel junction, comprising a first magnetic tunnel junction and a second magnetic tunnel junction, into the MRAM memory cell. The first and second magnetic tunnel junctions are mirrored on either side of a first metal layer, with their free layers both electrically contacting the first metal layer, and their fixed layers electrically contacting the second and third metal layers, respectively. When writing to the MRAM memory cell, data is written by applying write currents in different directions through the dual magnetic tunnel junctions. When reading from the MRAM memory cell, data is read by determining the difference in magnetoresistance between the first and second magnetic tunnel junctions.

[0147] First, because the two MTJs are mirror images, this symmetrical design makes the two MTJs relatively independent in physical position, but at the same time have similar electromagnetic properties. When there is strong external magnetic field interference, the two MTJs are affected in roughly the same way, thereby reducing storage errors caused by uneven magnetic fields. At the same time, under common-mode magnetic field interference conditions, the magnetic resistance of the two MTJs changes synchronously with the external magnetic field interference, but the magnetic resistance difference is not easy to change. By identifying the magnetic resistance difference, the stored data can be effectively read, thus ensuring the correct reading of the data.

[0148] Secondly, through this mirror layout and contact method, the current path is optimized, ensuring that the current can maintain similar path length and resistance characteristics when flowing through the two MTJs, thereby reducing uneven current distribution and energy loss. At the same time, the mirror layout also helps to ensure the thermal and electrical symmetry of the two tunnel junctions, further improving the stability and reliability of the storage unit. In addition, compared with the method of setting two MTJs in parallel, this mirror layout and contact method, on the one hand, makes the two MTJs relatively independent in physical position, reducing the direct electromagnetic coupling and thermal coupling between them, thereby reducing mutual interference; on the other hand, it helps to achieve higher integration and storage density. By optimizing the unit structure and layout, more storage units can be integrated in the same area, thereby increasing the overall storage capacity.

[0149] Figure 1 FIG. 1 shows a structural diagram of a differential MRAM storage unit according to an embodiment of the present disclosure. Figure 1As shown, the MRAM storage cell 100 includes: a MOS transistor 130, a dual magnetic tunnel junction, a first metal layer, a second metal layer, and a third metal layer; wherein the dual magnetic tunnel junction includes: a first magnetic tunnel junction 110 and a second magnetic tunnel junction 120; the first magnetic tunnel junction 110 and the second magnetic tunnel junction 120 respectively include a fixed layer, a non-magnetic tunnel layer, and a free layer arranged in sequence; the first magnetic tunnel junction 110 and the second magnetic tunnel junction 120 are mirror-imaged on both sides of the first metal layer, and the free layer of the first magnetic tunnel junction 110 and the free layer of the second magnetic tunnel junction 120 are respectively electrically in contact with the first metal layer; the fixed layer of the first magnetic tunnel junction 110 is electrically in contact with the second metal layer, and the fixed layer of the second magnetic tunnel junction 120 is electrically in contact with the third metal layer; the gate of the MOS transistor 130 is connected to a word line, the source of the MOS transistor 130 is connected to a source line, and the drain of the MOS transistor 130 is connected to the third metal layer.

[0150] The "fixed layer" in the magnetic tunnel junction involved in the embodiments of the present disclosure (for example, the first magnetic tunnel junction 110 and the second magnetic tunnel junction 120) is also called the "pinned ferromagnetic layer" or "reference layer". The magnetization direction of this layer is fixed and will not easily change with the external magnetic field or current; the "free layer" in the magnetic tunnel junction is also called the "free ferromagnetic layer". The magnetization direction of this layer can be changed according to the external magnetic field or current, so that it is parallel or anti-parallel to the magnetization direction of the fixed layer, which will put the magnetic tunnel junction in a low-resistance state or a high-resistance state. The two resistance states can represent binary data "0" and "1" respectively; the "non-magnetic tunneling layer" in the magnetic tunnel junction is also called the "tunnel layer", "non-magnetic isolation layer" or "insulating barrier layer". This layer is usually made of insulating materials such as MgO and is only a few atomic layers thick, allowing electrons to tunnel from one ferromagnetic layer to another through the quantum tunneling effect.

[0151] In addition, the MRAM memory cell of the embodiment of the present disclosure is an improvement on the existing STT-MRAM memory cell. Among them, STT-MRAM is a new type of MRAM that uses spin current to realize information writing. For the existing STT-MRAM memory cell, the writing principle is as follows:

[0152] A forward bitline current writes the data "1." When a high-density bitline current (containing an equal number of electrons with opposite spins) flows from the free layer to the pinned layer, the electrons exchange couple with the magnetic moment in the pinned layer, allowing electrons with spins parallel to the pinned layer's magnetic moment to pass through while electrons with spins antiparallel to the pinned layer's magnetic moment are reflected. The pinned layer acts as a "filter," halving the number of electrons and generating a spin current. Due to the thick and strongly magnetic nature of the pinned layer, the spin moment of the reflected electrons is insufficient to reverse the magnetic moment in the pinned layer. Spinning electrons passing through the pinned layer cross an extremely thin nonmagnetic isolation layer and reach the free layer. There, they exchange couple with the magnetic moment of the free layer, causing the magnetic moment of the free layer to rotate in the direction opposite to that of the pinned layer. Ultimately, the magnetic moments of the two ferromagnetic layers become antiparallel, the MTJ's resistance is high, and the STT-MRAM completes writing the data "1."

[0153] Reversing the bit line current writes the information "0." If the current in the bit line is reversed, when electrons with opposite spins flow through the free layer, the direction of the free layer's magnetic moment remains unchanged, and the current magnitude remains unchanged. When they pass through an extremely thin non-magnetic isolation layer and reach the pinned layer, they retain their original spin state. At this point, if the electron's spin direction aligns with the direction of the pinned layer's magnetic moment, it passes through the MTJ; if its spin direction is opposite to the direction of the pinned layer's magnetic moment, it is reflected. When the reflected spin electrons pass through the non-magnetic isolation layer again and reach the free layer, they transfer their spin moment to the magnetic moment of the free layer, increasing its precession angle until it reverses. At this point, the magnetic moments in the free and pinned layers are aligned parallel, the resistance of the MTJ is low, and the information "0" is written.

[0154] STT-MRAM polarizes the current through the fixed layer to form a spin current. The spin electrons in the spin current transfer the spin torque to the magnetic moment of the free layer, causing it to rotate according to the direction of the spin current, thereby writing information "0" or "1".

[0155] Based on the writing principle of the STT-MRAM storage cell described above, it can be seen that when the STT-MRAM storage cell is written, the direction of the write current (from the fixed layer to the free layer, or from the free layer to the fixed layer) is different, and the magnetic resistance of the MTJ is also different, that is, the magnetic resistance of the MTJ is correlated with the direction of the write current. The inventors of the present disclosure took advantage of this correlation and combined two MTJs and set them in a mirror image. In this way, when there is a write current running through the MTJ combination, regardless of the direction of the write current, the direction of the write current flowing through the two MTJs is bound to be different, resulting in the magnetic resistance of the two MTJs being bound to be different. When the write direction is changed, the magnetic resistance of the two MTJs will also change accordingly. Therefore, data is written based on the corresponding relationship between the direction of the write current and the difference in magnetic resistance of the two MTJs.

[0156] Figure 2FIG. 1 shows a schematic diagram of a connection between a differential MRAM storage unit and a data writing circuit according to an embodiment of the present disclosure. Figure 2 As shown, when the MRAM storage cell 100 is in a write state, the second metal layer, the word line, and the source line are respectively connected to a data write circuit, and a write current penetrating the dual magnetic tunnel junction is formed between the second metal layer and the drain of the MOS transistor 130 according to write data through the data write circuit, so that the data write circuit writes the write data into the MRAM storage cell 100 through the write current, wherein the direction of the write current corresponds to the write data.

[0157] According to an embodiment of the present disclosure, the direction of the write current includes a first direction and a second direction.

[0158] When the direction of the write current is the first direction, the write current is a first write current; when the direction of the write current is the second direction, the write current is a second write current.

[0159] According to an embodiment of the present disclosure, the direction of the write current corresponds to the write data, including:

[0160] The first write current corresponds to first write data; the second write current corresponds to second write data; wherein the first write data is 0 and the second write data is 1; or, the first write data is 1 and the second write data is 0.

[0161] According to an embodiment of the present disclosure, forming a write current penetrating the dual magnetic tunnel junction between the second metal layer and the drain of the MOS transistor according to write data includes:

[0162] When the write data is first write data, a first write current is formed between the second metal layer and the drain of the MOS transistor and penetrates the dual magnetic tunnel junction;

[0163] When the write data is second write data, a second write current penetrating the dual magnetic tunnel junction is formed between the second metal layer and the drain of the MOS transistor.

[0164] For example, the direction of the write current flowing from the second metal layer to the drain of the MOS transistor can be preset as a first direction, and the direction of the write current flowing from the drain of the MOS transistor to the second metal layer can be preset as a second direction. When writing to the MRAM memory cell, a first write current corresponding to the first direction corresponds to writing data "1", and a second write current corresponding to the second direction corresponds to writing data "0". In actual applications, the corresponding relationship can be set as needed.

[0165] When a write operation is performed on the MRAM memory cell according to the preset correspondence between the write current and the write data, the data is written by controlling the direction of the write current flowing through the dual magnetic tunnel junction through a data write circuit connected to the MRAM memory cell.

[0166] In the present disclosure, in a differential MRAM memory cell, when performing a write operation on the MRAM memory cell, the role of a MOS transistor (metal oxide semiconductor field effect transistor) can be defined as follows: on the one hand, it acts as a switch during the write operation, controlling the on / off of the write current. When the voltage on the word line turns on the MOS transistor, the data write circuit can provide a write current to the dual magnetic tunnel junction through the MOS transistor, thereby changing the magnetization state of the free layer according to the direction of the current, thereby achieving data writing; on the other hand, it controls the flow direction of the write current, specifically allowing or preventing the passage of current in a specific direction by using its conduction state, so that different data can be written corresponding to write currents in different directions.

[0167] The MOS transistor may be a PMOS (P-type MOS transistor) or an NMOS (N-type MOS transistor). The following specifically describes the implementation process of performing a write operation on the MRAM storage cell of the embodiment of the present disclosure when the MOS transistors are PMOS transistors and NMOS transistors.

[0168] When the MOS transistor in the MRAM storage unit is an NMOS transistor:

[0169] When a first write current is formed between the second metal layer and the drain of the MOS transistor and passes through the dual magnetic tunnel junction, a high level is input to the word line, and a forward bias voltage is applied between the gate and source of the MOS transistor (this means that the write line voltage needs to be higher than the source line voltage by a certain value, the specific value depends on the threshold voltage of the MOS transistor), so that the MOS transistor is turned on. At the same time, a first voltage is applied to the second metal layer, a second voltage is applied to the source line, and the first voltage is greater than the second voltage, thereby forming a first write current that flows from the second metal layer to the drain of the MOS transistor and passes through the dual magnetic tunnel junction, and the first write current flows out from the source of the MOS transistor.

[0170] When a second write current is formed between the second metal layer and the drain of the MOS transistor and penetrates the dual magnetic tunnel junction, a high level is input to the word line, and a forward bias voltage is applied between the gate and source of the MOS transistor (this means that the write line voltage needs to be higher than the source line voltage by a certain value, the specific value of which depends on the threshold voltage of the MOS transistor), so that the MOS transistor is turned on. At the same time, a first voltage is applied to the source line (the first voltage should be lower than the word line voltage), a second voltage is applied to the second metal layer, and the first voltage is higher than the second voltage, thereby forming a second write current that flows from the drain of the MOS transistor to the second metal layer and penetrates the dual magnetic tunnel junction, and the second write current flows out from the second metal layer.

[0171] When the MOS transistor in the MRAM storage unit is a PMOS transistor:

[0172] When a first write current is formed between the second metal layer and the drain of the MOS transistor and penetrates the dual magnetic tunnel junction, a high level is input to the word line, and a negative bias voltage is applied between the gate and source of the MOS transistor (this means that the write line voltage needs to be lower than the source line voltage by a certain value, the specific value depends on the threshold voltage of the MOS transistor), so that the MOS transistor is turned on. At the same time, a first voltage is applied to the second metal layer, a second voltage is applied to the source line, and the first voltage is greater than the second voltage, thereby forming a first write current that flows from the second metal layer to the drain of the MOS transistor and penetrates the dual magnetic tunnel junction, and the first write current flows out from the source of the MOS transistor.

[0173] When a second write current is formed between the second metal layer and the drain of the MOS transistor and penetrates the dual magnetic tunnel junction, a high level is input to the word line, and a negative bias voltage is applied between the gate and source of the MOS transistor (this means that the write line voltage needs to be lower than the source line voltage by a certain value, the specific value depends on the threshold voltage of the MOS transistor), so that the MOS transistor is turned on. At the same time, a first voltage is applied to the source line and a second voltage is applied to the second metal layer, and the first voltage is greater than the second voltage. A second write current is formed, flowing from the drain of the MOS transistor to the second metal layer and penetrating the dual magnetic tunnel junction, and the second write current flows out from the second metal layer.

[0174] When a write current is generated and passes through the double magnetic tunnel junction, a magnetic field is generated, which is sufficient to change the magnetization direction of the free layer in the magnetic tunnel junction.

[0175] According to an embodiment of the present disclosure, writing the write data into the MRAM storage cell by using the write current includes:

[0176] When the write current is the first write current, then:

[0177] The first write current flows from the fixed layer to the free layer of the first magnetic tunnel junction, causing the magnetization directions of the free layer of the first magnetic tunnel junction and the fixed layer of the first magnetic tunnel junction to be opposite, resulting in a high-resistance magnetoresistance state of the first magnetic tunnel junction. The first write current flows from the free layer to the fixed layer of the second magnetic tunnel junction, causing the magnetization directions of the free layer of the second magnetic tunnel junction and the fixed layer of the second magnetic tunnel junction to be the same, resulting in a low-resistance magnetoresistance state of the second magnetic tunnel junction, and a positive magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction, thereby writing the first write data. In one specific embodiment, the first write data is 1.

[0178] When the write current is the second write current, then:

[0179] The second write current flows from the free layer of the first magnetic tunnel junction to the pinned layer, causing the magnetization directions of the free layer of the first magnetic tunnel junction and the pinned layer of the first magnetic tunnel junction to be the same, resulting in a low-resistance magnetoresistance state of the first magnetic tunnel junction. The second write current flows from the pinned layer of the second magnetic tunnel junction to the free layer, causing the magnetization directions of the free layer of the second magnetic tunnel junction and the pinned layer of the second magnetic tunnel junction to be opposite, resulting in a high-resistance magnetoresistance state of the second magnetic tunnel junction, and a negative magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction, thereby writing the second write data. In one specific embodiment, the second write data is 0.

[0180] Once the magnetization directions of the free layers corresponding to the first and second magnetic tunnel junctions in the dual magnetic tunnel junctions are correctly set and the write current is turned off, the data of the MRAM storage cell is stably stored until the next write operation.

[0181] Figure 3 FIG. 1 shows a schematic diagram of a connection between a differential MRAM storage unit and a data reading circuit according to an embodiment of the present disclosure. Figure 3 As shown, when the MRAM memory cell 100 is in a read state, the first metal layer is connected to the first input terminal of a data read circuit, and the second metal layer and the third metal layer are respectively connected to the second input terminal of the data read circuit. This connection method allows the data read circuit to simultaneously access the resistance characteristics of two magnetic tunnel junctions (the first magnetic tunnel junction 110 and the second magnetic tunnel junction 120), so that the data read circuit reads the data of the MRAM memory cell 100 based on the difference in magnetoresistance between the first magnetic tunnel junction 110 and the second magnetic tunnel junction 120. The data of the MRAM memory cell 100 is output through the output terminal of the data read circuit.

[0182] When performing a read operation on the MRAM storage cell, the data read circuit must first be activated to prepare it to receive and process signals from the MRAM storage cell. Depending on the specific design of the MRAM, a small read current may be required to stabilize the state of the magnetic tunnel junction or increase signal strength. The data read circuit then measures the difference in magnetoresistance between the two magnetic tunnel junctions by comparing the current or voltage flowing through them. Because the magnetization direction of the free layer determines the resistance of the magnetic tunnel junction, the difference in magnetoresistance can reflect the stored data.

[0183] The magnetic resistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction includes a positive magnetic resistance difference and a negative magnetic resistance difference. The positive magnetic resistance difference is formed because the magnetic resistance of the first magnetic tunnel junction is greater than the magnetic resistance of the second magnetic tunnel junction, and the negative magnetic resistance difference is formed because the magnetic resistance of the first magnetic tunnel junction is less than the magnetic resistance of the second magnetic tunnel junction.

[0184] In this disclosure, in a differential MRAM memory cell, when a read operation is performed on the MRAM memory cell, the MOS transistor performs isolation and protection functions, remaining disconnected during the read operation. This isolates the data writing circuit from the data reading circuit, preventing unnecessary interference. This isolation mechanism helps ensure the accuracy and stability of the read data.

[0185] Figure 4 FIG. 1 shows a schematic diagram of a connection between a differential MRAM storage unit and a data reading circuit in a specific example of the present disclosure. Figure 4 As shown, in the specific example, the data reading circuit is implemented by a differential comparator, and the data of the MRAM storage cell 100 is read by comparing the voltages of the negative and positive electrodes of the differential comparator. The second metal layer and the third metal layer are respectively connected to the positive electrode of the differential comparator via a resistor R with the same resistance value.

[0186] According to an embodiment of the present disclosure, reading data of the MRAM storage cell according to the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction includes:

[0187] A voltage difference between a first input terminal and a second input terminal of the data reading circuit is determined according to a magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction.

[0188] Specifically, when the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction is a positive magnetoresistance difference, the voltage at the first input terminal of the data reading circuit is less than the voltage at the second input terminal of the data reading circuit. When the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction is a negative magnetoresistance difference, the voltage at the first input terminal of the data reading circuit is greater than the voltage at the second input terminal of the data reading circuit.

[0189] Data of the MRAM storage cell is read according to a voltage difference between the first input terminal and the second input terminal of the data reading circuit.

[0190] Specifically, when the voltage at the first input terminal of the data reading circuit is less than the voltage at the second input terminal of the data reading circuit, the data read from the MRAM storage cell is the first write data. When the voltage at the first input terminal of the data reading circuit is greater than the voltage at the second input terminal of the data reading circuit, the data read from the MRAM storage cell is the second write data.

[0191] exist Figure 4 In the differential comparator, the negative voltage It can be expressed as follows:

[0192]

[0193] Positive voltage of the differential comparator It can be expressed as follows:

[0194]

[0195] in, is the voltage of the first magnetic tunnel junction when reading the MRAM storage cell, is the voltage of the second magnetic tunnel junction when reading the MRAM storage cell, is the magnetoresistance of the first magnetic tunnel junction when reading the MRAM memory cell, is the resistance of the first magnetic tunnel junction when reading the MRAM storage cell, and R is Figure 4 The resistance of the resistor R.

[0196] According to the above two formulas, when R1 is larger than R2, that is, when the difference in magnetic resistance between the first magnetic tunnel junction and the second magnetic tunnel junction is a positive difference in magnetic resistance, the negative voltage of the differential comparator is Less than the positive voltage of the differential comparator , the differential comparator outputs a high level, and the read data is 1, that is, the first written data is 1. If R1 is smaller than R2, that is, when the magnetic resistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction is a negative magnetic resistance difference, the negative voltage of the differential comparator is Greater than the positive voltage of the differential comparator , the differential comparator outputs a low level, and the read data is 0, that is, the second written data is 0.

[0197] Figure 5 A schematic structural diagram of another differential-based MRAM storage cell according to an embodiment of the present disclosure is shown. The MRAM storage cell 500 includes: a MOS transistor, three dual magnetic tunnel junctions, a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, a fifth metal layer, a sixth metal layer, and a seventh metal layer; wherein the three dual magnetic tunnel junctions are: a first dual magnetic tunnel junction 510, a second dual magnetic tunnel junction 520, and a third dual magnetic tunnel junction 530; the dual magnetic tunnel junctions include: a first magnetic tunnel junction 110 and a second magnetic tunnel junction 120; the first magnetic tunnel junction 110 and the second magnetic tunnel junction 120 respectively include a fixed layer, a non-magnetic tunnel layer, and a free layer arranged in sequence.

[0198] The first magnetic tunnel junction 110 of the first double magnetic tunnel junction 510 and the second magnetic tunnel junction 120 of the first double magnetic tunnel junction 510 are mirror-imaged on both sides of the first metal layer, and the free layer of the first magnetic tunnel junction 110 of the first double magnetic tunnel junction 510 and the free layer of the second magnetic tunnel junction 120 of the first double magnetic tunnel junction 510 are respectively electrically in contact with the first metal layer; the fixed layer of the first magnetic tunnel junction 110 of the first double magnetic tunnel junction 510 is electrically in contact with the second metal layer, and the fixed layer of the second magnetic tunnel junction 120 of the first double magnetic tunnel junction 510 is electrically in contact with the third metal layer.

[0199] The first magnetic tunnel junction 110 of the second double magnetic tunnel junction 520 and the second magnetic tunnel junction 120 of the second double magnetic tunnel junction 520 are mirror-imaged on both sides of the fourth metal layer, and the free layer of the first magnetic tunnel junction 110 of the second double magnetic tunnel junction 520 and the free layer of the second magnetic tunnel junction 120 of the second double magnetic tunnel junction 520 are respectively electrically in contact with the fourth metal layer; the fixed layer of the first magnetic tunnel junction 110 of the second double magnetic tunnel junction 520 is electrically in contact with the third metal layer, and the fixed layer of the second magnetic tunnel junction 120 of the second double magnetic tunnel junction 520 is electrically in contact with the fifth metal layer.

[0200] The first magnetic tunnel junction 110 of the third double magnetic tunnel junction 530 and the second magnetic tunnel junction 120 of the third double magnetic tunnel junction 530 are mirror-imaged on both sides of the sixth metal layer, and the free layer of the first magnetic tunnel junction 110 of the third double magnetic tunnel junction 530 and the free layer of the second magnetic tunnel junction 120 of the third double magnetic tunnel junction 530 are respectively electrically in contact with the sixth metal layer; the fixed layer of the first magnetic tunnel junction 110 of the third double magnetic tunnel junction 530 is electrically in contact with the fifth metal layer, and the fixed layer of the second magnetic tunnel junction 120 of the third double magnetic tunnel junction 530 is electrically in contact with the seventh metal layer.

[0201] The gate of the MOS transistor 130 is connected to the word line, the source of the MOS transistor 130 is connected to the source line, and the drain of the MOS transistor 130 is connected to the seventh metal layer.

[0202] Figure 6 FIG. 1 shows another schematic diagram of a connection between a differential MRAM storage unit and a data writing circuit according to an embodiment of the present disclosure. Figure 6 As shown, when the MRAM storage cell 500 is in a write state, the second metal layer, the word line, and the source line are respectively connected to a data write circuit. The data write circuit forms a write current that penetrates the first double magnetic tunnel junction 510, the second double magnetic tunnel junction 520, and the third double magnetic tunnel junction 530 between the second metal layer and the drain of the MOS transistor 130 according to write data, so that the data write circuit writes the write data into the MRAM storage cell 500 through the write current, wherein the direction of the write current corresponds to the write data.

[0203] In specific Figure 6 When performing a write operation on the MRAM storage cell 500 shown in FIG. Figure 1 The writing process of the MRAM storage unit shown in FIG. Figure 6 In the MRAM storage cell 500 shown, one write process can sequentially write data into the first double magnetic tunnel junction 510 , the second double magnetic tunnel junction 520 , and the third double magnetic tunnel junction 530 .

[0204] Figure 7 FIG. 2 shows another schematic diagram of a connection between a differential MRAM storage unit and a data reading circuit according to an embodiment of the present disclosure. Figure 7As shown, when the MRAM memory cell 500 is in a read state, the first metal layer, the fourth metal layer, and the sixth metal layer are respectively connected to a first input terminal of a data read circuit, and the second metal layer, the third metal layer, the fifth metal layer, and the seventh metal layer are respectively connected to a second input terminal of the data read circuit, so that the data read circuit reads data of the MRAM memory cell 500 according to the magnetoresistance difference between the first magnetic tunnel junction 110 and the second magnetic tunnel junction 120 of each double magnetic tunnel junction, and the data of the MRAM memory cell 500 is output through an output terminal of the data read circuit; wherein the magnetoresistance difference between the first magnetic tunnel junction 110 and the second magnetic tunnel junction 120 includes a positive magnetoresistance difference and a negative magnetoresistance difference, the positive magnetoresistance difference being formed because the magnetoresistance of the first magnetic tunnel junction 110 is greater than that of the second magnetic tunnel junction 120, and the negative magnetoresistance difference being formed because the magnetoresistance of the first magnetic tunnel junction 110 is less than that of the second magnetic tunnel junction 120.

[0205] Figure 8 FIG. 1 shows another schematic diagram of a connection between a differential-based MRAM storage unit and a data reading circuit in a specific example of the present disclosure. Figure 8 As shown, in the specific example, the data reading circuit includes: a first data reading circuit, a second data reading circuit, a third data reading circuit, and a logic integration circuit. The output terminals of the first data reading circuit, the second data reading circuit, and the third data reading circuit are respectively connected to the logic integration circuit. The first data reading circuit, the second data reading circuit, and the third data reading circuit are respectively implemented using differential comparators, and the logic integration circuit can construct the required logical operations using standard CMOS logic gates (such as AND gates and OR gates).

[0206] like Figure 8 As shown, the first metal layer is connected to the first input terminal of the first data reading circuit, the fourth metal layer is connected to the first input terminal of the second data reading circuit, the sixth metal layer is connected to the first input terminal of the third data reading circuit, and the second metal layer, the third metal layer, the fifth metal layer and the seventh metal layer are all connected to the second input terminals of the first data reading circuit, the second data reading circuit and the third data reading circuit.

[0207] According to an embodiment of the present disclosure, the data reading circuit reads data of the MRAM storage cell according to the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction of each double magnetic tunnel junction, including:

[0208] The first data reading circuit determines the first read data based on the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction of the first double magnetic tunnel junction, which is recorded as D1; ​​the second data reading circuit determines the second read data based on the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction of the second double magnetic tunnel junction, which is recorded as D2; the third data reading circuit determines the third read data based on the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction of the third double magnetic tunnel junction, which is recorded as D3.

[0209] The logic integration circuit determines data of the MRAM storage cell according to the first read data, the second read data, and the third read data, and the data of the MRAM storage cell is output through an output terminal of the logic integration circuit.

[0210] The data D of the MRAM storage unit is expressed as follows:

[0211] D=(D1∧D2)∨(D2∧D3)∨(D1∧D3).

[0212] The logical operator ∧ represents logical AND, and ∨ represents logical OR.

[0213] The logical meaning of the above formula is: when any two of D1, D2 and D3 are 1, then D is 1; when any two of them are 0, then D is 0.

[0214] In specific Figure 6 When performing a read operation on the MRAM memory cell shown in FIG. Figure 1 The reading process of the MRAM storage unit shown in FIG. Figure 6 The MRAM storage cell shown first reads the write data stored in the first double magnetic tunnel junction, the second double magnetic tunnel junction, and the third double magnetic tunnel junction through the first data reading circuit, the second data reading circuit, and the third data reading circuit, and then performs a logical integration operation on the separately read write data, and uses the final result of the operation as the write data of the MRAM storage cell.

[0215] Figure 6 Another MRAM storage cell based on a differential form according to the embodiment of the present disclosure is shown. Figure 1 The differential MRAM memory cell according to the embodiment of the present disclosure has the following beneficial effects:

[0216] 1. Improve the reliability and fault tolerance of data storage. Figure 6The MRAM cell shown contains three dual magnetic tunnel junctions (six magnetic tunnel junctions). This multi-layered structure makes data storage more reliable. Even if one or two of the dual magnetic tunnel junctions fail or are misread, the data in the remaining structures remains accurate, improving overall fault tolerance and reliability.

[0217] 2. Enhanced resistance to external interference. The design of multiple dual magnetic tunnel junctions reduces the sensitivity of MRAM storage cells to external electromagnetic interference. Even with a certain degree of interference, the voting principle can still determine the correct written data based on the majority rule, reducing the impact of interference on data reading accuracy.

[0218] on the contrary, Figure 1 The embodiment of the present disclosure is a differential MRAM storage cell, compared to Figure 6 Another MRAM storage unit based on differential form in the embodiment of the present disclosure is simpler to implement, and has relatively lower cost and power consumption. In specific implementation, trade-offs can be made according to specific application scenarios and requirements. For example, in application scenarios with high fault tolerance and reliability requirements, such as aerospace, military equipment and other fields, it can be applied Figure 6 The MRAM storage cell shown can be applied in resource-constrained environments. Figure 1 The MRAM memory cell shown.

[0219] The present disclosure also provides an MRAM memory cell array based on a differential form. The MRAM memory cell array includes: N MRAM memory cells described in any one of the above descriptions arranged in an array, and N MOS tubes corresponding to the N MRAM memory cells, wherein N is an integer greater than 1. The second metal layer of each MRAM memory cell is connected to the source of the MOS tube corresponding to the MRAM memory cell, and the drains of the N MOS tubes are connected and then connected to the first source line; the sources of the MOS tubes of each MRAM memory cell are connected to each other and then connected to the second source line; the gate of the MOS tube corresponding to the MRAM memory cell is connected to the gate of the MOS tube of the MRAM memory cell and then connected to the word line corresponding to the MRAM memory cell; the first metal layer of each MRAM memory cell is connected to the first input end of the data reading circuit; the first source line and the second source line are respectively connected to the second input end of the data reading circuit, and the output end of the data reading circuit is connected to the bit line.

[0220] Figure 9 A schematic diagram of the structure of a differential MRAM memory cell array in a specific example of the present disclosure is shown. In the specific example, the MRAM memory cell array includes two Figure 1Taking the MRAM memory cell shown in FIG. 1 and the data reading circuit being implemented by a differential comparator as an example, the structure of the MRAM memory cell array is described.

[0221] like Figure 9 As shown, the MRAM storage cell array includes: 2 array-arranged Figure 1 The MRAM storage cells shown are respectively a first MRAM storage cell and a second MRAM storage cell, and two MOS transistors corresponding one-to-one to the two MRAM storage cells are respectively a first MOS transistor and a second MOS transistor, wherein the first MOS transistor corresponds to the first MRAM storage cell, and the second MOS transistor corresponds to the second MRAM storage cell.

[0222] The second metal layer of the first MRAM storage cell is connected to the source of the first MOS transistor, and the drain of the first MOS transistor is connected to the drain of the second MOS transistor and then connected to the first source line. The sources of the MOS transistors 130 in the first and second MRAM storage cells are connected to each other and then connected to the second source line. The gates of the first and second MOS transistors are respectively connected to the gates of the MOS transistors 130 of the first and second MRAM storage cells and then connected to their respective word lines, that is, the gate of the first MOS transistor is connected to the gate of the MOS transistor 130 of the first MRAM storage cell and then connected to the first word line, and the gate of the second MOS transistor is connected to the gate of the MOS transistor 130 of the second MRAM storage cell and then connected to the second word line. The first metal layers of the first and second MRAM storage cells are connected to the first input terminal of the data read circuit; the first source line and the second source line are respectively connected to the second input terminal of the data read circuit.

[0223] In the pair Figure 9 When performing a write operation on the MRAM memory cell array shown, if the first MRAM memory cell corresponding to the first word line needs to be written, the first word line is controlled to be high and the second word line is controlled to be low to enable the first MRAM memory cell. Then, the MOS transistor 130 and the first MOS transistor in the first MRAM memory cell are turned on. The MOS transistor 130 and the second MOS transistor in the second MRAM memory cell are not turned on and are in the off state.

[0224] In one specific implementation, if data 1 needs to be written, the first source line voltage is controlled to be greater than the second source line voltage so that current flows from top to bottom. Then, the magnetic resistance of the first magnetic tunnel junction of the first MRAM storage cell is large, and the magnetic resistance of the second magnetic tunnel junction of the first MRAM storage cell is small. The difference in magnetic resistance between the first magnetic tunnel junction and the second magnetic tunnel junction is a positive difference, thereby writing data 1.

[0225] If data 0 needs to be written, the first source line voltage is controlled to be lower than the second source line voltage so that current flows from bottom to top. Then, the magnetic resistance of the first magnetic tunnel junction of the first MRAM storage cell is small, and the magnetic resistance of the second magnetic tunnel junction of the first MRAM storage cell is large. The difference in magnetic resistance between the first magnetic tunnel junction and the second magnetic tunnel junction is a negative difference in magnetic resistance, thereby writing data 0.

[0226] In the pair Figure 9 When performing a read operation on the MRAM memory cell array shown, it is confirmed that no write operation is in progress and that all necessary control signals (such as word lines and source lines) have been set to the read mode level. At this time, a differential comparator compares the voltages at the positive and negative poles. If the negative pole voltage is lower than the positive pole voltage, it is a positive magnetoresistance difference, and the differential comparator outputs a high level, and the data read from the MRAM memory cell is 1; if the negative pole voltage is higher than the positive pole voltage, it is a negative magnetoresistance difference, and the differential comparator outputs a low level, and the data read from the MRAM memory cell is 0. The differential comparator outputs the read data to the bit lines through the output terminal for subsequent processing or display. The bit lines are typically designed in groups of 1, 8, 16, 32, or 64.

[0227] Figure 10 FIG. 1 shows a schematic diagram of a structure of a differential MRAM memory according to an embodiment of the present disclosure. Figure 10 As shown, the MRAM memory includes: an MRAM memory cell array cluster, a data writing circuit and a data reading circuit; the MRAM memory cell array cluster includes one or more MRAM memory cell arrays as described above. For the sake of clarity, Figure 10 An address decoder is also shown in FIG. 4 , which is not included in the MRAM memory.

[0228] The input end of the data writing circuit is connected to the external IO port for receiving writing data.

[0229] The output end of the data writing circuit is connected to the word line corresponding to the MRAM memory cell in the MRAM memory cell array, and the first source line and the second source line of the MRAM memory cell array, for outputting the written data.

[0230] The data write circuit is configured to generate a write current between a second metal layer of an MRAM memory cell in the MRAM memory cell array and a drain of a MOS transistor of the MRAM memory cell in the MRAM memory cell array according to the write data, the write current penetrating a double magnetic tunnel junction of the MRAM memory cell in the MRAM memory cell array, and write the write data into the MRAM memory cell in the MRAM memory cell array through the write current, wherein a direction of the write current corresponds to the write data.

[0231] The data reading circuit is configured to read data of the MRAM memory cell in the MRAM memory cell array based on a magnetoresistance difference between a first magnetic tunnel junction and a second magnetic tunnel junction of the MRAM memory cell, and the data of the MRAM memory cell is output through an output end of the data reading circuit; wherein the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction includes a positive magnetoresistance difference and a negative magnetoresistance difference, the positive magnetoresistance difference being formed because the magnetoresistance of the first magnetic tunnel junction is greater than the magnetoresistance of the second magnetic tunnel junction, and the negative magnetoresistance difference being formed because the magnetoresistance of the first magnetic tunnel junction is less than the magnetoresistance of the second magnetic tunnel junction.

[0232] During the writing process to the MRAM memory, the address decoder controls the word lines of the MRAM memory cells in the MRAM memory cell array, thereby controlling the gating of the corresponding MRAM memory cells.

[0233] According to an embodiment of the present disclosure, the direction of the write current includes a first direction and a second direction; when the direction of the write current is the first direction, the write current is the first write current; when the direction of the write current is the second direction, the write current is the second write current; the direction of the write current corresponds to the write data, including: the first write current corresponds to the first write data; the second write current corresponds to the second write data; wherein the first write data is 0 and the second write data is 1; or, the first write data is 1 and the second write data is 0.

[0234] According to an embodiment of the present disclosure, forming a write current penetrating a dual magnetic tunnel junction of an MRAM memory cell in the MRAM memory cell array between a second metal layer of the MRAM memory cell in the MRAM memory cell array and a drain of a MOS transistor of the MRAM memory cell in the MRAM memory cell array according to the write data includes: when the write data is first write data, forming a first write current penetrating the dual magnetic tunnel junction between the second metal layer and the drain of the MOS transistor; when the write data is second write data, forming a second write current penetrating the dual magnetic tunnel junction between the second metal layer and the drain of the MOS transistor.

[0235] According to an embodiment of the present disclosure, forming a first write current between the second metal layer and the drain of the MOS transistor and penetrating the dual magnetic tunnel junction includes:

[0236] When a high level is input to the word line to turn on the MOS transistor, and at the same time a first voltage is applied to the second metal layer and a second voltage is applied to the source line, and the first voltage is greater than the second voltage, a first write current is formed that flows from the second metal layer to the drain of the MOS transistor and penetrates the dual magnetic tunnel junction, and the first write current flows out from the source of the MOS transistor.

[0237] The forming of a second write current penetrating the dual magnetic tunnel junction between the second metal layer and the drain of the MOS transistor includes:

[0238] When a high level is input to the word line to turn on the MOS transistor, and at the same time a first voltage is applied to the source line and a second voltage is applied to the second metal layer, and the first voltage is greater than the second voltage, a second write current is generated that flows from the drain of the MOS transistor to the second metal layer and penetrates the double magnetic tunnel junction, and the second write current flows out from the second metal layer; wherein, turning on the MOS transistor includes: when the MOS transistor is an NMOS transistor, applying a forward bias voltage between the gate and source of the MOS transistor; when the MOS transistor is a PMOS transistor, applying a negative bias voltage between the gate and source of the MOS transistor, so that the MOS transistor is turned on.

[0239] According to an embodiment of the present disclosure, writing the write data into the MRAM storage cell by using the write current includes:

[0240] When the write current is the first write current, then:

[0241] The first write current flows from the fixed layer of the first magnetic tunnel junction to the free layer, so that the magnetization directions of the free layer of the first magnetic tunnel junction and the fixed layer of the first magnetic tunnel junction are opposite, and the magnetoresistance state of the first magnetic tunnel junction is a high-resistance state; the first write current flows from the free layer of the second magnetic tunnel junction to the fixed layer, so that the magnetization directions of the free layer of the second magnetic tunnel junction and the fixed layer of the second magnetic tunnel junction are the same, and the magnetoresistance state of the second magnetic tunnel junction is a low-resistance state, thereby writing the first write data.

[0242] When the write current is the second write current, then:

[0243] The second write current flows from the free layer of the first magnetic tunnel junction to the fixed layer, so that the magnetization directions of the free layer of the first magnetic tunnel junction and the fixed layer of the first magnetic tunnel junction are the same, and the magnetoresistance state of the first magnetic tunnel junction is a low resistance state; the second write current flows from the fixed layer of the second magnetic tunnel junction to the free layer, so that the magnetization directions of the free layer of the second magnetic tunnel junction and the fixed layer of the second magnetic tunnel junction are opposite, and the magnetoresistance state of the second magnetic tunnel junction is a high resistance state, thereby writing the second write data.

[0244] According to an embodiment of the present disclosure, the method of reading data of the MRAM memory cell in the MRAM memory cell array according to the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction includes:

[0245] A voltage difference between a first input terminal and a second input terminal of the data reading circuit is determined according to a magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction; and data of the MRAM storage cell is read according to the voltage difference between the first input terminal and the second input terminal of the data reading circuit.

[0246] According to an embodiment of the present disclosure, determining a voltage difference between a first input terminal and a second input terminal of the data reading circuit according to a magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction includes:

[0247] When the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction is a positive magnetoresistance difference, the voltage at the first input terminal of the data reading circuit is less than the voltage at the second input terminal of the data reading circuit; when the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction is a negative magnetoresistance difference, the voltage at the first input terminal of the data reading circuit is greater than the voltage at the second input terminal of the data reading circuit; and reading data of the MRAM storage cell according to the voltage difference between the first input terminal and the second input terminal of the data reading circuit includes:

[0248] When the voltage at the first input terminal of the data reading circuit is less than the voltage at the second input terminal of the data reading circuit, the data read from the MRAM storage cell is the first write data; when the voltage at the first input terminal of the data reading circuit is greater than the voltage at the second input terminal of the data reading circuit, the data read from the MRAM storage cell is the second write data.

[0249] Figure 11 A flowchart of a method for preparing a differential MRAM memory cell according to an embodiment of the present disclosure is shown. The MRAM memory cell includes: a MOS tube, a dual magnetic tunnel junction, a first metal layer, a second metal layer, and a third metal layer; wherein the dual magnetic tunnel junction includes: a first magnetic tunnel junction and a second magnetic tunnel junction, such as Figure 11 As shown, the preparation method includes the following steps S1110 to S1160:

[0250] In step S1110 , the MOS transistor is formed, and the MOS transistor is located at the bottom of the MRAM storage unit.

[0251] When forming the MOS transistor, the following steps are performed:

[0252] 1. Substrate Preparation: First, select a suitable semiconductor substrate (such as a silicon wafer) and perform cleaning and pretreatment, such as chemical mechanical polishing (CMP), to remove surface impurities and oxide layers. When selecting a substrate, if the MOS transistor to be formed is a PMOS transistor, choose a P-type silicon wafer as the substrate; if the MOS transistor to be formed is an NMOS transistor, choose an N-type silicon wafer as the substrate.

[0253] 2. Isolation region formation: An isolation region is formed on the substrate through shallow trench isolation (STI) or local oxidation of silicon (LOCOS) technology to define the active area of ​​the MOS tube.

[0254] 3. Gate oxide growth: A layer of high-quality silicon dioxide (SiO2) is grown on the active area as the gate oxide layer.

[0255] 4. Gate formation: The gate pattern is defined using photolithography and etching techniques, and then the gate structure is formed by metal deposition (such as polysilicon or polysilicon / metal stack) and back etching.

[0256] 5. Source and drain region doping: Ion implantation technology is used to form source and drain regions in the active areas on both sides of the gate, and annealing is performed to activate the doped atoms.

[0257] When forming the source and drain regions in the active areas on both sides of the gate by ion implantation technology, if the MOS transistor formed is a PMOS transistor, the source and drain need to be N-type doped to form N-type regions. The electrons in these regions will be repelled into the channel, leaving holes as conductive carriers. Then, N-type impurities (such as phosphorus P or arsenic As) are implanted into the active areas on both sides of the gate by ion implantation technology to form source and drain regions. If the MOS transistor formed is an NMOS transistor, the source and drain need to be P-type doped to form P-type regions. The holes in these regions will be repelled into the channel, leaving electrons as conductive carriers. Then, P-type impurities (such as boron B or indium In) are implanted into the active areas on both sides of the gate by ion implantation technology to form source and drain regions.

[0258] 6. Passivation layer deposition: Deposit a layer of silicon nitride (Si3N4) or silicon dioxide as a passivation layer to protect the MOS tube from the impact of subsequent processes.

[0259] In step S1120 , the third metal layer is formed on the MOS transistor.

[0260] When forming the third metal layer, the following steps are performed:

[0261] 1. Opening: Open a contact hole on the passivation layer through photolithography and etching technology to connect to the drain of the MOS tube.

[0262] 2. Metal deposition: Use physical vapor deposition (PVD), chemical vapor deposition (CVD) or electroplating to deposit a third metal layer (such as copper, aluminum or copper alloy) on the contact hole and the top of the exposed MOS tube to form a conductive path.

[0263] 3. Planarization: Use chemical mechanical polishing (CMP) and other technologies to remove excess metal and flatten the surface.

[0264] In step S1130 , a fixed layer, a non-magnetic tunneling layer, and a free layer of the second magnetic tunnel junction are sequentially formed on the third metal layer.

[0265] Specifically, a layer of magnetic material (such as cobalt iron boron CoFeB) is deposited on the third metal layer through sputtering or evaporation technology as the fixed layer of the second magnetic tunnel junction. Then, a layer of non-magnetic insulating material (such as magnesium oxide MgO) is deposited on the fixed layer as a non-magnetic tunneling layer, and its thickness is controlled to achieve the quantum tunneling effect. Finally, a layer of magnetic material is deposited on the non-magnetic tunneling layer as a free layer, whose magnetization direction can change with the external magnetic field.

[0266] In step S1140 , the first metal layer is formed on the free layer of the second magnetic tunnel junction.

[0267] In step S1150 , a free layer, a non-magnetic tunneling layer, and a fixed layer of the first magnetic tunnel junction are sequentially formed on the first metal layer.

[0268] In step S1160 , the second metal layer is formed on the fixed layer of the first magnetic tunnel junction.

[0269] It should be noted that during the entire preparation process, conditions such as temperature, pressure and atmosphere are strictly controlled to avoid material contamination and performance degradation.

[0270] Figure 12 A flow chart of another method for preparing a differential MRAM memory cell according to an embodiment of the present disclosure is shown. The MRAM memory cell includes: a MOS tube, a first dual magnetic tunnel junction, a second dual magnetic tunnel junction, a third dual magnetic tunnel junction, a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, a fifth metal layer, a sixth metal layer, and a seventh metal layer; wherein the dual magnetic tunnel junction includes: a first magnetic tunnel junction and a second magnetic tunnel junction. Figure 12 As shown, the preparation method includes the following steps S1210~S1270:

[0271] In step S1210 , the MOS transistor is formed, and the MOS transistor is located at the bottom of the MRAM storage unit; and the seventh metal layer is formed on the MOS transistor.

[0272] In step S1220, a fixed layer, a nonmagnetic tunneling layer and a free layer of the second magnetic tunnel junction of the third double magnetic tunnel junction are sequentially formed on the seventh metal layer; and the sixth metal layer is formed on the free layer of the second magnetic tunnel junction of the third double magnetic tunnel junction.

[0273] In step S1230, a free layer, a nonmagnetic tunnel layer and a fixed layer of the first magnetic tunnel junction of the third double magnetic tunnel junction are sequentially formed on the sixth metal layer; and the fifth metal layer is formed on the fixed layer of the first magnetic tunnel junction of the third double magnetic tunnel junction.

[0274] In step S1240, a fixed layer, a nonmagnetic tunnel layer and a free layer of the second magnetic tunnel junction of the second double magnetic tunnel junction are sequentially formed on the fifth metal layer; and a fourth metal layer is formed on the free layer of the second magnetic tunnel junction of the second double magnetic tunnel junction.

[0275] In step S1250, a free layer, a nonmagnetic tunnel layer and a fixed layer of the first magnetic tunnel junction of the second double magnetic tunnel junction are sequentially formed on the fourth metal layer; and a third metal layer is formed on the fixed layer of the second magnetic tunnel junction of the second double magnetic tunnel junction.

[0276] In step S1260, a fixed layer, a nonmagnetic tunnel layer and a free layer of the second magnetic tunnel junction of the first double magnetic tunnel junction are sequentially formed on the third metal layer; and a first metal layer is formed on the free layer of the second magnetic tunnel junction of the first double magnetic tunnel junction.

[0277] In step S1270, a free layer, a nonmagnetic tunnel layer and a fixed layer of the first magnetic tunnel junction of the first double magnetic tunnel junction are sequentially formed on the first metal layer; and a second metal layer is formed on the fixed layer of the first magnetic tunnel junction of the first double magnetic tunnel junction.

[0278] The present disclosure also provides a differential-type MRAM memory cell, which is manufactured according to any one of the manufacturing methods described in the present disclosure.

[0279] The present disclosure also provides a chip, comprising the MRAM storage unit described in any one of the embodiments of the present disclosure.

[0280] The present disclosure also provides a chip, comprising the MRAM memory described in any one of the embodiments of the present disclosure.

[0281] According to the technical solution provided by the embodiments of the present disclosure, a dual magnetic tunnel junction comprising a first magnetic tunnel junction and a second magnetic tunnel junction is innovatively introduced into an MRAM memory cell. The first and second magnetic tunnel junctions are mirror-imaged on either side of a first metal layer, with their free layers both electrically contacting the first metal layer and their fixed layers electrically contacting the second and third metal layers, respectively. When a write operation is performed on the MRAM memory cell, data is written by applying write currents in different directions through the dual magnetic tunnel junctions. When a read operation is performed on the MRAM memory cell, data is read by determining the difference in magnetoresistance between the first and second magnetic tunnel junctions. Because the two MTJs are mirror-imaged, this symmetrical design allows the two MTJs to be relatively independent in physical location while having similar electromagnetic properties. When there is strong external magnetic field interference, the two MTJs are affected in roughly the same way, thereby reducing storage errors caused by uneven magnetic fields. At the same time, under common-mode magnetic field interference conditions, the two MTJ magnetoresistances change synchronously with the external magnetic field interference, but the magnetoresistance difference is not easy to change. By identifying the magnetoresistance difference, the stored data can be effectively read, thereby ensuring the correct reading of the data, thereby effectively resisting external magnetic field interference.

[0282] The above description is merely a preferred embodiment of the present disclosure and an illustration of the technical principles employed. Those skilled in the art should understand that the scope of the invention herein is not limited to technical solutions formed by specific combinations of the aforementioned technical features. It also encompasses other technical solutions formed by any combination of the aforementioned technical features or their equivalents, without departing from the inventive concept. For example, a technical solution formed by replacing the aforementioned features with (but not limited to) technical features with similar functions disclosed in this disclosure.

Claims

1. A differential MRAM storage cell, characterized in that: The MRAM storage cell includes: a MOS transistor, a dual magnetic tunnel junction, a first metal layer, a second metal layer, and a third metal layer; wherein the dual magnetic tunnel junction includes: a first magnetic tunnel junction and a second magnetic tunnel junction; the first magnetic tunnel junction and the second magnetic tunnel junction respectively include a fixed layer, a non-magnetic tunnel layer, and a free layer arranged in sequence; The first magnetic tunnel junction and the second magnetic tunnel junction are mirror-imaged and arranged on both sides of the first metal layer. The free layer of the first magnetic tunnel junction and the free layer of the second magnetic tunnel junction are respectively in electrical contact with the first metal layer. The fixed layer of the first magnetic tunnel junction is in electrical contact with the second metal layer, and the fixed layer of the second magnetic tunnel junction is in electrical contact with the third metal layer. The gate of the MOS transistor is connected to the word line, the source of the MOS transistor is connected to the source line, and the drain of the MOS transistor is connected to the third metal layer; When the MRAM storage cell is in a write state, the second metal layer, the word line, and the source line are respectively connected to a data write circuit, and a write current penetrating the dual magnetic tunnel junction is formed between the second metal layer and the drain of the MOS transistor according to write data through the data write circuit, so that the data write circuit writes the write data into the MRAM storage cell through the write current, wherein the direction of the write current corresponds to the write data; When the MRAM memory cell is in a read state, the first metal layer is connected to a first input terminal of a data read circuit, and the second metal layer and the third metal layer are respectively connected to a second input terminal of the data read circuit, so that the data read circuit reads data of the MRAM memory cell based on the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction, and the data of the MRAM memory cell is output through the output terminal of the data read circuit; wherein the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction includes a positive magnetoresistance difference and a negative magnetoresistance difference, the positive magnetoresistance difference being formed because the magnetoresistance of the first magnetic tunnel junction is greater than that of the second magnetic tunnel junction, and the negative magnetoresistance difference being formed because the magnetoresistance of the first magnetic tunnel junction is less than that of the second magnetic tunnel junction.

2. The MRAM memory cell according to claim 1, wherein: The direction of the write current includes a first direction and a second direction; When the direction of the write current is the first direction, the write current is the first write current; When the direction of the write current is the second direction, the write current is the second write current; The direction of the write current corresponds to the write data, including: The first write current corresponds to the first write data; the second write current corresponds to the second write data; The first written data is 0, and the second written data is 1; or the first written data is 1, and the second written data is 0.

3. The MRAM memory cell according to claim 2, wherein: The step of forming a write current penetrating the dual magnetic tunnel junction between the second metal layer and the drain of the MOS transistor according to the write data includes: When the write data is first write data, a first write current is formed between the second metal layer and the drain of the MOS transistor and penetrates the dual magnetic tunnel junction; When the write data is second write data, a second write current penetrating the dual magnetic tunnel junction is formed between the second metal layer and the drain of the MOS transistor.

4. The MRAM memory cell according to claim 3, wherein: The step of forming a first write current between the second metal layer and the drain of the MOS transistor and penetrating the dual magnetic tunnel junction includes: When a high level is input to the word line to turn on the MOS transistor, and at the same time a first voltage is applied to the second metal layer and a second voltage is applied to the source line, and the first voltage is greater than the second voltage, a first write current is generated that flows from the second metal layer to the drain of the MOS transistor and penetrates the dual magnetic tunnel junction, and the first write current flows out from the source of the MOS transistor; The forming of a second write current penetrating the dual magnetic tunnel junction between the second metal layer and the drain of the MOS transistor includes: When a high level is input to the word line to turn on the MOS transistor, and a first voltage is applied to the source line and a second voltage is applied to the second metal layer, and the first voltage is greater than the second voltage, a second write current is generated that flows from the drain of the MOS transistor to the second metal layer and penetrates the dual magnetic tunnel junction, and the second write current flows out from the second metal layer; Wherein, turning on the MOS transistor includes: when the MOS transistor is an NMOS transistor, applying a forward bias voltage between the gate and source of the MOS transistor; when the MOS transistor is a PMOS transistor, applying a negative bias voltage between the gate and source of the MOS transistor, so that the MOS transistor is turned on.

5. The MRAM memory cell according to claim 4, wherein: Writing the write data into the MRAM storage unit by the write current includes: When the write current is the first write current, then: The first write current flows from the fixed layer to the free layer of the first magnetic tunnel junction, causing the magnetization directions of the free layer of the first magnetic tunnel junction and the fixed layer of the first magnetic tunnel junction to be opposite, and the magnetoresistance state of the first magnetic tunnel junction to be a high-resistance state; the first write current flows from the free layer to the fixed layer of the second magnetic tunnel junction, causing the magnetization directions of the free layer of the second magnetic tunnel junction and the fixed layer of the second magnetic tunnel junction to be the same, and the magnetoresistance state of the second magnetic tunnel junction to be a low-resistance state, and the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction to be a positive magnetoresistance difference, thereby writing the first write data; When the write current is the second write current, then: The second write current flows from the free layer of the first magnetic tunnel junction to the fixed layer, so that the magnetization directions of the free layer of the first magnetic tunnel junction and the fixed layer of the first magnetic tunnel junction are the same, and the magnetoresistance state of the first magnetic tunnel junction is a low resistance state; the second write current flows from the fixed layer of the second magnetic tunnel junction to the free layer, so that the magnetization directions of the free layer of the second magnetic tunnel junction and the fixed layer of the second magnetic tunnel junction are opposite, the magnetoresistance state of the second magnetic tunnel junction is a high resistance state, and the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction is a negative magnetoresistance difference, thereby writing the second write data.

6. The MRAM memory cell according to claim 2, wherein: The method of reading data of the MRAM storage cell according to the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction includes: determining a voltage difference between a first input terminal and a second input terminal of the data reading circuit according to a magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction; Data of the MRAM storage cell is read according to a voltage difference between the first input terminal and the second input terminal of the data reading circuit.

7. The MRAM memory cell according to claim 6, wherein: The step of determining a voltage difference between a first input terminal and a second input terminal of the data reading circuit according to a magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction comprises: When the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction is a positive magnetoresistance difference, the voltage at the first input terminal of the data reading circuit is less than the voltage at the second input terminal of the data reading circuit; When the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction is a negative magnetoresistance difference, the voltage at the first input terminal of the data reading circuit is greater than the voltage at the second input terminal of the data reading circuit; The step of reading data of the MRAM storage cell according to a voltage difference between a first input terminal and a second input terminal of the data reading circuit includes: When the voltage at the first input terminal of the data reading circuit is less than the voltage at the second input terminal of the data reading circuit, the data read from the MRAM storage cell is the first write data; When the voltage at the first input terminal of the data reading circuit is greater than the voltage at the second input terminal of the data reading circuit, the data read from the MRAM storage cell is the second write data.

8. A differential MRAM storage cell, characterized in that: The MRAM storage cell includes: a MOS transistor, three dual magnetic tunnel junctions, a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, a fifth metal layer, a sixth metal layer, and a seventh metal layer; wherein the three dual magnetic tunnel junctions are respectively: a first dual magnetic tunnel junction, a second dual magnetic tunnel junction, and a third dual magnetic tunnel junction; the dual magnetic tunnel junctions include: a first magnetic tunnel junction and a second magnetic tunnel junction; the first magnetic tunnel junction and the second magnetic tunnel junction respectively include a fixed layer, a non-magnetic tunnel layer, and a free layer arranged in sequence; The first magnetic tunnel junction of the first double magnetic tunnel junction and the second magnetic tunnel junction of the first double magnetic tunnel junction are mirror-imaged and arranged on both sides of the first metal layer. The free layer of the first magnetic tunnel junction of the first double magnetic tunnel junction and the free layer of the second magnetic tunnel junction of the first double magnetic tunnel junction are respectively in electrical contact with the first metal layer. The fixed layer of the first magnetic tunnel junction of the first double magnetic tunnel junction is in electrical contact with the second metal layer, and the fixed layer of the second magnetic tunnel junction of the first double magnetic tunnel junction is in electrical contact with the third metal layer. The first magnetic tunnel junction of the second double magnetic tunnel junction and the second magnetic tunnel junction of the second double magnetic tunnel junction are mirror-imaged and arranged on both sides of the fourth metal layer. The free layer of the first magnetic tunnel junction of the second double magnetic tunnel junction and the free layer of the second magnetic tunnel junction of the second double magnetic tunnel junction are respectively in electrical contact with the fourth metal layer. The fixed layer of the first magnetic tunnel junction of the second double magnetic tunnel junction is in electrical contact with the third metal layer, and the fixed layer of the second magnetic tunnel junction of the second double magnetic tunnel junction is in electrical contact with the fifth metal layer. The first magnetic tunnel junction of the third double magnetic tunnel junction and the second magnetic tunnel junction of the third double magnetic tunnel junction are mirror-imaged and arranged on both sides of the sixth metal layer. The free layer of the first magnetic tunnel junction of the third double magnetic tunnel junction and the free layer of the second magnetic tunnel junction of the third double magnetic tunnel junction are respectively in electrical contact with the sixth metal layer. The pinned layer of the first magnetic tunnel junction of the third double magnetic tunnel junction is in electrical contact with the fifth metal layer, and the pinned layer of the second magnetic tunnel junction of the third double magnetic tunnel junction is in electrical contact with the seventh metal layer. The gate of the MOS transistor is connected to the word line, the source of the MOS transistor is connected to the source line, and the drain of the MOS transistor is connected to the seventh metal layer; When the MRAM storage cell is in a write state, the second metal layer, the word line, and the source line are respectively connected to a data write circuit, and a write current is formed between the second metal layer and the drain of the MOS transistor according to write data, penetrating the first double magnetic tunnel junction, the second double magnetic tunnel junction, and the third double magnetic tunnel junction, so that the data write circuit writes the write data into the MRAM storage cell through the write current, wherein the direction of the write current corresponds to the write data; When the MRAM memory cell is in a read state, the first metal layer, the fourth metal layer, and the sixth metal layer are respectively connected to a first input terminal of a data read circuit, and the second metal layer, the third metal layer, the fifth metal layer, and the seventh metal layer are respectively connected to a second input terminal of the data read circuit, so that the data read circuit reads data of the MRAM memory cell based on a magnetoresistance difference between a first magnetic tunnel junction and a second magnetic tunnel junction of each double magnetic tunnel junction, and the data of the MRAM memory cell is output through an output terminal of the data read circuit. The magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction includes a positive magnetoresistance difference and a negative magnetoresistance difference, wherein the positive magnetoresistance difference is formed because the magnetoresistance of the first magnetic tunnel junction is greater than that of the second magnetic tunnel junction, and the negative magnetoresistance difference is formed because the magnetoresistance of the first magnetic tunnel junction is less than that of the second magnetic tunnel junction.

9. The MRAM memory cell according to claim 8, wherein: The data reading circuit includes: a first data reading circuit, a second data reading circuit, a third data reading circuit and a logic integration circuit, wherein the output ends of the first data reading circuit, the second data reading circuit and the third data reading circuit are respectively connected to the logic integration circuit; The first metal layer, the fourth metal layer, and the sixth metal layer are respectively connected to a first input terminal of a data reading circuit, and the second metal layer, the third metal layer, the fifth metal layer, and the seventh metal layer are respectively connected to a second input terminal of the data reading circuit, comprising: The first metal layer is connected to the first input terminal of the first data reading circuit, the fourth metal layer is connected to the first input terminal of the second data reading circuit, the sixth metal layer is connected to the first input terminal of the third data reading circuit, and the second metal layer, the third metal layer, the fifth metal layer and the seventh metal layer are all connected to the second input terminals of the first data reading circuit, the second data reading circuit and the third data reading circuit.

10. The MRAM memory cell according to claim 9, wherein: The data reading circuit reads data of the MRAM storage cell according to a magnetoresistance difference between a first magnetic tunnel junction and a second magnetic tunnel junction of each double magnetic tunnel junction, comprising: The first data reading circuit determines first read data according to a magnetoresistance difference between a first magnetic tunnel junction and a second magnetic tunnel junction of the first double magnetic tunnel junction, which is recorded as D1; The second data reading circuit determines second read data according to a magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction of the second double magnetic tunnel junction, which is recorded as D2; The third data reading circuit determines third read data according to the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction of the third double magnetic tunnel junction, which is recorded as D3; The logic integration circuit determines the data of the MRAM storage cell according to the first read data, the second read data, and the third read data, and the data of the MRAM storage cell is output through the output terminal of the logic integration circuit; The data D of the MRAM storage unit is expressed as follows: D=(D1∧D2)∨(D2∧D3)∨(D1∧D3).

11. A differential MRAM memory cell array, characterized in that: include: N MRAM memory cells according to any one of claims 1 to 10 arranged in an array, and N MOS transistors corresponding one-to-one to the N MRAM memory cells, wherein N is an integer greater than 1; The second metal layer of each MRAM storage cell is connected to the source of the MOS tube corresponding to the MRAM storage cell, and the drains of the N MOS tubes are connected to the first source line; The sources of the MOS transistors of each MRAM storage cell are connected to each other and then to the second source line; the gates of the MOS transistors corresponding to the MRAM storage cells are connected to the gates of the MOS transistors of the MRAM storage cells and then to the word lines corresponding to the MRAM storage cells; The first metal layer of each MRAM storage cell is connected to the first input terminal of the data reading circuit; The first source line and the second source line are respectively connected to the second input terminal of the data reading circuit; An output terminal of the data reading circuit is connected to a bit line.

12. A differential MRAM memory, characterized in that: include: MRAM memory cell array cluster, data writing circuit and data reading circuit; The MRAM memory cell array cluster comprises one or more MRAM memory cell arrays according to claim 11; The input end of the data writing circuit is connected to the external IO port for receiving write data; The output end of the data writing circuit is connected to the word line corresponding to the MRAM memory cell in the MRAM memory cell array, and the first source line and the second source line of the MRAM memory cell array, for outputting the written data; The data write circuit is configured to generate a write current between a second metal layer of an MRAM memory cell in the MRAM memory cell array and a drain of a MOS transistor of the MRAM memory cell in the MRAM memory cell array according to the write data, so as to penetrate a double magnetic tunnel junction of the MRAM memory cell in the MRAM memory cell array, and write the write data into the MRAM memory cell in the MRAM memory cell array through the write current, wherein a direction of the write current corresponds to the write data; The data reading circuit is configured to read data of the MRAM memory cell in the MRAM memory cell array based on a magnetoresistance difference between a first magnetic tunnel junction and a second magnetic tunnel junction of the MRAM memory cell, and the data of the MRAM memory cell is output through an output end of the data reading circuit; wherein the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction includes a positive magnetoresistance difference and a negative magnetoresistance difference, the positive magnetoresistance difference being formed because the magnetoresistance of the first magnetic tunnel junction is greater than the magnetoresistance of the second magnetic tunnel junction, and the negative magnetoresistance difference being formed because the magnetoresistance of the first magnetic tunnel junction is less than the magnetoresistance of the second magnetic tunnel junction.

13. The MRAM memory according to claim 12, wherein: The direction of the write current includes a first direction and a second direction; When the direction of the write current is the first direction, the write current is the first write current; When the direction of the write current is the second direction, the write current is the second write current; The direction of the write current corresponds to the write data, including: The first write current corresponds to the first write data; the second write current corresponds to the second write data; The first written data is 0, and the second written data is 1; or the first written data is 1, and the second written data is 0.

14. The MRAM memory according to claim 13, wherein: The step of forming a write current penetrating a double magnetic tunnel junction of an MRAM memory cell in the MRAM memory cell array between a second metal layer of the MRAM memory cell in the MRAM memory cell array and a drain of a MOS transistor of the MRAM memory cell in the MRAM memory cell array according to the write data comprises: When the write data is first write data, a first write current is formed between the second metal layer and the drain of the MOS transistor and penetrates the dual magnetic tunnel junction; When the write data is second write data, a second write current penetrating the dual magnetic tunnel junction is formed between the second metal layer and the drain of the MOS transistor.

15. The MRAM memory according to claim 14, wherein: The step of forming a first write current between the second metal layer and the drain of the MOS transistor and penetrating the dual magnetic tunnel junction includes: When a high level is input to the word line to turn on the MOS transistor, and at the same time a first voltage is applied to the second metal layer and a second voltage is applied to the source line, and the first voltage is greater than the second voltage, a first write current is generated that flows from the second metal layer to the drain of the MOS transistor and penetrates the dual magnetic tunnel junction, and the first write current flows out from the source of the MOS transistor; The forming of a second write current penetrating the dual magnetic tunnel junction between the second metal layer and the drain of the MOS transistor includes: When a high level is input to the word line to turn on the MOS transistor, and a first voltage is applied to the source line and a second voltage is applied to the second metal layer, and the first voltage is greater than the second voltage, a second write current is generated that flows from the drain of the MOS transistor to the second metal layer and penetrates the dual magnetic tunnel junction, and the second write current flows out from the second metal layer; Wherein, turning on the MOS transistor includes: when the MOS transistor is an NMOS transistor, applying a forward bias voltage between the gate and source of the MOS transistor; when the MOS transistor is a PMOS transistor, applying a negative bias voltage between the gate and source of the MOS transistor, so that the MOS transistor is turned on.

16. The MRAM memory according to claim 15, wherein: Writing the write data into the MRAM storage unit by the write current includes: When the write current is the first write current, then: The first write current flows from the fixed layer to the free layer of the first magnetic tunnel junction, so that the magnetization directions of the free layer of the first magnetic tunnel junction and the fixed layer of the first magnetic tunnel junction are opposite, and the magnetoresistance state of the first magnetic tunnel junction is a high-resistance state; the first write current flows from the free layer to the fixed layer of the second magnetic tunnel junction, so that the magnetization directions of the free layer of the second magnetic tunnel junction and the fixed layer of the second magnetic tunnel junction are the same, and the magnetoresistance state of the second magnetic tunnel junction is a low-resistance state, thereby writing the first write data; When the write current is the second write current, then: The second write current flows from the free layer of the first magnetic tunnel junction to the fixed layer, so that the magnetization directions of the free layer of the first magnetic tunnel junction and the fixed layer of the first magnetic tunnel junction are the same, and the magnetoresistance state of the first magnetic tunnel junction is a low resistance state; the second write current flows from the fixed layer of the second magnetic tunnel junction to the free layer, so that the magnetization directions of the free layer of the second magnetic tunnel junction and the fixed layer of the second magnetic tunnel junction are opposite, and the magnetoresistance state of the second magnetic tunnel junction is a high resistance state, thereby writing the second write data.

17. The MRAM memory according to claim 13, wherein: The method of reading data of the MRAM memory cell according to a magnetoresistance difference between a first magnetic tunnel junction and a second magnetic tunnel junction of the MRAM memory cell in the MRAM memory cell array includes: determining a voltage difference between a first input terminal and a second input terminal of the data reading circuit according to a magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction; Data of the MRAM storage cell is read according to a voltage difference between the first input terminal and the second input terminal of the data reading circuit.

18. The MRAM memory according to claim 17, wherein: The step of determining a voltage difference between a first input terminal and a second input terminal of the data reading circuit according to a magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction comprises: When the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction is a positive magnetoresistance difference, the voltage at the first input terminal of the data reading circuit is less than the voltage at the second input terminal of the data reading circuit; When the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction is a negative magnetoresistance difference, the voltage at the first input terminal of the data reading circuit is greater than the voltage at the second input terminal of the data reading circuit; The step of reading data of the MRAM storage cell according to a voltage difference between a first input terminal and a second input terminal of the data reading circuit includes: When the voltage at the first input terminal of the data reading circuit is less than the voltage at the second input terminal of the data reading circuit, the data read from the MRAM storage cell is the first write data; When the voltage at the first input terminal of the data reading circuit is greater than the voltage at the second input terminal of the data reading circuit, the data read from the MRAM storage cell is the second write data.

19. A method for preparing a differential MRAM memory cell, characterized in that: The MRAM storage cell includes: a MOS transistor, a dual magnetic tunnel junction, a first metal layer, a second metal layer, and a third metal layer; wherein the dual magnetic tunnel junction includes: a first magnetic tunnel junction and a second magnetic tunnel junction, and the preparation method includes: forming the MOS transistor, wherein the MOS transistor is located at the bottom of the MRAM storage unit; forming the third metal layer on the MOS tube; forming a fixed layer, a non-magnetic tunneling layer and a free layer of the second magnetic tunnel junction in sequence on the third metal layer; forming the first metal layer on the free layer of the second magnetic tunnel junction; forming a free layer, a non-magnetic tunneling layer and a fixed layer of the first magnetic tunnel junction in sequence on the first metal layer; forming the second metal layer on the fixed layer of the first magnetic tunnel junction; The gate of the MOS transistor is connected to the word line, the source of the MOS transistor is connected to the source line, and the drain of the MOS transistor is connected to the third metal layer; When the MRAM storage cell is in a write state, the second metal layer, the word line, and the source line are respectively connected to a data write circuit, and a write current penetrating the dual magnetic tunnel junction is formed between the second metal layer and the drain of the MOS transistor according to write data through the data write circuit, so that the data write circuit writes the write data into the MRAM storage cell through the write current, wherein the direction of the write current corresponds to the write data; When the MRAM memory cell is in a read state, the first metal layer is connected to a first input terminal of a data read circuit, and the second metal layer and the third metal layer are respectively connected to a second input terminal of the data read circuit, so that the data read circuit reads data of the MRAM memory cell based on the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction, and the data of the MRAM memory cell is output through the output terminal of the data read circuit; wherein the magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction includes a positive magnetoresistance difference and a negative magnetoresistance difference, the positive magnetoresistance difference being formed because the magnetoresistance of the first magnetic tunnel junction is greater than that of the second magnetic tunnel junction, and the negative magnetoresistance difference being formed because the magnetoresistance of the first magnetic tunnel junction is less than that of the second magnetic tunnel junction.

20. A method for preparing a differential MRAM memory cell, characterized in that: The MRAM storage cell includes: a MOS transistor, a first double magnetic tunnel junction, a second double magnetic tunnel junction, a third double magnetic tunnel junction, a first metal layer, a second metal layer, a third metal layer, a fourth metal layer, a fifth metal layer, a sixth metal layer, and a seventh metal layer; wherein the double magnetic tunnel junction includes: a first magnetic tunnel junction and a second magnetic tunnel junction, and the preparation method includes: forming the MOS transistor, wherein the MOS transistor is located at the bottom of the MRAM storage unit; forming the seventh metal layer on the MOS transistor; forming a fixed layer, a non-magnetic tunneling layer and a free layer of the second magnetic tunnel junction of the third double magnetic tunnel junction in sequence on the seventh metal layer; forming the sixth metal layer on the free layer of the second magnetic tunnel junction of the third double magnetic tunnel junction; forming a free layer, a non-magnetic tunneling layer and a fixed layer of a first magnetic tunnel junction of the third double magnetic tunnel junction in sequence on the sixth metal layer; forming the fifth metal layer on the fixed layer of the first magnetic tunnel junction of the third double magnetic tunnel junction; forming a fixed layer, a non-magnetic tunneling layer and a free layer of the second magnetic tunnel junction of the second double magnetic tunnel junction in sequence on the fifth metal layer; forming a fourth metal layer on the free layer of the second magnetic tunnel junction of the second double magnetic tunnel junction; forming a free layer, a non-magnetic tunneling layer and a fixed layer of the first magnetic tunnel junction of the second double magnetic tunnel junction in sequence on the fourth metal layer; forming a third metal layer on the fixed layer of the second magnetic tunnel junction of the second double magnetic tunnel junction; forming a fixed layer, a non-magnetic tunneling layer and a free layer of the second magnetic tunnel junction of the first double magnetic tunnel junction in sequence on the third metal layer; forming a first metal layer on the free layer of the second magnetic tunnel junction of the first double magnetic tunnel junction; forming a free layer, a non-magnetic tunneling layer and a fixed layer of a first magnetic tunnel junction of the first double magnetic tunnel junction in sequence on the first metal layer; forming a second metal layer on the fixed layer of the first magnetic tunnel junction of the first double magnetic tunnel junction; The gate of the MOS transistor is connected to the word line, the source of the MOS transistor is connected to the source line, and the drain of the MOS transistor is connected to the seventh metal layer; When the MRAM storage cell is in a write state, the second metal layer, the word line, and the source line are respectively connected to a data write circuit, and a write current is formed between the second metal layer and the drain of the MOS transistor according to write data, penetrating the first double magnetic tunnel junction, the second double magnetic tunnel junction, and the third double magnetic tunnel junction, so that the data write circuit writes the write data into the MRAM storage cell through the write current, wherein the direction of the write current corresponds to the write data; When the MRAM memory cell is in a read state, the first metal layer, the fourth metal layer, and the sixth metal layer are respectively connected to a first input terminal of a data read circuit, and the second metal layer, the third metal layer, the fifth metal layer, and the seventh metal layer are respectively connected to a second input terminal of the data read circuit, so that the data read circuit reads data of the MRAM memory cell based on a magnetoresistance difference between a first magnetic tunnel junction and a second magnetic tunnel junction of each double magnetic tunnel junction, and the data of the MRAM memory cell is output through an output terminal of the data read circuit. The magnetoresistance difference between the first magnetic tunnel junction and the second magnetic tunnel junction includes a positive magnetoresistance difference and a negative magnetoresistance difference, wherein the positive magnetoresistance difference is formed because the magnetoresistance of the first magnetic tunnel junction is greater than that of the second magnetic tunnel junction, and the negative magnetoresistance difference is formed because the magnetoresistance of the first magnetic tunnel junction is less than that of the second magnetic tunnel junction.

21. A differential MRAM storage cell, characterized in that: The MRAM memory cell is manufactured according to the manufacturing method according to any one of claims 19 to 20.

22. A chip, characterized in that: The MRAM memory cell comprises the MRAM memory cell according to any one of claims 1 to 10.

23. A chip, characterized in that: The MRAM memory cell according to claim 21 is included.

24. A chip, characterized in that: The MRAM memory comprises the MRAM memory according to any one of claims 12 to 18.

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