Nitride device capable of selectively growing P-GaN cap layer and manufacturing method thereof

Abstract

The invention discloses a nitride device capable of selectively growing a P-GaN cap layer and a manufacturing method thereof.The device comprises an epitaxial layer, a source electrode, a first dielectric layer, a P-GaN layer, a first dielectric layer and a drain electrode are sequentially arranged on the epitaxial layer, a second dielectric layer is arranged on part of the upper surface of the first dielectric layer, and the P-GaN layer is arranged on the second dielectric layer. A P-GaN layer is arranged on the upper surface of the remaining part of the first dielectric layer, and a gate cap metal layer is arranged on the upper surface of the P-GaN layer. The selective secondary epitaxy P-GaN is adopted, so that the manufacturing cost of the device is reduced, the P-GaN in a non-gate region does not need to be etched, the AlGaN barrier layer cannot be damaged, the interface state density cannot be increased, and the dynamic performance of the device can be further improved.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor technology, and in particular relates to a nitride device capable of selectively growing a P-GaN cap layer and a manufacturing method thereof. Background Art

[0002] In the early days, due to the lack of corresponding homogeneous epitaxial substrates, GaN films were mainly grown on sapphire substrates using MOCVD technology. However, the poor thermal conductivity of sapphire makes it difficult for GaN devices to adapt to the reliability requirements of high voltage and high current of power electronic devices. Currently, SiC-based GaN and GaN grown on GaN self-supporting substrates are widely used, but they are expensive. Therefore, the research of large-size, low-manufacturing-cost Si-based GaN devices is the development trend of GaN power electronic devices. Si-based aluminum gallium nitride / gallium nitride high electron mobility transistors are the structures commonly used in Si-based GaN power electronic devices in the world. They are lateral devices, different from the vertical structure used in Si power electronic devices.

[0003] The depletion-mode AlGaN / GaN high electron mobility transistor is a normally-on device. When no gate voltage is applied, the device is always on, which not only increases the cost, but also has a great impact on the reliability and performance of the device. Therefore, achieving enhancement mode is a core issue in the development of Si-based GaN power electronic devices. In actual production practice, P-channel GaN is difficult to prepare and the surface state density of AlGaN is high, so it is difficult to borrow the MOS device technology of Si process. At present, there are four main methods to achieve enhancement mode: gate trench etching technology, F ion implantation technology, P-GaN cap layer technology, enhancement Si-MOSFET and GaN-HEMT cascade structure. The P-GaN cap layer technology process is relatively simple and easy to implement, so it is widely used. It has great application prospects both in the field of discrete GaN devices and in the field of fully integrated GaN power devices. The earliest P-GaN AlGaN / GaN HEMT device was a 600 V normally-off device developed by Panasonic for power electronic devices (Y. Uemoto et al. IEEE Transactions on Electron Device, vol. 54, no. 12, pp. 3393-3399, 2007, doi). After that, researchers conducted related research on improving the breakdown voltage, reducing the on-resistance and enhancing the gate reliability.

[0004] In terms of breakdown voltage, according to the current public reports, L. Heuken et al. (L. Heuken, IEEE Transactions on Electron Devices, 2020, 67(3): 1113-1116) reported that the device has a vertical breakdown voltage greater than 1.2 kV and a lifespan greater than 50 years. In terms of power quality factor, YH Wu et al. (YH Wu, IEEE Transactions on Electron Devices, 2021, 68(9): 4543-4549) reported that the GaN HEMT has a high reverse turn-off voltage of 2 kV and a power factor of 397 MW / cm 2 Power quality factor; currently published reports show that among P-GaN gate GaN HEMTs with a breakdown voltage of 600 V, the best performing device has an off-state leakage of 10 nA / mm at zero volt gate bias and an on-resistance of about 13 Ω*mm (K. Tanaka, Japanese Journal of Applied Physics, vol. 52, no. 4s, 2013); HX Jiang et al. (HX Jiang, IEEE Transactions on Electron Devices, 2021, 68 (2): 653-657) reported a P-GaN gate GaN HEMT with a breakdown voltage of 1344 V and a grounded substrate drain current density of 1 μA / mm; X. Wei (X. Wei, Proceedings of the 5 th Electron Devices Technology&Manufacturing conference, Chengdu, China, 2021, 1-3) reported a P-GaN gate GaN HEMT with a maximum drain current density of 120.41 mA / mm and an on-resistance of 11.91 Ω*mm. When the drain length of the device is increased to 10 μm, its maximum drain current density can reach 160 mA / mm.

[0005] P-GaN cap layer GaN HEMT is not only continuously improving in device performance, but also in device preparation process. In the application of GaN power electronic devices, a threshold voltage higher than 1 V can ensure its safe operation, and the threshold voltage of P-GaN gate transistor is basically adjusted by P-GaN doping concentration and AlGaN barrier thickness. Since both threshold voltage and on-resistance change with the 2DEG concentration of the heterojunction of P-GaN and AlGaN barrier layer, a compromise needs to be considered during the research process. Based on this consideration, current researchers have mainly developed three technical solutions for P-GaN HEMT: IMEC and other companies mainly use MOCVD to grow the epitaxial structure of the entire device in one step, and then etch the P-GaN in the non-gate area through controllable dry etching to restore the 2DEG under the AlGaN. This method is called "primary epitaxy"; "secondary epitaxy" is to first grow the epitaxial material to the AlGaN barrier layer, then etch a part of the barrier layer in the gate area, and then put it into MOCVD for full-wafer secondary epitaxial growth of P-GaN; another method is the hydrogen ion passivation method developed by the Suzhou Institute of Nano-Tech and Nano-Bionics of the Chinese Academy of Sciences, which injects H ions into the P-GaN in the non-gate area to form a chemical bond between Mg and H, thereby making the P-GaN in the non-gate area invalid to restore the 2DEG layer in the non-gate area and achieve device conduction.

[0006] In the one-step epitaxial scheme, the AlGaN layer in the gate region and the non-gate region has the same thickness and Al composition. In general, in order to obtain a higher threshold voltage, the AlGaN barrier layer should be thin and have a low Al composition, but the 2DEG concentration in the barrier layer that meets this requirement is low. Since the barrier layer thickness and Al composition in the gate region and the non-gate region are the same, the lower 2DEG concentration in the non-gate region will increase the on-resistivity of the device, and the thinner AlGaN barrier layer in the non-gate region will cause the 2DEG to be easily affected by surface states, interface states, and Mg diffusion in P-GaN. In actual research, a compromise needs to be considered between reducing the on-resistivity and increasing the threshold voltage, and it is difficult to improve the overall performance.

[0007] The secondary epitaxial solution uses a thicker AlGaN barrier layer, and then thins the gate region to a certain thickness in the subsequent process, so that the threshold voltage can be increased and the on-resistance can be reduced at the same time. Although the secondary epitaxy method plays a great role in improving device performance, this method also has certain problems. When using the secondary epitaxy method to prepare P-GaN, it is generally adopted to use the method of full-chip epitaxy GaN and then use ICP to etch away the P-GaN in the non-gate area, and finally retain the P-GaN layer in the gate area, but this will cause etching damage to the AlGaN barrier layer in the non-gate area, thereby increasing the surface state density of the barrier layer. This increase in surface state density will greatly affect the reliability of the device gate. Not only that, the etching damage of the barrier layer will also cause a decrease in the 2DEG concentration, and the dynamic conduction characteristics of the GaN HEMT will be affected. The etching damage seriously affects the life and performance of the device. In addition, after etching part of the AlGaN layer, the full-chip MOCVD secondary epitaxy is performed, and finally the GaN in the non-gate area is etched. This preparation process increases the cost of device preparation.

[0008] The H ion implantation scheme is to passivate the Mg doped in P-GaN by injecting H ions, so that the 2DEG in the non-gate area is restored to a conductive channel. The problem with this method is that the H ion implantation process is immature, and the injection direction and depth of the H ions cannot be accurately controlled during the injection process, which will increase the cost of device preparation and is not conducive to the large-scale application of the device. Moreover, H ions are unstable after being implanted into P-GaN, so the injected H ions may cause reliability problems in the device, bringing challenges to the engineering application of the device.

[0009] In summary, these three technical solutions all have shortcomings, so a new method for obtaining P-GaN is needed to solve the problems caused by the above three methods. Summary of the invention

[0010] Technical problem solved: In response to the above technical problem, the present invention provides a nitride device capable of selectively growing a P-GaN cap layer and a method for manufacturing the same, which can effectively solve the shortcomings of the above method, such as high cost, etching damage and instability.

[0011] Technical solution: In the first aspect, the present invention provides a nitride device capable of selectively growing a P-GaN cap layer, comprising an epitaxial layer, on which a source electrode, a second dielectric layer and a drain electrode are arranged from left to right, and a first P-GaN layer, a second P-GaN layer and a gate cap metal layer are arranged from bottom to top between the middle of the second dielectric layer and the epitaxial layer.

[0012] Preferably, the epitaxial layer includes, from bottom to top, a substrate, a GaN buffer layer and an AlGaN barrier layer.

[0013] Preferably, the first dielectric layer material is SiN or SiO 2 , with a thickness of 50 nm-100 nm; the material of the second dielectric layer is SiN or SiO 2 , thickness is 50 nm-100 nm.

[0014] Preferably, the thickness of the first P-GaN layer is 30 nm-50 nm, and the thickness of the second P-GaN layer is 50 nm-100 nm.

[0015] Preferably, the gate cap metal layer is made of Pd or W, and has a thickness of 70 nm-100 nm.

[0016] In a second aspect, the present invention provides a method for manufacturing a nitride device capable of selectively growing a P-GaN cap layer according to the first aspect, comprising the following steps: S1, depositing a first P-GaN layer on the AlGaN barrier layer of the epitaxial layer by MOCVD; S2, growing a first dielectric layer on the first P-GaN layer by LPCVD, coating a photoresist layer on the first dielectric layer, and defining a window in the gate electrode region of the device by photolithography; S3, using the photoresist layer as a mask to remove the first dielectric layer of the window, and then removing the photoresist layer to obtain a window from the first dielectric layer to the surface of the first P-GaN layer, that is, a gate region window; S4, growing a second P-GaN layer and a gate cap metal layer in sequence from bottom to top in the gate region window on the first P-GaN layer by regional epitaxy, and then removing the first P-GaN layer and the first dielectric layer outside the gate region by dry etching; S5, depositing a second dielectric layer on the upper surface of the gate cap metal layer and the AlGaN barrier layer; S6, coating a photoresist layer on the second dielectric layer, and defining two windows on the photoresist layer in the source electrode region and the drain electrode region of the device by photolithography; S7, using the photoresist layer as a mask to remove the second dielectric layer in the source electrode region and the drain electrode region of the device, and then removing the photoresist layer to obtain a source window and a drain window; S8. Deposit metal layers as source and drain electrodes of the device on the AlGaN barrier layers in the two window regions respectively, and make the source and drain electrodes form ohmic contacts with the AlGaN barrier layers through a low-temperature source-drain ohmic contact process. Finally, a target device is obtained by using a multi-metal system.

[0017] Preferably, the etching and removal method of the first dielectric layer and the second dielectric layer is a reactive ion etching method, and the etching is performed in a fluorine-based atmosphere.

[0018] Preferably, a selective epitaxial method is used for the secondary epitaxial growth of the P-GaN layer, and the twice epitaxial growth method can effectively avoid the influence of dry etching on the non-gate region.

[0019] Beneficial effects: The present invention adopts a method of selective secondary epitaxial P-GaN, which not only improves the shortcomings of the primary and secondary epitaxial schemes and the H ion implantation scheme, but also absorbs the advantages of the secondary epitaxial scheme; and after the secondary epitaxial P-GaN, the P-GaN in the non-gate area is not etched, and the AlGaN barrier layer in the non-gate area is not damaged; the selective secondary epitaxial P-GaN not only reduces the device manufacturing cost, but also does not need to etch the P-GaN in the non-gate area, which will not damage the AlGaN barrier layer and increase the interface state density, and can further improve the dynamic performance of the device; in addition, the two-step epitaxial P-GaN method can effectively avoid the etching influence of the first dry etching on the barrier layer in the non-gate area. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is a schematic diagram of the general structure of the epitaxial material used in GaN HEMT; Figure 2-Figure 10 It is a schematic diagram of the steps of preparing a nitride device capable of selectively growing a P-GaN cap layer by using the manufacturing method of the present invention; Serial numbers in the figure: 11, substrate, 12, GaN buffer layer, 13, AlGaN barrier layer, 14, first P-GaN layer, 15, first dielectric layer, 16, photoresist layer, 17, second P-GaN layer, 18, gate cap metal layer, 19, second dielectric layer, 20, source electrode, 21, drain electrode. DETAILED DESCRIPTION

[0021] The present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments: Example 1

[0022] like Figure 1 , which is a schematic diagram of the general structure of epitaxial materials used in GaN HEMT, includes, from bottom to top, a substrate 11, a GaN buffer layer 12, and an AlGaN barrier layer 13. For the materials used for the substrate 11, the formation of the GaN buffer layer 12 and the AlGaN barrier layer 13 in the GaN HEMT, reference may be made to relevant literature reports.

[0023] like Figure 2 As shown, a high-quality first P-GaN layer 14 is grown on the AlGaN barrier layer 13 by MOCVD. The first P-GaN layer 14 is mainly used to protect the barrier layer in the non-gate region from being affected by etching. The thickness of the first dielectric layer 14 is 30 nm, and the material is P-type GaN.

[0024] like Figure 3 As shown, a high-quality first dielectric layer 15 is deposited on the first P-GaN layer 14 by using LPCVD.

[0025] like Figure 4 As shown, a photoresist layer 16 is coated on the upper surface of the first dielectric layer 15, and the photoresist layer 16 is used as a mask. After photolithography, development and other steps, a gate area window is formed in the first dielectric layer 15 and the photoresist layer 16 in the gate electrode area. The width of the window is determined according to the gate size of the device to be developed.

[0026] like Figure 5 As shown, the first dielectric layer 15 in the gate window is removed by reactive plasma etching in a F-based atmosphere, and then the photoresist on the first dielectric layer 15 is removed, so that a gate window is obtained on the first dielectric layer 15. Reactive plasma etching of SiN in a F-based atmosphere can bring about better verticality. After etching, the surface is thermally annealed and wet BTB (BOE solution, tetramethylammonium hydroxide solution and BOE solution, respectively) surface cleaned. After this treatment, the etching damage and etching residue problems caused by F ions can be effectively reduced.

[0027] like Figure 6 As shown, secondary epitaxy is performed on the first P-GaN layer 14 in the gate window, and a second P-GaN layer 17 is selectively epitaxially grown in the gate region, and then the remaining photoresist layer 16 is removed. This step is no longer epitaxial on the entire wafer, and there is no need to perform ICP etching to etch away the GaN in the non-gate region. Therefore, the AlGaN barrier layer 13 does not need to deal with the interface state density problem and etching residue problem caused by etching. The thickness of the epitaxial P-GaN layer 17 is 80 nm, and the Mg doping concentration is 2.5×10 19 / cm 3 After opening the dielectric layer in the gate region, the wafer was patterned using photolithography and then loaded into an ion implanter for N ion implantation to isolate the active region and greatly reduce the lateral leakage of the device in the off state. The implantation dose was 1.8×10 14 / cm 2The N ions can make the GaN channel form a high resistance state. Ion implantation is a common process for active area isolation. It is to inject an ion beam into the material so that a series of physical and chemical interactions occur between the ion beam and the atoms or molecules in the material. The incident ions gradually lose energy until they stay in the material and cause changes in the material composition, structure and performance. The ion implantation cannot penetrate the area protected by the photoresist. Therefore, N ion implantation is performed after photolithography patterning, and the photoresist is removed after ion implantation. After the N ion implantation isolates the active area, the gate cap metal layer 18 is deposited on the second P-GaN layer 17 using an electron beam evaporation device. The gate cap metal layer 18 can be a metal such as Pd, W, etc. The metal type determines its work function. The larger the work function, the higher the barrier height of the Schottky junction formed by the gate metal / P-GaN. The Schottky barrier height has a greater impact on the leakage under the gate forward bias. After the gate metal is deposited, the gate metal and P-GaN interface are thermally annealed to reduce the surface state density. In this embodiment, the metal of the gate cap metal layer 18 is Pd, and the thickness thereof is 200 nm, which is beneficial for obtaining a better gate control capacitance while prolonging the gate life.

[0028] like Figure 7 As shown, the first dielectric layer 15 in the non-gate region and the redundant first P-GaN layer 14 are removed by wet processing.

[0029] like Figure 8 As shown, a high-quality second dielectric layer 19 (SiN) is deposited on the first P-GaN layer 17, and the wafer is loaded into LPCVD for dielectric deposition. The SiN dielectric deposition thickness is 90 nm. The second dielectric layer 19 plays a protective and passivation role. Suitable surface passivation can effectively suppress the surface states on the surface of the barrier layer. The SiN dielectric layer will suppress the current collapse effect caused by the surface states.

[0030] like Fig. 9 As shown, a photoresist layer 16 is coated on the second dielectric layer 19, and windows are formed on the source electrode 20 and the drain electrode 21 regions on the AlGaN barrier layer 13 through steps such as photolithography and development, and the dielectric material is removed in turn by reactive plasma. The sizes of the source window and the drain window are determined according to the sizes of the source and drain of the device being developed.

[0031] like Fig.10As shown, the ohmic contact in the source electrode 20 and the drain electrode 21 region is prepared. In this embodiment, the source electrode 20 and the drain electrode 21 region use a Ti / Al / Ti / Au multi-metal system, and the ohmic contact is prepared under a low-temperature ohmic contact process. Because high-temperature ohmic contact will cause the gate metal to undergo secondary annealing at high temperature, which will increase the forward leakage of the gate and seriously affect the reliability of the gate, this embodiment uses a low-temperature ohmic contact process to prepare the ohmic contact in the source and drain electrode regions, which effectively avoids the impact of high-temperature ohmic contact. The metal thickness of the source and drain electrode regions is 2 μm. When the source and drain electrodes are metal-thickened, a field plate structure and an external pin connection are simultaneously generated. The wafer with the thickened source and drain electrode metal is surface-planarized using a dielectric or insulating material, and then a window is opened on the pin connection plate, and the device is connected to the external package to obtain a complete AlGaN / GaNHEMT device with a Schottky gate structure of a selective secondary epitaxial P-GaN layer.

[0032] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A nitride device capable of selectively growing a P-GaN cap layer, characterized in that: It comprises an epitaxial layer, on which a source electrode (20), a second dielectric layer (19) and a drain electrode (21) are arranged in sequence from left to right, and between the middle of the second dielectric layer (19) and the epitaxial layer, a first P-GaN layer (14), a second P-GaN layer (17) and a gate cap metal layer (18) are arranged in sequence from bottom to top.

2. A nitride device capable of selectively growing a P-GaN cap layer according to claim 1, characterized in that: The epitaxial layer comprises, from bottom to top, a substrate (11), a GaN buffer layer (12) and an AlGaN barrier layer (13).

3. A nitride device capable of selectively growing a P-GaN cap layer according to claim 1, characterized in that: The material of the first dielectric layer (15) is SiN or SiO2, and the thickness is 50 nm-100 nm; the material of the second dielectric layer (19) is SiN or SiO2, and the thickness is 50 nm-100 nm.

4. The nitride device capable of selectively growing a P-GaN cap layer according to claim 1, characterized in that: The thickness of the first P-GaN layer (14) is 30 nm-50 nm, and the thickness of the second P-GaN layer (17) is 50 nm-100 nm.

5. The nitride device capable of selectively growing a P-GaN cap layer according to claim 1, characterized in that: The gate cap metal layer (18) is made of Pd or W and has a thickness of 70 nm-100 nm.

6. A method for manufacturing a nitride device capable of selectively growing a P-GaN cap layer according to any one of claims 1 to 5, characterized in that: The following steps are involved: S1, depositing a first P-GaN layer (14) on the AlGaN barrier layer (13) of the epitaxial layer by using MOCVD; S2, growing a first dielectric layer (15) on the first P-GaN layer (14) by using LPCVD, coating a photoresist layer (16) on the first dielectric layer (15), and defining a window in the gate electrode region of the device by using a photolithography method; S3, using the photoresist layer (16) as a mask to remove the first dielectric layer (15) of the window, and then removing the photoresist layer (16) to obtain a window from the first dielectric layer (15) to the surface of the first P-GaN layer (14), that is, a gate region window; S4, in the gate region window on the first P-GaN layer (14), sequentially growing a second P-GaN layer (17) and a gate cap metal layer (18) from bottom to top by regional epitaxy, and then removing the first P-GaN layer (14) and the first dielectric layer (15) outside the gate region by dry etching; S5, depositing a second dielectric layer (19) on the upper surfaces of the gate cap metal layer (18) and the AlGaN barrier layer (13); S6, coating a photoresist layer (16) on the second dielectric layer (19), and defining two windows on the photoresist layer (16) in the source electrode region and the drain electrode region of the device by photolithography; S7, using the photoresist layer (16) as a mask to remove the second dielectric layer (19) in the source electrode region and the drain electrode region of the device, and then removing the photoresist layer (16) to obtain a source window and a drain window; S8. Depositing metal layers as a device source electrode (20) and a drain electrode (21) on the AlGaN barrier layer (13) in the two window regions respectively, and forming an ohmic contact between the source electrode (20) and the drain electrode (21) and the AlGaN barrier layer (13) through a low-temperature source-drain ohmic contact process, and finally obtaining a target device by using a multi-metal system.

7. The manufacturing method according to claim 6, characterized in that: The etching removal method of the first dielectric layer (15) and the second dielectric layer (19) is a reactive ion etching method, and the etching is performed in a fluorine-based atmosphere.

8. The manufacturing method according to claim 6, characterized in that: The selective epitaxial growth method is used for the secondary epitaxial growth of the P-GaN layer, and the twice epitaxial growth method can effectively avoid the influence of dry etching on the non-gate area.

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