Power semiconductor device, power semiconductor module, power converter including same, and method of manufacturing same

Abstract

The invention relates to a power semiconductor device, a power semiconductor module, a power converter including the same and a manufacturing method thereof. The power semiconductor device includes: a substrate; a first conductive type epitaxial layer disposed on the substrate; a second conductive type well partially disposed on the first conductive type epitaxial layer; a second conductive type ion implantation region partially disposed in the second conductive type well; a source region partially disposed in the second conductive type well and disposed on the second conductive type ion implantation region; a gate insulating layer disposed on the source region and the second conductive type well; a gate electrode disposed on the gate insulating layer; an interlayer insulating layer disposed on the gate electrode; and a source electrode disposed on the source electrode region. The gate insulating layer may include a channel gate insulating layer having a first thickness and a protruding gate insulating layer having a second thickness thicker than the first thickness. The concentration in the Rb region, which is a lateral resistor of the second conductivity type ion implantation region, may be higher than the concentration of the second conductivity type well.

Description

Technical Field

[0001] The present disclosure relates to a power semiconductor device, a power semiconductor module, a power converter and a method for manufacturing the same. Background Art

[0002] Power semiconductors are one of the key factors in determining the efficiency, speed, durability and reliability of power electronic systems.

[0003] With recent developments in the power electronics industry, as previously used silicon (Si) power semiconductors have reached their physical limits, research on WBG (wide bandgap) power semiconductors such as silicon carbide (SiC) and gallium nitride (GaN) to replace Si power semiconductors is being actively conducted.

[0004] The band gap energy of WBG power semiconductor devices is approximately 3 times that of Si power semiconductor devices, resulting in low intrinsic carrier concentration, high dielectric breakdown field (approximately 4 to 20 times), high thermal conductivity (approximately 3 to 13 times), and large electron saturation velocity (approximately 2 to 2.5 times).

[0005] Due to these characteristics, WBG power semiconductor devices can operate in high temperature, high voltage environments and have high switching speeds and low switching losses. Among them, gallium nitride (GaN) power semiconductor devices can be used in low voltage systems, and silicon carbide (SiC) power semiconductor devices can be used in high voltage systems.

[0006] According to the structure, the SiC MOSFET of the related art can be classified as a trench structure MOSFET, a vertical double injection structure MOSFET (DIMOSFET) or a lateral diffusion structure MOSFET, etc. DIMOSFET is also called a planar MOSFET or a VDMOSFET.

[0007] On the other hand, the power MOSFET needs to have low conduction loss and low switching loss characteristics. In addition, the power MOSFET needs to be stable enough to prevent parasitic bipolar devices from operating under high current conditions such as unclamped inductive switching (UIS) conditions.

[0008] Power MOSFET devices tend to lose stability under UIS conditions because the parasitic NPN bipolar device operates in the presence of high inductive currents in the device. This results in a temperature rise and voltage drop in the internal base resistor (Rb), which can cause severe damage.

[0009] In addition, when UIS occurs, instantaneous voltage and current spikes occur inside the device, which may cause destruction of the power semiconductor device.

[0010] Therefore, UIS is one of the important issues to be considered when designing and manufacturing power semiconductor devices.

[0011] In the internal MOSFET technology, a stepped gate insulating layer has been studied to improve the switching loss characteristics. The stepped gate insulating layer structure is a structure in which a thick insulating layer is provided in a region other than the P well where a channel can be formed, and through this structure, the switching loss characteristics can be improved by reducing the oxide capacitance Cgd formed between the gate and the drain.

[0012] However, in a DIMOSFET provided with a stepped gate insulating layer of an internal technology, there is a problem that the amount of di / dt variation increases and UIS characteristics deteriorate.

[0013] That is, there is a technical contradiction problem in that when the internal technology adopts a stepped insulating layer structure to improve the switching loss characteristics, instantaneous voltage and current spikes occur as the UIS characteristics of the power MOSFET device deteriorate, thereby causing damage to the power semiconductor device.

[0014] The above information disclosed in this Background section is only for enhancement of understanding of the background of the described technology and therefore it may contain information that does not form the prior art that is already known to a person of ordinary skill in the art. Summary of the invention

[0015] Accordingly, the present disclosure is directed to a power semiconductor device, a power semiconductor module, a power converter, and a method of manufacturing the same that substantially obviate one or more problems due to the above limitations and disadvantages.

[0016] Additional features and advantages of the present disclosure will be set forth in the following description, and in part will be apparent from the description, or may be learned by practicing the present disclosure. Other advantages of the present disclosure will be realized and obtained through the structures particularly pointed out in its written description and claims and the accompanying drawings.

[0017] More specifically, the present disclosure aims to provide a power semiconductor device and a power converter including the power semiconductor device, which can solve the technical contradiction that when the internal technology adopts a stepped insulation layer structure to improve the switching loss characteristics, instantaneous voltage and current spikes appear as the UIS characteristics of the power MOSFET device deteriorate, thereby causing damage to the power semiconductor device.

[0018] The present disclosure is not limited to those described in this section, but includes those that can be understood through the description of the present disclosure.

[0019] To achieve the above and other advantages, and in accordance with the present disclosure, as implemented and broadly described, a power semiconductor device includes: a substrate; a first conductive type epitaxial layer, which is arranged on the substrate; a second conductive type well, which is partially arranged on the first conductive type epitaxial layer; a second conductive type ion injection region, which is partially arranged in the second conductive type well; a source region, which is partially arranged in the second conductive type well and on the second conductive type ion injection region; a gate insulating layer, which is arranged on the source region and the second conductive type well; a gate, which is arranged on the gate insulating layer, an interlayer insulating layer, which is arranged on the gate; and a source, which is arranged on the source region.

[0020] The gate insulating layer may include a channel gate insulating layer having a first thickness and a protruding gate insulating layer having a second thickness thicker than the first thickness.

[0021] The concentration in the Rb region, which is a lateral resistance of the second conductive type ion implantation region, may be higher than that of the second conductive type well.

[0022] The concentration in the Rb region, which is a lateral resistance of the second conductive type ion implantation region, may be 90 to 100 times higher than the concentration of the second conductive type well.

[0023] The source may include a protruding source contact electrode disposed in the recessed region of the second conductive type ion implantation region and in the source region.

[0024] The protruding source contact electrode may be in contact with an upper surface of the source region and a side surface of the source region.

[0025] The power converter according to this aspect may include at least one of the power semiconductor devices as above.

[0026] In another aspect of the present disclosure, a method for manufacturing a power semiconductor device includes the following steps: preparing a substrate including a first conductive type epitaxial layer; forming a first hard mask pattern on the first conductive type epitaxial layer, and forming a second conductive type well; forming a second hard mask pattern on the side wall of the first hard mask pattern; forming a first conductive type source region by injecting ions into the second conductive type well using the first hard mask pattern and the second hard mask pattern as ion implantation masks; forming a third hard mask pattern on the first hard mask pattern and the second hard mask pattern; using the first hard mask pattern, the second hard mask pattern and the third hard mask pattern as self-aligned ion implantation masks to form a second conductive type ion implantation region in the second conductive type well; removing the first hard mask pattern, the second hard mask pattern and the third hard mask pattern; and forming a gate insulating layer, a gate and an interlayer insulating layer in sequence on the source region and the second conductive type well.

[0027] In another aspect of the present disclosure, a power semiconductor device includes: a first conductive type epitaxial layer, which is arranged on a substrate; a second conductive type well, which is arranged on the first conductive type epitaxial layer; a second conductive type ion injection region, which is arranged in the second conductive type well; a source region, which is arranged on the second conductive type ion injection region in the second conductive type well; a recessed portion, which is arranged between two adjacent source regions located between a first gate and a second gate and reaches an upper portion of the second conductive type ion injection region; and a source, which is filled in the recessed portion to contact the second conductive type ion injection region, wherein the second conductive type ion injection region has a lateral length in a cross-sectional view that is at least the same as the total length of the two adjacent source regions and the recessed portion.

[0028] The step of forming the second conductive type ion implantation region may perform ion implantation in a self-aligned manner using the first hard mask pattern, the second hard mask pattern and the third hard mask pattern as ion implantation masks, and form a first conductive type source region in the second conductive type well through the second conductive type ion implantation region.

[0029] The second conductive type ion implantation region may be arranged to surround a region below the source region.

[0030] The concentration in the Rb region, which is a lateral resistance of the second conductive type ion implantation region, may be higher than that of the second conductive type well.

[0031] The concentration in the Rb region, which is a lateral resistance of the second conductive type ion implantation region, may be 90 to 100 times higher than the concentration of the second conductive type well.

[0032] The gate insulating layer may include a channel gate insulating layer having a first thickness and a protruding gate insulating layer having a second thickness thicker than the first thickness.

[0033] Furthermore, the method for manufacturing a power semiconductor device according to this aspect may include the step of forming a source on the source region after patterning a layer disposed on an upper side of the source region.

[0034] The source region may include a protruding source contact electrode disposed in the recessed region of the second conductive type ion implantation region and in the source region.

[0035] The protruding source contact electrode may be in contact with an upper surface of the source region and a side surface of the source region.

[0036] The technical effects of the power semiconductor and the power converter including the power semiconductor according to this aspect may include any one of the following.

[0037] According to this aspect of the present disclosure, the following technical effects are achieved: a power semiconductor device and a power converter including the power semiconductor device are provided, which can resolve the following technical contradictions: when the internal technology adopts a stepped insulating layer structure to improve the switching loss characteristics, instantaneous voltage and current spikes appear as the UIS characteristics of the power MOSFET device deteriorate, thereby causing damage to the power semiconductor device.

[0038] For example, the gate insulating layer may include a channel gate insulating layer and a protruding gate insulating layer, so that a thick protruding gate insulating layer may be provided in a region other than the P-well where a channel may be formed. Therefore, the switching loss characteristics of the device may be improved by reducing the value of the Miller capacitance (Cgd) associated with the switching speed by reducing the oxide capacitance (Cgd) formed between the gate and the drain.

[0039] At the same time, according to this aspect, the alignment accuracy of arranging the second conductive type ion implantation region below the source region can be significantly improved. Therefore, by reducing the Rb resistance, there is a special technical effect that can solve the technical contradiction of UIS characteristic degradation.

[0040] For example, in this aspect, after a certain thickness of a CVD (Chemical Vapor Deposition) film is deposited in a self-aligned structure of the source region, ion implantation into the second conductive type ion implantation region may be performed by self-alignment.

[0041] For example, in this aspect, the second conductive type ion implantation region can be formed under the source region by a self-aligned method rather than an optical method by strongly implanting ions after depositing an insulating layer having a certain thickness. Thus, the second conductive type ion implantation region can be formed thinly surrounding the source region while ensuring the thickness of the second conductive type well as the P-body to withstand the internal pressure.

[0042] Therefore, this aspect can be controlled so that the second conductive type ion implantation region can accurately surround the area below the source region compared to related optical alignment methods, and the Rb (i.e., internal base resistance) associated with the operation of the parasitic NPN BJT (i.e., bipolar junction transistor) can be significantly reduced.

[0043] For example, in the internal technology, the concentration of the Rb region is similar to that of the second conductivity type well as the second conductivity type body. However, according to this aspect, the concentration of the Rb region can be similar to that of the second conductivity type ion implantation region. Therefore, this aspect has the following special technical effects, by having a higher concentration than the related art and significantly reducing the Rb resistance to suppress the operation of the parasitic NPN BJT, thereby improving the UIS characteristic degradation.

[0044] For example, according to this aspect, the Rb resistance can be drastically reduced by having a concentration similar to that of the second conductive type ion implantation region and having a concentration 10 times higher than that of the related art.

[0045] In addition, according to this aspect, the Rb resistance can be drastically reduced by having a concentration similar to that of the second conductive type ion implantation region and 30 times higher than that of the related art.

[0046] In addition, according to this aspect, the Rb resistance can be drastically reduced by having a concentration similar to that of the second conductive type ion implantation region and 50 times higher than that of the related art.

[0047] For example, according to this aspect, by having a concentration similar to that of the second conductive type ion implantation region, the concentration of the Rb region can be 90 to 100 times higher than that of the related art, thereby significantly reducing the Rb resistance. Therefore, there is a special technical effect that can improve the degradation of UIS characteristics by suppressing the operation of the parasitic NPN BJT.

[0048] In addition, in the internal technology, a self-aligned structure only for the source region is possible, but in this respect, ion implantation is possible up to the second conductive type ion implantation region in a self-aligned manner. Therefore, the degree of freedom of contact alignment of subsequent processes can be increased, which has the technical effect of significantly increasing the cell density and improving the Ron characteristics.

[0049] The source may include a protruding source contact electrode having a main contact shape disposed in a recessed region of the second conductive type ion implantation region and in the source region. The protruding source contact electrode may contact the top surface of the source region and the side surface of the source region, so that there is a composite technical effect of widening the contact area and improving the Ron characteristic.

[0050] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The accompanying drawings are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this disclosure and illustrate aspects of the disclosure and together with the description serve to explain the principles of the disclosure.

[0052] In the attached picture:

[0053] Figure 1 is an exemplary view of a power converter according to one aspect of the present disclosure;

[0054] Figure 2 is a cross-sectional view of a power semiconductor device according to one aspect of the present disclosure;

[0055] Figure 3A is a cross-sectional view of a power semiconductor device according to one aspect of the present disclosure;

[0056] Figure 3B yes Figure 3A A partial view of a cross-sectional view of a power semiconductor device is shown;

[0057] Figure 4 yes Figure 3B A detailed view of region D of the cross-sectional view of the power semiconductor device shown; and

[0058] FIG. 5A to FIG. 5H is a cross-sectional view of a manufacturing process of a power semiconductor device according to one aspect of the present disclosure. DETAILED DESCRIPTION

[0059] Hereinafter, a disclosure according to one aspect for solving the above-mentioned problems will be described in more detail with reference to the accompanying drawings.

[0060] The suffixes "module" and "unit" used for elements in the following description are given only in consideration of the ease of writing this specification, and do not give particularly important meanings or roles by themselves. Therefore, "module" and "unit" can be used interchangeably.

[0061] Terms including ordinal numbers such as first and second may be used to describe various elements, but the elements are not limited to these terms. These terms are used only for the purpose of distinguishing one element from another.

[0062] Unless the context clearly indicates otherwise, a singular expression includes a plural expression.

[0063] In the present application, terms such as “includes,” “has,” or “comprising” are intended to mean that features, quantities, steps, operations, components, parts, or a combination thereof are described in the specification without excluding one or other features, quantities, steps, operations, components, parts, or a combination thereof, or any combination thereof.

[0064] Figure 1 is an exemplary diagram of a power converter 1000 according to one aspect of the present disclosure.

[0065] The power converter 1000 may receive DC power from a battery or a fuel cell, convert it into AC power, and supply the AC power to a predetermined load. For example, the power converter 1000 according to this aspect of the present disclosure may include an inverter that receives DC power from a battery, converts the DC power into three-phase AC power, and supplies the three-phase AC power to the motor M. The motor M may provide power to an electric vehicle or a fuel cell vehicle.

[0066] The power converter 1000 according to this aspect of the present disclosure may include a plurality of power semiconductor devices. The power semiconductor devices may be metal oxide semiconductor field effect transistors (MOSFETs), but are not limited thereto, and may include insulated gate bipolar transistors (IGBTs).

[0067] For example, the power converter 1000 may include a plurality of power semiconductor devices 100a, 100b, 100c, 100d, 100e, and 100f, and may include a plurality of diodes (not shown). Each of the plurality of diodes may be internally incorporated into each of the power semiconductor devices 100a, 100b, 100c, 100d, 100e, and 100f in the form of an internal diode, but is not limited thereto, and may be provided separately.

[0068] In this aspect of the present disclosure, DC power may be converted into AC power through on-off control of the plurality of power semiconductor devices 100 a to 100 f .

[0069] For example, in the power converter 1000 , the first power semiconductor device 100 a may be turned on and the second power semiconductor device 100 b may be turned off in a first period of one cycle to supply positive polarity power to the motor M.

[0070] In a second period of one cycle, the first power semiconductor device 100 a may be turned off and the second power semiconductor device 100 b may be turned on to provide negative polarity power to the motor M.

[0071] In this regard, a group of power semiconductor devices arranged in series in the high voltage line and the low voltage line on the input side may be referred to as an arm.

[0072] For example, the first power semiconductor device 100a and the second power semiconductor device 100b may constitute the first arm 12a, and the third power semiconductor device 100c and the fourth power semiconductor device 100d may constitute the second arm 12b. The fifth power semiconductor device 100e and the sixth power semiconductor device 100f may constitute the third arm 12c.

[0073] In an arm, the upper power semiconductor device and the lower power semiconductor device may be controlled not to be turned on at the same time. For example, in a first arm, the first power semiconductor device 100a and the second power semiconductor device 100b may not be turned on at the same time but may be turned on and off alternately.

[0074] Each of the power semiconductor devices 100a to 100f can receive high power in the off state. For example, when the second power semiconductor device 100b is turned off during the on period of the first power semiconductor device 100a, the input voltage can be applied to the second power semiconductor device 100b in the original state. The voltage input to the second power semiconductor device 100b can be a relatively high voltage, and the withstand voltage of each power semiconductor device 100a to 100f can be designed to have a high level to withstand such a high voltage.

[0075] Each of the power semiconductor devices 100a to 100f can conduct a high current in an on state. The motor M can be driven with a relatively high current, and the high current can be supplied to the motor M through the turned-on power semiconductors.

[0076] The high voltage applied to each of the power semiconductor devices 100a to 100f may result in high switching losses. The high current conduction of the power semiconductor devices 100a to 100f may result in high conduction losses. In order to dissipate the heat generated by such switching losses or conduction losses, the power semiconductor devices 100a to 100f may be packaged as a power semiconductor module including a heat sink.

[0077] The power semiconductor device 100 of this aspect may be a silicon carbide (SiC) power semiconductor device, may operate in a high temperature, high voltage environment, and may have a high switching speed and low switching loss.

[0078] Furthermore, the power converter 1000 according to this aspect may include a plurality of power semiconductor modules.

[0079] For example, Figure 1 The plurality of power semiconductor devices 100 a to 100 f shown in FIG. 1 may be packaged into one power semiconductor module, or the power semiconductor devices constituting each arm may be packaged into one power semiconductor module.

[0080] For example, Figure 1 The illustrated first power semiconductor device 100 a , second power semiconductor device 100 b , third power semiconductor device 100 c , fourth power semiconductor device 100 d , fifth power semiconductor device 100 e , and sixth power semiconductor device 100 f may be packaged into one power semiconductor module.

[0081] In addition, there may be an additional power semiconductor device disposed in parallel with each of the power semiconductor devices 100a to 100f to increase current capacity. In this case, the number of power semiconductor devices included in the power semiconductor module may be greater than six.

[0082] The power converter 1000 according to this aspect may also include a diode-type power semiconductor device in addition to the transistor-type power semiconductor devices 100a to 100f. For example, a first diode (not shown) may be arranged in parallel with the first power semiconductor device 100a, and a second diode (not shown) may be arranged in parallel with the second power semiconductor device 100b. In addition, these diodes may be packaged together in a power semiconductor module. In addition, a diode may be arranged in each power semiconductor device in the form of an internal diode.

[0083] Next, the power semiconductor devices constituting each arm may be packaged into one power semiconductor module.

[0084] For example, the first power semiconductor device 100a and the second power semiconductor device 100b constituting the first arm may be packaged as a first power semiconductor module. The third power semiconductor device 100c and the fourth power semiconductor device 100d constituting the second arm may be packaged into the second power semiconductor module. And the fifth power semiconductor device 100e and the sixth power semiconductor device 100f constituting the third arm may be packaged into the third power semiconductor module.

[0085] In addition, there may be an additional power semiconductor device arranged in parallel with each power semiconductor device 100a to 100f to increase the current capacity. In this case, the number of power semiconductor devices included in each power semiconductor module may be more than two. In addition, each arm may include a diode-type power semiconductor device (not shown) in addition to the transistor-type power semiconductor devices 100a to 100f, and these diodes may also be packaged together in one power semiconductor module. In addition, a diode may be provided in each power semiconductor device in the form of an internal diode.

[0086] Next, Figure 2 yes Figure 1 A cross-sectional view of one of the power semiconductor devices shown.

[0087] The power semiconductor device 100 according to this aspect of the present disclosure may include a source 130 disposed above the semiconductor epitaxial layer 120 , a gate 175 , and a drain 105 disposed below the semiconductor epitaxial layer 120 .

[0088] In the form of MOSFET, the source 130 or the gate 175 may include an Al-based metal, and the drain 105 may include a Ti / Ni / Ag metal including a Ti layer, a Ni layer or an Ag layer, or NiV / Ag, V (vanadium) / Ni / Ag, etc., but is not limited thereto.

[0089] The present disclosure aims to provide a power semiconductor device and a power converter including the power semiconductor device, which can solve the technical contradiction that when the internal technology adopts a stepped insulation layer structure to improve the switching loss characteristics, instantaneous voltage and current spikes appear as the UIS (i.e., unclamped inductive switching) characteristics of the power MOSFET device deteriorate, thereby causing damage to the power semiconductor device.

[0090] First, a power semiconductor device according to internal technology will be described.

[0091] In order to improve the switching loss characteristics in the internal MOSFET technology, a study has been conducted in which a stepped gate insulating layer may include a thick insulating layer in a region other than the P well where a channel may be formed. The stepped gate insulating layer may improve the switching loss characteristics by reducing the oxide capacitance Cgd formed between the gate and the drain.

[0092] However, in a DIMOSFET having a stepped gate insulating layer of an internal technology, there is a problem in that the amount of variation in di / dt increases and UIS characteristics deteriorate, resulting in instantaneous voltage and current spikes that cause destruction of the power semiconductor device.

[0093] Specifically, in a DIMOSFET provided with a stepped gate insulating layer, a P-type region may be formed based on a photo process under an N+ contact region serving as a source region.

[0094] However, due to the difficulty in aligning a P-type region directly below an N+ contact region, the problem of increased Rb resistance associated with the operation of a parasitic NPN BJT has been studied. The Rb resistance refers to the lateral resistance of a P-type region of opposite polarity directly below an N+ contact region.

[0095] Therefore, in the DIMOSFET internal technology with a stepped gate insulating layer, the di / dt variation increases due to the problem of increased Rb resistance, and the UIS characteristics deteriorate, resulting in instantaneous voltage and current spikes. Therefore, there is a technical problem that causes the destruction of the power semiconductor device.

[0096] Hereinafter, a power semiconductor device 100 according to one aspect for solving the above-mentioned technical problems will be described.

[0097] Figure 3A is a cross-sectional view of a power semiconductor device 100 according to one aspect of the present disclosure, and Figure 3B yes Figure 3A A partial view of a cross-sectional view of a power semiconductor device 100 is shown.

[0098] First refer to Figure 3AThe power semiconductor device 100 according to this aspect of the present disclosure may include a drain 110, a substrate 111, a first conductive type epitaxial layer 112, a second conductive type well 113, a second conductive type epitaxial layer 112, a conductive ion implantation region 114, a first conductive type source region 115, a gate insulating layer 136, a gate 134, an interlayer insulating layer 132 and at least one of a source 130.

[0099] The first conductivity type may be an N type, and the second conductivity type may be a P type, but are not limited thereto. The substrate 111 and the first conductivity type epitaxial layer 112 may include silicon carbide (SiC), but are not limited thereto.

[0100] Specifically, the power semiconductor device 100 according to this aspect may include a substrate 111, a first conductive epitaxial layer 112 arranged on the substrate 111, a second conductive well 113 partially arranged on the first conductive epitaxial layer 112, a second conductive ion injection region 114 partially arranged on the second conductive well 113, and a source region 115 partially arranged in the second conductive well 113 and arranged on the second conductive ion injection region 114.

[0101] In addition, the power semiconductor device 100 according to this aspect may include a gate insulating layer 136 disposed on the source region 115 and the second conductive type well 113, a gate 134 disposed on the gate insulating layer 136, an interlayer insulating layer 132 disposed on the gate 134, and a source 130 disposed on the source region 115. A predetermined channel C may be defined between the gate 134 and the source region 115.

[0102] In the following, reference will be made to Figure 3B and Figure 4 Detailed features of the power semiconductor device 100 according to this aspect of the present disclosure are described in detail.

[0103] Figure 3B yes Figure 3A A partial view of a cross-sectional view of the power semiconductor device 100 is shown, and Figure 4 yes Figure 3B Detailed cross-sectional view of region D of power semiconductor device 100 is shown.

[0104] According to this aspect of the present disclosure, a power semiconductor device and a power converter including the power semiconductor device are able to solve the following problem: when the internal technology adopts a stepped insulation layer structure to improve the switching loss characteristics, instantaneous voltage and current spikes occur as the UIS characteristics of the power MOSFET device deteriorate, thereby causing damage to the power semiconductor device.

[0105] For example, refer to Figure 4① The gate insulating layer 136 may include a channel gate insulating layer 136a and a protruding gate insulating layer 136b, so that a thick protruding gate insulating layer 136b may be provided in a region other than the P well where a channel may be formed. Therefore, the switching loss characteristics of the device may be improved by reducing the value of the Miller capacitance (Cgd) associated with the switching speed by reducing the oxide capacitance (Cgd) formed between the gate and the drain.

[0106] At the same time, according to this aspect of the present disclosure, ② can significantly improve the alignment accuracy of disposing the second conductive type ion implantation region 114 below the source region 115. Therefore, by reducing the Rb resistance (region A), UIS characteristic degradation can be improved.

[0107] For example, after a certain thickness of a CVD film is deposited in a self-aligned structure for the source region 115 , ion implantation may be performed on the second conductive type ion implantation region 114 by a self-aligned method.

[0108] The second conductive type ion implantation region 114 can be formed under the source region 115 in a self-aligned method rather than using an optical method by performing strong ion implantation after depositing an insulating layer having a certain thickness. Thus, the second conductive type ion implantation region 114 can be formed to thinly surround the source region 115 while ensuring the thickness of the second conductive type well 113 as a P-body to withstand the internal pressure.

[0109] Therefore, compared with the related optical alignment method, the second conductive type ion implantation region 114 can accurately surround the region under the source region 115, and Rb (internal base resistance) associated with the operation of the parasitic NPN BJT can be significantly reduced.

[0110] For example, in the internal technology, the concentration of the Rb region is similar to that of the second conductivity type well 113 as the second conductivity type body. However, according to this aspect of the present disclosure, the concentration of the Rb region can be similar to that of the second conductivity type ion implantation region 114. Therefore, aspects of the present disclosure can suppress the operation of the parasitic NPN BJT by reducing the Rb resistance with a higher concentration than the known technology, thereby improving the UIS characteristics.

[0111] In addition, in the internal technology, only a self-aligned structure for the source region 115 is possible, but in the aspect of the present disclosure, in the self-aligned method, ion implantation is possible up to the second conductive type ion implantation region 114. Therefore, the degree of freedom of contact alignment of the subsequent process can be increased, thereby significantly increasing the cell density and improving the Ron characteristics.

[0112] Furthermore, in one aspect of the present disclosure, the source 130 may include a barrier metal layer 130 b and a protruding source contact electrode 130 p .

[0113] The source 130 of this aspect may include a protruding source contact electrode 130p having a body contact shape disposed in the recessed region of the second conductive type ion implantation region 114 and the source region 115. The protruding source contact electrode 130p may contact the top surface 115T of the source region and the side surface 115S of the source region, so that there is a composite technical effect of widening the contact area and improving the Ron characteristic.

[0114] Next, we will refer to FIG. 5A to FIG. 5H A manufacturing process of the power semiconductor device 100 according to this aspect is described.

[0115] Reference Figure 5A , a substrate 111 including a first conductive type epitaxial layer 112 may be prepared. The first conductive type epitaxial layer 112 may include a first conductive type buffer layer 112a and a first conductive type drift layer 112b.

[0116] The substrate 111 and the first conductive type epitaxial layer 112 may include a 4H-SiC material, but are not limited thereto. For example, the substrate 111 and the first conductive type epitaxial layer 112 may include 3C-SiC or 6H-SiC.

[0117] Next, a second conductivity type well 113 may be formed in the first conductivity type epitaxial layer 112 .

[0118] For example, a first hard mask pattern 120M1 may be formed on the first conductive type epitaxial layer 112, and ions may be implanted using the first hard mask pattern 120M1 as a mask to form the second conductive type well 113. The second conductive type well 113 may be a P-type body, but is not limited thereto.

[0119] The first hard mask pattern 120M1 may include a polysilicon pattern 125 and an oxide pattern 126 , but is not limited thereto.

[0120] The second conductive well 113 may have a diameter of about 1×10 16 cm -3 About 2×10 19 cm -3 Ion implantation is performed using a P-type dopant at a concentration of . For example, Al or boron may be implanted, but is not limited thereto.

[0121] Next, refer to Figure 5B A second hard mask preliminary layer 127 may be formed on the first hard mask pattern 120M1 and etched back to form a Figure 5C The second hard mask pattern 120M2 is shown. The second hard mask pattern 120M2 may be formed on the sidewalls of the first hard mask pattern 120M1. The second hard mask preliminary layer 127 may include polysilicon, but is not limited thereto.

[0122] Next, refer to Figure 5D , the first conductive type source region 115 may be formed by implanting ions into the second conductive type well 113 using the first hard mask pattern 120M1 and the second hard mask pattern 120M2 as ion implantation masks.

[0123] For example, the first conductive type source region 115 can be formed by self-aligning the source region 115 with a thickness of about 1×10 18 cm -3 About 7×10 19 cm -3 The N-type dopant such as nitrogen or phosphorus is ion-implanted to form the N-type dopant.

[0124] Next, refer to Figure 5E , a third hard mask pattern 120M3 may be formed on the first hard mask pattern 120M1 and the second hard mask pattern 120M2.

[0125] For example, the third hard mask pattern 120M3 may be formed of an oxide on an upper surface of the first hard mask pattern 120M1, a sidewall of the second hard mask pattern 120M2, and the first conductive type source region 115. However, it is not limited thereto.

[0126] Next, the second conductive type ion implantation region 114 may be formed by performing ion implantation using the first hard mask pattern 120M1 , the second hard mask pattern 120M2 , and the third hard mask pattern 120M3 as ion implantation masks in a self-aligned manner.

[0127] For example, the second conductive type ion implantation region 114 may be formed by implanting Al or boron into the second conductive type well 113 at a deeper position passing through the first conductive type source region 115 .

[0128] In this aspect, instead of using an optical method, an insulating layer having a certain thickness is deposited as the third hard mask pattern 120M3, and the second conductive type ion implantation region 114 may be formed by performing strong ion implantation under the source region 115 in a self-aligned method.

[0129] Thus, in this aspect, the second conductivity type ion implantation region 114 can be controlled to precisely surround the region below the source region 115 and the Rb resistance associated with the operation of the parasitic NPN BJT can be significantly reduced compared to related photo-alignment methods.

[0130] For example, in the internal technology, the concentration of the Rb region is similar to that of the second conductive type well 113 as the second conductive type body. However, according to this aspect, since the concentration of the Rb region can be similar to that of the second conductive type ion implantation region 114, the concentration of the Rb region can be 90 to 100 times higher than that of the related art. Therefore, the Rb resistance can be drastically reduced, thereby suppressing the operation of the parasitic NPN BJT, so that the UIS characteristics can be improved.

[0131] In addition, since ions can be implanted in self-alignment not only in the source region 115 but also in the second conductive type ion implantation region 114, the degree of freedom in subsequent processes such as contact alignment can be increased. Therefore, there is a technical effect of significantly improving the cell density, thereby improving the Ron characteristic.

[0132] Next, refer to Fig. 5F , the first hard mask pattern 120M1, the second hard mask pattern 120M2, and the third hard mask pattern 120M3 may be removed by CMP (Chemical Mechanical Polishing) or etching.

[0133] Next, refer to Figure 5G , a gate insulating layer 136 may be formed on the source region 115 and the second conductive well 113 , a gate 134 may be formed on the gate insulating layer 136 , and an interlayer insulating layer 132 may be formed on the gate 134 .

[0134] The gate insulating layer 136 may be a thermal oxide layer or a deposited oxide layer, but is not limited thereto. The gate 134 may be formed of polysilicon, but is not limited thereto. The interlayer insulating layer 132 may be formed of an oxide film or a nitride film, but is not limited thereto.

[0135] The gate insulating layer 136 may include a channel gate insulating layer 136a and a protruding gate insulating layer 136b. This aspect may reduce oxide capacitance Cgd formed between the gate and the drain by placing the thick protruding gate insulating layer 136b in a region other than the P well where a channel may be formed.

[0136] According to this aspect, the Miller capacitance Cgd value associated with the switching speed can be reduced by reducing the oxide capacitance Cgd, so that the switching loss characteristics of the device can be improved.

[0137] Next, refer to Figure 5H , after patterning a layer disposed on an upper side of the source region 115 , a source 130 may be formed on the source region 115 .

[0138] The source electrode 130 may be formed of Al or the like, but is not limited thereto. In addition, the source electrode 130 may further include a barrier metal layer 130b (eg, Figure 3A , Figure 3B and Figure 4shown).

[0139] The source 130 of this aspect may include a protruding source contact electrode 130 p having a body contact shape disposed in the recessed region of the second conductive type ion implantation region 114 and the source region 115 .

[0140] In this regard, since the protruding source contact electrode 130 p contacts the top surface 115T of the source region and the side surface 115S of the source region, the contact area may be widened, resulting in a composite technical effect of improving the Ron characteristic.

[0141] According to this aspect, the following technical effects are achieved: a power semiconductor device and a power converter including the power semiconductor device are provided, which can solve the following technical contradictions: when the internal technology adopts a stepped insulation layer structure to improve the switching loss characteristics, instantaneous voltage and current spikes appear as the UIS characteristics of the power MOSFET device deteriorate, thereby causing damage to the power semiconductor device.

[0142] For example, the gate insulating layer 136 of this aspect may include a channel gate insulating layer 136a and a protruding gate insulating layer 136b, so that a thick protruding gate insulating layer 136b may be provided in a region other than the P well forming the channel. Therefore, the switching loss characteristics of the device can be improved by reducing the value of the Miller capacitance (Cgd) associated with the switching speed by reducing the oxide capacitance (Cgd) formed between the gate and the drain.

[0143] At the same time, according to this aspect of the present disclosure, the alignment accuracy of placing the second conductive type ion implantation region 114 below the source region 115 can be significantly improved. Therefore, by reducing the Rb resistance (region A), there is a special technical effect that can solve the technical contradiction of UIS characteristic degradation.

[0144] For example, in this aspect, after a certain thickness of a CVD film is deposited in a self-aligned structure for the source region 115 , ion implantation may be performed on the second conductive type ion implantation region 114 by self-alignment.

[0145] For example, in this aspect, the second conductive type ion implantation region 114 can be formed under the source region 115 in a self-aligned method rather than using an optical method by strongly implanting ions after depositing an insulating layer having a certain thickness. Thus, the second conductive type ion implantation region 114 can be formed to thinly surround the source region 115 while ensuring the thickness of the second conductive type well 113 as a P-body to withstand the internal pressure.

[0146] Therefore, this aspect of the present disclosure can be controlled so that the second conductivity type ion implantation region 114 can accurately surround the area under the source region 115 and can significantly reduce Rb (internal base resistance) associated with the operation of the parasitic NPN BJT compared to related optical alignment methods.

[0147] For example, in the internal technology, the concentration of the Rb region is similar to that of the second conductivity type well 113 as the second conductivity type body. However, according to this aspect, the concentration of the Rb region can be similar to that of the second conductivity type ion implantation region 114. Therefore, this aspect has the following special technical effects, by having a higher concentration than the related art and significantly reducing the Rb resistance to suppress the operation of the parasitic NPN BJT, thereby improving the UIS characteristic degradation.

[0148] In addition, in the internal technology, a self-aligned structure is possible only for the source region 115, but in this regard, ions are implanted in a self-aligned manner up to the second conductive type ion implantation region 114. Therefore, the degree of freedom of contact alignment of subsequent processes can be increased, which has the technical effect of significantly increasing the cell density and improving the Ron characteristics.

[0149] In addition, in one aspect, the source 130 may include a protruding source contact electrode 130p having a body contact shape disposed in the recessed region of the second conductive type ion implantation region 114 and the source region 115. The protruding source contact electrode 130p may contact the top surface 115T of the source region and the side surface 115S of the source region, so that there is a composite technical effect of widening the contact area and improving the Ron characteristic.

[0150] It is obvious to those skilled in the art that various modifications and changes can be made in the power semiconductor device, power semiconductor module, power converter and manufacturing method thereof of the present disclosure without departing from the spirit or scope of the various aspects. Therefore, the present disclosure is intended to cover the modifications and changes of various aspects provided within the scope of the attached claims and their equivalents.

Claims

1. A power semiconductor device, comprising: A first conductivity type epitaxial layer, wherein the first conductivity type epitaxial layer is disposed on a substrate; A second conductivity type well, wherein the second conductivity type well is partially disposed on the first conductivity type epitaxial layer; a second conductive type ion implantation region, wherein the second conductive type ion implantation region is partially disposed in the second conductive type well; a source region, the source region being partially disposed in the second conductive type well and disposed on the second conductive type ion implantation region; a gate insulating layer, the gate insulating layer being disposed on the source region and the second conductive type well; a gate, the gate being disposed on the gate insulating layer; an interlayer insulating layer, wherein the interlayer insulating layer is disposed on the gate; as well as a source electrode, the source electrode being arranged on the source electrode region, The gate insulating layer includes a channel gate insulating layer having a first thickness and a protruding gate insulating layer having a second thickness thicker than the first thickness, and The second conductive type ion implantation region has a concentration in the Rb region that is higher than the concentration of the second conductive type well.

2. The power semiconductor device according to claim 1, wherein: The concentration in the Rb region is the lateral resistance of the second conductive type ion implantation region, and the lateral resistance is 90 to 100 times higher than that of the second conductive type well.

3. The power semiconductor device according to claim 1, wherein: The source includes a protruding source contact electrode, and the protruding source contact electrode is arranged in the recessed region of the second conductive type ion implantation region and the source region.

4. The power semiconductor device according to claim 3, wherein: The protruding source contact electrode contacts an upper surface of the source region and a side surface of the source region. 5 . The power semiconductor device according to claim 1 , further comprising a recessed portion disposed between two adjacent source regions and reaching an upper portion of the second conductive type ion implantation region.

6. The power semiconductor device according to claim 5, wherein: The source electrode is filled in the recess to contact the second conductive type ion implantation region.

7. The power semiconductor device according to claim 6, wherein: The second conductive type ion implantation region has a lateral length in a cross-sectional view that is at least the same as a total length of the two adjacent source regions and the recessed portion. 8 . A power converter, comprising the power semiconductor device according to claim 1 .

9. A method for manufacturing a power semiconductor device, the method comprising the following steps: preparing a substrate including a first conductivity type epitaxial layer; forming a first hard mask pattern on the first conductive type epitaxial layer, and forming a second conductive type well; forming a second hard mask pattern on sidewalls of the first hard mask pattern; forming a first conductivity type source region by implanting ions into the second conductivity type well using the first hard mask pattern and the second hard mask pattern as ion implantation masks; forming a third hard mask pattern on the first hard mask pattern and the second hard mask pattern; forming a second conductivity type ion implantation region in the second conductivity type well using the first hard mask pattern, the second hard mask pattern, and the third hard mask pattern as a self-aligned ion implantation mask; removing the first hard mask pattern, the second hard mask pattern, and the third hard mask pattern; as well as A gate insulating layer, a gate and an interlayer insulating layer are sequentially formed on the source region and the second conductive well.

10. The method according to claim 9, wherein: The step of forming the second conductive type ion injection region is configured as: using the first hard mask pattern, the second hard mask pattern and the third hard mask pattern as the ion injection masks to perform ion injection in a self-aligned manner, and forming the first conductive type source region in the second conductive type well through the second conductive type ion injection region.

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