Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate; the at least one groove is formed in the substrate; the gate structure extends along the first direction and covers partial surfaces of the substrate on two sides of the groove and partial side walls and the bottom of the groove, the part of the substrate below the surface covered by the gate structure is used as a channel region, and the part of the substrate below the surface covered by the gate structure is used as a gate region. And the channel width of the channel region is the sum of the length of the gate structure along the first direction and two times of the depth of all the grooves. According to the semiconductor device, the groove is additionally formed in the substrate to increase the channel width so as to increase the corresponding current, so that the semiconductor device has enough driving capability, and the performance of the semiconductor device is guaranteed.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), also known as MOS tube. In MOS tube, the gate voltage is changed to control the on and off of the MOS tube. When the MOS tube is turned on, the current flows between the source and the drain, and the magnitude of the current is positively correlated with the channel width (that is, the length of the gate). To make the current larger, the channel width is required to be larger. As the size of semiconductor devices continues to shrink, the channel width is also shrinking. The shrinking channel width will lead to a decrease in the current when the MOS tube is turned on, that is, the driving ability of the MOS tube when it is turned on is reduced, thereby affecting its performance. Summary of the invention

[0003] A series of simplified concepts are introduced in the Summary of the Invention, which will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0004] In view of the existing problems, the present invention provides a semiconductor device, comprising: substrate; at least one groove disposed in the substrate; A gate structure extends along a first direction and covers a portion of the surface of the substrate located on both sides of the groove and a portion of the sidewalls and bottom of the groove, wherein a portion of the substrate below the surface covered by the gate structure serves as a channel region, and a channel width of the channel region is the sum of the length of the gate structure along the first direction and twice the depth of all the grooves.

[0005] Exemplarily, the semiconductor device also includes a source and a drain, which are respectively formed in the substrate on both sides of the gate structure, wherein the first direction is perpendicular to the second direction, the second direction is a connection direction connecting the source and the drain, and in the second direction, the width of the groove is greater than or equal to the width of the gate structure.

[0006] Exemplarily, when there are multiple grooves, the multiple grooves are arranged at intervals along the first direction; and / or When there are plural grooves, the plurality of grooves have the same depth, or at least two of the plurality of grooves have different depths.

[0007] Exemplarily, the gate structure includes a gate dielectric layer and a gate electrode layer, wherein the gate dielectric layer covers a portion of the surface of the substrate located on both sides of the groove and a portion of the sidewalls and bottom of the groove, the gate electrode layer covers the gate dielectric layer, and the top surface of the gate electrode layer is higher than the top of the groove.

[0008] In another aspect, the present invention provides a method for manufacturing a semiconductor device, the method comprising: providing a substrate; forming at least one groove in the substrate; A gate structure extending along a first direction is formed, the gate structure covers a portion of the surface of the substrate located on both sides of the groove and a portion of the sidewalls and bottom of the groove, wherein a portion of the substrate below the surface covered by the gate structure serves as a channel region, and a channel width of the channel region is the sum of the length of the gate structure along the first direction and twice the depth of all the grooves.

[0009] Exemplarily, after forming the groove and before forming the gate structure, the manufacturing method further includes: A first ion implantation is performed at least on a region of the substrate that is intended to be used as a channel region to adjust a threshold voltage.

[0010] Exemplarily, the forming of the gate structure extending along the first direction includes: forming a gate dielectric material layer on the bottom and sidewalls of the groove and on the surface of the substrate; Depositing a gate electrode material layer to cover the gate dielectric material layer and fill the groove; The gate electrode material layer and the gate dielectric material layer are sequentially etched to form a gate electrode layer and a gate dielectric layer respectively, wherein the gate electrode layer and the gate dielectric layer constitute the gate structure, and the top surface of the gate electrode layer is higher than the top of the groove.

[0011] Exemplarily, the manufacturing method further includes: A source and a drain are respectively formed in the substrate on both sides of the gate structure, wherein the first direction is perpendicular to a second direction, the second direction is a connection direction connecting the source and the drain, and in the second direction, the width of the groove is greater than or equal to the width of the gate structure.

[0012] Exemplarily, a plurality of grooves are formed in the substrate, and the plurality of grooves are arranged at intervals along the first direction; and / or The plurality of grooves have the same depth, or at least two of the plurality of grooves have different depths.

[0013] Exemplarily, when the plurality of grooves have the same depth, the channel width W of the channel region is ch Satisfies the following formula:

[0014] Wherein, W is the length of the gate structure along the first direction, D is the depth of the groove, and N is the number of grooves.

[0015] The semiconductor device and the manufacturing method thereof of the embodiment of the present invention form a groove in the substrate before forming the gate structure extending in the first direction, so that the channel width becomes the sum of the length of the gate structure in the first direction and twice the depth of all the grooves, thereby obtaining a larger channel width. With the increase of the channel width, the current between the source and the drain increases under the same area, so that when the size of the semiconductor device continues to shrink, it can ensure that the MOS tube has sufficient driving ability when it is turned on, thereby ensuring its performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other purposes, features and advantages of the present application will become more apparent by describing the embodiments of the present application in more detail in conjunction with the accompanying drawings. The accompanying drawings are used to provide a further understanding of the embodiments of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the present application and do not constitute a limitation of the present application. In the accompanying drawings, the same reference numerals generally represent the same components or steps. In the accompanying drawings: Figure 1 A schematic diagram of the structure of a MOS tube in the related art is shown; Figure 2 A flow chart showing a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention; Figures 3A-3C A schematic cross-sectional view in a first direction of a device obtained by sequentially implementing a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention; Figure 3D A schematic cross-sectional view in a second direction of a device obtained by sequentially implementing a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention; Figure 3E A schematic cross-sectional view in a first direction of a device obtained by implementing a method for manufacturing a semiconductor device according to another exemplary embodiment of the present invention; Figure 4 A schematic three-dimensional diagram of a device obtained after a method for manufacturing a semiconductor device according to an exemplary embodiment of the present invention is sequentially implemented is shown. DETAILED DESCRIPTION

[0017] In order to make the purpose, technical solutions and advantages of the present application more obvious, the example embodiments according to the present application will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application, and it should be understood that the present application is not limited to the example embodiments described herein. Based on the embodiments of the present application described in the present application, all other embodiments obtained by those skilled in the art without creative work should fall within the scope of protection of the present application.

[0018] In related technologies, the semiconductor integrated circuit industry has experienced exponential development. Technological advances in IC materials and design have produced generations of semiconductor integrated circuits, each generation of which is smaller and more complex than the previous generation. In some semiconductor devices, such as metal MOS tubes, the stability of their performance has also been affected due to the continuous reduction in size. Taking MOS tubes as an example, MOS tubes are usually used as a switching device to control the flow of current in the circuit. Figure 1 The schematic diagram of the structure of a MOS tube in the related art shown in the figure, the gate electrode layer 303 and the gate dielectric layer 302 on the substrate 300 form a gate structure, the substrate on both sides of the gate structure also includes a source (not shown) and a drain (not shown), and the substrate covered by the gate structure is a channel region. By changing the voltage of the gate structure, the opening and closing of the MOS tube are controlled. When the MOS tube is turned on, the current flows between the source and the drain, and the magnitude of the current is positively correlated with the channel width W. In the related art, the channel width W is equal to the length of the gate structure. Therefore, as the size of the MOS tube continues to shrink in proportion, the length of the gate structure in the MOS tube is also reduced, so that when the MOS tube is turned on, the current becomes smaller, and the driving ability of the MOS tube is weakened, thereby affecting the performance of the MOS tube.

[0019] Therefore, in view of the existence of the above-mentioned technical problems, the present invention proposes a method for manufacturing a semiconductor device, such as Figure 2 As shown, the following steps are included: Step S210: providing a substrate; Step S220: forming at least one groove in the substrate; Step S230: forming a gate structure extending along a first direction, wherein the gate structure covers a portion of the surface of the substrate located on both sides of the groove and a portion of the sidewalls and the bottom of the groove, wherein a portion of the substrate below the surface covered by the gate structure serves as a channel region, and a channel width of the channel region is the sum of the length of the gate structure along the first direction and twice the depth of all the grooves.

[0020] According to the manufacturing method of the semiconductor device provided by the present invention, at least one groove is first formed in the substrate before forming the gate structure, and then the gate structure and the channel region extending along the first direction are formed, so that the channel width is the sum of the length of the gate structure along the first direction and twice the depth of all the grooves. As the channel width increases, the current also increases under the same area.

[0021] In order to fully understand the present invention, detailed steps and structures will be presented in the following description to illustrate the technical solution proposed by the present invention. The preferred embodiments of the present invention are described in detail below, but in addition to these detailed descriptions, the present invention may also have other implementations.

[0022] Below, reference FIG. 3A to FIG. 3E The method for manufacturing a semiconductor device of the present invention is described in detail, wherein: FIG. 3A to FIG. 3E The cross-sectional schematic diagram shows a semiconductor device obtained by sequentially implementing the method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0023] Exemplarily, the method for manufacturing a semiconductor device of the present invention comprises the following steps: First, step S210 is performed to provide a substrate 300 .

[0024] Exemplarily, the substrate 300 may be any suitable semiconductor substrate, such as a silicon substrate, and may also be at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, including multilayer structures composed of these semiconductor materials, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), or may also be double-sided polished silicon wafers (Double Side Polished Wafers, DSP), or may also be ceramic substrates such as alumina, quartz or glass substrates, etc.

[0025] Then, step S220 is performed. Figure 3A , Figure 4 As shown, at least one groove 301 is formed in a substrate 300 .

[0026] In a specific example, a method for forming at least one groove 301 in a substrate 300 includes: firstly forming a patterned photoresist layer on the surface of the substrate 300, the patterned photoresist layer defining the size and position of the groove 301 to be formed, and then etching the substrate 300 using the patterned photoresist layer as a mask to form the groove 301. Exemplarily, various etching methods commonly used in the art may be used to perform etching treatment to form the groove 301, such as a reactive ion etching method, and then removing the photoresist layer.

[0027] The number of grooves 301 can be reasonably set according to actual needs. For example, multiple grooves 301 are formed in the substrate 300, and the multiple grooves 301 are arranged at intervals along the first direction A; and / or the multiple grooves 301 have the same depth, or at least two grooves 301 in the multiple grooves 301 have different depths.

[0028] like Figure 3A , Figure 4 As shown, the plurality of grooves 301 are arranged at intervals along the first direction A and have the same depth. In another embodiment, the depths of the plurality of grooves 301 may be partially or completely different, and the grooves 301 may be arranged according to actual needs.

[0029] Illustratively, after forming the groove and before forming the gate structure, the method of the present application further includes performing a first ion implantation on at least a region of the substrate that is intended to be used as a channel region, so as to adjust a threshold voltage.

[0030] The threshold voltage of the MOS tube is proportional to the amount of charge doped in the channel. The doping concentration of the substrate in the channel region of the MOS tube can be enhanced or supplemented by the ion implantation method, thereby effectively controlling and adjusting the threshold voltage of the MOS tube. Specifically, the first ion implantation method can be to use a medium of appropriate thickness as a mask in the area outside the predetermined channel region, wherein the medium can be a metal layer, silicon dioxide or photoresist, etc., and the mask is used to prevent the high-energy ion beam from penetrating the area that does not need to be implanted, and the ion beam is implanted into the area predetermined to be used as the channel region, so that the doping concentration of the channel region can be adjusted, thereby adjusting the threshold voltage.

[0031] Then, step S230 is performed to form a gate structure extending along a first direction, wherein the gate structure covers a portion of the surface of the substrate located on both sides of the groove and a portion of the sidewalls and bottom of the groove, wherein a portion of the substrate below the surface covered by the gate structure serves as a channel region, and a channel width of the channel region is the sum of the length of the gate structure along the first direction and twice the depth of all the grooves.

[0032] The gate structure covers part of the surface of the substrate on both sides of the groove and part of the sidewalls and bottom of the groove, so that the channel width after adding the groove is wider than the channel width without adding the groove. The value of the widened channel width is twice the depth of all grooves, thereby increasing the current passing through the channel.

[0033] Exemplarily, forming a gate structure extending along a first direction includes: forming a gate dielectric material layer on the bottom and sidewalls of the groove and on the surface of the substrate; Depositing a gate electrode material layer to cover the gate dielectric material layer and fill the groove; The gate electrode material layer and the gate dielectric material layer are sequentially etched to form a gate electrode layer and a gate dielectric layer respectively, wherein the gate electrode layer and the gate dielectric layer constitute the gate structure, and the top surface of the gate electrode layer is higher than the top of the groove.

[0034] like Figure 3B As shown, a gate dielectric material layer 3021 is formed on the bottom and sidewalls of the groove 301 and the surface of the substrate 300. Specifically, the gate dielectric material layer 3021 can be formed by a thermal oxidation process, a physical vapor deposition process, or a chemical vapor deposition process, and the gate dielectric material layer 3021 includes but is not limited to a silicon oxide layer or a silicon oxynitride layer.

[0035] After forming the gate dielectric material layer 3021, as Figure 3C As shown, a gate electrode material layer 3031 is deposited to cover the gate dielectric material layer 3021 and fill the groove 301. The gate electrode material layer 3031 includes but is not limited to a polysilicon layer or an aluminum layer. Exemplarily, various deposition methods commonly used in the art can be used to form the gate electrode material layer 3031 and fill the groove 301. For example, it can be formed by chemical vapor deposition, physical vapor deposition or atomic layer deposition. Next, the gate electrode material layer 3031 and the gate dielectric material layer 3021 are etched in turn. Various conventional etching processes in the art can be used to etch the gate electrode material layer 3031 and the gate dielectric material layer 3021 to form the following respectively: Figure 3D The gate electrode layer 303 and the gate dielectric layer 302 are shown.

[0036] Exemplarily, the manufacturing method further includes: forming a source electrode and a drain electrode in the substrate on both sides of the gate structure, respectively, wherein Figure 4 As shown, the first direction A is perpendicular to the second direction B. The second direction B is a connection direction connecting the source and the drain. In the second direction B, the width of the groove 301 is greater than or equal to the width of the gate structure.

[0037] like Figure 3DAs shown, sidewalls 3032 may be formed on both sides of the gate structure. Specifically, the sidewalls 3032 may be formed by a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process. The sidewalls include but are not limited to a silicon oxide layer, a silicon nitride layer, or an ONO structure (i.e., a stacked structure of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer). Based on the gate structure and the sidewall 3032, the substrate 300 is subjected to a second ion implantation to form a source 304 and a drain 305 on both sides of the gate structure and the sidewall 3032, respectively. Figure 4 As shown, in the second direction B, the gate structure passes through the groove 301 along the center line in the first direction A, and the width of the groove 301 is greater than or equal to the width of the gate structure.

[0038] In another embodiment, in the second direction, a side of the groove close to the gate structure is within the gate structure but the center line of the gate structure along the first direction does not pass through the groove, that is, part of the gate structure is located within the groove, and part of the gate structure is located on the flat substrate surface outside the groove in the second direction.

[0039] Exemplarily, when the plurality of grooves have the same depth, the channel width W of the channel region is ch Satisfies the following formula:

[0040] Wherein, W is the length of the gate structure along the first direction, D is the depth of the groove, and N is the number of grooves.

[0041] like Figure 3A and 3C As shown, a plurality of grooves 301 with the same depth D are formed on the substrate 300. ,and When W is fixed, reducing W1 and W2 can form more grooves 301, which is equivalent to increasing the depth D. The channel depth W ch When the number of grooves 301 is not increased, the channel depth W can also be increased by increasing the depth D of the grooves. ch increases, thereby increasing the current.

[0042] In another embodiment, Figure 3E As shown, a plurality of grooves 301 are formed on the substrate 300, and the depths of the grooves 301 are not completely the same. In this case, the channel width is the sum of the length of the gate structure along the first direction and twice the depths of all the grooves. Taking three grooves 301 as an example, two of the grooves 301 have the same depth D1, and the third groove 301 has a different depth, and the depth of the third groove 301 is D2. Then the channel width W ch= W+2D1+2D2+2D1= W+2(2D1+D2) Similarly, when the depths of the plurality of grooves 301 on the substrate 300 are different, the channel width is also satisfied to be the sum of the length of the gate structure along the first direction and twice the depths of all the grooves, which will not be elaborated any more.

[0043] The method for manufacturing a semiconductor device of the present invention is not only applicable to manufacturing MOS tubes, but also applicable to manufacturing various devices such as metal-oxide-semiconductor capacitors (MOSCAP), varactors, lateral double-diffused MOSFETs (LDMOS), etc.

[0044] The description of the key steps of the method for manufacturing the semiconductor device of the present invention has been completed. The preparation of a complete semiconductor device may also include other steps, which will not be described one by one here.

[0045] It is worth mentioning that the above steps are only examples, and the order of the above steps can be adjusted without conflict.

[0046] The present invention also provides a semiconductor device, such as Figure 4 As shown, including: A substrate 300; at least one groove 301, disposed in the substrate 300; The gate structure extends along the first direction and covers a portion of the surface of the substrate 300 located on both sides of the groove 301 and a portion of the sidewalls and the bottom of the groove 301, wherein the portion of the substrate 300 below the surface covered by the gate structure serves as a channel region, and the channel width of the channel region is the sum of the length of the gate structure along the first direction and twice the depth of all the grooves 301.

[0047] At least one groove 301 is set on the substrate 300, and the gate structure covers a portion of the surface of the substrate 300 located on both sides of the groove 301 as well as a portion of the sidewalls and the bottom of the groove 301. In addition, the portion of the substrate 300 below the surface covered by the gate structure is used as a channel region, so that the depth of the groove 301 is also converted into the channel width. In this way, the effect of increasing the channel width can be achieved while the length of the gate structure in the first direction remains unchanged, thereby increasing the current passing through the channel.

[0048] Exemplarily, as shown in 3D, the semiconductor device further includes a source 304 and a drain 305, the source 304 and the drain 305 are respectively formed in the substrate on both sides of the gate structure, wherein the first direction is perpendicular to the second direction, the second direction is the connection direction connecting the source 304 and the drain 305, and in the second direction, the width of the groove 301 is greater than or equal to the width of the gate structure. The semiconductor device can be a MOS tube or other devices with similar structures. Exemplarily, as Figure 3D As shown, sidewall spacers 3032 are also provided on both sides of the gate structure and located on both sides of the gate electrode layer 303 .

[0049] Exemplarily, when the number of the grooves is multiple, the multiple grooves are arranged at intervals along the first direction; and / or when the number of the grooves is multiple, the multiple grooves have the same depth, or at least two of the multiple grooves have different depths.

[0050] like Figure 3A-3C and Figure 3E As shown, when there are multiple grooves 301, the multiple grooves 301 are arranged at intervals along the first direction. The depths of the multiple grooves 301 can be the same or different.

[0051] For example, Figure 3A-3D As shown, the gate structure includes a gate dielectric layer 302 and a gate electrode layer 303, wherein the gate dielectric layer 302 covers a portion of the surface of the substrate 300 located on both sides of the groove 301 and a portion of the sidewalls and the bottom of the groove 301, and the gate electrode layer 303 covers the gate dielectric layer 302, and the top surface of the gate electrode layer is higher than the top of the groove, and the gate dielectric layer 302 plays an isolation and protection role.

[0052] The structure of the semiconductor device of the present invention has been introduced so far. The complete device may also include other component structures, which will not be described in detail here.

[0053] According to the semiconductor device and the manufacturing method thereof provided by the present invention, a groove is first formed in the substrate before the gate structure extending in the first direction is formed, so that the channel width becomes the sum of the length of the gate structure in the first direction and twice the depth of all the grooves, thereby obtaining a larger channel width. The channel width increases, and the current between the source and the drain increases under the same area. Therefore, when the size of the semiconductor device continues to shrink, it can be ensured that the semiconductor device has sufficient driving capability when it is turned on, thereby ensuring its performance.

[0054] It should be noted that the above embodiments illustrate the present application rather than limit the present application, and that those skilled in the art may design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference symbol between brackets should not be constructed as a limitation on the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "one" or "an" preceding an element does not exclude the presence of multiple such elements. The present application may be implemented with the aid of hardware including several different elements and with the aid of appropriately programmed computers. In a unit claim listing several on-board systems, several of these on-board systems may be embodied by the same hardware item. The use of the words first, second, and third, etc. does not indicate any order. These words may be interpreted as names.

[0055] The above is only a specific implementation method or description of a specific implementation method of the present application, and the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. The protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; at least one groove disposed in the substrate; A gate structure extends along a first direction and covers a portion of the surface of the substrate located on both sides of the groove and a portion of the sidewalls and bottom of the groove, wherein a portion of the substrate below the surface covered by the gate structure serves as a channel region, and a channel width of the channel region is the sum of the length of the gate structure along the first direction and twice the depth of all the grooves.

2. The semiconductor device according to claim 1, wherein It also includes a source and a drain, which are respectively formed in the substrate on both sides of the gate structure, wherein the first direction is perpendicular to the second direction, the second direction is a connection direction connecting the source and the drain, and in the second direction, the width of the groove is greater than or equal to the width of the gate structure.

3. The semiconductor device according to claim 1, wherein When there are multiple grooves, the multiple grooves are arranged at intervals along the first direction; and / or When there are plural grooves, the plurality of grooves have the same depth, or at least two of the plurality of grooves have different depths.

4. The semiconductor device according to claim 1, wherein The gate structure includes a gate dielectric layer and a gate electrode layer, wherein the gate dielectric layer covers a portion of the surface of the substrate located on both sides of the groove and a portion of the sidewalls and bottom of the groove, and the gate electrode layer covers the gate dielectric layer, and the top surface of the gate electrode layer is higher than the top of the groove.

5. A method for manufacturing a semiconductor device, characterized in that: The manufacturing method comprises: providing a substrate; forming at least one groove in the substrate; A gate structure extending along a first direction is formed, the gate structure covers a portion of the surface of the substrate located on both sides of the groove and a portion of the sidewalls and bottom of the groove, wherein a portion of the substrate below the surface covered by the gate structure serves as a channel region, and a channel width of the channel region is the sum of the length of the gate structure along the first direction and twice the depth of all the grooves.

6. The manufacturing method according to claim 5, characterized in that: After forming the groove and before forming the gate structure, the manufacturing method further includes: A first ion implantation is performed at least on a region of the substrate that is intended to be used as a channel region to adjust a threshold voltage.

7. The manufacturing method according to claim 5, characterized in that: The forming of a gate structure extending along a first direction comprises: forming a gate dielectric material layer on the bottom and sidewalls of the groove and on the surface of the substrate; Depositing a gate electrode material layer to cover the gate dielectric material layer and fill the groove; The gate electrode material layer and the gate dielectric material layer are sequentially etched to form a gate electrode layer and a gate dielectric layer respectively, wherein the gate electrode layer and the gate dielectric layer constitute the gate structure, and the top surface of the gate electrode layer is higher than the top of the groove.

8. The manufacturing method according to claim 5, characterized in that: The manufacturing method further comprises: A source and a drain are respectively formed in the substrate on both sides of the gate structure, wherein the first direction is perpendicular to a second direction, the second direction is a connection direction connecting the source and the drain, and in the second direction, the width of the groove is greater than or equal to the width of the gate structure.

9. The manufacturing method according to claim 5, characterized in that: forming a plurality of grooves in the substrate, wherein the plurality of grooves are arranged at intervals along the first direction; and / or The plurality of grooves have the same depth, or at least two of the plurality of grooves have different depths.

10. The manufacturing method according to claim 9, characterized in that: When the plurality of grooves have the same depth, the channel width W of the channel region is ch Satisfies the following formula: ； Wherein, W is the length of the gate structure along the first direction, D is the depth of the groove, and N is the number of grooves.

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