Field effect transistor and preparation method thereof

Abstract

The invention discloses a field effect transistor and a preparation method thereof, the field effect transistor comprises a substrate, a drift layer, a JEFT region, a first body region and a barrier layer, the drift layer is located at one side of the substrate, the drift layer comprises the JFET region, one side, away from the substrate, of the drift layer is provided with a first surface, and the drift layer is provided with a first doping type; the barrier layer is located in the JFET region, the multiple first body regions are located on the two sides of the barrier layer, the first body regions are symmetrically located in the drift layer along the symmetry axis, and the first body regions are of the second doping type. When the device is in a blocking state, the concentration of the JFET region is increased, so that the gate oxide layer at the top of the region generates a relatively high electric field to cause breakdown of the gate oxide layer, and the barrier layer can reduce the risk that the gate oxide layer is broken down. The problem that in the prior art, in order to reduce the on-state resistance of the field effect transistor, the doping concentration of a JFET region is increased, and consequently the field effect transistor is prone to failure in the blocking state is solved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor devices, and in particular, to a field effect transistor and a method for preparing the same. Background Art

[0002] In a planar field-effect transistor (MOSFET, Metal-Oxide-Semiconductor Field-EffectTransistor), the part between the two P-type body regions is called the junction field effect region (JFET, Junction FET), which is the region where the current must flow when the device is in the on state. The JFET region and part of the P-type body region need to be made into a gate oxide dielectric to isolate the semiconductor from the gate electrode to avoid gate-source shorting. The doping concentration of the JFET region directly affects the on-resistance of the MOSFET. Therefore, in the production of planar MOSFET, the JFET region is usually re-doped to obtain a higher concentration than the epitaxial layer to reduce the on-state resistance. However, this technology is limited in reducing the on-resistance, because in the blocking state of the device, the increase in the concentration of the JFET region will cause the gate oxide layer on the top of the region to generate a higher electric field, causing the gate oxide layer to break down, thereby causing a gate-drain short and causing the device to fail. Summary of the invention

[0003] The present application provides a field effect transistor and a method for preparing the same, in order to solve the problem in the related art that in order to reduce the on-resistance of the field effect transistor, the doping concentration of the JFET region is increased, resulting in the field effect transistor being prone to failure in a blocking state.

[0004] According to one aspect of the present application, a field effect transistor is provided, comprising: a substrate having a first doping type; a drift layer located on one side of the substrate, the drift layer comprising a JFET region, the drift layer having a first surface on a side facing away from the substrate, and the drift layer having the first doping type, and the drift layer having a symmetry axis in a thickness direction; a barrier layer located in the JFET region; a plurality of first body regions located on both sides of the barrier layer, a surface of the first body region on a side facing away from the substrate being located in the first surface, the first body regions being symmetrically located in the drift layer along the symmetry axis, and the first body regions having a second doping type.

[0005] Optionally, the field effect transistor further includes a first sub-doping region and a second sub-doping region, wherein: the first sub-doping region is located on a side of the second sub-doping region close to the blocking layer, the first sub-doping region has a first doping type, and the second sub-doping region has a second doping type.

[0006] Optionally, the first body region includes a first sub-body region and a second sub-body region, the second sub-body region is located on a side of the first sub-body region away from the substrate, the second sub-body region is located on a side of the first sub-doping region away from the second sub-doping region, and the doping concentration of the second sub-body region is lower than the doping concentration of the first sub-body region.

[0007] Optionally, the field effect transistor further comprises a gate structure, and the gate structure is located on a side of the barrier layer away from the drift layer.

[0008] Optionally, the field effect transistor further includes an insulating layer, and the insulating layer is located on a side of the gate structure away from the drift layer.

[0009] Optionally, the barrier layer in the drift layer has a thickness of 0.2 μm to 0.5 μm.

[0010] Optionally, the field effect transistor further includes a source, an insulating layer and a drain, wherein: the insulating layer is located on a side of the drift layer away from the substrate, the source is located on a side of the insulating layer away from the substrate, and the drain is located on a side of the substrate away from the drift layer.

[0011] According to another aspect of the present application, a method for preparing a field effect transistor is provided, comprising: providing a substrate, the substrate having a first doping type; forming a drift layer on one side of the substrate, and forming a JFET region in the drift layer, the drift layer being located on one side of the substrate, the drift layer having a first surface on a side facing away from the substrate, and the drift layer having the first doping type, and the drift layer having a symmetry axis in a thickness direction; forming a barrier layer in the JFET region; forming first body regions on both sides of the barrier layer, the first body region being located in the drift layer, a surface of the first body region on a side facing away from the substrate being located in the first surface, the first body region being symmetrically located in the drift layer along the symmetry axis, and the first body region having a second doping type.

[0012] Optionally, the step of forming the barrier layer includes: etching the JFET region so that the JFET region has a first groove; depositing a barrier material on a side of the preliminary drift layer away from the substrate, the barrier material filling the first groove to form the barrier layer.

[0013] Optionally, the step of forming multiple first body regions includes: performing a first ion implantation in the preliminary drift region to form multiple first preliminary body regions; performing a second ion implantation in the first preliminary body region to form a first sub-doping region; performing a third ion implantation in the first preliminary body region to form a second sub-doping region, the second sub-doping region being located on a side of the first sub-doping region away from the blocking layer to form the first body region.

[0014] A field effect transistor provided by the present application includes a substrate, a drift layer, a first body region and a barrier layer, wherein the substrate has a first doping type; the drift layer is located on one side of the substrate, the drift layer has a JFET region, the drift layer has a first surface on a side facing away from the substrate, and the drift layer has the first doping type, and the drift layer has a symmetry axis in a thickness direction; the barrier layer is located in the JFET region, a plurality of first body regions are located on both sides of the barrier layer, a surface of the first body region on a side facing away from the substrate is located in the first surface, the first body regions are symmetrically located in the drift layer along the symmetry axis, and the first body regions have a second doping type; the barrier layer is located in the drift layer and between adjacent first body regions. The blocking layer is located at the center of the JFET region. Although increasing the concentration of the JFET region can reduce the on-state resistance, when the device is in a blocking state, the gate oxide layer on the top of the region will generate a higher electric field, causing the gate oxide layer to break down. The above-mentioned blocking layer can reduce the risk of the above-mentioned gate oxide layer being broken down and protect the effectiveness of the field effect transistor, thereby solving the problem in the related art that in order to reduce the on-state resistance of the field effect transistor, the doping concentration of the JFET region is increased, resulting in the field effect transistor being prone to failure in the blocking state. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings constituting a part of the present application are used to provide a further understanding of the present application. The illustrative embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0016] Figure 1 is a cross-sectional schematic diagram of a field effect transistor provided according to an embodiment of the present application;

[0017] Figure 2 It is a schematic flow chart of a method for preparing a field effect transistor provided in an embodiment of the present application;

[0018] Figure 3 It is a cross-sectional schematic diagram of a base body after providing a substrate in a method for preparing a field effect transistor provided in an embodiment of the present application;

[0019] Figure 4 is Figure 3 A schematic cross-sectional view of a substrate after a preliminary drift layer is formed on the substrate provided in the invention and a barrier layer is formed in the preliminary drift layer;

[0020] Figure 5 is Figure 4 A schematic cross-sectional view of a substrate after a first preliminary body region is formed in a preliminary drift layer formed in the substrate;

[0021] Figure 6 is Figure 5A schematic cross-sectional view of a substrate after a first sub-doping region and a second sub-doping region are formed in a first preliminary region formed in the substrate;

[0022] Figure 7 is Figure 6 A schematic cross-sectional view of a substrate after a gate structure is formed on the barrier layer;

[0023] Figure 8 is Figure 7 A schematic cross-sectional view of a substrate after an insulating layer is formed on the gate structure formed in FIG.

[0024] The above drawings include the following reference numerals:

[0025] 10. substrate; 20. drift layer; 201. JFET region; 202. preliminary drift layer; 30. first body region; 301. first preliminary body region; 31. first sub-doping region; 32. second sub-doping region; 33. first sub-body region; 330. first sub-preparatory body region; 34. second sub-body region; 340. second sub-preparatory body region; 40. blocking layer; 50. gate structure; 51. gate oxide layer; 52. gate; 60. insulating layer; 70. source; 80. drain. DETAILED DESCRIPTION

[0026] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0027] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0028] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0029] As mentioned in the prior art, the doping concentration of the JFET region directly affects the on-resistance of the MOSFET. Therefore, in the manufacture of planar MOSFET, the JFET region is usually re-doped to obtain a higher concentration than the epitaxial layer to reduce the on-resistance. The increased concentration in the JFET region will cause the gate oxide layer at the top of the region to generate a higher electric field when the device is in a blocking state, causing the gate oxide layer to break down, thereby causing a gate-drain short circuit and causing the field effect transistor device to fail. To this end, the present application proposes a field effect transistor and a method for preparing the same.

[0030] In order to solve the above technical problem, according to an embodiment of the present application, a field effect transistor is provided. Figure 1 is a cross-sectional schematic diagram of a field effect transistor according to an embodiment of the present application. Figure 1 As shown, the field effect transistor includes: a substrate 10 having a first doping type; a drift layer 20 located on one side of the substrate 10, the drift layer 20 including a JFET region 201, the drift layer 20 having a first surface on a side away from the substrate 10, and the drift layer 20 having the first doping type, and the drift layer 20 having a symmetry axis in a thickness direction; a barrier layer 40 located in the JFET region 201; a plurality of first body regions 30 located on both sides of the barrier layer 40, the surface of the first body region 30 on a side away from the substrate 10 being located in the first surface, the first body regions 30 being symmetrically located in the drift layer 20 along the symmetry axis, and the first body regions 30 having a second doping type.

[0031] In order to reduce the on-resistance of the device, the doping concentration of the JFET region is usually increased, but this will cause the gate oxide layer at the top of the region to generate a higher electric field when the device is in a blocking state, and the gate oxide layer at the middle position of the two adjacent first body regions is easily broken down. The present application sets a barrier layer in the JFET region between the adjacent first body regions, while ensuring that the on-resistance of the device is low, and reduces the risk of the gate oxide layer being broken down when the device is in a blocking state, thereby protecting the field effect transistor and improving the reliability of the device.

[0032] In MOSFET devices, the main flow channel of electron current in the JFET region is close to the first body region, and in the blocking state, the gate oxide layer is prone to breakdown at the middle of the two adjacent first body regions. Therefore, a shallow trench is etched in the middle of the JFET region between the two adjacent first body regions and filled with a barrier layer. Even if other JFET regions outside the trench are doped with a higher concentration, the barrier layer protects the gate oxide layer at the location where breakdown is likely to occur in the blocking state, which reduces the probability of breakdown and even prevents breakdown.

[0033] In the above embodiment, if Figure 1As shown, after the barrier layer 40 is provided in the device, the on-state resistance of the device can be better reduced, and the barrier layer 40 will also protect the gate oxide layer from being broken down. The substrate 10 and the drift layer 20 have the same doping type, and the doping concentration of the drift layer 20 is lower than the doping concentration of the substrate 10. The doping concentration of the drift layer 20 is about two orders of magnitude lower than the doping concentration of the substrate 10. The first body region 30 is of the second doping type, such as the drift layer 20 is of N type and the first body region 30 is of P type. The barrier layer 40 can be an insulating dielectric layer, and those skilled in the art can reasonably select the type of the barrier layer according to actual conditions, and this application does not make specific limitations.

[0034] For example, when the on-voltage of the device is 3300 V, the doping concentration of the JFET region in the prior art ranges from 1E16 to 3E16 cm -3 The doping concentration of the JFET region of the present application may range from 3E16 to 5E16 cm -3 , and the on-resistance of the present application is reduced by 15% compared with the on-resistance in the prior art. The present application not only reduces the on-resistance of the device, but also reduces the risk of the gate oxide layer being broken down when the device is in a blocking state.

[0035] In the prior art, trench-type transistors usually thicken the gate oxide layer to protect the reliability of the gate oxide layer in the blocking state. This is achieved by thickening the necessary structure of the transistor, and the gate oxide layer wraps the bottom and sidewalls of the gate. The present application is a planar transistor, and the barrier layer is not a necessary structure of the device, and the width of the barrier layer is less than or equal to 1μm. If the barrier layer is made too wide to wrap the bottom of the gate oxide layer, it will affect the channel of the device's electronic current and increase the on-resistance.

[0036] In some optional embodiments, such as Figure 1 As shown, the field effect transistor also includes a first sub-doping region 31 and a second sub-doping region 32, wherein: the first sub-doping region 31 is located on a side of the second sub-doping region 32 close to the blocking layer 40, the first sub-doping region 31 has a first doping type, and the second sub-doping region 32 has a second doping type.

[0037] In the above optional implementation, if Figure 1 As shown, the first body region 30 may be a silicon carbide matrix region, N-type ions may be implanted into the first body region 30 to form a first sub-doping region 31 , and P-type ions may be implanted into the first body region 30 to form a second sub-doping region 32 .

[0038] In some optional embodiments, such as Figure 1As shown, the first body region 30 includes a first sub-body region 33 and a second sub-body region 34. The second sub-body region 34 is located on the side of the first sub-body region 33 away from the substrate 10, and the second sub-body region 34 is located on the side of the first sub-doping region 31 away from the second sub-doping region 32. The doping concentration of the second sub-body region 34 is lower than the doping concentration of the first sub-body region 33.

[0039] In the above optional implementation, if Figure 1 As shown, in the process of forming the first body region 30 , ions are implanted into the drift layer 20 to form sub-body regions with two doping concentrations, wherein the doping concentration of the first sub-body region 33 is high and the doping concentration of the second sub-body region 34 is low.

[0040] In some optional embodiments, such as Figure 1 As shown, the field effect transistor further includes a gate structure 50 . The gate structure 50 is located on a side of the barrier layer 40 away from the drift layer 20 .

[0041] In the above optional implementation, if Figure 1 As shown, the gate structure 50 includes a gate oxide layer 51 and a gate 52. Before forming the gate structure 50, the device is subjected to a high temperature ion activation process. The thickness of the gate oxide layer 51 is 0.04 μm to 0.12 μm, such as 0.06 μm, 0.1 μm and 0.11 μm; the gate structure 50 also includes a gate 52, and the thickness of the gate 52 is 0.5 μm to 0.9 μm, such as 0.6 μm, 0.7 μm and 0.8 μm. The gate oxide layer 51 can be an insulating dielectric layer, and the material of the gate 52 can be polysilicon.

[0042] In some optional embodiments, such as Figure 1 As shown, the field effect transistor further includes an insulating layer 60 . The insulating layer 60 is located on a side of the gate structure 50 away from the drift layer 20 .

[0043] In the above optional implementation, if Figure 1 As shown, the insulating layer 60 can be used as an isolation dielectric layer for the source 70 and the gate structure 50. The insulating layer 60 has an opening for the source electrode to facilitate electrical connection between the source 70 and the gate 52. The insulating layer 60 can be made of any one of silicon dioxide, silicon nitride and aluminum oxide.

[0044] In some optional embodiments, such as Figure 1 As shown, the barrier layer 40 in the drift layer 20 has a thickness of 0.2 μm to 0.5 μm.

[0045] In the above optional implementation, if Figure 1As shown, setting the thickness of the barrier layer 40 within the above range can effectively reduce the risk of the gate oxide layer 51 being broken down. For example, the thickness of the barrier layer 40 is 0.3 μm or 0.4 μm.

[0046] In some optional embodiments, such as Figure 1 As shown, the field effect transistor further includes a source 70, an insulating layer 60 and a drain 80, wherein: the insulating layer 60 is located on a side of the drift layer 20 away from the substrate 10, the source 70 is located on a side of the insulating layer 60 away from the substrate 10, and the drain 80 is located on a side of the substrate 10 away from the drift layer 20.

[0047] In the above optional implementation, if Figure 1 As shown, the source 70 is located on the side of the insulating layer 60 away from the gate structure 50, and the source 70 covers the above-mentioned first body region 30. The drain 80 is located on the side of the substrate 10 away from the drift layer 20. The material of the above-mentioned source 70 and drain 80 can be any one or more of copper, aluminum, chromium, silver and tungsten, and this application does not make specific limitations.

[0048] When the device is in a blocking state and the doping concentration of the JFET region is high, the gate oxide layer above the JFET region between the two first body regions is easily broken down. The present application sets a shallow trench in the middle of the JFET region and sets a barrier layer in the shallow trench so that the barrier layer is located in the center of the JFET region. The barrier layer can reduce the risk of the gate oxide layer being broken down and protect the effectiveness of the field effect transistor, thereby solving the problem in the related art that in order to reduce the on-resistance of the field effect transistor, the doping concentration of the JFET region is increased, resulting in the field effect transistor being easily failed in the blocking state.

[0049] According to another aspect of the present application, a method for preparing a field effect transistor is provided, such as Figure 2 As shown, including:

[0050] Step S100: providing a substrate, wherein the substrate has a first doping type;

[0051] Step S200: forming a drift layer on one side of the substrate, and forming a JFET region in the drift layer, wherein the drift layer is located on one side of the substrate, a side of the drift layer facing away from the substrate has a first surface, and the drift layer has the first doping type, and the drift layer has a symmetry axis in a thickness direction;

[0052] Step S300: forming a barrier layer in the JFET region;

[0053] Step S400: forming a first body region on both sides of the barrier layer, the first body region being located in the drift layer, a surface of the first body region facing away from the substrate being located in the first surface, the first body region being symmetrically located in the drift layer along the symmetry axis, and the first body region having a second doping type.

[0054] In order to reduce the on-state resistance of the device, the doping concentration of the JFET region is usually increased. However, when the device is in a blocking state, a higher electric field will be generated in the gate oxide layer on the top of the region, causing breakdown of the gate oxide layer. The present application provides a blocking layer in the JFET region between the adjacent first body regions, thereby reducing both the on-state resistance of the device and the risk of breakdown of the gate oxide layer of the device in a blocking state. The barrier layer is provided to protect the field effect transistor and improve the reliability of the device.

[0055] The exemplary embodiments of the method for preparing a field effect transistor provided according to the present invention will be described in more detail below in conjunction with the accompanying drawings. However, these exemplary embodiments can be implemented in a variety of different forms and should not be construed as being limited to the embodiments described herein. It should be understood that these embodiments are provided to make the disclosure of this application thorough and complete, and to fully convey the concepts of these exemplary embodiments to those of ordinary skill in the art.

[0056] First, if Figure 3 As shown, step S100 is performed: providing a substrate 10, wherein the substrate 10 has a first doping type.

[0057] Specifically, a substrate 10 having a first doping type is provided, wherein the substrate 10 may be silicon carbide.

[0058] After the step of providing a substrate, as Figures 4 to 6 As shown, step S200 is performed: a drift layer 20 is formed on one side of the substrate 10, and a JFET region 201 is formed in the drift layer 20, wherein the drift layer 20 is located on one side of the substrate 10, and the side of the drift layer 20 facing away from the substrate 10 has a first surface, and the drift layer 20 has the first doping type, and the drift layer 20 has a symmetry axis in the thickness direction.

[0059] In some optional embodiments, such as Figure 4 As shown, the step of forming the above-mentioned barrier layer 40 includes: etching the above-mentioned JFET region 201 so that the above-mentioned JFET region 201 has a first groove; depositing a barrier material on the side of the above-mentioned preliminary drift layer 202 away from the above-mentioned substrate 10, and the above-mentioned barrier material fills the above-mentioned first groove to form the above-mentioned barrier layer 40.

[0060] In the above optional implementation, if Figure 4As shown, a preliminary drift layer 202 is first formed on the substrate 10, ions are implanted into the preliminary drift layer 202 to form a JFET region 201, and etching is performed in the middle of the JFET region 201 to form a first groove, the depth of the first groove can be 0.2μm~0.5μm, and a blocking material such as silicon dioxide or silicon nitride is filled on the preliminary drift layer 202. The blocking material fills the first groove, and then the excess blocking material is patterned to form a blocking layer 40.

[0061] In some optional embodiments, such as Figure 5 and Figure 6 As shown, the steps of forming multiple first body regions 30 include: performing a first ion implantation in the preliminary drift region to form multiple first preliminary body regions 301; performing a second ion implantation in the above-mentioned first preliminary body regions 301 to form a first sub-doping region 31; performing a third ion implantation in the above-mentioned first preliminary body regions 301 to form a second sub-doping region 32, and the above-mentioned second sub-doping region 32 is located on the side of the above-mentioned first sub-doping region 31 away from the above-mentioned barrier layer 40, forming the above-mentioned first body region 30.

[0062] In the above optional implementation, if Figure 5 As shown, after the step of forming the barrier layer 40, ion implantation is performed again in the preparatory drift region to form a first sub-preparatory region 330, and ion implantation is performed in the first sub-preparatory region 330 to form a second sub-preparatory region 340. The first sub-preparatory region 330 and the second sub-preparatory region 340 form the above-mentioned first preparatory region 301, and the doping concentration of the second sub-preparatory region 340 is lower than that of the first sub-preparatory region 330.

[0063] In the above optional implementation, if Figure 6 As shown, ion implantation is performed in the first preliminary region to form a first sub-doping region 31 and a second sub-doping region 32 , and the first sub-doping region 31 and the second sub-doping region 32 have different doping types.

[0064] After the steps of forming the first sub-doping region and the second sub-doping region, Figure 7 As shown, a preliminary gate oxide layer and a preliminary gate are formed on the side of the drift layer 20 away from the substrate 10, and then the preliminary gate oxide layer and the preliminary gate are simultaneously patterned to form a gate oxide layer 51 and a gate 52, and the gate oxide layer 51 and the gate 52 form a gate structure 50, as shown in FIG. Figure 8 As shown, an insulating layer 60 is formed on the gate structure 50. Figure 1 As shown, a source electrode 70 is formed on the insulating layer 60, and a drain electrode 80 is formed on the side of the substrate 10 away from the drift layer 20, wherein the insulating layer 60 has an opening for electrically connecting the gate electrode 52 to the source electrode 70, and the source electrode 70 contacts the second sub-doping region 32 to form an ohmic contact, thereby improving the performance of the field effect transistor.

[0065] Exemplarily, the method for preparing a field effect transistor provided in the present application comprises the following steps: Figure 3 As shown, a silicon carbide substrate 10 having a first doping type is provided, such as Figure 4 As shown, an epitaxial layer with the same type of doping as the substrate 10 is formed as a preliminary drift layer 202, doping is performed in the preliminary drift layer 202 to form a JFET region 201, a first groove is formed by etching at the center of the JFET region 201, a silicon dioxide barrier material is deposited on the preliminary drift layer 202 so that the barrier material fills the first groove, and the excess barrier material is removed to obtain a barrier layer 40. Figure 5 As shown, ion implantation is performed in the preparatory drift region to form a P-type first sub-preparatory region 330, and ion implantation is performed in the first sub-preparatory region 330 to form a P-type second sub-preparatory region 340. The doping concentration of the second sub-preparatory region 340 is lower than that of the first sub-preparatory region 330. The first sub-preparatory region 330 and the second sub-preparatory region 340 form the above-mentioned first preparatory region 301. Figure 6 As shown, an N-type first sub-doping region 31 and a P-type second sub-doping region 32 are formed in the first preliminary body region, thereby forming a first sub-body region 33 and a second sub-body region 34, which form a first body region 30, and the structure formed above is subjected to high temperature treatment. Figure 7 As shown, a preliminary gate oxide layer and a preliminary gate are formed on the barrier layer 40, and then the preliminary gate oxide layer and the preliminary gate are simultaneously patterned to form a gate oxide layer 51 and a gate 52, the gate oxide layer 51 and the gate 52 form a gate structure 50, the material of the gate oxide layer 51 is silicon dioxide, and the material of the gate 52 is polysilicon, as shown in FIG. Figure 8 As shown, an insulating layer 60 is formed on the gate structure 50. Figure 1 As shown, a source electrode 70 is formed on the insulating layer 60, the source electrode 70 contacts the first body region 30, and a drain electrode 80 is formed on the other side of the substrate 10. The source electrode 70 and the drain electrode 80 are composed of metal layers of titanium, nickel and silver, thereby obtaining a field effect transistor.

[0066] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0067] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:

[0068] An embodiment of the present application provides a field effect transistor. Usually, in order to reduce the on-resistance of the device, the doping concentration of the JFET region is increased. However, in this case, when the device is in a blocking state, a high electric field will be generated at the gate oxide layer, especially in the middle region of the JFET, which can easily cause the gate oxide layer to break down. The present application sets a blocking layer at the middle position of the JFET region, which can reduce the risk of the gate oxide layer being broken down, thereby protecting the field effect transistor. Under the protection of the blocking layer, the JFET region can have a very high doping concentration, which not only reduces the on-resistance of the device, but also improves the reliability of the device in the blocking state.

[0069] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. A field effect transistor, characterized in that: include: a substrate having a first doping type; A drift layer, located on one side of the substrate, the drift layer comprising a JFET region, a side of the drift layer facing away from the substrate having a first surface, the drift layer having the first doping type, and the drift layer having a symmetry axis in a thickness direction; A barrier layer located in the JFET region; A plurality of first body regions are located on both sides of the barrier layer, a surface of the first body region facing away from the substrate is located in the first surface, the first body region is symmetrically located in the drift layer along the symmetry axis, and the first body region has a second doping type.

2. The field effect transistor according to claim 1, characterized in that The field effect transistor further includes a first sub-doping region and a second sub-doping region, wherein: The first sub-doping region is located at a side of the second sub-doping region close to the barrier layer, the first sub-doping region has a first doping type, and the second sub-doping region has a second doping type.

3. The field effect transistor according to claim 2, characterized in that: The first body region includes a first sub-body region and a second sub-body region, the second sub-body region is located on a side of the first sub-body region away from the substrate, the second sub-body region is located on a side of the first sub-doping region away from the second sub-doping region, and the doping concentration of the second sub-body region is lower than the doping concentration of the first sub-body region.

4. The field effect transistor according to claim 3, characterized in that: The field effect transistor further includes a gate structure, and the gate structure is located on a side of the barrier layer away from the drift layer.

5. The field effect transistor according to claim 4, characterized in that: The field effect transistor further includes an insulating layer, and the insulating layer is located on a side of the gate structure away from the drift layer.

6. The field effect transistor according to claim 1, characterized in that The thickness of the barrier layer in the drift layer is 0.2 μm-0.5 μm.

7. The field effect transistor according to any one of claims 1 to 6, characterized in that The field effect transistor further includes a source, an insulating layer and a drain, wherein: the insulating layer is located on a side of the drift layer away from the substrate, the source is located on a side of the insulating layer away from the substrate, and the drain is located on a side of the substrate away from the drift layer.

8. A method for preparing a field effect transistor, characterized in that: For preparing a field effect transistor according to any one of claims 1 to 7, the preparation method comprising: providing a substrate, the substrate having a first doping type; A drift layer is formed on one side of the substrate, and a JFET region is formed in the drift layer, wherein the drift layer is located on one side of the substrate, a side of the drift layer facing away from the substrate has a first surface, the drift layer has the first doping type, and the drift layer has a symmetry axis in a thickness direction; forming a barrier layer in the JFET region; A first body region is formed on both sides of the barrier layer, the first body region is located in the drift layer, a surface of the first body region facing away from the substrate is located in the first surface, the first body region is symmetrically located in the drift layer along the symmetry axis, and the first body region has a second doping type.

9. The preparation method according to claim 8, characterized in that: The step of forming the barrier layer comprises: Performing an etching process on the JFET region so that the JFET region has a first groove; A barrier material is deposited on a side of the preliminary drift layer facing away from the substrate, and the barrier material fills the first groove to form the barrier layer.

10. The preparation method according to claim 8, characterized in that: The step of forming a plurality of first body regions comprises: Performing a first ion implantation in the preliminary drift region to form a plurality of first preliminary body regions; Performing a second ion implantation in the first preliminary region to form a first sub-doping region; A third ion implantation is performed in the first preliminary body region to form a second sub-doping region, wherein the second sub-doping region is located at a side of the first sub-doping region away from the barrier layer to form the first body region.

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