Bottom electrode-insulating layer-top electrode structure, preparation method thereof and microelectronic device

Abstract

The invention relates to the field of microelectronic devices, in particular to a bottom electrode-insulating layer-top electrode structure, a preparation method thereof and a microelectronic device. The preparation method comprises the following steps: providing a substrate, and forming a bottom electrode on the surface of the substrate; forming an insulating layer on the bottom electrode, wherein the insulating layer is made of metal oxide; sequentially forming a buffer layer and a top electrode on the insulating layer, wherein the buffer layer is made of a selenium material or a tellurium material; and the buffer layer is removed through an annealing process, so that the insulating layer and the top electrode are in lossless contact, and a bottom electrode-insulating layer-top electrode structure is obtained. According to the method, the buffer layer is introduced between the insulating layer and the top electrode, so that damage-free and stress-free contact between the insulating layer and the top electrode is realized, local stress and damage introduced into the insulating layer in the direct deposition process of the top electrode are reduced, the yield of the device is improved, and the volatility of the device is reduced; and large-scale device integration can be realized.

Description

Technical Field

[0001] The present invention relates to the field of microelectronic devices, and in particular to a bottom electrode-insulating layer-top electrode structure and a preparation method thereof, and a microelectronic device. Background Art

[0002] The bottom electrode-insulating layer-top electrode structure can realize functional devices such as memristors and neuromorphic devices. By applying voltage between the two layers of electrodes, the resistance state in the insulating layer is changed, thereby realizing information storage and neuromorphic computing functions. The quality of the insulating layer has a great influence on the devices based on this structure. If there are defects, stress, etc. in the insulating layer, it will affect the change of the resistance state in the insulating layer, and then affect the yield of the device, causing the device to have greater volatility, limiting the application of related devices. Studies have found that damage and stress may be introduced into the insulating layer during the deposition of the top electrode, which may reduce the yield of the device and increase the volatility of the device. Some studies have proposed to reduce the damage and stress introduced in the insulating layer by mechanically transferring the top electrode (Highly Reliable Low-Voltage Memristive Switching and Artificial Synapse Enabled by van der Waals Integration. Matter 2020, 2, 965-976. DOI: 10.1016 / j.matt.2020.01.011. and Highly Stable HfO2 Memristors through van der Waals Electrode Lamination and Delamination. Nano Lett. 2023, 23, 9928-9935. DOI: 10.1021 / acs.nanolett.3c02888), but this mechanical transfer method is prone to cracks and wrinkles, and introduces bubbles and impurities at the interface, making it difficult to achieve large-scale consistency, and therefore difficult to achieve large-scale device integration.

[0003] Therefore, the prior art still needs to be improved and developed. Summary of the invention

[0004] In view of the above-mentioned deficiencies in the prior art, the object of the present invention is to provide a bottom electrode-insulating layer-top electrode structure and a preparation method and a microelectronic device thereof, aiming to solve the problem that the existing method will bring new problems and difficulty in achieving large-scale device integration when reducing the damage and stress introduced by the top electrode to the insulating layer.

[0005] Specifically, the technical solution of the present invention is as follows:

[0006] A first aspect of the present invention provides a method for preparing a bottom electrode-insulating layer-top electrode structure, comprising the steps of:

[0007] Providing a substrate, and forming a bottom electrode on a surface of the substrate;

[0008] forming an insulating layer on the bottom electrode, wherein the material of the insulating layer comprises a metal oxide;

[0009] forming a buffer layer and a top electrode in sequence on the insulating layer, wherein the material of the buffer layer is a selenium material or a tellurium material;

[0010] The buffer layer is removed by an annealing process, so that the insulating layer and the top electrode are in lossless contact, thereby obtaining the bottom electrode-insulating layer-top electrode structure.

[0011] A second aspect of the present invention provides a bottom electrode-insulating layer-top electrode structure prepared by the preparation method of the present invention.

[0012] A third aspect of the present invention provides a microelectronic device, which includes the bottom electrode-insulating layer-top electrode structure described in the present invention.

[0013] Beneficial effects: The method of the present invention achieves damage-free and stress-free contact between the insulating layer and the top electrode by introducing a buffer layer between the insulating layer and the top electrode, reduces the local stress and damage introduced in the insulating layer during the direct deposition of the top electrode, thereby improving the yield of the device and reducing the volatility of the device; and the method of the present invention can avoid the disadvantages of easily generating cracks and wrinkles through mechanical transfer, and introducing bubbles and impurities at the interface, can achieve large-scale consistency, and can realize large-scale device integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 The present invention provides a schematic flow chart of a method for preparing a bottom electrode-insulating layer-top electrode structure.

[0015] Figure 2 This is a schematic diagram of the process flow for preparing the bottom electrode-insulating layer-top electrode structure provided in Example 1. DETAILED DESCRIPTION

[0016] The present invention provides a bottom electrode-insulating layer-top electrode structure and a preparation method thereof and a microelectronic device. In order to make the purpose, technical solution and effect of the present invention clearer and more specific, the present invention is further described in detail below. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0017] The present invention proposes a new preparation method for the basic structure of "bottom electrode-insulating layer-top electrode" in microelectronic devices such as memristors and neuromorphic devices. The basic idea is: introducing a buffer layer between the insulating layer and the top electrode. The buffer layer material has a low deposition temperature and a suitable volatilization temperature, so it will not damage the insulating layer during the deposition process, reducing the damage and stress to the insulating layer during the direct deposition of the top electrode. The buffer layer can be removed by a simple annealing process at a suitable temperature, thereby achieving damage-free and stress-free contact between the insulating layer and the top electrode, thereby improving the yield of the device and reducing the volatility of the device.

[0018] According to one embodiment of the present invention, a method for preparing a bottom electrode-insulating layer-top electrode structure is provided, which comprises the steps of:

[0019] S1, providing a substrate, and forming a bottom electrode on the surface of the substrate;

[0020] S2, forming an insulating layer on the bottom electrode, wherein the material of the insulating layer comprises a metal oxide;

[0021] S3, sequentially forming a buffer layer and a top electrode on the insulating layer, wherein the material of the buffer layer is a selenium material or a tellurium material;

[0022] S4. Remove the buffer layer through an annealing process to ensure lossless contact between the insulating layer and the top electrode, thereby obtaining the bottom electrode-insulating layer-top electrode structure.

[0023] The embodiment of the present invention introduces a buffer layer between the insulating layer and the top electrode, and the buffer layer material is selected from selenium materials or tellurium materials with a low deposition temperature and a suitable volatilization temperature. Since the buffer layer material has a low deposition temperature, it will not cause damage to the insulating layer during the deposition process, reducing the damage and stress on the surface of the insulating layer during the direct deposition of the top electrode. In addition, the buffer layer material has a suitable volatilization temperature and can be removed by a simple annealing process at a suitable temperature, thereby achieving damage-free and stress-free contact between the insulating layer and the top electrode, thereby improving the yield of the device and reducing the volatility of the device. The method proposed in the embodiment of the present invention is simple and efficient, and avoids the shortcomings of cracks and wrinkles that are easily generated by mechanical transfer, and the introduction of bubbles and impurities at the interface, and can achieve large-scale consistency and large-scale device integration.

[0024] In step S1, in one embodiment, the step of forming a bottom electrode on the surface of the substrate specifically includes:

[0025] S11, coating a photoresist on the surface of the substrate, and performing a preset bottom electrode patterning process on the substrate by using a photolithography process;

[0026] S12, depositing a bottom electrode material, removing the photoresist on the substrate, and forming a patterned bottom electrode on the surface of the substrate.

[0027] In one embodiment, the steps of step S11 specifically include: applying photoresist on the surface of the substrate by spin coating, pre-baking the substrate, exposing a preset bottom electrode pattern on the substrate by a laser direct writing lithography machine, and obtaining a patterned substrate after development.

[0028] In one embodiment, step S12 specifically includes: depositing a bottom electrode material on a patterned substrate, removing the photoresist on the substrate by a lift-off process, and obtaining a patterned bottom electrode formed on the surface of the substrate.

[0029] In the present invention, the material and shape of the substrate are conventional substrates in the prior art and are not limited here.

[0030] In the present invention, a preset photolithography pattern can be prepared by using photoresist and photolithography process at a specific position of the substrate according to specific needs. The specific shape of the photolithography pattern can be set according to actual needs, and the specific shape is not limited here. After depositing the bottom electrode material, the photoresist on the substrate needs to be removed to form a predetermined patterned bottom electrode structure. The use of photoresist and photolithography process to pattern the substrate, and the subsequent removal of the photoresist are all conventional techniques in the art and are not limited here.

[0031] In step S2 , in one embodiment, forming an insulating layer on the bottom electrode is intended to mean forming an insulating layer both on the patterned bottom electrode and on the substrate not covered by the bottom electrode.

[0032] In one embodiment, the insulating layer is made of a non-conductive metal oxide, preferably HfO2, Al2O3 or VO2.

[0033] In one embodiment, the thickness of the insulating layer is 0.5 nm to 50 nm. For example, the thickness of the insulating layer can be 0.5 nm, 1 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, or 50 nm. Within this thickness range, the device has a lower operating voltage and energy consumption.

[0034] In step S3, in one embodiment, the thickness of the buffer layer is 2 nm to 50 nm. For example, the thickness of the buffer layer can be 2 nm, 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, or 50 nm. The thickness of the buffer layer is within this range and can be easily removed by an annealing process.

[0035] In step S4, in one embodiment, the annealing process is an atmosphere annealing process or a vacuum annealing process, which can be selected according to the different buffer layer materials used. In the present invention, an atmosphere annealing process is preferably selected, wherein the gas used is one or more of hydrogen, argon and nitrogen, the annealing temperature is 120°C to 200°C, and the annealing time is 0.5h to 2h. For example, the annealing temperature can be 120°C, 130°C, 140°C, 150°C, 160°C, 170°C, 180°C, 190°C, 200°C; the annealing time can be 0.5h, 1h, 1.5h, 2h.

[0036] In this embodiment, the buffer layer is removed by an annealing process, so that there is lossless contact between the insulating layer and the top electrode, thereby avoiding the problem of damage and stress on the surface of the insulating layer caused by directly depositing the top electrode on the insulating layer.

[0037] According to an embodiment of the present invention, the material of the bottom electrode is the same as or different from the material of the top electrode, which can be selected according to the working mechanism of the device.

[0038] In the present invention, the bottom electrode material and the top electrode material can be selected from existing electrode materials, and no limitation is made here.

[0039] According to an embodiment of the present invention, the preparation method further comprises: before the step of sequentially forming a buffer layer and a top electrode on the insulating layer, applying a photoresist on the insulating layer, and patterning the insulating layer into a preset top electrode by a photolithography process; before the step of removing the buffer layer by an annealing process, removing the photoresist on the insulating layer. At this time, the intermediate structure of bottom electrode-insulating layer-buffer layer-top electrode is prepared.

[0040] In the present invention, the layers in the bottom electrode-insulating layer-top electrode structure can be prepared by magnetron sputtering technology, thermal evaporation technology, electron beam evaporation technology or vacuum arc evaporation technology, and the relevant coating technologies are conventional technologies in the field and are not limited here.

[0041] According to one embodiment of the present invention, there is also provided a bottom electrode-insulating layer-top electrode structure prepared by the preparation method of the present invention.

[0042] According to one embodiment of the present invention, a microelectronic device is further provided, comprising the bottom electrode-insulating layer-top electrode structure described in the present invention.

[0043] According to one embodiment of the present invention, the microelectronic device is a memristor, a neuromorphic device, or the like.

[0044] like Figure 1As shown, a method for preparing a bottom electrode-insulating layer-top electrode structure provided by the present invention includes:

[0045] A substrate is provided, and a bottom electrode is formed on the surface of the substrate; an insulating layer (metal oxide film) is deposited on the bottom electrode; a buffer layer material is deposited on the insulating layer to form a buffer layer, and a top electrode material is deposited to form a top electrode; the buffer layer is removed by an annealing process, thereby obtaining the bottom electrode-insulating layer-top electrode structure of the present invention.

[0046] The present invention will be further described below by means of specific examples.

[0047] Example 1

[0048] This embodiment provides a method for preparing a bottom electrode-insulating layer-top electrode structure, which is specifically as follows:

[0049] The SiO2 / Si (285nm SiO2) substrate was ultrasonically cleaned with acetone, anhydrous ethanol, and deionized water for 5 minutes. After drying with a nitrogen gun, the residual water and oxygen on the surface of the substrate were removed by plasma cleaning. On the substrate, a photoresist with a thickness of 1μm was applied by spin coating. The substrate was pre-baked to evaporate the solvent in the photoresist and dry the film. The preset bottom electrode pattern was exposed on the substrate by a laser direct writing lithography machine, and a patterned substrate was obtained after development. An electron beam evaporation coating machine was used in a temperature of less than 10 -4 Pa, deposit a Ti (5nm) / Pt (30nm) thin film of bottom electrode material, and then remove the photoresist by lift-off process to obtain the bottom electrode structure on the substrate. Use atomic layer deposition process to deposit a 5nm thick HfO2 film as an insulating layer. Spin coating a photoresist with a thickness of 1μm on the substrate prepared with the insulating layer. Pre-bake the substrate to evaporate the solvent in the photoresist, and dry and shape the film. Expose the preset top electrode pattern on the substrate by laser direct writing photolithography machine, and obtain a patterned substrate after development. Use electron beam evaporation coating machine, in less than 10 -4 Pa, first deposit a buffer layer material Se (10nm) film as a buffer layer, and then deposit a top electrode material Ag (30nm) film as a top electrode. Then remove the photoresist through a lift-off process to obtain a bottom electrode-insulating layer-buffer layer-top electrode structure on the substrate. Then place it in an annealing furnace, pass argon gas at a gas flow rate of 200 standard cubic centimeters per minute (SCCM), annealing temperature of 150°C, annealing time of 4h, remove the Se material of the buffer layer, and obtain a Pt-HfO2-Ag structure. Figure 2 This is a schematic diagram of the process flow for preparing the bottom electrode-insulating layer-top electrode structure provided in this embodiment.

[0050] Example 2

[0051] This embodiment provides a method for preparing a bottom electrode-insulating layer-top electrode structure, which is specifically as follows:

[0052] The SiO2 / Si (285nm SiO2) substrate was ultrasonically cleaned with acetone, anhydrous ethanol, and deionized water for 5 minutes. After drying with a nitrogen gun, the residual water and oxygen on the surface of the substrate were removed by plasma cleaning. On the substrate, a photoresist with a thickness of 1μm was applied by spin coating. The substrate was pre-baked to evaporate the solvent in the photoresist and dry the film. The preset bottom electrode pattern was exposed on the substrate by a laser direct writing lithography machine, and a patterned substrate was obtained after development. An electron beam evaporation coating machine was used in a temperature of less than 10 -4 Pa, Ti (5nm) / Pt (30nm) film was deposited. The photoresist was removed by lift-off process to obtain the bottom electrode structure on the substrate. A 5nm thick Al2O3 film was deposited as an insulating layer by atomic layer deposition process. A photoresist with a thickness of 1μm was applied by spin coating on the substrate with the insulating layer prepared. The substrate was pre-baked to evaporate the solvent in the photoresist and the film was dried and fixed. The preset top electrode pattern was exposed on the substrate by laser direct writing lithography machine, and the patterned substrate was obtained after development. An electron beam evaporation coating machine was used in a temperature less than 10 -4 Pa vacuum, first deposit a Se (10nm) film as a buffer layer, and then deposit an Ag (30nm) film as a top electrode. The photoresist is removed by a lift-off process to obtain a bottom electrode-insulating layer-buffer layer-top electrode structure on the substrate. Then place it in an annealing furnace, pass argon gas at a gas flow rate of 200 standard cubic centimeters per minute (SCCM), annealing temperature of 150 ° C, annealing time of 4h, remove the Se material of the buffer layer, and obtain a Pt-Al2O3-Ag structure.

[0053] Example 3

[0054] This embodiment provides a method for preparing a bottom electrode-insulating layer-top electrode structure, which is specifically as follows:

[0055] The SiO2 / Si (285nm SiO2) substrate was ultrasonically cleaned with acetone, anhydrous ethanol, and deionized water for 5 minutes. After drying with a nitrogen gun, the residual water and oxygen on the surface of the substrate were removed by plasma cleaning. On the substrate, a photoresist with a thickness of 1μm was applied by spin coating. The substrate was pre-baked to evaporate the solvent in the photoresist and dry the film. The preset bottom electrode pattern was exposed on the substrate by a laser direct writing lithography machine, and a patterned substrate was obtained after development. An electron beam evaporation coating machine was used in a temperature of less than 10 -4Pa, Ti (5nm) / Pt (30nm) thin film is deposited. The photoresist is removed by lift-off process to obtain the bottom electrode structure on the substrate. A 5nm thick VO2 film is deposited as an insulating layer by magnetron sputtering process. A photoresist with a thickness of 1μm is applied by spin coating on the substrate with the insulating layer prepared. The substrate is pre-baked to evaporate the solvent in the photoresist and the film is dried and fixed. The preset top electrode pattern is exposed on the substrate by laser direct writing photolithography machine, and a patterned substrate is obtained after development. An electron beam evaporation coating machine is used to coat the top electrode pattern on the substrate at a temperature of less than 10 -4 Pa, first deposit a Se (10nm) film as a buffer layer, and then deposit a Ti (5nm) / Pt (30nm) film as a top electrode. The photoresist is removed by a lift-off process to obtain a bottom electrode-insulating layer-buffer layer-top electrode structure on the substrate. Then place it in an annealing furnace, pass argon gas at a gas flow rate of 200 standard cubic centimeters per minute (SCCM), annealing temperature of 150 ° C, annealing time of 4h, remove the Se material of the buffer layer, and obtain a Ti / Pt-VO2-Ti / Pt structure.

[0056] Example 4

[0057] This embodiment provides a method for preparing a bottom electrode-insulating layer-top electrode structure, which is specifically as follows:

[0058] The SiO2 / Si (285nm SiO2) substrate was ultrasonically cleaned with acetone, anhydrous ethanol, and deionized water for 5 minutes. After drying with a nitrogen gun, the residual water and oxygen on the surface of the substrate were removed by plasma cleaning. On the substrate, a photoresist with a thickness of 1μm was applied by spin coating. The substrate was pre-baked to evaporate the solvent in the photoresist and dry the film. The preset bottom electrode pattern was exposed on the substrate by a laser direct writing lithography machine, and a patterned substrate was obtained after development. An electron beam evaporation coating machine was used in a temperature of less than 10 -4 Pa, Ti (5nm) / Pt (30nm) thin film is deposited. The photoresist is removed by lift-off process to obtain the bottom electrode structure on the substrate. A 5nm thick VO2 film is deposited as an insulating layer by magnetron sputtering process. A photoresist with a thickness of 1μm is applied by spin coating on the substrate with the insulating layer prepared. The substrate is pre-baked to evaporate the solvent in the photoresist and the film is dried and fixed. The preset top electrode pattern is exposed on the substrate by laser direct writing photolithography machine, and a patterned substrate is obtained after development. An electron beam evaporation coating machine is used to coat the top electrode pattern on the substrate at a temperature of less than 10 -4Pa, first deposit a Se (5nm) film as a buffer layer, and then deposit a Ti (5nm) / Pt (30nm) film as a top electrode. The photoresist is removed by a lift-off process to obtain a bottom electrode-insulating layer-buffer layer-top electrode structure on the substrate. Then place it in an annealing furnace, introduce argon gas at a gas flow rate of 200 standard cubic centimeters per minute (SCCM), anneal at 150 ° C, and anneal for 4 hours to remove the Se material of the buffer layer and obtain a Ti / Pt-VO2-Ti / Pt structure.

[0059] It should be understood that the application of the present invention is not limited to the above examples. For ordinary technicians in this field, improvements or changes can be made based on the above description. All these improvements and changes should fall within the scope of protection of the claims attached to the present invention.

Claims

1. A method for preparing a bottom electrode-insulating layer-top electrode structure, characterized in that: Includes steps: Providing a substrate, and forming a bottom electrode on a surface of the substrate; forming an insulating layer on the bottom electrode, wherein the material of the insulating layer comprises a metal oxide; forming a buffer layer and a top electrode in sequence on the insulating layer, wherein the material of the buffer layer is a selenium material or a tellurium material; The buffer layer is removed by an annealing process, so that the insulating layer and the top electrode are in lossless contact, thereby obtaining the bottom electrode-insulating layer-top electrode structure.

2. The method for preparing a bottom electrode-insulating layer-top electrode structure according to claim 1, characterized in that: The thickness of the buffer layer is 2nm-50nm.

3. The method for preparing a bottom electrode-insulating layer-top electrode structure according to claim 1, characterized in that: The metal oxide is HfO2, Al2O3 or VO2.

4. The method for preparing a bottom electrode-insulating layer-top electrode structure according to claim 1, characterized in that: The thickness of the insulating layer is 0.5 nm to 50 nm.

5. The method for preparing a bottom electrode-insulating layer-top electrode structure according to claim 1, characterized in that: The annealing process is an atmosphere annealing process, wherein the gas used is one or more of hydrogen, argon and nitrogen, the annealing temperature is 120° C. to 200° C., and the annealing time is 0.5 h to 2 h.

6. The method for preparing a bottom electrode-insulating layer-top electrode structure according to claim 1, characterized in that: The material of the bottom electrode is the same as or different from that of the top electrode.

7. The method for preparing a bottom electrode-insulating layer-top electrode structure according to claim 1, characterized in that: The step of forming a bottom electrode on the substrate surface specifically includes: Applying photoresist on the surface of the substrate, and performing a preset bottom electrode patterning process on the substrate by using a photolithography process; The bottom electrode material is deposited, the photoresist on the substrate is removed, and a patterned bottom electrode is formed on the surface of the substrate.

8. The method for preparing a bottom electrode-insulating layer-top electrode structure according to claim 1, characterized in that: The preparation method further comprises: Before the step of sequentially forming a buffer layer and a top electrode on the insulating layer, a photoresist is coated on the insulating layer, and a predetermined top electrode patterning process is performed on the insulating layer by a photolithography process; Before the step of removing the buffer layer through an annealing process, the photoresist on the insulating layer is removed.

9. A bottom electrode-insulating layer-top electrode structure prepared by the preparation method according to any one of claims 1 to 8.

10. A microelectronic device, characterized in that: It includes the bottom electrode-insulating layer-top electrode structure as claimed in claim 9.

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