Area efficient asynchronous circuit generator

Abstract

An apparatus may include a controller programmed to receive information about a synchronized digital circuit including a plurality of Boolean gates, determine a critical path through each synchronized combined sub-circuit block of the digital circuit, identify a first set of Boolean gates of the plurality of Boolean gates located in the critical path, and determine a second set of Boolean gates of the plurality of Boolean gates located in the critical path. A hybrid equivalent gate is determined for each Boolean gate in the first set of Boolean gates, where the hybrid equivalent gate has a synchronous input, a dual-track asynchronous input, and a dual-track output, and a modified digital circuit is generated by replacing each Boolean gate in the first set of Boolean gates with a corresponding hybrid equivalent gate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Application No. 63 / 346,711, filed on May 27, 2022; the contents of which are incorporated by reference in their entirety into this application.

[0003] Federally Sponsored Research Statement

[0004] This invention was made with Government support under Contract No. 1916722 awarded by the National Science Foundation. The U.S. Government has certain rights in this invention. Technical Field

[0005] The present invention relates to asynchronous circuit design, and more particularly, to designing area efficient asynchronous circuit generators. Background Art

[0006] Most integrated circuit (IC) designs are synchronous in nature and utilize a global clock to ensure that data arrives at the inputs of combinatorial processing blocks at the same time. The faster the clock operates, the faster the IC can operate, thereby improving its performance. However, many mixed-signal ICs also utilize analog and radio frequency (RF) components. When a synchronous IC includes analog and RF components, a digital clock signal triggers the synchronized switching of transistors in the combinatorial logic gates. This in turn causes high-power spikes that can propagate through the circuit as digital noise, which can increase the noise floor of the analog and RF components, thereby reducing the signal-to-noise ratio (SNR) of these components, which can degrade their performance. In addition, due to the predictable or timed data processing, the synchronized power consumption of combinatorial processing blocks or synchronous ICs may make them vulnerable to side-channel attacks, which may expose sensitive data.

[0007] Therefore, in order to increase the SNR of mixed-signal ICs and reduce the vulnerability to side-chain attacks, asynchronous circuits can be utilized. One method of generating asynchronous circuits is to use null convention logic (NCL) gates. However, the use of NCL gates significantly increases the size of asynchronous circuits compared to synchronous circuits. Therefore, an improved method of generating asynchronous circuits is desired. Summary of the invention

[0008] In an embodiment, an apparatus may include a controller programmed to receive information about a synchronized digital circuit including a plurality of Boolean gates, determine a critical path through each synchronized combinational sub-circuit block of the digital circuit, identify a first group of Boolean gates in the plurality of Boolean gates that are located in the critical path, determine a hybrid equivalent gate for each Boolean gate in the first group of Boolean gates, wherein the hybrid equivalent gate has a synchronous input, a dual-rail asynchronous input, and a dual-rail output, and generate a modified digital circuit by replacing each Boolean gate in the first group of Boolean gates with a corresponding hybrid equivalent gate.

[0009] In another embodiment, a method may include receiving information about a synchronized digital circuit including a plurality of Boolean gates, determining a critical path through each synchronized combinational sub-circuit block of the digital circuit, identifying a first group of Boolean gates in the plurality of Boolean gates that are located in the critical path, determining a hybrid equivalent gate for each Boolean gate in the first group of Boolean gates, wherein the hybrid equivalent gate has a synchronous input, a dual-rail asynchronous input, and a dual-rail output, and generating a modified digital circuit by replacing each Boolean gate in the first group of Boolean gates with a corresponding hybrid equivalent gate.

[0010] In another embodiment, a digital circuit may include a plurality of Boolean gates. Each gate in a first set of Boolean gates along a critical path through each synchronized combinational subcircuit block of the digital circuit may include a hybrid equivalent gate. The hybrid equivalent gate may have a synchronous input, a dual-rail input, and a dual-rail output. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The embodiments described in the accompanying drawings are illustrative and exemplary in nature and are not intended to limit the present disclosure. The following illustrative detailed description can be understood when read in conjunction with the following drawings, in which similar structures are indicated with similar reference numerals, and in which:

[0012] Figure 1A schematically depicts an example NAND gate according to one or more embodiments shown and described herein;

[0013] Figure 1B schematically depicts a circuit diagram of the NAND gate of FIG. 1 according to one or more embodiments shown and described herein;

[0014] Figure 2A schematically depicts a null-convention logical equivalent NAND gate in accordance with one or more embodiments shown and described herein;

[0015] Figure 2B Schematically depicts a schematic diagram of a system according to one or more embodiments shown and described herein. Figure 2A The sub-circuit of the low output of the NAND gate;

[0016] Figure 2CSchematically depicts a schematic diagram of a system according to one or more embodiments shown and described herein. Figure 2A The high output sub-circuit of the NAND gate;

[0017] Figure 3 depicts a schematic diagram of a computing device according to one or more embodiments shown and described herein;

[0018] Figure 4 Depicts an embodiment according to one or more embodiments shown and described herein. Figure 3 A schematic diagram of a memory module of a computing device;

[0019] Figure 5 schematically depicts a critical path through a digital circuit according to one or more embodiments shown and described herein;

[0020] Fig. 6A schematically depicts an example or door according to one or more embodiments shown and described herein;

[0021] Figure 6B Schematically depicts a schematic diagram of a system according to one or more embodiments shown and described herein. Fig. 6A The circuit diagram of the OR gate;

[0022] Fig. 7A schematically depicts a null-convention logical equivalent OR gate in accordance with one or more embodiments shown and described herein;

[0023] Figure 7B Schematically depicts a schematic diagram of a system according to one or more embodiments shown and described herein. Fig. 7A The high output subcircuit of the OR gate;

[0024] Figure 7C Schematically depicts a schematic diagram of a system according to one or more embodiments shown and described herein. Fig. 7A The subcircuit of the low output of the OR gate;

[0025] Fig. 8A schematically depicts a hybrid OR gate according to one or more embodiments shown and described herein;

[0026] Figure 8B Schematically depicts Fig. 8A A high output subcircuit of a mixed OR gate;

[0027] Figure 8C Schematically depicts Fig. 8A A subcircuit of the low output of the mixed OR gate;

[0028] Fig. 9depicts a flow chart of a method for determining a hybrid equivalent gate in accordance with one or more embodiments shown and described herein;

[0029] Fig.10 depicts a flow chart of a method for converting a synchronous circuit to an asynchronous circuit according to one or more embodiments shown and described herein;

[0030] Fig.11 A table showing transistor counts for standard Boolean gates, NCL equivalent gates, and hybrid gates according to one or more embodiments shown and described herein; and

[0031] Fig.12 A table showing transistor counts for the standard reference circuit, the NCL equivalent circuit, and the hybrid equivalent circuit. DETAILED DESCRIPTION

[0032] Embodiments disclosed herein are directed to an area efficient asynchronous circuit generator. As discussed above, one way to both increase the SNR of an IC and reduce the IC's susceptibility to side channel attacks is to convert synchronous circuits to asynchronous circuits. Asynchronous circuits do not use clocks, thus reducing both the noise and security vulnerabilities introduced by such clocks.

[0033] One way to implement asynchronous circuits is to use NCL gates. Null Convention Logic is a symbolically complete logic that expresses processes completely in terms of logic itself and expresses asynchronous digital circuits intrinsically and conveniently. NCL circuits operate by allowing data to flow in waves. Data waves are processed only when all input data is available, which makes it self-synchronous. Since data is processed only when available, no timing assumptions are required, which guarantees data order and correct data arrival at the receiver under various gate, processing and line delays.

[0034] NCL gates are dual-rail, with two separate wires for each signal. One wire represents a logic "0" and one wire represents a logic "1", and handshaking, rather than clocking, is used to enable circuit elements to transfer data between elements at the appropriate time. Asynchronous registers and NCL logic gates allow the construction of completely delay-insensitive designs.

[0035] Asynchronous NCL circuits are implemented using threshold gates with hysteresis. A threshold gate has two or more inputs and a single output and is denoted by TH. mn , where if the gate is in its n of the input mThe output of a gate is asserted or set when the (threshold) has valid "data" on it. That is, when its threshold is reached, its output is asserted. The output remains asserted until all inputs have transitioned back to "empty" during the reset phase, which creates hysteresis. In addition to being clockless, NCL asynchronous circuits are also asynchronous or time-distributed and have low power consumption, which also helps prevent side-channel attacks. NCL gates are typically implemented by setting data to Vdd and empty to Vss.

[0036] Using NCL TH mn Asynchronous circuits implemented with gates are particularly good at mitigating potential data leakage from ICs. Specifically, because synchronous circuits are all clocked, it is relatively simple for an untrusted agent to reverse engineer information from indirect measurements taken from the IC. For asynchronous circuits without clocks, this is even more difficult for an untrusted agent. In addition, the lack of a clock reduces the propagation of noise through the circuit.

[0037] However, one of the drawbacks of NCL asynchronous circuit design is that a large area overhead is required for asynchronous circuits that are equivalent to synchronous circuit logic. For example, Figure 1A An example 2-input NAND gate 100 is shown, and Figure 1B FIG. 1 shows a circuit diagram of a NAND gate 100. Figure 1A As described in , the NAND gate 100 has two inputs A and B and a single output Z. Figure 1B As shown in FIG. 1 , NAND gate 100 utilizes four metal oxide semiconductor (MOS) field effect transistors (FETs).

[0038] On the other hand, Figure 2B The NCL equivalent NAND gate 200 is shown. Figure 2A and Figure 2B FIG. 2 shows a circuit diagram for implementing the NCL NAND gate 200. Figure 2A As shown in FIG. 1 , NCL NAND gate 200 has a dual rail input with lines A1 and A0 , a dual rail input with lines B1 and B0 , and a dual rail output with lines Z1 and Z0 . Figure 2B FIG. 1 shows a circuit diagram of a threshold gate TH22 driving a low output Z0, and FIG. Figure 2C The circuit diagram of threshold gate TH12 driving high output Z1 is shown. NCL NAND gate 200 utilizes 14 FETs between two threshold gates TH22 and TH12. In general, the circuit scale of NCL equivalent gates is usually 2.5 to 3.5 times that of their standard logic equivalent gates.

[0039] Due to the area overhead of NCL gates, the cost of asynchronous versions of standard circuits can be extremely expensive. Specifically, one method of converting a synchronous circuit to an asynchronous circuit is to replace all or part of the gates in the standard circuit with NCL asynchronous equivalent gates. However, because of the increase in the size of NCL asynchronous gates as discussed above, this can greatly increase the size and cost of the asynchronous circuit compared to the synchronous circuit.

[0040] One approach to reducing the increased size of converting a synchronous circuit to an asynchronous circuit is to replace only the gates along the critical path of the circuit. However, NCL gates require signal conditioning circuitry, which adds a delay to the arrival time of the input signal driving the logic gate. Therefore, replacing the gates of a synchronous circuit along the critical path may result in a modified or different critical path. Therefore, it may be necessary to replace all of the gates of a synchronous circuit with NCL gates, which results in a large increase in circuit size, or to continually determine new critical paths and redesign the asynchronous circuit accordingly, which is difficult to achieve.

[0041] Therefore, hybrid gates are disclosed in embodiments herein. The hybrid gates disclosed herein include all required signal conditioning and, therefore, do not increase combinatorial input delays or change the critical path of the circuit. Thus, the hybrid gates disclosed herein can be used to replace only gates along the critical path of a synchronous circuit in order to convert a synchronous circuit to an asynchronous circuit.

[0042] Now go to Figure 3 , shows a schematic diagram of a computing device 300. The computing device 300 can be used to convert a synchronous circuit into an asynchronous circuit, as described herein. Figure 3 As shown in FIG. 3 , computing device 300 includes a processor 302 , a communication path 304 , one or more memory modules 306 , and a data storage component 308 , details of which are described in subsequent paragraphs.

[0043] Processor 302 can be any device capable of executing machine-readable and executable instructions. Therefore, processor 302 can be a controller, an integrated circuit, a chip, a calculator, or any other computing device. Processor 302 is coupled to a communication path 304, which provides signal interconnectivity between the various modules of computing device 300. Therefore, communication path 304 can allow the modules coupled to communication path 304 to operate in a distributed computing environment. Specifically, each module can operate as a node that can send and / or receive data. As used herein, the term "communicatively coupled" means that coupled components can exchange data signals with each other, such as, for example, electrical signals via a conductive medium, electromagnetic signals via air, optical signals via optical waveguides, and the like.

[0044] Thus, the communication path 304 may be formed from any medium capable of transmitting a signal, such as, for example, a wire, a conductive trace, an optical waveguide, and the like. In some embodiments, the communication path 304 may facilitate the transmission of wireless signals such as Wi-Fi, Bluetooth®, near field communication (NFC), and the like. In addition, the communication path 304 may be formed from a combination of media capable of transmitting a signal. In one embodiment, the communication path 304 includes a combination of conductive traces, wires, connectors, and buses that cooperate to allow transmission of electrical data signals to components such as processors, memories, sensors, input devices, output devices, and communication devices. Thus, the communication path 304 may include a CAN bus, a VAN bus, and the like. Furthermore, it should be noted that the term "signal" means a waveform (e.g., electrical, optical, magnetic, mechanical, or electromagnetic) capable of propagating through a medium, such as DC, AC, a sine wave, a triangle wave, a square wave, vibrations, and the like.

[0045] The computing device 300 includes one or more memory modules 306 coupled to the communication path 304. The one or more memory modules 306 may include RAM, ROM, flash memory, hard disk drive, or any device capable of storing machine-readable and executable instructions so that the machine-readable and executable instructions can be accessed by the processor 302. The machine-readable and executable instructions may include logic or algorithms written in any programming language of any generation (e.g., 1GL, 2GL, 3GL, 4GL, or 5GL), such as, for example, a machine language that can be directly executed by a processor, or an assembly language, object-oriented programming (OOP), a scripting language, microcode, etc., which can be compiled or assembled into machine-readable and executable instructions and stored on the one or more memory modules 306. Alternatively, the machine-readable and executable instructions may be written in a hardware description language (HDL), such as logic implemented via a field programmable gate array (FPGA) configuration or an application-specific integrated circuit (ASIC), or other equivalents. Therefore, the methods described herein may be implemented in any conventional computer programming language, as pre-programmed hardware elements, or as a combination of hardware and software components.

[0046] Computing device 300 includes data storage component 308. Data storage component 308 can store data used by various components of computing device 300. In addition, data storage component 308 can input data related to synchronous circuits to be converted to asynchronous.

[0047] Reference now Figure 4, schematically illustrates a memory module 306 of a computing device 300. The memory module 306 includes a data input module 400, a critical path determination module 402, an NCL gate determination module 404, a hybrid gate determination module 406, a handshake trigger insertion module 408, and a latch insertion module 410. Each of the data input module 400, the critical path determination module 402, the NCL gate determination module 404, the hybrid gate determination module 406, the handshake trigger insertion module 408, and the latch insertion module 410 may be a program module in the form of an operating system, an application program module, and other program modules stored on one or more memory modules 306. Such program modules may include, but are not limited to, routines, subroutines, programs, objects, components, data structures, etc. for performing specific tasks or executing specific data types, which will be described below.

[0048] The data input module 400 receives data about a synchronous circuit to be converted into an asynchronous circuit. Specifically, the data input module 400 receives data indicating a circuit design of the synchronous circuit. In the illustrated example, the data input module 400 receives a structured Verilog netlist indicating a circuit design of the synchronous circuit. However, in other examples, the data input module 400 may receive data about the synchronous circuit in other formats.

[0049] In an embodiment, the circuit design received by data input module 400 includes a plurality of logic gates. Computing device 300 may generate a modified circuit design that replaces a subset of the logic gates of the input circuit with hybrid gates as disclosed herein.

[0050] Still reference Figure 4 , the critical path determination module 402 determines the critical delay path through all combinational sub-circuit blocks of the circuit design received by the data input module 400. This can be accomplished using a variety of known techniques. Specifically, the critical path determination module 402 can determine the critical path by performing an O(N•log(N)) breadth-first search, where N is the number of nodes in the graph representing the combinational circuit.

[0051] Figure 5 A portion of an example circuit 500 is shown having combinatorial logic including a plurality of logic gates. Figure 5 The critical path 502 of the circuit 500 is shown in FIG. Figure 5 In the example circuit 500 of FIG. 5 , the critical path determination module 402 can identify the critical path 502, and the computing device 300 can replace the logic gates in the critical path 502 with the hybrid gates, as further disclosed below. By replacing only the gates in the critical path with the hybrid gates, the minimum number of gates is replaced, thereby minimizing the increase in the size of the resulting asynchronous circuit.

[0052] Return to reference Figure 4 , the NCL gate determination module 404 may determine the NCL equivalent gates for each logic gate in the critical path identified by the critical path determination module 402. In an embodiment, the NCL gate determination module 404 may use direct replacement or other known techniques to determine the NCL equivalent gates for each logic gate in the identified critical path.

[0053] Fig. 6A shows a standard 2-input OR gate 600, and Figure 6B FIG. 4 shows the circuit design of the OR gate 600. Fig. 6A As shown in FIG, OR gate 600 has two Boolean input signals A and B, and a single Boolean output signal Z. Each of signals A, B, and Z may have a Boolean value of either logic "1" or logic "0".

[0054] Fig. 7A An NCL equivalent OR gate 700 is shown. Fig. 7A As shown in FIG. 1 , the OR gate 700 includes two dual-rail input signals A (A1 and A0 lines) and B (B1 and B0 lines), and a dual-rail output signal Z (Z1 and Z0 lines). Each dual-rail signal has two lines of logic "1" and logic "0" driven by two sub-circuits. Figure 7B A first subcircuit or threshold gate 702 is shown for driving a high output Z1, and Figure 7C A second subcircuit or threshold gate 704 is shown for driving the low output Z0.

[0055] The NCL threshold gate consists of four nets, a first net that sets Z, a second net that resets Z, a third net that holds Z at Vss, and a fourth net that holds Z at Vdd. Figure 7C In the example of , threshold gate 704 includes a first network 706 that sets Z, a second network 708 that resets Z, a third network 710 that holds Z at Vss, and a fourth network 712 that holds Z at Vdd. Figure 7B In the example of , threshold gate 702 includes a first network 714 that sets Z and a second network 716 that resets Z. However, for threshold gate 702, a third network that holds Z at Vss and a fourth network that holds Z at Vdd are not required.

[0056] Return to reference Figure 4, the hybrid gate determination module 406 can replace each gate in the critical path determined by the critical path determination module 402 with a hybrid gate, as disclosed herein. For reliable asynchronous circuits, replacing Boolean logic gates in the critical path with hybrid equivalent gates must not change the critical path. As a result of this assertion, all non-critical path (standard Boolean) signal values ​​arrive at the critical path hybrid gate inputs before the critical path asynchronous NCL signals.

[0057] The hybrid gates disclosed herein have two types of inputs, standard Boolean inputs and dual-rail asynchronous NCL inputs. Since hybrid gates are creating asynchronous paths through combinatorial blocks, they only have dual-rail asynchronous outputs. Therefore, except for rare cases like specific combinatorial block inputs, hybrid gates only have a single dual-rail NCL input, and the other inputs will be standard Boolean inputs. For a standard 2-input gate, the hybrid equivalent gate will have one dual-rail NCL input and one Boolean input. For a standard 3-input gate, the hybrid equivalent gate will have one dual-rail NCL input and two Boolean inputs. For a standard gate with additional inputs, the hybrid equivalent gate will have additional Boolean inputs.

[0058] To ensure compliance with the above assertions, the hybrid gate must require no external signal conditioning on its inputs and the hybrid gate design must ensure that the signal propagation delay through the hybrid gate is greater than or equal to the delay through the Boolean gate it replaces. This is usually not a problem because the hybrid gate has at least two levels of transistor delay and additional delay can be added by careful transistor sizing. However, this should be verified before manufacturing or implementation.

[0059] As discussed above, in order to avoid the required signal conditioning of the NCL gates changing the critical path of the circuit, the disclosed hybrid gate includes signal conditioning. In this way, the hybrid gate can be directly inserted into the critical path. Its single dual-rail NCL input can be directly interfaced to the NCL output of the previous hybrid gate in the critical path. If the hybrid gate is the first gate in the critical path, its NCL input is fed by the NCL register cell. Its other (non-NCL) Boolean inputs are driven by the outputs of the non-critical path Boolean gates. The single NCL output of the hybrid gate drives the NCL input of the next hybrid gate in the critical delay path.

[0060] refer to Figure 7A-7C For the example NCL OR gate 700, a data (Vdd) value applied to either a logic "1" line or a logic "0" line asserts its logic value. In other words, Vdd applied to a logic "1" line implies that the NCL signal has a logic "1", and Vdd applied to a logic "0" line implies a logic "0" value on the NCL signal. Thus, the disclosed hybrid gate is capable of supporting both single-rail Boolean inputs and asynchronous dual-rail NCL inputs and outputs.

[0061] The difficult part of the hybrid gate design is handling the Boolean logic "0" input. Because the hybrid gate output is a dual rail NCL output signal, the logic "0" value is represented by the Vdd voltage level on the logic "0" line. Thus, the hybrid gate needs to handle the Boolean logic "0" input and generate the Vdd voltage level on the NCL logic "0" output line. The traditional CMOS gate design does not work because it requires inverting the logic "0" Boolean signal value, and the additional inversion will change the critical path. To handle this, a non-traditional weak transistor design is utilized.

[0062] Fig. 8A An example hybrid OR gate 800 that may be determined by the hybrid gate determination module 406 is shown, and Figure 8B and Figure 8C The subcircuit of an example OR gate 800 is shown. Specifically, Figure 8B A subcircuit 802 of the hybrid OR gate 800 is shown for driving the high output Z1, and Figure 8C A subcircuit 804 of the hybrid OR gate 800 is shown for driving the low output Z0. Figure 8A-8C The hybrid OR gate 800 has a dual-rail input (lines A1 and A0), a Boolean input B, and a dual-rail output (lines Z1 and Z0).

[0063] Fig. 9 4 shows a flow chart of a method that can be performed by the blending door determination module 406 to determine the design of the blending door. Specifically, Fig. 9 The NCL gate determined by the NCL gate determination module 404 is converted into a hybrid gate by the method of Fig. 9 The method is used to analyze the specific NCL gate determined by the NCL gate determination module 404, thereby converting the specific NCL gate into a hybrid gate. Fig. 9 The method may be performed by the hybrid gate determination module 406 for each gate in the critical path identified by the critical path determination module 402. Specifically, Fig. 9 Method to modify the two threshold gates of NCL gate.

[0064] At step 900, the hybrid gate determination module 406 determines whether the Set Z to Vdd network of the NCL gate includes a B1 input or a B0 input. If the Set Z to Vdd network of the NCL gate includes a B1 input, then at step 902, the B1 input is replaced with a B input into a strong N-type transistor (nFET). Alternatively, if the Set Z to Vdd network of the NCL gate includes a B0 input, then at step 904, the B0 input is replaced with a B input into a weak P-type transistor (pFET). Then, at step 906, an additional weak nFET with a B input is added to the Keep Z at Vss network.

[0065] The resulting reset network of the hybrid gate is next modified using known techniques to conform to the modified set Z network. For example, if we use both A0 and A1 in the set Z network of the hybrid gate, then the reset Z network of the hybrid gate should include both A0 and A1 in series. Then a null value on both A0 and A1 will reset Z to null. If the set Z network of the hybrid gate only contains A0 (or A1), then the reset Z of the hybrid gate only requires A0 (or A1). In this case, you only need a null value on A0 (or A1) to reset Z to null. This is true regardless of whether weak transistors are used in the set Z network. The keep Z at Vdd network of the hybrid gate remains unchanged from the keep Z at Vdd network of the NCL equivalent gate.

[0066] The hybrid door determination module 406 can utilize Fig. 9 The method can be used to determine the design of any type of logic gate. However, for the purpose of illustration, the method is specifically discussed with respect to the design of an OR gate. Specifically, Fig. 9 The method can be used to Figure 7A-7C The NCL OR gate is converted to Figure 8A-8C A mixed OR gate 800 is provided.

[0067] for Figure 7B The threshold gate 702, in Fig. 9 At step 900, the blend door determination module 406 determines that the setup Z network 708 includes input B1. Thus, control proceeds to step 902 and the B1 input of the setup Z network 708 is replaced by input Figure 8B The threshold gate 802 sets the B input of the Z network 806 to a strong nFET.

[0068] Additionally, the A0 input is added to the Set-Z network so that the blend gate will not assert itself until either A0 or A1 has a data value on it. Specifically, because A1 and A0 are in the critical path, the A1 or A0 signal value is the last to arrive in the blend gate. The values ​​of all other (standard) logic signals B, C, D, etc. arrive before the values ​​on A1 and A0. In operation, the blend gate should not switch until a data value arrives at A1 or A0. Figure 7B In the example of , a data value on A1 or a logic value "1" on B and a data value on A0 will cause the mixed gate to assert. If A0 is not included, the mixed gate can assert itself when B arrives.

[0069] for Figure 7C The threshold gate 704, in Fig. 9 At step 900, the blend door determination module 406 determines that the setup Z network 706 includes input B0. Thus, control proceeds to step 902 and the B0 input of the setup Z network is replaced by input Figure 8CThe threshold gate 804 sets the B input of the weak pFET in the Z network 814. Then, control passes to 904 and a weak nFET with a B input is added Figure 8C Keep Z at VSS network 818. Figure 8A-8C The operation of the blend door is discussed below.

[0070] for Figure 8A-8C The OR gate has three critical cases to analyze: A=“1”→Z=“a”, B=“1”→Z=“1”, and A=B=“0”→Z=“0”. For the A=“1” case, the output Z should go to logic “1” regardless of the value on the Boolean input B. In asynchronous NCL, this corresponds to data (Vdd) on the logic “1” line Z1, and empty (Vss) on the logic “0” line Z0. Since the NCL input signal A is in the critical path, the dual-rail NCL line A1 will go to Vdd after the value on the Boolean input B (which is not of interest for this case) arrives. Since A1 goes to Vdd, A0 will remain at Vss according to NCL convention. Figure 8A-8C In the example above, with A1 = Vdd, Z1 will be set to Vdd, and with A0 = Vss, Z0 will remain at Vss. In addition, Z1 will remain at Vdd (hysteresis) until A1 is reset to Vss.

[0071] For the case of B = "1", the output Z should become logic "1" regardless of the value that the NCL input signal A eventually becomes. In the new data path scheme, B becomes "1", then A1 or A0 will become data (Vdd) while the other remains empty (Vss). Figure 8A-8C In the example, if A1=Vdd (A0=Vss), the logic "1" output line Z1 will be Vdd, and the logic "0" output line Z0 will be Vss. Otherwise, if A0=Vdd (A1=Vss), the logic "1" output line Z1 will become Vdd, and the logic "0" output line Z0 will remain Vss. So the setting of the logic "1" output line Z1 does not matter what value signal A becomes. In addition, Z1 will remain at Vdd until A is reset (A1=A0=Vss).

[0072] It should be noted that for both of the above cases, the Boolean input is a logic "1" or don't care value. For the last case, where the Boolean signal has a control value of "0", Fig. 9 The pFET design flow of the method comes into play.

[0073] for Figure 8A-8C In the example of A=B=“0”, the output should eventually become logic “0”. For NCL, both A1 and A0 are initialized to empty (Vss). Figure 8A-8CIn the example of the OR gate, these null values ​​force Z1=Z0=Vss, regardless of the value on the Boolean input B. Based on the data path assertion, B goes to "0" before A is asserted. With B="0", when A0 is asserted to Vdd (A1 is still Vss), Z1 will remain at Vss, however, Zb in the Z0 subcircuit will be pulled down by the weak BpFET and Z0 will go to Vdd. In this way, the logic "0" output line Z0 is set. Furthermore, Z0 will remain set to Vdd until A is reset (A1=A0=Vss).

[0074] To satisfy the assertion that the hybrid equivalent gate does not change the critical path, the propagation delay of the hybrid gate must be greater than or equal to the delay of the replaced Boolean gate. Given that the assertion is true, it can be safely assumed that all Boolean combinational signal values ​​arrive before the NCL dual-rail signal values. To guarantee the assertion, the designer can carefully control the hybrid gate transistor size. A simple scheme is to start with standard proportional transistor widths for the nMOS and pMOS transistors in the hybrid gate and perform Spice simulations to compare the propagation delays between the Boolean logic gates and their hybrid replacements. The width of the hybrid gate transistors can be adjusted to increase the hybrid propagation delay (the delay between the NCL dual-rail input change and the corresponding dual-rail output change) to a percentage difference that ensures reliable operation of the envelope for the specific target technology manufacturing node.

[0075] Return to reference Figure 4 , the handshake trigger insertion module 408 may drive the asynchronous NCL input (eg, Figure 8A-8C The flip-flops at inputs A1 and A0 of the NCL controller are replaced with their NCL asynchronous equivalents. The latch insertion module 410 can replace the flip-flops of gates that are not in the critical path with low-overhead latches controlled by NCL asynchronous handshakes.

[0076] Fig.10 A flow chart depicts an example method that may be performed by computing device 300 to convert a synchronous circuit to an asynchronous circuit. At step 1000, data input module 400 receives information about a synchronous digital circuit. Specifically, data input module 400 receives a circuit diagram of a synchronous circuit to be converted to an asynchronous circuit. In some examples, data input module 400 may receive a structured Verilog netlist.

[0077] At step 1002, the critical path determination module 402 determines a critical path through each synchronized combinational sub-circuit block of the digital circuit received by the data input module 400. In some examples, the critical path determination module 402 can determine the critical path by performing a breadth-first search of the digital circuit. At step 1004, the critical path determination module 402 identifies all Boolean gates along the determined critical path.

[0078] At step 1006, the hybrid gate determination module 406 determines hybrid equivalent gates for all gates along the identified critical path. In the illustrated example, the NCL gate determination module 404 first determines the NCL equivalent gates for all gates along the identified critical path. Then, the hybrid gate determination module 406 uses Fig. 9 The method converts NCL equivalent gates into hybrid gates.

[0079] At step 1008, the hybrid gate determination module 406 generates a modified digital circuit by replacing the Boolean gates along the determined critical path with the determined hybrid gates. The handshake flip-flop insertion module 408 can then replace the flip-flops that drive the asynchronous inputs of the hybrid equivalent gates with null convention logic asynchronous gates. The latch insertion module 410 can then replace other flip-flops with latches to complete the modified digital circuit. The resulting modified digital circuit is an asynchronous equivalent circuit of the received synchronous circuit.

[0080] To test the disclosed embodiments, two asynchronous versions of multiple benchmark circuits were generated. The first set of asynchronous circuits was generated by replacing all standard Boolean gates of the benchmark circuits with NCL equivalent gates. The second set of asynchronous circuits was generated using the disclosed method of replacing only the gates along the critical path with hybrid gates.

[0081] Fig.11 A table showing transistor counts for various standard Boolean gates and their semi-static NCL and hybrid equivalent gates is shown. Although the hybrid equivalent gates have transistor counts similar to the semi-static NCL gates, in the disclosed method, only the standard gates along the critical path need to be replaced with hybrid gates, while gates not along the critical path remain as standard Boolean gates.

[0082] Fig.12 The number of FETs required for several benchmark circuits using standard Boolean gates, using semi-static NCL gates to replace all Boolean gates, and using the disclosed hybrid circuit replacing only critical path gates with hybrid gates are shown. Fig.12 Also shown are the proportions of transistor increases required for the semi-static NCL circuit and the disclosed hybrid circuit. Fig.12As can be seen in Figure 2, the disclosed hybrid circuit requires significantly fewer transistors than the semi-static NCL circuit. On average, the NCL semi-static version of the benchmark circuit requires 2.47 times the number of transistors as the standard Boolean circuit. However, the disclosed hybrid circuit requires only 6% more transistors than the standard Boolean circuit on average.

[0083] It should now be appreciated that the embodiments described herein are directed to an area efficient asynchronous circuit generator. The disclosed method is based on replacing a standard Boolean gate in a digital circuit with a hybrid gate having a dual rail asynchronous NCL input and one or more standard Boolean inputs. The main advantage of the disclosed hybrid gate is that all signal conditioning required to convert the standard Boolean input to the asynchronous input is contained within the hybrid gate. Therefore, no additional signal conditioning is required. This feature, as well as the controlled delay ensures that when the hybrid gate is inserted, the critical path will remain intact.

[0084] The disclosed method can convert a synchronous circuit into an asynchronous circuit using the method disclosed herein in a systematic manner. The resulting asynchronous circuit is only slightly larger than a standard Boolean circuit. Therefore, the asynchronous circuit generated using the disclosed technique is smaller and cheaper than the asynchronous circuit generated using other methods.

Claims

1. An apparatus comprising a controller programmed to: receiving information about a synchronized digital circuit including a plurality of Boolean gates; determining a critical path through each synchronized combinational sub-circuit block of the digital circuit; identifying a first group of Boolean gates in the plurality of Boolean gates that are in the critical path; determining a hybrid equivalent gate for each Boolean gate in the first set of Boolean gates, wherein the hybrid equivalent gate has a synchronous input, a dual-rail asynchronous input, and a dual-rail output; and A modified digital circuit is generated by replacing each Boolean gate in the first set of Boolean gates with a corresponding hybrid equivalent gate.

2. The apparatus of claim 1, wherein the information about the synchronized digital circuit comprises a structured Verilog netlist. 3 . The apparatus of claim 1 , wherein the controller is programmed to determine the critical path by performing a breadth-first search.

4. The apparatus of claim 1 , wherein the controller is programmed to generate the modified digital circuit by: Replace the flip-flops in the digital circuit that drive the asynchronous inputs of the hybrid equivalent gates with null-convention logic asynchronous equivalents; and Flip-flops in the digital circuit that do not drive the asynchronous inputs of the hybrid equivalent gates are replaced with latches controlled by asynchronous handshaking.

5. The apparatus of claim 1 , wherein the controller is programmed to determine the hybrid equivalent gate for each gate by: determining an NCL equivalent gate having a first dual rail input with wires A1 and A0, a second dual rail input with wires B1 and B0, a dual rail output with wires Z1 and Z0, a first subcircuit associated with Z1, and a second subcircuit associated with Z0; For the first subcircuit and the second subcircuit, determining whether to set the Z network to B1 input or B0 input; Based on determining that the setup Z network includes a B1 input, replacing the B1 input with a synchronous B input connected to a strong nFET; as well as Based on determining that the Set Z network includes a B0 input, the B0 input is replaced with a synchronous B input connected to a weak pFET, and a synchronous B input connected to a weak nFET is added to the Hold Z at Vss network.

6. The apparatus of claim 5, wherein the controller is programmed to determine the mixed equivalent gate by modifying a reset network for the first subcircuit and the second subcircuit to conform to the set-Z network.

7. The apparatus of claim 1, wherein the critical path through each synchronized combinational sub-circuit block of the digital circuit is the same as the critical path through each combinational sub-circuit block of the modified digital circuit.

8. The apparatus of claim 1, wherein a propagation delay of each hybrid equivalent gate is greater than or equal to a delay of each Boolean gate of the first set of Boolean gates.

9. A method comprising: receiving information about a synchronized digital circuit including a plurality of Boolean gates; determining a critical path through each synchronized combinational sub-circuit block of the digital circuit; identifying a first group of Boolean gates in the plurality of Boolean gates that are in the critical path; determining a hybrid equivalent gate for each Boolean gate in the first set of Boolean gates, wherein the hybrid equivalent gate has a synchronous input, a dual-rail asynchronous input, and a dual-rail output; as well as A modified digital circuit is generated by replacing each Boolean gate in the first set of Boolean gates with a corresponding hybrid equivalent gate.

10. The method of claim 9, wherein the information about the synchronized digital circuit comprises a structured Verilog netlist. The method of claim 9 , further comprising determining the critical path by performing a breadth-first search.

12. The method of claim 9, further comprising generating the modified digital circuit by: Replace the flip-flops in the digital circuit that drive the asynchronous inputs of the hybrid equivalent gates with null-convention logic asynchronous equivalents; and Flip-flops in the digital circuit that do not drive the asynchronous inputs of the hybrid equivalent gates are replaced with latches controlled by asynchronous handshaking.

13. The method of claim 9, further comprising determining the hybrid equivalent gate for each gate by: determining an NCL equivalent gate having a first dual rail input with wires A1 and A0, a second dual rail input with wires B1 and B0, a dual rail output with wires Z1 and Z0, a first subcircuit associated with Z1, and a second subcircuit associated with Z0; For the first sub-circuit and the second sub-circuit, determining whether to set the Z network to B1 input or B0 input; and Based on determining that the setup Z network includes a B1 input, the B1 input is replaced with a synchronous B input connected to a strong nFET.

14. The method of claim 9, further comprising determining the hybrid equivalent gate for each gate by: determining an NCL equivalent gate having a first dual rail input with wires A1 and A0, a second dual rail input with wires B1 and B0, a dual rail output with wires Z1 and Z0, a first subcircuit associated with Z1, and a second subcircuit associated with Z0; For the first sub-circuit and the second sub-circuit, determining whether to set the Z network to B1 input or B0 input; and Based on determining that the Set Z network includes a B0 input, the B0 input is replaced with a synchronous B input connected to a weak pFET, and a synchronous B input connected to a weak nFET is added to the Hold Z at Vss network.

15. The method of claim 13, further comprising determining the mixed equivalent gate by modifying a reset network for the first subcircuit and the second subcircuit to conform to the set-Z network.

16. The method of claim 14, further comprising determining the mixed equivalent gate by modifying a reset network for the first subcircuit and the second subcircuit to conform to the set-Z network.

17. The method of claim 9, wherein the critical path through each synchronized combinational sub-circuit block of the digital circuit is the same as the critical path through each combinational sub-circuit block of the modified digital circuit.

18. The method of claim 9, wherein a propagation delay of each hybrid equivalent gate is greater than or equal to a delay of each Boolean gate of the first set of Boolean gates.

19. A digital circuit, comprising: A plurality of Boolean gates, wherein each gate in a first set of Boolean gates along a critical path through each synchronized combinational sub-circuit block of the digital circuit comprises a hybrid equivalent gate, wherein the hybrid equivalent gate has a synchronous input, a dual-rail asynchronous input, and a dual-rail output.

20. The digital circuit of claim 19, wherein: A null-convention logic asynchronous equivalent flip-flop drives the asynchronous input of the mixed equivalent gate; and A latch controlled by an asynchronous handshake drives the synchronous input of the hybrid equivalent gate.

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