Imaging device

Abstract

An imaging device according to one embodiment of the present invention includes a photoelectric conversion section, a first active element, and a first semiconductor layer. The photoelectric conversion unit generates an electric charge corresponding to the amount of received light. The first active element performs a predetermined operation on the charge generated by the photoelectric conversion portion, and includes a gate electrode including a first electrode portion, a second electrode portion, and a third electrode portion. The first electrode part and the second electrode part are arranged side by side in a first direction. The third electrode portion connects the first electrode portion and the second electrode portion to each other. The first semiconductor layer includes a first surface and a second surface facing each other, and the first electrode portion and the second electrode portion of the gate electrode are embedded on a first surface side within the first semiconductor layer. The first semiconductor layer includes a first semiconductor region between the first electrode portion and the second electrode portion. The first semiconductor region is undoped.

Description

Technical Field

[0001] The present invention relates to, for example, an imaging device. Background Art

[0002] For example, Patent Document 1 discloses a solid-state imaging device in which an amplifier transistor is formed on one surface of a semiconductor substrate. The amplifier transistor includes a gate electrode including a vertical gate electrode portion buried in the depth direction from the one surface. The semiconductor substrate includes a p-type layer as a well layer.

[0003] Citation List

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2021-34435 Summary of the invention

[0006] By the way, in the image pickup device having a three-dimensional structure as described above, it is necessary to reduce the generation of dark current.

[0007] Therefore, it is desirable to provide an imaging device capable of improving device characteristics.

[0008] According to an embodiment of the present invention, an image pickup device includes a photoelectric conversion unit, a first active element, and a first semiconductor layer. The photoelectric conversion unit generates a charge corresponding to the amount of light received. The first active element performs a predetermined operation on the charge generated by the photoelectric conversion unit, and the first active element includes a gate electrode including a first electrode unit, a second electrode unit, and a third electrode unit. The first electrode unit and the second electrode unit are arranged side by side in a first direction. The third electrode unit connects the first electrode unit and the second electrode unit to each other. The first semiconductor layer includes a first surface and a second surface opposite to each other, the first electrode unit and the second electrode unit of the gate electrode are buried on the first surface side in the first semiconductor layer, and the first semiconductor layer includes a first semiconductor region located between the first electrode unit and the second electrode unit. The first semiconductor region is undoped.

[0009] In the image pickup device according to an embodiment of the present invention, the first electrode portion and the second electrode portion of the first active element constituting the gate electrode are buried in the first semiconductor layer, and the undoped first semiconductor region is formed between the first electrode portion and the second electrode portion in the first semiconductor layer. This allows the entire first semiconductor layer between the first electrode portion and the second electrode portion to be used as a channel region. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram showing an example of a functional configuration of an image pickup apparatus according to an embodiment of the present invention.

[0011] Figure 2 It shows Figure 1 A schematic plan view showing the general structure of the imaging device shown.

[0012] Figure 3 is shown along Figure 2 Schematic diagram of the cross-sectional configuration along line AA′ shown in FIG.

[0013] Figure 4 yes Figure 1 The equivalent circuit diagram of the unit cell is shown.

[0014] Figure 5 It shows Figure 1 The diagram is a schematic diagram of an example of a cross-sectional configuration of the imaging device shown.

[0015] Fig. 6A It shows Figure 5 A schematic diagram of an example of a planar layout of the first substrate is shown.

[0016] Figure 6B It shows Figure 5 A schematic diagram of an example of a planar layout of the second substrate is shown.

[0017] Fig. 7A is along Figure 6B Schematic cross-sectional view along line II′ shown in .

[0018] Figure 7B is along Figure 6B Schematic cross-sectional view along line II-II′ shown in FIG.

[0019] Figure 7C is along Figure 6B Schematic cross-sectional view along line III-III′ shown in .

[0020] Fig.7D is along Figure 6B Schematic cross-sectional view along line IV-IV′ shown in .

[0021] Figure 8 It is a schematic diagram for explaining the channel formed in the cutout portion.

[0022] Fig. 9 is an expanded view of the channel formed in the cutout portion.

[0023] Fig. 10A It shows Fig. 7A Schematic cross-sectional view of an example of a manufacturing process of a pixel transistor shown in FIG.

[0024] Fig. 10B It shows Fig. 10A Schematic cross-sectional view of the subsequent process.

[0025] Fig. 10C It shows Fig. 10B Schematic cross-sectional view of the subsequent process.

[0026] Fig. 10D It shows Fig. 10C Schematic cross-sectional view of the subsequent process.

[0027] Fig. 10E It shows Fig. 10D Schematic cross-sectional view of the subsequent process.

[0028] Fig.10F It shows Fig.10E Schematic cross-sectional view of the subsequent process.

[0029] Figure 10G It shows Fig.10F Schematic cross-sectional view of the subsequent process.

[0030] Fig. 10H It shows Figure 10G Schematic cross-sectional view of the subsequent process.

[0031] Fig.10I It shows Fig. 10H Schematic cross-sectional view of the subsequent process.

[0032] Fig.10J It shows Fig.10I Schematic cross-sectional view of the subsequent process.

[0033] Fig.11 is a schematic cross-sectional view for explaining another structure of the pixel transistor of the present invention.

[0034] Fig.12 It is used to illustrate Fig.11 A schematic cross-sectional view of the manufacturing process of a pixel transistor is shown.

[0035] Fig.13 It is used to illustrate Fig. 7A Schematic cross-sectional view of another example of a manufacturing process of a pixel transistor shown in FIG.

[0036] Fig.14 Is used to explain the Figure 3 A schematic diagram of the path of the input signal of the camera device is shown.

[0037] Fig.15 It is used to illustrate Figure 3 Schematic diagram of the signal path of the pixel signal of the camera device shown.

[0038] Fig.16 is a schematic plan view showing the configuration of a pixel transistor as Comparative Example 1.

[0039] Fig.17 is along Fig.16 Schematic cross-sectional view along line VV′ shown in .

[0040] Fig.18 is along Fig.16 Schematic cross-sectional view along line VI-VI′ shown in .

[0041] Fig.19 is a schematic diagram showing an example of a planar layout of fins.

[0042] Fig. 20 is a schematic cross-sectional view showing an example of the shape of a fin formed by etching.

[0043] Fig.21 is a schematic cross-sectional view showing another example of the shape of a fin formed by etching.

[0044] Fig. 22 is a schematic plan view showing the configuration of a pixel transistor as Comparative Example 2.

[0045] Fig.23 is along Fig. 22 Schematic cross-sectional view along line VIII-VIII′ shown in .

[0046] Fig.24 is along Fig. 22 Schematic cross-sectional view along line IX-IX′ shown in FIG.

[0047] Fig.25 3 is a characteristic diagram showing the transconductance (gm) of each of Comparative Example 2 and the embodiment.

[0048] Fig.26 : is a characteristic diagram showing the current-voltage characteristics of each of Comparative Example 2 and the embodiment.

[0049] Fig. 27 is a schematic cross-sectional view of a pixel transistor according to Modification 1 of the present invention.

[0050] Fig.28 is a characteristic diagram showing the relationship between the noise current (Isub) and the life span based on the sidewall width.

[0051] Fig.29A Schematic cross-sectional views illustrating a manufacturing process of a pixel transistor according to Modification 2 of the present invention.

[0052] Fig.29B It shows Fig.29ASchematic cross-sectional view of the subsequent process.

[0053] Fig.29C It shows Fig.29B Schematic cross-sectional view of the subsequent process.

[0054] Fig.29D It shows Fig.29C Schematic cross-sectional view of the subsequent process.

[0055] Fig.29E It shows Fig.29D Schematic cross-sectional view of the subsequent process.

[0056] Fig.29F It shows Fig.29E Schematic cross-sectional view of the subsequent process.

[0057] Figure 29G It shows Fig.29F Schematic cross-sectional view of the subsequent process.

[0058] Fig.29H It shows Figure 29G Schematic cross-sectional view of the subsequent process.

[0059] Fig.29I It shows Fig.29H Schematic cross-sectional view of the subsequent process.

[0060] Fig.29J It shows Fig.29I Schematic cross-sectional view of the subsequent process.

[0061] Figure 29K It shows Fig.29J Schematic cross-sectional view of the subsequent process.

[0062] Fig.30 is a schematic plan view showing the configuration of a pixel transistor according to Modification 2 of the present invention.

[0063] Fig.31 It shows that Figure 1 A block diagram of a configuration example of an electronic device of the imaging device shown.

[0064] Fig.32A It shows the use of Figure 1 Schematic diagram of an example of the overall structure of the light detection system of the imaging device shown in FIG.

[0065] Fig.32B It shows Fig.32A A diagram showing an example of a circuit configuration of a light detection system.

[0066] Fig.33is a block diagram showing an example of a schematic configuration of a vehicle control system.

[0067] Fig.34 It is a diagram for assisting in explaining an example of the installation positions of the vehicle exterior information detection unit and the camera unit.

[0068] Fig.35 It is a diagram showing an example of a schematic configuration of an endoscopic surgery system.

[0069] Fig.36 : is a block diagram showing an example of the functional configuration of a camera head and a camera control unit (CCU: camera control unit). DETAILED DESCRIPTION

[0070] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The following description is a specific example of the present invention, and the present invention is not limited to the embodiments described below. In addition, the present invention is not limited to the positions, sizes, and size ratios of the various components shown in the various drawings. It should be noted that the description will be given in the following order.

[0071] 1. Embodiment (Example of an image pickup device including a pixel transistor including an undoped semiconductor region formed up to the bottom of a fin)

[0072] 2. Modifications

[0073] 2-1. Modification 1 (Another Example of the Structure of the Pixel Transistor)

[0074] 2-2. Modification 2 (Another Example of a Method for Manufacturing a Pixel Transistor)

[0075] 3. Application examples

[0076] 4. Application examples

[0077] [1. Implementation Plan]

[0078] [Functional structure of the imaging device]

[0079] Figure 1 : is a block diagram showing an example of a functional configuration of an image pickup apparatus (image pickup apparatus 1 ) according to an embodiment of the present invention.

[0080] For example, Figure 1 The imaging device 1 in the embodiment includes an input section 510A, a row driving section 520, a timing control section 530, a pixel array section 540, a column signal processing section 550, an image signal processing section 560, and an output section 510B.

[0081] In the pixel array section 540, pixels 541 are repeatedly arranged in an array. More specifically, a unit cell 539 including a plurality of pixels is used as a repeating unit. The unit cells 539 are repeatedly arranged in an array having a row direction and a column direction. It should be noted that herein, for convenience, the row direction is sometimes referred to as the H direction, and the column direction orthogonal to the row direction is sometimes referred to as the V direction. Figure 1 In the example of FIG. 5 , one unit cell 539 includes, for example, four pixels (pixels 541A, 541B, 541C, and 541D).

[0082] In the pixel array section 540, a plurality of row drive signal lines 542 and a plurality of vertical signal lines (column readout lines) 543 are provided together with the pixels 541A, 541B, 541C, and 541D. Each row 0 drive signal line 542 drives the pixels 541 included in each of the plurality of unit cells 539 arranged side by side in the row direction in the pixel array section 540. Thus, each pixel arranged side by side in the row direction in the unit cell 539 is driven. As will be described below, Figure 4 As described in detail, a plurality of transistors are provided in the unit cell 539. In order to drive the plurality of transistors respectively, a plurality of row drive signal lines 542 are connected to one unit cell 539. A vertical signal line (column readout line) 543 is also connected to the unit cell 539. Pixel signals are read out from each of the pixels 541A, 541B, 541C, and 541D included in the unit cell 539 via the vertical signal line (column readout line) 543.

[0083] For example, the row driving section 520 includes: a row address control section or a row decoder section; and a row driving circuit section. The row address control section determines the position of the row to be driven by the pixel. The row driving circuit section generates signals for driving the pixels 541A, 541B, 541C, and 541D.

[0084] The column signal processing section 550 is connected to the vertical signal line 543, for example. The column signal processing section 550 includes a load circuit section that forms a source follower circuit together with the pixels 541A, 541B, 541C, and 541D (unit cell 539). The column signal processing section 550 may include an amplifier circuit section that amplifies the signal read out from the unit cell 539 via the vertical signal line 543. The column signal processing section 550 may include a noise processing section. For example, the noise processing section removes the noise level of the system from the signal read out from the unit cell 539 as a result of the photoelectric conversion.

[0085] The column signal processing unit 550 includes, for example, an analog digital converter (ADC). The analog digital converter converts the signal read out from the unit cell 539 or the analog signal subjected to the above-mentioned noise processing into a digital signal. For example, the ADC includes a comparator unit and a counter unit. The comparator unit compares the analog signal as the conversion object with the reference signal as the comparison object. The counter unit measures the time until the comparison result of the comparator unit is inverted. The column signal processing unit 550 may also include a horizontal scanning circuit unit for performing control of scanning of the readout column.

[0086] The timing control section 530 supplies the row driving section 520 and the column signal processing section 550 with respective signals for controlling timing based on, for example, a reference clock signal or a timing control signal input to the device.

[0087] The image signal processing section 560 is a circuit that performs various signal processing on data obtained as a result of photoelectric conversion or data obtained as a result of the imaging operation of the imaging device 1. For example, the image signal processing section 560 includes an image signal processing circuit section and a data holding section. The image signal processing section 560 may include a processor section.

[0088] An example of the signal processing performed by the image signal processing section 560 includes a tone curve correction process in which the grayscale is increased when the AD-converted image data is data when a dark subject is photographed, and the grayscale is reduced when the AD-converted image data is data when a bright subject is photographed. In this case, it is preferable to store tone curve characteristic data in advance in the data holding section of the image signal processing section 560. The tone curve characteristic data belongs to the tone curve based on which the grayscale of the image data is corrected.

[0089] For example, the input unit 510A is suitable for inputting the above-mentioned reference clock signal, timing control signal, characteristic data, etc. from outside the device to the camera device 1. Examples of the timing control signal include a vertical synchronization signal and a horizontal synchronization signal. For example, the characteristic data will be stored in the data holding unit of the image signal processing unit 560. For example, the input unit 510A includes an input terminal 511, an input circuit unit 512, an input amplitude change unit 513, an input data conversion circuit unit 514, and a power supply unit (not shown).

[0090] The input terminal 511 is an external terminal suitable for inputting data. The input circuit unit 512 is suitable for allowing the signal input to the input terminal 511 to be captured inside the camera device 1. The input amplitude change unit 513 changes the amplitude of the signal captured by the input circuit unit 512 to an amplitude that is easy to use inside the camera device 1. The input data conversion circuit unit 514 reorders the data string of the input data. For example, the input data conversion circuit unit 514 includes a serial-parallel conversion circuit. The serial-parallel conversion circuit converts a serial signal received as input data into a parallel signal. It should be noted that in the input unit 510A, the input amplitude change unit 513 and the input data conversion circuit unit 514 can be omitted. The power supply unit can provide power set for various voltages required inside the camera device 1 based on the power supplied to the camera device 1 from the outside.

[0091] When the camera apparatus 1 is connected to an external storage device, the input unit 510A may be provided with a memory interface circuit for receiving data from the external storage device. Examples of the external storage device include flash memory, SRAM, and DRAM.

[0092] The output unit 510B outputs the image data to the outside of the device. Examples of the image data include image data captured by the camera 1 and image data subjected to signal processing by the image signal processing unit 560. For example, the output unit 510B includes an output data conversion circuit unit 515, an output amplitude change unit 516, an output circuit unit 517, and an output terminal 518.

[0093] For example, the output data conversion circuit unit 515 includes a parallel-serial conversion circuit. The output data conversion circuit unit 515 converts a parallel signal used inside the camera device 1 into a serial signal. The output amplitude change unit 516 changes the amplitude of the signal used inside the camera device 1. The signal with the changed amplitude is easier to use in an external device connected to the outside of the camera device 1. The output circuit unit 517 is a circuit that outputs data from the inside of the camera device 1 to the outside of the device. The output circuit unit 517 drives the wiring connected to the output terminal 518 outside the camera device 1. The output terminal 518 outputs data from the camera device 1 to the outside of the device. In the output unit 510B, the output data conversion circuit unit 515 and the output amplitude change unit 516 can be omitted.

[0094] When the camera apparatus 1 is connected to an external storage device, the output unit 510B may be provided with a memory interface circuit for outputting data to the external storage device. Examples of the external storage device include flash memory, SRAM, and DRAM.

[0095] [Schematic Structure of the Camera Device]

[0096] Figure 2 and Figure 3 Each of the above diagrams shows an example of a schematic configuration of the image pickup device 1. The image pickup device 1 includes three substrates (a first substrate 100, a second substrate 200, and a third substrate 300). Figure 2 The planar structures of the first substrate 100, the second substrate 200 and the third substrate 300 are schematically shown, and Figure 3 The cross-sectional configuration of the first substrate 100 , the second substrate 200 , and the third substrate 300 stacked on each other is schematically shown. Figure 3 Corresponding to the Figure 2 The cross-sectional structure of the line AA′ shown in . The imaging device 1 is an imaging device having a three-dimensional structure in which three substrates (a first substrate 100, a second substrate 200, and a third substrate 300) are bonded together. The first substrate 100 includes a semiconductor layer 100S and a wiring layer 100T. The second substrate 200 includes a semiconductor layer 200S and a wiring layer 200T. The third substrate 300 includes a semiconductor layer 300S and a wiring layer 300T. Here, for the sake of convenience, the wiring included in each of the first substrate 100, the second substrate 200, and the third substrate 300 and the interlayer insulating film around the wiring are collectively referred to as wiring layers (100T, 200T, 300T) provided in the corresponding substrates (the first substrate 100, the second substrate 100, and the third substrate 300). The first substrate 100, the second substrate 200, and the third substrate 300 are stacked in sequence. The semiconductor layer 100S, the wiring layer 100T, the semiconductor layer 200S, the wiring film 200T, the wiring layer 300T, and the semiconductor layer 300S are arranged in this order in the stacking direction. The specific configurations of the first substrate 100, the second substrate 200, and the third substrate 300 will be described later. Figure 3 The arrow shown in represents the incident direction of the light L toward the imaging device 1. Herein, for the sake of convenience, in the subsequent cross-sectional views, the light incident side of the imaging device 1 is sometimes referred to as "lower", "lower side" or "below", and the side of the imaging device 1 opposite to the light incident side is sometimes referred to as "upper", "upper side" or "above". In addition, herein, for the sake of convenience, with respect to each substrate including a semiconductor layer and a wiring layer, the wiring layer side is sometimes referred to as the front side, and the semiconductor layer side is sometimes referred to as the back side. It should be noted that the contents described in this specification are not limited to the above-mentioned names. The imaging device 1 is, for example, a back-illuminated imaging device, in which light is incident from the back side of the first substrate 100 including a photodiode.

[0097] The pixel array section 540 and the unit cell 539 included in the pixel array section 540 each include a first substrate 100 and a second substrate 200. The first substrate 100 is provided with a plurality of pixels 541A, 541B, 541C and 541D included in the unit cell 539. Each of these pixels 541 includes a photodiode (photodiode PD described later) and a transfer transistor (transfer transistor TR described later). The second substrate 200 is provided with a pixel circuit (pixel circuit 210 described later) included in the unit cell 539. The pixel circuit reads out the pixel signal transmitted from the photodiode of each of the pixels 541A, 541B, 541C and 541D via the transfer transistor, or resets the photodiode. In addition to including such a pixel circuit, the second substrate 200 also includes a plurality of row drive signal lines 542 extending in the row direction and a plurality of vertical signal lines 543 extending in the column direction. The second substrate 200 also includes a power supply line 544 extending in the row direction. For example, the third substrate 300 includes an input section 510A, a row driving section 520, a timing control section 530, a column signal processing section 550, an image signal processing section 560, and an output section 510B. For example, the row driving section 520 is disposed in a region partially overlapping with the pixel array section 540 in the stacking direction (hereinafter, referred to as the stacking direction) of the first substrate 100, the second substrate 200, and the third substrate 300. More specifically, the row driving section 520 is disposed in a region overlapping with the end portion of the pixel array section 540 in the H direction in the stacking direction ( Figure 2 ). For example, the column signal processing unit 550 is arranged in an area that partially overlaps with the pixel array unit 540 in the stacking direction. More specifically, the column signal processing unit 550 is arranged in an area that overlaps with the pixel array unit 540 near the end portion located in the V direction in the stacking direction. Although the illustration is omitted, the input unit 510A and the output unit 510B may also be arranged in a portion other than the third substrate 300. For example, the input unit 510A and the output unit 510B may also be arranged in the second substrate 200. Alternatively, the input unit 510A and the output unit 510B may also be arranged on the back side (light incident surface) of the first substrate 100. It should be noted that the aforementioned pixel circuit provided in the second substrate 200 is sometimes alternatively referred to as a pixel transistor circuit, a pixel transistor group, a pixel transistor, a pixel readout circuit, or a readout circuit. In this article, it uses the name of the pixel circuit.

[0098] For example, the first substrate 100 and the second substrate 200 are connected by through electrodes (for example, Figure 5The through electrodes 120E and 121E in the second substrate 200 are electrically connected to each other. For example, the second substrate 200 and the third substrate 300 are electrically connected to each other via the contact portions 201, 202 and the contact portions 301, 302. The second substrate 200 is provided with the contact portions 201 and 202, and the third substrate 300 is provided with the contact portions 301 and 302. The contact portion 201 of the second substrate 200 contacts the contact portion 301 of the third substrate 300, and the contact portion 202 of the second substrate 200 contacts the contact portion 302 of the third substrate 300. The second substrate 200 includes a contact region 201R provided with a plurality of contact portions 201 and a contact region 202R provided with a plurality of contact portions 202. The third substrate 300 includes a contact region 301R provided with a plurality of contact portions 301 and a contact region 302R provided with a plurality of contact portions 302. In the stacking direction, the contact regions 201R and 301R are arranged between the pixel array section 540 and the row drive section 520. In other words, for example, the contact regions 201R and 301R are respectively arranged in the region of the row drive section 520 (third substrate 300) and the pixel array section 540 (second substrate 200) that overlap each other in the stacking direction, or in the region near the region. For example, each of the contact regions 201R and 301R is arranged at the end of the region in the H direction. For example, in the third substrate 300, the contact region 301R is arranged at a position overlapping with a portion of the row drive section 520, specifically, at a position overlapping with the end of the row drive section 520 in the H direction. For example, the contact portions 201 and 301 connect the row drive section 520 arranged in the third substrate 300 and the row drive signal line 542 arranged in the second substrate 200 to each other. For example, the contact portions 201 and 301 may also connect the input portion 510A provided in the third substrate 300 to each of the power supply line 544 and the reference potential line (reference potential line VSS described later). In the stacking direction, the contact regions 202R and 302R are provided between the pixel array portion 540 and the column signal processing portion 550. In other words, for example, the contact regions 202R and 302R are provided in the region of the column signal processing portion 550 (third substrate 300) and the pixel array portion 540 (second substrate 200) overlapping each other in the stacking direction, or in the region near the region. For example, each of the contact regions 202R and 302R is provided at the end of the region in the V direction. In the third substrate 300, for example, the contact region 301R is provided at a position overlapping with a portion of the column signal processing portion 550, specifically, at a position overlapping with the end of the column signal processing portion 550 in the V direction.For example, the contact portions 202 and 302 are adapted to connect a pixel signal (a signal corresponding to an amount of charge generated as a result of photoelectric conversion of a photodiode) output from each of the plurality of unit cells 539 included in the pixel array portion 540 to a column signal processing portion 550 provided in the third substrate 300. Thereby, the pixel signal is transmitted from the second substrate 200 to the third substrate 300.

[0099] Figure 3 is an example of a cross-sectional view of the camera device 1. The first substrate 100, the second substrate 200 and the third substrate 300 are electrically connected to each other via wiring layers 100T, 200T and 300T. For example, the camera device 1 includes an electrical connection portion that electrically connects the second substrate 200 and the third substrate 300 to each other. Specifically, the contact portions 201, 202, 301 and 302 each include an electrode formed of a conductive material. For example, the conductive material includes a metal material such as copper (Cu), aluminum (Al) or gold (Au). For example, the contact areas 201R, 202R, 301R and 302R electrically connect the second substrate and the third substrate to each other by directly bonding the wiring formed as electrodes, thereby enabling input and / or output of signals between the second substrate 200 and the third substrate 300.

[0100] The electrical connection portion that electrically connects the second substrate 200 and the third substrate 300 to each other may be provided at a desired position. Figure 3 As described as contact regions 201R, 202R, 301R, and 302R in FIG. 1 , the electrical connection portion may be provided in a region overlapping with the pixel array portion 540 in the stacking direction. Alternatively, the electrical connection portion may be provided in a region not overlapping with the pixel array portion 540 in the stacking direction. Specifically, the electrical connection portion may be provided in a region overlapping with a peripheral portion arranged outside the pixel array portion 540 in the stacking direction.

[0101] For example, the first substrate 100 and the second substrate 200 are provided with connection holes H1 and H2. The connection holes H1 and H2 each extend through the first substrate 100 and the second substrate 200. Figure 2As shown, the connection hole portions H1 and H2 are arranged outside the pixel array portion 540 (or the portion overlapping the pixel array portion 540). For example, the connection hole portion H1 is arranged to be located outside the pixel array portion 540 in the H direction, and the connection hole portion H2 is arranged to be located outside the pixel array portion 540 in the V direction. For example, the connection hole portion H1 reaches the input portion 510A provided in the third substrate 300, and the connection hole portion H2 reaches the output portion 510B provided in the third substrate 300. Each of the connection hole portions H1 and H2 may be a hollow, or may at least partially include a conductive material. For example, there is a configuration in which an electrode formed as the input portion 510A and / or the output portion 510B is connected to a bonding wire. Alternatively, there is a configuration in which an electrode formed as the input portion 510A and / or the output portion 510B is connected to a conductive material provided in the connection hole portions H1 and H2. The conductive material provided in the connection holes H1 and H2 may be buried in a part or the whole of the connection holes H1 and H2. The conductive material may also be formed on the side walls of the connection holes H1 and H2.

[0102] It should be noted that Figure 3 A structure is shown in which the input section 510A and the output section 510B are provided in the third substrate 300, but this is not limitative. For example, by transmitting a signal of the third substrate 300 to the second substrate 200 via the wiring layers 200T and 300T, the input section 510A and / or the output section 510B can be provided in the second substrate 200. Similarly, by transmitting a signal of the second substrate 200 to the first substrate 100 via the wiring layers 100T and 200T, the input section 510A and / or the output section 510B can be provided in the first substrate 100.

[0103] Pixels 541A, 541B, 541C, and 541D include constituent elements that are shared with each other. Hereinafter, in order to distinguish the constituent elements of each of the pixels 541A, 541B, 541C, and 541D from each other, an identification number 1 is added to the end of the reference numeral of the constituent element of the pixel 541A, an identification number 2 is added to the end of the reference numeral of the constituent element of the pixel 541B, an identification number 3 is added to the end of the reference numeral of the constituent element of the pixel 541C, and an identification number 4 is added to the end of the reference numeral of the constituent element of the pixel 541D. In the case where it is not necessary to distinguish the constituent elements of each of the pixels 541A, 541B, 541C, and 541D from each other, the identification numbers at the end of the reference numerals of the constituent elements of each of the pixels 541A, 541B, 541C, and 541D are omitted.

[0104] Figure 4539 is an equivalent circuit diagram showing a configuration example of a unit cell 539. The unit cell 539 includes: a plurality of pixels 541 (in Figure 4 , four pixels 541A, 541B, 541C, and 541D); one pixel circuit 210 connected to the plurality of pixels 541; and a vertical signal line 543 connected to the pixel circuit 210. For example, the pixel circuit 210 includes four transistors, specifically, an amplifier transistor AMP, a selection transistor SEL, a reset transistor RST, and an FD (floating diffusion) conversion gain switching transistor FDG. As described above, the unit cell 539 is constructed such that the pixel signals of each of the four pixels 541 (pixels 541A, 541B, 541C, and 541D) set as two adjacent pixels are sequentially output to the vertical signal line 543 by causing one pixel circuit 210 to operate in a time division manner. The state in which one pixel circuit 210 is connected to a plurality of pixels 541 and the pixel signals of the plurality of pixels 541 are output by one pixel circuit 210 in a time division manner is referred to as "a plurality of pixels 541 share one pixel circuit 210".

[0105] The pixels 541A, 541B, 541C, and 541D have components common to each other.

[0106] For example, each of the pixels 541A, 541B, 541C, and 541D includes a photodiode PD, a transfer transistor TR, and a floating diffusion FD. The transfer transistor TR is electrically connected to the photodiode PD. The floating diffusion FD is electrically connected to the transfer transistor TR. The cathode of the photodiode PD is electrically connected to the source of the transfer transistor TR, and the anode of the photodiode PD is electrically connected to a reference potential line (e.g., ground GND). The photodiode PD performs photoelectric conversion on the incident light and generates a charge corresponding to the amount of light received. For example, the transfer transistor TR is an n-type CMOS (Complementary Metal Oxide Semiconductor) transistor. The drain of the transfer transistor TR is electrically connected to the floating diffusion FD, and the gate of the transfer transistor TR is electrically connected to a drive signal line. The drive signal line is a part of a plurality of row drive signal lines 542 connected to one unit cell 539. The transfer transistor TR transfers the charge generated by the photodiode PD to the floating diffusion FD. The floating diffusion FD is an n-type diffusion layer region formed in a p-type semiconductor layer. The floating diffusion FD is a charge holding mechanism for temporarily holding the charge transferred from the photodiode PD, and is also a charge-voltage conversion mechanism for generating a voltage corresponding to the amount of the charge.

[0107] The four floating diffusions FD (floating diffusions FD1, FD2, FD3, and FD4) included in one unit cell 539 are electrically connected to each other and are all electrically connected to the gate of the amplifier transistor AMP and the source of the FD conversion gain switching transistor FDG. The drain of the FD conversion gain switching transistor FDG is connected to the source of the reset transistor RST, and the gate of the FD conversion gain switching transistor FDG is connected to the drive signal line. The drive signal line is a part of the plurality of row drive signal lines 542 connected to one unit cell 539. The drain of the reset transistor RST is connected to the power supply line VDD, and the gate of the reset transistor RST is connected to the drive signal line. The drive signal line is a part of the plurality of row drive signal lines 542 connected to one unit cell 539. The gate of the amplifier transistor AMP is connected to the floating diffusion FD, the drain of the amplifier transistor AMP is connected to the power supply line VDD, and the source of the amplifier transistor AMP is connected to the drain of the selection transistor SEL. The source of the selection transistor SEL is connected to the vertical signal line 543, and the gate of the selection transistor SEL is connected to the drive signal line. The driving signal line is a part of a plurality of row driving signal lines 542 connected to one unit cell 539 .

[0108] When the transfer transistor TR is in an on state, the transfer transistor TR transfers the charge of the photodiode PD to the floating diffusion FD. For example, the gate of the transfer transistor TR (transfer gate TG) includes a so-called vertical electrode and is provided from a semiconductor layer (described later) to a semiconductor layer. Figure 5 The front side of the semiconductor layer 100S in the semiconductor layer 100S extends to the depth where the PD is located. The reset transistor RST resets the potential of the floating diffusion FD to a predetermined potential. When the reset transistor RST is in the on state, the reset transistor RST resets the potential of the floating diffusion FD to the potential of the power supply line VDD. The selection transistor SEL controls the output timing of the pixel signal from the pixel circuit 210. The amplifier transistor AMP generates a voltage signal corresponding to the level of the charge retained in the floating diffusion FD as a pixel signal. The amplifier transistor AMP is connected to the vertical signal line 543 via the selection transistor SEL. The amplifier transistor AMP, together with the load circuit part connected to the vertical signal line 543, constitutes a source follower in the column signal processing part 550. When the selection transistor SEL is in the on state, the amplifier transistor AMP outputs the voltage of the floating diffusion FD to the column signal processing part 550 via the vertical signal line 543. For example, the reset transistor RST, the amplifier transistor AMP and the selection transistor SEL are each an n-type CMOS transistor.

[0109] The FD conversion gain switching transistor FDG is used to change the gain of the charge-voltage conversion of the floating diffusion FD. Generally speaking, when taking an image in a dim place, the pixel signal is small. Based on Q=CV, when performing charge-voltage conversion, if the capacitance (FD capacitance C) of the floating diffusion FD is large, then V when converted to voltage by the amplifier transistor AMP is small. In contrast, a bright place will produce a larger pixel signal. Therefore, unless the FD capacitance C is large enough, the floating diffusion FD cannot fully receive the charge of the photodiode PD. In addition, in order to prevent V from being too large when converted to voltage by the amplifier transistor AMP (in other words, to make V smaller), the FD capacitance C must be large. Taking this into account, when the FD conversion gain switching transistor FDG is in the on state, the gate capacitance of the FD conversion gain switching transistor FDG is increased. This causes the FD capacitance C to become larger as a whole. On the contrary, when the FD conversion gain switching transistor FDG is in the off state, the FD capacitance C becomes smaller as a whole. In this way, the FD capacitance C is made variable by switching the FD conversion gain switching transistor FDG between on and off, so that the conversion efficiency can be switched. For example, the FD conversion gain switching transistor FDG is an n-type CMOS transistor.

[0110] It should be noted that a configuration in which the FD conversion gain switching transistor FDG is not provided may also be adopted. In this case, for example, the pixel circuit 210 includes, for example, three transistors, namely, an amplifier transistor AMP, a selection transistor SEL, and a reset transistor RST. For example, the pixel circuit 210 may include at least one of the following pixel transistors: These pixel transistors include, but are not limited to, an amplifier transistor AMP, a selection transistor SEL, a reset transistor RST, and an FD conversion gain switching transistor FDG.

[0111] The selection transistor SEL may also be arranged between the power line VDD and the amplifier transistor AMP. In this case, the drain of the reset transistor RST is electrically connected to the power line VDD and the drain of the selection transistor SEL. The source of the selection transistor SEL is electrically connected to the drain of the amplifier transistor AMP, and the gate of the selection transistor SEL is electrically connected to the row drive signal line 542. The source of the amplifier transistor AMP (the output end of the pixel circuit 210) is electrically connected to the vertical signal line 543, and the gate of the amplifier transistor AMP is electrically connected to the source of the reset transistor RST. It should be noted that, although the illustration is omitted, the number of pixels 541 sharing a pixel circuit 210 may be other than 4. For example, two or eight pixels 541 may share a pixel circuit 210.

[0112] [Cross-sectional structure of imaging device]

[0113] Figure 5An example of a cross-sectional configuration of the first substrate 100 , the second substrate 200 , and the third substrate 300 of the image pickup device 1 in a direction perpendicular to the main surface is shown. Figure 5 The cross section is schematically shown for easy understanding of the positional relationship between constituent elements and may be different from the actual cross section. Fig. 6A An example of a planar layout of the first substrate 100 is schematically shown. Figure 6B An example of a planar layout of the second substrate 200 is schematically shown. In the image pickup device 1, the first substrate 100, the second substrate 200, and the third substrate 300 are stacked in sequence. The image pickup device 1 also includes a light receiving lens 401 located on the back side (light incident side) of the first substrate 100. For example, a color filter layer (not shown) may be provided between the light receiving lens 401 and the first substrate 100. For example, the light receiving lens 401 is provided for each of the pixels 541A, 541B, 541C, and 541D, respectively. For example, the image pickup device 1 is a back-illuminated image pickup device. The image pickup device 1 includes a pixel array portion 540 arranged in a central portion and a peripheral portion (not shown) arranged outside the pixel array portion 520.

[0114] The first substrate 100 includes a semiconductor layer 100S and a wiring layer 100T which are arranged in order from the light receiving lens 401 side. For example, the semiconductor layer 100S is formed of a silicon substrate. The photodiode PD is formed so as to be buried in the semiconductor layer 100S. Specifically, for example, the semiconductor layer 100S has a p-well layer 112 at a part of the front side (the surface located on the wiring layer 100T side) and near the part, and has an n-type semiconductor region 111 in a region other than that (a region deeper than the p-well layer 112). For example, the n-type semiconductor region 111 and the p-well layer 112 form a pn junction photodiode PD. The p-well layer 112 is a p-type semiconductor region. Here, the semiconductor layer 100S is equivalent to a specific example of the "second semiconductor layer" in one embodiment of the present invention.

[0115] The floating diffusion FD and the VSS contact region 118 are provided near the front surface of the semiconductor layer 100S. The floating diffusion FD is formed by an n-type semiconductor region provided in the p-well layer 112. Fig. 6AAs shown, for example, the floating diffusions FD (floating diffusions FD1, FD2, FD3, and FD4) of each of the pixels 541A, 541B, 541C, and 541D are arranged close to each other in the central portion of the unit cell 539. The four floating diffusions FD (floating diffusions FD1, FD2, FD3, and FD4) included in the unit cell 539 are electrically connected to each other via an electrical connection mechanism (pad portion 120 described later) within the first substrate 100 (more specifically, within the wiring layer 100T). In addition, each floating diffusion FD is connected from the first substrate 100 to the second substrate 200 (more specifically, from the wiring layer 100T to the wiring layer 200T) via an electrical mechanism (through electrode 120E described later). Within the second substrate 200 (more specifically, inside the wiring layer 200T), each floating diffusion FD is electrically connected to the gate of the amplifier transistor AMP and the source of the FD conversion gain switching transistor FDG through the above-mentioned electrical mechanism.

[0116] The VSS contact region 118 is a region electrically connected to the reference potential line VSS, and is arranged to be separated from the floating diffusion portion FD. For example, in each of the pixels 541A, 541B, 541C, and 541D each having a square shape, the floating diffusion portion is arranged at one corner, and the VSS contact region 118 is arranged at the corner opposite thereto on the diagonal line. For example, the VSS contact region 118 is formed by a p-type semiconductor region. For example, the VSS contact region 118 is connected to a ground potential or a fixed potential. Thereby, a reference potential is supplied to the semiconductor layer 100S.

[0117] In the first substrate 100, a transfer transistor TR is also provided together with the photodiode PD, the floating diffusion FD, and the VSS contact region 118. The photodiode PD, the floating diffusion FD, the VSS contact region 118, and the transfer transistor TR are provided in each of the pixels 541A, 541B, 541C, and 541D. The transfer transistor TR is provided on the front side of the semiconductor layer 100S (i.e., the side opposite to the light incident surface side, or the second substrate 200 side). The transfer transistor TR includes a transfer gate TG. For example, the transfer gate TG includes: a horizontal portion TGb opposite to the front side of the semiconductor layer 100S; and a vertical portion TGa provided in the semiconductor layer 100S. The vertical portion TGa extends in the thickness direction of the semiconductor layer 100S. One end of the vertical portion TGa is connected to the horizontal portion TGb, and the other end of the vertical portion TGa is provided in the n-type semiconductor region 111. The transfer transistor TR is formed of such a vertical transistor, thereby preventing the occurrence of pixel signal transmission failure and improving the readout efficiency of the pixel signal.

[0118] Note that the transfer transistor TR may also be formed of a planar transistor. In this case, for example, the transfer gate TG is provided on the front surface of the semiconductor layer 100S. A gate insulating film is provided between the semiconductor layer 100S and the transfer gate TG.

[0119] The semiconductor layer 100S is provided with a pixel separation portion 117 for separating the pixels 541A, 541B, 541C, and 541D from each other. The pixel separation portion 117 is formed in a normal direction of the semiconductor layer 100S (a direction perpendicular to the front surface of the semiconductor layer 100S (in a direction perpendicular to the front surface of the semiconductor layer 100S)). Figure 5 , extending in the Z-axis direction). The pixel separation portion 117 is provided to separate the pixels 541A, 541B, 541C, and 541D from each other. For example, the pixel separation portion 117 has a lattice-like planar shape. For example, the pixel separation portion 117 electrically and optically separates the pixels 541A, 541B, 541C, and 541D from each other. For example, the pixel separation portion 117 includes a light shielding film 117A and an insulating film 117B. For example, tungsten (W) or the like can be used as the light shielding film 117A. The insulating film 117B is provided between the light shielding film 117A and the p-well layer 112 or the n-type semiconductor region 111. For example, the insulating film 117B is formed of silicon oxide (SiO). For example, the pixel separation portion 117 has a full trench isolation (FTI: Full Trench Isolation) structure, and is provided to penetrate the semiconductor layer 100S. Although illustration is omitted, the pixel separation portion 117 is not limited to the FTI structure in which the pixel separation portion 117 is provided to penetrate the semiconductor layer 100S. For example, the pixel separation portion 117 may have a deep trench isolation (DTI: Deep Trench Isolation) structure in which the pixel separation portion 117 is provided not to penetrate the semiconductor layer 100S. The pixel separation portion 117 extends in the normal direction of the semiconductor layer 100S and is formed in a partial region of the semiconductor layer 100S.

[0120] For example, a first pinning region 113 and a second pinning region 116 are provided in the semiconductor layer 100S. The first pinning region 113 is provided near the back surface of the semiconductor layer 100S and is arranged between the n-type semiconductor region 111 and the fixed charge film 114. The second pinning region 116 is provided on the side of the pixel separation portion 117, specifically, between the pixel separation portion 117 and the p-well layer 112 or the n-type semiconductor region 111. For example, the first pinning region 113 and the second pinning region 116 are each formed by a p-type semiconductor region.

[0121] A fixed charge film 114 having a negative fixed charge is provided between the semiconductor layer 100S and the insulating film 115. By the electric field induced by the fixed charge film 114, a first pinning region 113 of a hole accumulation layer is formed at the interface on the light receiving surface (back side) side of the semiconductor layer 100S. Thereby, the generation of dark current due to the interface energy level on the light receiving surface side of the semiconductor layer 100S is suppressed. For example, the fixed charge film 114 includes an insulating film having a negative fixed charge. Examples of the material of the insulating film having a negative fixed charge include hafnium oxide, zirconium oxide, aluminum oxide, titanium oxide, or tantalum oxide.

[0122] A light shielding film 117A is provided between the fixed charge film 114 and the insulating film 115. The light shielding film 117A may be provided so as to be continuous with the light shielding film 117A included in the pixel separation portion 117. For example, the light shielding film 117A between the fixed charge film 114 and the insulating film 115 is selectively provided at a position opposite to the pixel separation portion 117 in the semiconductor layer 100S. The insulating film 115 is provided so as to cover the light shielding film 117A. For example, the insulating film 115 is formed of silicon oxide.

[0123] The wiring layer 100T provided between the semiconductor layer 100S and the second substrate 200 has, in order from the semiconductor layer 100S side: pad portions 120 and 121; a passivation film 122; an interlayer insulating film 123; and a bonding film 124. For example, the horizontal portion TGb of the transfer gate TG is provided in the wiring layer 100T. It should be noted that the wiring layer 100T is not limited to the above-described configuration, and the wiring layer 100T may have a configuration including wiring and an insulating film.

[0124] Each of the pad portions 120 and 121 is located on the front surface of the semiconductor layer 100S via an insulating film (not shown) and is arranged in a selective region on the front surface. The pad portion 120 is suitable for connecting the floating diffusion portions FD (floating diffusion portions FD1, FD2, FD3, and FD4) of each of the pixels 541A, 541B, 541C, and 541D to each other. For example, for each unit cell 539, the pad portion 120 is arranged in the central portion of the unit cell 539 in a plan view. The pad portion 120 is arranged to cross the pixel separation portion 117, and is arranged to overlap with at least a portion of each of the floating diffusion portions FD1, FD2, FD3, and FD4. Specifically, for example, Fig. 6AAs shown, the pad portion 120 is arranged in the following area: the area overlaps with at least a portion of each of the multiple floating diffusion portions FD (floating diffusion portions FD1, FD2, FD3 and FD4) of the shared pixel circuit 210 and at least a portion of the pixel separation portion 117 formed between the multiple photodiodes PD (photodiodes PD1, PD2, PD3 and PD4) of the shared pixel circuit 210 in a direction perpendicular to the front surface of the semiconductor layer 100S.

[0125] The pad portion 121 is suitable for connecting a plurality of VSS contact regions 118 to each other. For example, in one unit cell 539 and another unit cell 539 adjacent to each other in the V direction, the VSS contact region 118 provided in each of the pixels 541C and 541D of the one unit cell 539 is electrically connected to the VSS contact region 118 provided in each of the pixels 541A and 541B of the other unit cell 539 through the pad portion 121. For example, the pad portion 121 is provided so as to cross the pixel separation portion 117, and is arranged so as to overlap with at least a portion of each of the four VSS contact regions 118. Specifically, the pad portion 121 is provided in a region that overlaps with at least a portion of each of the plurality of VSS contact regions 118 and at least a portion of the pixel separation portion 117 formed between the plurality of VSS contact regions 118 in a direction perpendicular to the front surface of the semiconductor layer 100S.

[0126] By providing the pad portion 120, the number of wirings for connecting each floating diffusion portion FD to the pixel circuit 210 (for example, the gate electrode of the amplifier transistor AMP) can be reduced in the entire chip. Similarly, by providing the pad portion 121, the number of wirings for providing a potential to each VSS contact region 118 can be reduced in the entire chip. This can reduce the area of ​​the entire chip, suppress electrical interference between wirings in miniaturized pixels, and / or reduce costs by, for example, reducing the number of components.

[0127] For example, the pad portions 120 and 121 are respectively formed of polysilicon (Poly Si), more specifically, doped polysilicon to which impurities are added. The pad portions 120 and 121 are each preferably formed of a conductive material having high heat resistance such as polysilicon, tungsten (W), titanium (Ti) or titanium nitride (TiN). Thus, the pixel circuit 210 can be formed after the semiconductor layer 200S of the second substrate 200 is attached to the first substrate 100.

[0128] Each of the pad portions 120 and 121 may also be formed of a metal material such as tantalum nitride (TaN), aluminum (Al), or copper (Cu).

[0129] For example, the passivation film 122 is arranged on the entire front surface of the semiconductor layer 100S in a manner covering the pad portions 120 and 121. For example, the passivation film 122 is formed by a silicon nitride (SiN) film. The interlayer insulating film 123 covers the pad portions 120 and 121 across the passivation film 122. For example, the interlayer insulating film 123 is arranged on the entire front surface of the semiconductor layer 100S. For example, the interlayer insulating film 123 is formed by a silicon oxide (SiO) film. The bonding film 124 is arranged on the bonding surface between the first substrate 100 (specifically, the wiring layer 100T) and the second substrate 200. In other words, the bonding film 124 is in contact with the second substrate 200. The bonding film 124 is arranged on the entire main surface of the first substrate 100. For example, the bonding film 124 is formed by a silicon nitride film.

[0130] For example, the light receiving lens 401 is opposed to the semiconductor layer 100S via the fixed charge film 114 and the insulating film 115. For example, the light receiving lens 401 is provided at a position opposed to the photodiode PD of each of the pixels 541A, 541B, 541C, and 541D.

[0131] The second substrate 200 includes a semiconductor layer 200S and a wiring layer 200T which are sequentially arranged from the first substrate 100 side. The semiconductor layer 200S is formed of a silicon substrate. For example, in the semiconductor layer 200S, a well region 211 is arranged in a selective region, which will be described in detail later. For example, Figure 6B As shown, a pixel circuit 210 arranged for each unit cell 539 is provided in the second substrate 200. For example, a well region 211 is provided around an active region 200X of four transistors included in the pixel circuit 210. The well region 211 is equivalent to a specific example of the "second semiconductor region" in one embodiment of the present invention, and is, for example, a p-type semiconductor region. For example, the pixel circuit 210 is provided on the front side (wiring layer 200T side) of the semiconductor layer 200S. In the imaging device 1, the second substrate 200 is attached to the first substrate 100, and the back side (semiconductor layer 200S side) of the second substrate 200 faces the front side (wiring layer 100T side) of the first substrate 100. In other words, the second substrate 200 and the first substrate 100 are attached in a face-to-back manner. Here, the semiconductor layer 200S is equivalent to a specific example of the "first semiconductor layer" in one embodiment of the present invention.

[0132] An insulating region 212 and an element isolation region 213 are provided in the second substrate 200. The insulating region 212 divides the semiconductor layer 200S. The element isolation region 213 is provided in a portion of the semiconductor layer 200S in the thickness direction.

[0133] The insulating region 212 is a region suitable for arranging the through electrodes 120E and 121E and the through electrode TGV so that the through electrodes 120E and 121E and the through electrode TGV are insulated from the semiconductor layer 200S. The through electrodes 120E and 121E are suitable for electrically connecting the first substrate 100 and the second substrate 200 to each other. In other words, the semiconductor layer 200S is divided by the insulating region 212, and the through electrodes 120E, 121E and the through electrode TGV are arranged in the insulating region 212. The thickness of the insulating region 212 is substantially the same as that of the semiconductor layer 200S. For example, the insulating region 212 is formed of silicon oxide.

[0134] The through electrodes 120E and 121E are provided to penetrate the insulating region 212 in the thickness direction. The upper end of each of the through electrodes 120E and 121E is connected to the wiring (the first wiring layer W1, the second wiring layer W2, and the third wiring layer W3) in the wiring layer 200T. The through electrodes 120E and 121E are each provided to penetrate the insulating region 212, the bonding film 124, the interlayer insulating film 123, and the passivation film 122. The lower ends of the through electrodes 120E and 121E are connected to the pad portions 120 and 121, respectively. The through electrode 120E is suitable for electrically connecting the pad portion 120 and the pixel circuit 210 to each other. In other words, the floating diffusion portion FD in the first substrate 100 is electrically connected to the pixel circuit 210 in the second substrate 200 through the through electrode 120E. The through electrode 121E is suitable for electrically connecting the pad portion 121 and the reference potential line VSS in the wiring layer 200T to each other. In other words, the VSS contact region 118 in the first substrate 100 is electrically connected to the reference potential line VSS in the second substrate 200 through the through electrode 121E.

[0135] The through electrode TGV is arranged to penetrate the insulating region 212 in the thickness direction. The upper end of the through electrode TGV is connected to the wiring in the wiring layer 200T. The through electrode TGV is arranged to penetrate the insulating region 212, the bonding film 124, the interlayer insulating film 123 and the passivation film 122. The lower end of the through electrode TGV is connected to the transmission gate TG. Such a through electrode TGV is suitable for electrically connecting the transmission gate TG (transmission gate TG1, TG2, TG3 and TG4) of each of the pixels 541A, 541B, 541C and 541D to the wiring (a part of the row drive signal line 542) in the wiring layer 200T. In other words, through the through electrode TGV, the transmission gate TG in the first substrate 100 is electrically connected to the wiring TRG in the second substrate 200, thereby allowing the drive signal to be transmitted to each transmission transistor TR (transmission transistor TR1, TR2, TR3 and TR4).

[0136] The element separation region 213 is arranged on the front side of the semiconductor layer 200S. The element separation region 213 has a shallow trench isolation (STI: Shallow Trench Isolation) structure. In the element separation region 213, the semiconductor layer 200S is first partially removed in the thickness direction (the direction perpendicular to the main surface of the second substrate 200), and then the portion where the semiconductor layer 200S has been removed is filled with an insulating film. For example, the insulating film is formed of silicon oxide. Using the element separation region 213, element separation can be implemented between multiple transistors included in the pixel circuit 210 according to the layout of the pixel circuit 210. The semiconductor layer 200S extends below the element separation region 213 (in the deep part of the semiconductor layer 200S). In the present embodiment, a well region 211 is selectively formed below the element separation region 213.

[0137] As described above, for example, the pixel circuit 210 includes four transistors, specifically, an amplifier transistor AMP, a selection transistor SEL, a reset transistor RST, and an FD conversion gain switching transistor FDG. Figure 6B As shown, among the four transistors, the amplifier transistor AMP and the selection transistor SEL are arranged side by side in the X-axis direction, and the reset transistor RST and the FD conversion gain switching transistor FDG are arranged side by side in the X-axis direction. The amplifier transistor AMP and the selection transistor SEL arranged side by side in the X-axis direction are arranged in a continuous semiconductor layer 200S. The reset transistor RST and the FD conversion gain switching transistor FDG arranged side by side in the X-axis direction are arranged in a continuous semiconductor layer 200S. The element separation between the amplifier transistor AMP and the selection transistor SEL is achieved by the element separation region 213. The element separation between the reset transistor RST and the FD conversion gain switching transistor FDG is achieved by the element separation region 213. The semiconductor layer 200S provided with the amplifier transistor AMP and the selection transistor SEL and the semiconductor layer 200S provided with the reset transistor RST and the FD conversion gain switching transistor FDG are separated by the insulating region 212.

[0138] Here, the amplifier transistor AMP, the selection transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG each correspond to a specific example of the "first active element" in one embodiment of the present invention. In addition, in the case where one of the above four transistors is regarded as the "first active element", the transistor arranged side by side with the transistor and formed in the same semiconductor layer 200S corresponds to the "second active element" in one embodiment of the present invention. Specifically, for example, in the case where the amplifier transistor AMP is regarded as the "first active element", the selection transistor SEL formed in the same semiconductor layer 200S and arranged side by side with the amplifier transistor AMP in the X-axis direction corresponds to the "second active element".

[0139] A detailed description is given below of the structure of the amplifier transistor AMP, the selection transistor SEL, the reset transistor RST, the FD conversion gain switching transistor FDG, and the semiconductor layer 200S provided with these transistors. It should be noted that in the case where the constituent elements of the amplifier transistor AMP, the selection transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG do not need to be distinguished from each other, they are referred to as pixel transistors.

[0140] For example, the amplification transistor AMP, the selection transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG each preferably has a three-dimensional structure such as a fin type.

[0141] A transistor with a three-dimensional structure refers to a transistor having a plurality of gate electrode planes opposite to a channel, or a transistor having a gate electrode curved surface around a channel. In such a transistor with a three-dimensional structure, when the transistor has the same footprint as a planar transistor, the effective gate width can be increased compared to a planar transistor. Therefore, a large amount of current flows through the transistor with a three-dimensional structure, and the transconductance (gm) becomes higher. Therefore, in a transistor with a three-dimensional structure, the operating speed can be increased compared to a planar transistor. In addition, random noise (RN) can also be reduced. In addition, the gate area of ​​a transistor with a three-dimensional structure is increased compared to a planar transistor, so the RTS (Random Telegraph Signal) noise is reduced.

[0142] Fig. 7A Schematically shows the Figure 6B The cross-sectional structure corresponding to the line II′ shown in FIG. Figure 7B Schematically shows the Figure 6B The line II-II′ shown in FIG. 1 corresponds to the cross-sectional structure. Figure 7CSchematically shows the Figure 6B The line III-III′ shown in FIG. 1 corresponds to the cross-sectional structure. Fig.7D Schematically shows the Figure 6B The line IV-IV′ shown in FIG. 1 corresponds to the cross-sectional structure.

[0143] In this embodiment, each pixel transistor including the amplifier transistor AMP, the selection transistor SEL, the reset transistor RST and the FD conversion gain switching transistor FDG has a fin 200A, a gate electrode 214G, a source region 214S, a drain region 214D and an LDD (lightly doped drain: Lightly Doped Drain) region 214L. The fin 200A extends in a single direction. The gate electrode 214G surrounds the upper surface and two side walls of the fin 200A. The source region 214S and the drain region 214D are respectively formed at the two ends in the extension direction of the fin 200A. The LDD region 214L is respectively arranged between the gate electrode 214G and the source region 214S and between the gate electrode 214G and the drain region 214D. In addition, each pixel transistor also includes a sidewall 215 and a gate insulating film 216. The sidewall 215 surrounds the gate electrode 214G formed on the semiconductor layer 200S. The gate insulating film 216 is provided between the gate electrode 214G and the semiconductor layer 200S.

[0144] The fin 200A is formed by processing the semiconductor layer 200S from the front side 200S1. For example, the fin 200A extends in the Y-axis direction and has a side wall that is substantially perpendicular to the front side 200S1 of the semiconductor layer 200S. In other words, the fin 200A is arranged to stand upright on the front side 200S1 of the semiconductor layer 200S with a substantially constant width in a direction substantially perpendicular to the front side 200S1. In the present embodiment, the fin 200A is formed by an undoped semiconductor layer 200S. Here, "undoped" refers to a state in which ions for element separation are not passed. The undoped region is equivalent to a specific example of the "first semiconductor region" in one embodiment of the present invention.

[0145] It should be noted that Fig. 7A and Figure 7B Each shows an example in which the side wall of the fin 200A is formed upright relative to the front surface 200S1 of the semiconductor layer 200S; however, the side wall of the base of the fin 200A may also form a curved surface so that the base is expanded. Thereby, stress concentration on the base of the fin 200A can be relieved, so that fracture during the manufacturing process can be prevented and the yield rate is improved.

[0146] Each pixel transistor includes one or more fins 200A. Specifically, for example, the amplifier transistor AMP has two fins 200A arranged side by side in the X-axis direction. The selection transistor SEL, the reset transistor RST, and the FD conversion gain switching transistor FDG each have one fin 200A.

[0147] The gate electrode 214G includes vertical portions 214Ga and 214Gb and a horizontal portion 214Gc. The vertical portions 214Ga and 214Gb are disposed in the semiconductor layer 200S. The horizontal portion 214Gc is opposite to the front surface 200S1 of the semiconductor layer 200S. Each of the vertical portions 214Ga and 214Gb extends in the thickness direction of the semiconductor layer 200S. One end of each of the vertical portions 214Ga and 214Gb is connected to the horizontal portion 214Gc, and the other end is disposed in the semiconductor layer 200S. Specifically, the gate electrode 214G includes: vertical portions 214Ga and 214Gb, which are respectively buried in the semiconductor layer 200S along the side walls of the fin 200A; and a horizontal portion 214Gc, which connects the vertical portion 214Ga and the vertical portion 214Gb disposed side by side in the X-axis direction across the fin 200A. The vertical portion 214Ga is equivalent to a specific example of the "first electrode portion" in one embodiment of the present invention, the vertical portion 214Gb is equivalent to a specific example of the "second electrode portion" in one embodiment of the present invention, and the horizontal portion 214Gc is equivalent to a specific example of the "third electrode portion" in one embodiment of the present invention.

[0148] In addition, like the amplifier transistor AMP, the transistor having two fins 200A further includes a vertical portion 214Gd located between the vertical portion 214Ga and the vertical portion 214Gb. Like the vertical portions 214Ga and 214Gb, one end of the vertical portion 214Gd is connected to the horizontal portion 214Gc, and the other end is disposed in the semiconductor layer 200S. The vertical portion 214Gd is equivalent to a specific example of a "fourth electrode portion" in one embodiment of the present invention.

[0149] In addition, the active region 200X of the semiconductor layer 200S included in each pixel transistor has a cutout portion X. Specifically, the cutout portion X is provided in a fin 200A portion located at the outer edge of the active region 200X having a substantially rectangular shape, and the vertical portions 214Ga and 214Gb of the gate 214 are buried in the fin 200A portion.

[0150] Figure 8 A channel formed at the cutout portion X of the semiconductor layer 200S is schematically shown. Fig. 92 is a development diagram of a channel formed at a cutout portion X of a semiconductor layer 200S in a pixel transistor (eg, a selection transistor SEL) having one fin 200A.

[0151] In this embodiment, for example, Figure 6B As shown, the horizontal portion 214Gc of the gate electrode 214G covers the entire fin 200A extending in the Y-axis direction, and also extends to cover a portion of each of the source region 214S and the drain region 214D respectively provided at both ends of the fin 200A. As a result, a channel is formed in the cutout portion X. Specifically, as Figure 8 and Fig. 9 As shown, the surface channel 214Ca is formed near the front side 200S1 of the semiconductor layer 200S opposite to the horizontal portion 214Gc of the gate electrode 214G; the sidewall channel 214Cb is formed at the side wall of the fin 200A opposite to each of the side surfaces of the vertical portions 214Ga and 214Gb of the gate electrode 214G; the bottom channel 214Cc is formed at the semiconductor layer 200S opposite to the bottom surface of each of the vertical portions 214Ga and 214Gb; and the transmission channel 214Cd is formed at the semiconductor layer 200S opposite to a pair of side surfaces of each of the vertical portions 214Ga and 214Gb opposite to each other in the Y-axis direction (for example, opposite to Figure 7B The dotted shaded portion in FIG. 200S is opposite to the semiconductor layer 200S. It should be noted that Fig. 9 As shown, the width of the sidewall channel 214Cb in the Y-axis direction is narrowed from the front surface 200S1 of the semiconductor layer 200S toward the back surface 200S2. This allows the current to flow through the bottom channel 214Cc and the transfer channel 214Cd while flowing through the surface channel 214Ca and the sidewall channel 214Cb.

[0152] For example, the wiring layer 200T includes a passivation film 221, an interlayer insulating film 222, and multilayer wiring (a first wiring layer W1, a second wiring layer W2, and a third wiring layer W3). For example, the passivation film 221 contacts the front of the semiconductor layer 200S and covers the entire front of the semiconductor layer 200S. The passivation film 221 covers the gate electrodes of each of the selection transistor SEL, the amplifier transistor AMP, the reset transistor RST, and the FD conversion gain switching transistor FDG. The interlayer insulating film 222 is disposed between the passivation film 221 and the third substrate 300. The interlayer insulating film 222 separates the multilayer wiring (the first wiring layer W1, the second wiring layer W2, and the third wiring layer W3) from each other. For example, the interlayer insulating film 222 is formed of silicon oxide.

[0153] In the wiring layer 200T, for example, the first wiring layer W1, the second wiring layer W2, the third wiring layer W3, and the contact portions 201 and 202 are provided in order from the semiconductor layer 200S side, and they are insulated from each other by the interlayer insulating film 222. In the interlayer insulating film 222, a plurality of connection portions for connecting the first wiring layer W1, the second wiring layer W2, or the third wiring layer W3 to the lower layer of each of them are provided. These connection portions are portions obtained by burying a conductive material in a connection hole provided in the interlayer insulating film 222.

[0154] For example, the through electrode 120E is connected to the gate of the amplifier transistor AMP and the source of the FD conversion gain switching transistor FDG through the first wiring layer W1. For example, the through electrode 121E is connected to a connection portion connected to a VSS contact region provided in the semiconductor layer 200S through the first wiring layer W1. Thereby, the VSS contact region of the semiconductor layer 200S and the VSS contact region 118 of the semiconductor layer 100S are electrically connected to each other.

[0155] The contact portions 201 and 202 may be respectively arranged at corresponding positions overlapping with the pixel array portion 540 in a plan view, or may be arranged in a peripheral portion located outside the pixel array portion 520. The contact portions 201 and 202 are arranged on the front side of the second substrate 200 (the surface on the wiring layer 200T side). For example, the contact portions 201 and 202 each include a metal such as Cu (copper) or Al (aluminum). The contact portions 201 and 202 are exposed on the front side of the wiring layer 200T (the surface on the third substrate 300 side). The contact portions 201 and 202 are used to attach the second substrate 200 and the third substrate 300 to each other while electrically connecting the second substrate 200 and the third substrate 300 to each other.

[0156] For example, the third substrate 300 includes a wiring layer 300T and a semiconductor layer 300S which are sequentially arranged from the second substrate 200 side. For example, the front side of the semiconductor layer 300S is arranged on the second substrate 200 side. The semiconductor layer 300S is formed of a silicon substrate. A circuit is provided in a portion of the front side of the semiconductor layer 300S. Specifically, for example, in a portion of the front side of the semiconductor layer 300S, at least a portion of the input section 510A, the row drive section 520, the timing control section 530, the column signal processing section 550, the image signal processing section 560, and the output section 510B are provided. For example, the wiring layer 300T provided between the semiconductor layer 300S and the second substrate 200 includes: an interlayer insulating film; a multilayer wiring separated by an interlayer insulating film; and contact portions 301 and 302. The contact portions 301 and 302 are exposed on the front side of the wiring layer 300T (the surface on the second substrate 200 side). The contact portion 301 contacts the contact portion 201 of the second substrate 200, and the contact portion 302 contacts the contact portion 202 of the second substrate 200. The contact portions 301 and 302 are each electrically connected to a circuit (e.g., at least one of the input portion 510A, the row driving portion 520, the timing control portion 530, the column signal processing portion 550, the image signal processing portion 560, and the output portion 510B) formed in the semiconductor layer 300S. For example, the contact portions 301 and 302 each include a metal such as Cu (copper) or aluminum (Al). For example, an external terminal is connected to the input portion 510A via the connection hole portion H1, and an external terminal is connected to the output portion 510B via the connection hole portion H2.

[0157] [Method for manufacturing pixel transistor]

[0158] FIG. 10A to FIG. 10J They are shown respectively Figure 6B An example of a method for manufacturing a pixel transistor is shown in FIG.

[0159] First, a hard mask is formed on the front surface 200S1 of the semiconductor layer 200S, and photolithography and etching are performed. Fig. 10A As shown, a plurality of trenches H3 are formed at the front surface 200S1 of the semiconductor layer 200S, and a plurality of fins 200A are formed vertically at equal intervals on the entire surface of the front surface 200S1 of the semiconductor layer 200S. As a result, each fin 200A having a substantially constant width and standing in a substantially vertical direction is formed at the front surface 200S1 of the semiconductor layer 200S.

[0160] Then, if Fig. 10BAs shown in FIG. 1 , a silicon nitride film is formed as a hard mask 231 in such a manner as to fill the trenches H3 between the plurality of fins 200A. Then, the surface of the hard mask 231 is ground and planarized by chemical mechanical polishing (CMP). Fig. 10C As shown, the hard mask 231 is patterned by photolithography and etching in a manner to protect the active area 200X of the pixel transistor. Fig. 10D As shown, the fins 200A exposed from the hard mask 231 are etched. At this time, a portion of the fins 200A remains, thereby forming a protrusion 200B.

[0161] Then, if Fig.10E As shown in FIG. 2 , p-type impurities (e.g., boron (B)) are implanted into the semiconductor layer 200S exposed from the hard mask 231, thereby forming a well region 211. Therefore, the well region 211 is formed outside the fin 200A, and thus, the fin 200A in which all fin portions are in an undoped state is formed. Fig.10F As shown in FIG. 1 , an oxide film 232 is formed on the semiconductor layer 200S by, for example, thermal oxidation. Figure 10G As shown, the oxide film 232 and the hard mask 231 are ground by CMP to flatten their surfaces. As a result, an element isolation region 213 for isolating adjacent pixel transistors is formed. At this time, the convex portion 200B formed in the semiconductor layer 200S can improve the adhesion strength between the semiconductor layer 200S and the element isolation region 213 by being embedded in the element isolation region 213.

[0162] Then, if Fig. 10H As shown, for example, the hard mask 231 is removed by a hot phosphoric acid solution, and then a continuous gate insulating film 216 is formed on the side and upper surfaces of each of the plurality of fins 200A and on the surface of the semiconductor layer 200S exposed between adjacent fins 200A. Fig.10I As shown in FIG. 2 , a polysilicon film 233 is formed to fill between adjacent fins 200A and between the fins 200A and the element isolation region 213. Next, as shown in FIG. Fig.10J As shown, the polysilicon film 233 is processed. As a result, the gate electrode 214G of the pixel transistor (for example, each of the amplifier transistor AMP and the selection transistor SEL) is formed.

[0163] Then, n-type impurities (e.g., phosphorus (P)) are implanted in the active region 200X of the semiconductor layer 200S exposed from the gate electrode 214G, thereby forming the LDD region 214L, and then, the sidewall 215 is formed on the side of the gate electrode 214G. Finally, n-type impurities (e.g., arsenic (As)) are implanted at a higher concentration than that of the LDD region 214L, thereby forming the source region 214S and the drain region 214D. Thus, the Fig. 7A Pixel transistor shown in FIG.

[0164] It should be noted that Fig. 7A etc. show an example in which the well region 211 is selectively formed only under the element separation region 213; however, this is not restrictive. Fig.11 As shown, the well region 211 may extend over the entire back surface 200S2 of the semiconductor layer 200S without reaching the base of the fin 200A. This enables more stable element separation. Fig.12 As shown, before the front side 200S1 of the semiconductor layer 200S is processed by photolithography and etching to form a plurality of fins 200A, p-type impurities (e.g., boron (B)) can be injected from the front side 200S1 of the semiconductor layer 200S by ion implantation, etc., thereby forming a well region 211 extending throughout the entire back side 200S2 of the semiconductor layer 200S.

[0165] also, Fig. 10A An example is shown in which a plurality of fins 200A are formed vertically at equal intervals on the entire surface of the front surface 200S1 of the semiconductor layer 200S; however, this is not restrictive. For example, as in the imaging device 1 of the present embodiment, in the case where the photodiode PD and the pixel circuit 210 are provided on different substrates, a plurality of pixel transistors included in the pixel circuit 210 can also be densely arranged. Therefore, for example, Fig.13 As shown, the groove H3 can be provided only in a predetermined area to form a plurality of fins 200A. In other words, it is not necessary to form the fins 200A as dummy objects. By making a plurality of pixel transistors densely arranged, it is also possible to form fins 200A erected in a substantially vertical direction with a substantially constant width without forming the fins 200A as dummy objects.

[0166] [Operation of the camera device]

[0167] Next, refer to Fig.14 and Fig.15 The operation of the imaging device 1 will be described. Fig.14 and Fig.15 Corresponding to Figure 3 A diagram with arrows indicating the paths of various signals has been added. Fig.14 The paths of input signals, power supply potential, and reference potential input from the outside to the imaging device 1 are shown by arrows. Fig.15 The signal path of the pixel signal output from the image pickup device 1 to the outside is shown by arrows. For example, the input signal (e.g., pixel clock and synchronization signal) input to the image pickup device 1 via the input portion 510A is transmitted to the row drive portion 520 of the third substrate 300, and the row drive portion 520 generates a row drive signal. The row drive signal is transmitted to the second substrate 200 via the contact portions 301 and 201. In addition, the row drive signal also reaches each unit cell 539 of the pixel array portion 540 via the row drive signal line 542 in the wiring layer 200T. The drive signal other than the drive signal of the transmission gate TG among the row drive signals reaching the unit cell 539 of the second substrate 200 is input to the pixel circuit 210, and each transistor included in the pixel circuit 210 is driven. The drive signal of the transmission gate TG is input to the transmission gate TG of the first substrate 100, and the pixel 541 is driven. In addition, the power supply potential and the reference potential provided to the input section 510A (input terminal 511) of the third substrate 300 from the outside of the image pickup device 1 are transmitted to the second substrate 200 via the contact sections 301 and 201, and are also provided to the pixel circuit 210 of each unit cell 539 via the wiring in the wiring layer 200T. The reference potential is also provided to the pixel 541 of the first substrate 100. On the other hand, the pixel signal obtained by the photoelectric conversion of the pixel 541 of the first substrate 100 is transmitted to the pixel circuit 210 of the second substrate 200 for each unit cell 539. The pixel signal based on the pixel signal is transmitted from the pixel circuit 210 to the third substrate 300 via the vertical signal line 543 and the contact sections 202 and 302. The pixel signal is output to the outside via the output section 510B after being processed by the column signal processing section 550 and the image signal processing section 560 of the third substrate 300.

[0168] [Function and Effect]

[0169] Fig.16 The planar structure of a pixel transistor as Comparative Example 1 is schematically shown. Fig.17 Schematically shows the Fig.16 The cross-sectional structure corresponding to the line VV′ shown in FIG. Fig.18 Schematically shows the Fig.16 For example, in the case where the MOS transistors arranged side by side are separated from each other, for example, if they are n-type transistors, then Fig.17As shown, a p-type well 1211 is formed without gaps from below the element separation portion 1213 having an STI structure in a manner that covers transistors of the same type that are adjacent to each other. This results in the formation of a diode between the well 1211 and each of the source region 1214S and the drain region 1214D. By applying a voltage to the well 1211 so that the diode does not operate, it is possible to prevent current from flowing between transistors that are adjacent to each other. Specifically, for example, a voltage that is lower than or equal to the lowest voltage among the voltages used in the transistors is applied to the p-type well 1211. This can prevent current from flowing from the drain region 1214D having the highest voltage to the source region 1214S of the adjacent transistor.

[0170] In a general NMOS transistor manufacturing process, after processing the element separation portion 1213, for example, p-type impurities (for example, boron (B)) are injected, thereby forming a well 1211 on the entire surface of the semiconductor layer 1200. Then, a trench is formed, and then various processes including gate processing, LDD injection, sidewall processing, and injection of n-type impurities (for example, arsenic (As)) for forming a source region and a drain region are performed. Thus, a well 1211 having a structure such as a semiconductor layer 1200 is formed. Fig.17 and Fig.18 In the transistor formed in this way, Fig.17 and Fig.18 As shown, because the p-type well 1211 is formed at the base of the fin 1200A, an area is created where it is difficult for current to flow even if the channel is inverted. For example, when the gm of a planar NMOS transistor is 1, even if a fin-type transistor in which the channel length (L) / channel width (W) is designed so that gm is 1.6 times is made, the gm of the fin-type transistor made by the above method will become 1.4. In addition, since the base of the fin 1200A does not contribute to the channel, the RTS (random telegraph signal) noise is not improved as expected.

[0171] In contrast, in the image pickup device 1 of the present embodiment, in the pixel transistor having the fin-type three-dimensional structure, the entire fin 200A formed between the vertical portions 214Ga and 214Gb constituting the gate electrode 214G is formed using the undoped semiconductor layer 200S. Thus, the entire fin 200A can be used as a channel region. Therefore, gm can be improved compared to a general fin-type transistor. In addition, RTS noise can be improved.

[0172] As described above, in the imaging device 1 of the present embodiment, device characteristics can be improved compared to an imaging device including a general fin-type pixel transistor.

[0173] Fig.19 An example of a planar layout of a plurality of fins 1200A is schematically shown. Fig. 20 Schematically shows an example of the cross-sectional shape of each fin 1200A when forming the fin 1200A by etching based on the Fig.19 plane layout shown. Fig. 20 Schematically shows another example of the cross-sectional shape of each fin 1200A when forming the fin 1200A by etching based on the Fig.19 plane layout shown. For example, in the case of forming multiple fins 1200A having the Fig.19 plane layout shown by anisotropic etching, the sides of the fins 1200A are tapered. Anisotropic dry etching can be performed vertically by utilizing the balance between the redeposition of the reaction product of both the etching gas and the material to be etched and the etching. However, when the etching area varies at the periphery, the difference between the etching areas changes the balance between the deposition and the etching of the reaction product.

[0174] As Fig.19 shown, in a layout where the pitch between adjacent fins 1200A increases in the order of W2 < W1 < W3 < W4, for example, when adjusting the flow rate and pressure of the etching gas, and the voltage of the electrode, etc. so that the respective side walls of the fins 1200A adjacent to each other at the pitch W2 are upright, as Fig. 20 shown, the respective side walls of the fins 1200A adjacent to each other at the pitch W2 can be processed upright, but the side walls of other parts are tapered according to the pitch. In addition, when adjusting the flow rate and pressure of the etching gas, and the voltage of the electrode, etc. so that the side walls of the fins 1200A between the pitch W3 and the pitch W4 are upright, as Fig.21 shown, the side walls of the fins 1200A arranged at a pitch smaller than the pitch W3 or W4 are over-etched, and the fins 1200A respectively have a curved cross-sectional shape. Thus, when the gate insulating film is formed on the surface of the fin 1200A having a curved cross-sectional shape, the gate insulating film formed at the indented portion becomes extremely thin, which may lead to a reduction in durability, breakdown, etc.

[0175] In order to solve this problem, a possible method is to arrange dummy fins so that the spacing between adjacent fins is equal and the etching area of ​​the periphery is uniform. However, in the case where a through electrode is arranged at the periphery as in the imaging device 1 of the present embodiment, dummy fins cannot be easily arranged. Therefore, the above-mentioned solid-state imaging device adopts the following shape of the vertical gate electrode portion: wherein the fin width narrows in the depth direction of the semiconductor substrate. However, because the fin width at the base is wider, the pitch of the transistor is thereby limited by the fin width at the base. This leads to the problem of increased transistor size. In addition, it is necessary to study the etching conditions for how to prevent the fins from having a curved cross-sectional shape under each layout.

[0176] In the imaging device 1 of the present embodiment, as described above, the plurality of fins 120A and the active region 120X are processed separately. Fig. 10A As shown, a groove H3 is formed so that a plurality of fins 200A including a dummy fin 200A can be arranged at equal intervals, and then the dummy fin 200A is selectively removed to form an element separation region 213. In this way, the side walls of all fins 200A can be processed roughly upright. Therefore, the size of the transistor in the width direction (X-axis direction) of the fin 200A can be reduced, thereby improving the area efficiency. In addition, the width of each groove H3 used to form the fin 200A is roughly constant. Therefore, the research time for etching conditions can be reduced. In addition, by making the side walls of the fin 200A roughly upright, the short channel effect (SCE: short channel effect) can be improved.

[0177] Fig. 22 The planar structure of a pixel transistor as Comparative Example 2 is schematically shown. Fig.23 Schematically shows the Fig. 22 The line VIII-VIII′ shown in FIG. 1 corresponds to the cross-sectional configuration. Fig.24 Schematically shows the Fig. 22 The cross-sectional structure corresponding to the line IX-IX′ shown in FIG. Fig.25 The transconductance (gm) of each of Comparative Example 2 and the embodiment is shown. Fig.26 The current-voltage characteristics of Comparative Example 2 and the embodiment are shown. Fig.23As shown, when the buried portion of the gate electrode 1214G is not tapered, a channel is formed at the bottom surface of the buried gate electrode 1214G. However, because there is an element separation portion 1213 at each of the two ends of the channel at the bottom surface, the current will not flow even if the channel is reversed. In addition, if the depth of the fin 1200A is to be increased (for example, to 200nm), and the source region 1214S and the drain region 1214D are to be formed to a depth corresponding to the base of the fin 1200A, impurities will diffuse into the vertical channel portion. This results in a transistor that cannot be turned off. Typically, the depth limit of the source region 1214S and the drain region 1214D is approximately 100nm to 150nm, and the impurity concentration is reduced in deeper portions than this. Therefore, in the vertical channel portion of the fin 1200A having a depth greater than 100 nm to 150 nm, the resistance of the source region 1214S and the drain region 1214D increases, and current does not flow much.

[0178] In contrast, in the image pickup device 1 of the present embodiment, a cutout portion X is formed at the outer edge of the active region 200X having a substantially rectangular shape, the vertical portions 214Ga and 214Gb of the gate 214 are formed at the cutout portion X, and the horizontal portion 214Gc extends to cover a portion of the source region 214S and a portion of the drain region 214D. Therefore, in addition to the surface channel 214Ca, a sidewall channel 214Cb, a bottom channel 214Cc, and a transfer channel 214Cd are formed at the cutout portion X. Therefore, as shown in FIG. Fig.25 and Fig.26 As shown, compared with the above-mentioned transistor (Comparative Example 2), even when the area of ​​the transistor is the same, a transistor with higher gm can be provided, and the transistor has more excellent current-voltage characteristics.

[0179] The following is a description of Modification 1 and Modification 2, Application Examples, and Application Examples of the present invention. In the following, components similar to those in the above-described embodiment are denoted by the same reference numerals, and description thereof is omitted where appropriate.

[0180] [2. Modifications]

[0181] [2-1. Modification 1]

[0182] Fig. 27 The cross-sectional structure of a pixel transistor according to Modification 1 of the present invention is schematically shown.

[0183] In the above-described embodiment, an example has been described in which the width of the horizontal portion 214Gc included in the gate electrode 214G extending on the source region 214S side and the width of the horizontal portion 214Gc extending on the drain region 214D side are the same as each other; however, this is not restrictive. In this modification, Fig. 27 As shown, the width ( W5 ) of the horizontal portion 214Gc included in the gate electrode 214G extending on the drain region 214D side is set to be larger than the width ( W6 ) of the horizontal portion 214Gc extending on the source region 214S side ( W5 > W6 ).

[0184] In NMOS transistors, there is a problem that the current value decreases due to the increase in threshold voltage or the decrease in mobility caused by the occurrence of the hot carrier injection (HCI) phenomenon. As a countermeasure for this, an LDD region is formed in such a way that the electric field on the drain side does not increase, and then a side wall is formed around the gate electrode, and a source region and a drain region with a higher impurity concentration than the LDD region are formed. Fig.28 The relationship between noise current (Isub) and lifetime based on sidewall width is shown. This shows that if the sidewall width is reduced to reduce the footprint, the lifetime will be shortened.

[0185] In contrast, in this modification, the horizontal portion 214Gc included in the gate electrode 214G is made to protrude more on the drain region 214D side to which a high voltage is applied. The protrusion of the horizontal portion 214Gc on the drain region 214D side can achieve an effect similar to the effect achieved by the formation of the side wall 215. Specifically, by making the horizontal portion 214Gc protrude more on the drain region 214D side, the distance between the drain region 214D and the channel end is ensured. This can relax the electric field at the end of the gate electrode 142G. In addition, a sufficient area for forming the LDD region 214L that can relax the electric field can be ensured between the drain region 214D and the channel region.

[0186] Therefore, the size of the transistor in the current flow direction (Y-axis direction) can be reduced without sacrificing the life.

[0187] [2-2. Modification 2]

[0188] Figures 29A to 29K An example of a method for manufacturing a pixel transistor according to Modification 2 of the present invention is respectively shown.

[0189] First, if Fig.29A As shown in FIG. 1 , the semiconductor layer 200S having the well region 211 formed therein in advance is subjected to photolithography and etching to process the semiconductor layer 200S except for the active region. Then, as shown in FIG. Fig.29BAs shown in FIG. 1 , a silicon nitride film (SiN film) 235 is formed, and its surface is planarized by CMP, and then a hard mask 234 is patterned by photolithography. Then, as shown in FIG. Fig.29C As shown, the SiN film 235 is etched, and then p-type impurities (for example, boron (B)) are implanted into the semiconductor layer 200S exposed from the SiN film 235 to extend the well region 211 .

[0190] Then, if Fig.29D As shown in FIG. 1 , an oxide film to be the element isolation region 213 is formed on the semiconductor layer 200S by, for example, thermal oxidation. Then, as shown in FIG. Fig.29E As shown in FIG. 2 , the oxide film and SiN film 235 to be the element isolation region 213 are polished by CMP to flatten the surface, and then a hard mask 236 is formed. As the hard mask 236, for example, an oxide film or a multilayer film obtained by stacking a silicon nitride film on an oxide film can be used. Then, as shown in FIG. Fig.29F As shown, the hard mask 236 is patterned by photolithography.

[0191] Then, if Figure 29G As shown in FIG. 1 , the semiconductor layer 200S exposed from the hard mask 236 is etched to form trenches H3 having the same width. Thus, a plurality of fins 200A are formed. Then, as shown in FIG. Fig.29H As shown, the hard mask 236 is removed using a hot phosphoric acid solution. Then, as shown in FIG. Fig.29I As shown, a continuous gate insulating film 216 is formed on the side and upper surfaces of each of the plurality of fins 200A and on the surface of the semiconductor layer 200S exposed between the adjacent fins 200A. Then, a polysilicon film 233 is formed to fill between the adjacent fins 200A and between the fins 200A and the element isolation region 213.

[0192] Then, if Fig.29J As shown, the polysilicon film 233 is processed. As a result, the gate electrode 214G of the pixel transistor (for example, each of the amplifier transistor AMP and the selection transistor SEL) is formed. Then, n-type impurities (for example, phosphorus (P)) are injected into the active region 200X of the semiconductor layer 200S exposed from the gate electrode 214G to form the LDD region 214L, and then the sidewall 215 is formed on the side of the gate electrode 214G. Finally, n-type impurities (for example, arsenic (As)) are injected at a higher concentration than the concentration of the LDD region 214L to form the source region 214S and the drain region 214D. Thus, the Figure 29K Pixel transistor shown in FIG.

[0193] Fig.30 Schematically shows Figure 29KThe planar structure of the amplifier transistor AMP and the selection transistor SEL shown. In the pixel transistor manufactured by the manufacturing process of this modification, since the element separation region 213 is formed first, the groove H3 for forming the cutout portion X and formed at the outer edge of the active region is retained as it is. Therefore, the width of each of the vertical portions 214Ga and 214Gb of the gate electrode 214G is wider than the width of each of the vertical portions 214Ga and 214Gb of the gate electrode 214G formed at the cutout portion X in the pixel transistor manufactured by the manufacturing process described in the above embodiment. Specifically, in the above embodiment, for example, the width of each of the vertical portions 214Ga and 214Gb of the gate electrode 214G is smaller than the width of the vertical portion 214Gd buried in the active region of the amplifier transistor AMP; but in contrast, the width of each of the vertical portions 214Ga and 214Gb of the gate electrode 214G formed by the manufacturing process of this modification is approximately the same as the width of the vertical portion 214Gd buried in the active region of the amplifier transistor AMP. Accordingly, the area of ​​the gate electrode 214G increases.

[0194] As described above, although the area efficiency is reduced compared with the pixel transistor of the above embodiment, by forming a plurality of fins 200A after forming the element isolation region 213 , a pixel transistor that can achieve effects similar to those of the above embodiment can be formed.

[0195] [3. Application examples]

[0196] [Application example 1]

[0197] For example, the above-described imaging device 1 and the like can be applied to any type of electronic equipment having an imaging function. Examples of such electronic equipment include camera systems such as digital cameras or video cameras, and mobile phones having an imaging function. Fig.31 The schematic structure of the electronic device 1000 is shown.

[0198] For example, the electronic device 1000 includes a lens group 1001 , an imaging device 1 , a DSP (Digital Signal Processor) circuit 1002 , a frame memory 1003 , a display unit 1004 , a storage unit 1005 , an operation unit 1006 , and a power supply unit 1007 , which are interconnected via a bus 1008 .

[0199] The lens group 1001 receives incident light (image light) from the subject and forms an image on the imaging surface of the imaging device 1. The imaging device 1 converts the amount of incident light formed on the imaging surface by the lens group 1001 into an electrical signal in units of pixels and provides the electrical signal to the DSP circuit 1002 as a pixel signal.

[0200] The DSP circuit 1002 is a signal processing circuit that processes a signal supplied from the image pickup device 1. The DSP circuit 1002 outputs image data obtained by processing the signal from the image pickup device 1. The frame memory 1003 temporarily holds the image data processed by the DSP circuit 1002 in units of frames.

[0201] For example, the display unit 1004 includes a panel display device such as a liquid crystal panel or an organic electroluminescence (EL) panel, etc. The display unit 1004 records image data of moving images or still images captured by the imaging device 1 in a recording medium such as a semiconductor memory or a hard disk.

[0202] The operation section 1006 outputs operation signals regarding various functions possessed by the electronic device 1000 according to operations performed by the user. The power supply section 1007 appropriately supplies various power sources used as operation power sources for the DSP circuit 1002, the frame memory 1003, the display section 1004, the storage section 1005, and the operation section 1006 to these power supply objects.

[0203] [Application example 2]

[0204] Fig.32A An example of the overall configuration of a light detection system 2000 including the image pickup device 1 is schematically shown. Fig.32B 2 shows an example of a circuit configuration of a light detection system 2000. The light detection system 2000 includes: a light emitting device 2001 as a light source section for emitting infrared light L2; and a light detection device 2002 as a light receiving section including a photoelectric conversion element. As the light detection device 2002, the above-mentioned image pickup device 1 can be used. The light detection system 2000 may further include a system control section 2003, a light source driving section 2004, a sensor control section 2005, a light source side optical system 2006, and a camera side optical system 2007.

[0205] The light detection device 2002 is configured to detect light L1 and light L2. Light L1 is ambient light from the outside and is detected by the subject (object to be detected) 2100 ( Fig.32A) after being reflected by the light detecting device 2001. Light L2 is light emitted by the light emitting device 2001 and then reflected by the subject 2100. For example, light L1 is visible light, and for example, light L2 is infrared light. Light L1 can be detected by the photoelectric conversion portion of the light detecting device 2002, and light L2 can be detected by the photoelectric conversion region in the light detecting device 2002. Image information of the subject 2100 can be obtained from light L1, and distance information between the subject 2100 and the light detecting system 2000 can be obtained from light L2. For example, the light detecting system 2000 can be installed on an electronic device such as a smartphone or a moving body such as a vehicle. For example, the light emitting device 2001 may include a semiconductor laser, a surface emitting semiconductor laser, or a vertical cavity surface emitting laser (VCSEL). As a method for detecting light L2 emitted from the light emitting device 2001 by the light detecting device 2002, for example, an iTOF (indirect time of flight) method can be adopted; however, this is not restrictive. In the iTOF method, for example, the photoelectric conversion unit can measure the distance to the subject 2100 based on the time-of-flight (TOF) of light. For example, as a method for detecting the light L2 emitted from the light emitting device 2001 by the photodetection device 2002, a structured light method or a stereoscopic vision method can also be adopted. For example, in the structured light method, by projecting light having a predetermined pattern onto the subject 2100 and analyzing the degree of distortion of the projection pattern, the distance between the light detection system 2000 and the subject 2100 can be measured. In addition, in the stereoscopic vision method, by using two or more cameras and acquiring two or more images taken by observing the subject 2100 from two or more different viewpoints, the distance between the light detection system 2000 and the subject 2100 can be measured. It should be noted that the light emitting device 2001 and the light detection device 2002 can be synchronously controlled by the system control unit 2003.

[0206] [4. Application examples]

[0207] [Application examples of endoscopic surgery systems]

[0208] The technology of the present invention (the present technology) is applicable to various products. For example, the technology of the present invention can be applied to an endoscopic surgery system.

[0209] Fig.33 : is a diagram showing an example of a schematic configuration of an endoscopic surgery system to which the technology according to the present invention (the present technology) can be applied.

[0210] exist Fig.33, a state is shown in which an operator (doctor) 11131 is using an endoscopic surgery system 11000 to perform surgery on a patient 11132 on a bed 11133. As shown in the figure, the endoscopic surgery system 11000 includes: an endoscope 11100; other surgical instruments 11110 such as a pneumoperitoneum tube 11111 and an energy treatment instrument 11112; a support arm device 11120 for supporting the endoscope 11100; and a cart 11200 equipped with various devices for endoscopic surgery.

[0211] The endoscope 11100 includes: a lens barrel 11101, a region of which has a predetermined length from the distal end is inserted into a body cavity of a patient 11132; and a camera head 11102 connected to the proximal end of the lens barrel 11101. In the illustrated example, the endoscope 11100 is shown as being constructed of a hard lens barrel 11101. However, the endoscope 11100 may also be constructed of a soft lens barrel.

[0212] The lens barrel 11101 has an opening at its distal end, and the objective lens is embedded in the opening. The light source device 11203 is connected to the endoscope 11100 so that the light generated by the light source device 11203 is guided to the distal end of the lens barrel 11101 by using a light guide extending inside the lens barrel 11101, and the light is irradiated toward the observation object in the body cavity of the patient 11132 via the objective lens. It should be noted that the endoscope 11100 can be a straight-view mirror, or can be an oblique mirror or a side-view mirror.

[0213] An optical system and an imaging element are provided inside the camera head 11102, so that reflected light (observation light) from an observation object is focused on the imaging element through the optical system. The imaging element performs photoelectric conversion on the observation light, and generates an electrical signal corresponding to the observation light, that is, an image signal corresponding to the observation image. The image signal is transmitted to the CCU 11201 as RAW data.

[0214] The CCU 11201 includes a central processing unit (CPU) or a graphics processing unit (GPU), etc., and comprehensively controls the operations of the endoscope 11100 and the display device 11202. In addition, the CCU 11201 receives an image signal from the camera head 11102, and performs various image processing such as development processing (demosaic processing) on ​​the image signal to display an image based on the image signal.

[0215] The display device 11202 displays an image based on an image signal that has been subjected to image processing by the CCU 11201 , under the control of the CCU 11201 .

[0216] For example, the light source device 11203 includes a light source such as a light emitting diode (LED), and supplies irradiation light for imaging a surgical site or the like to the endoscope 11100 .

[0217] The input device 11204 is an input interface for the endoscopic surgery system 11000. The user can input various information or instructions to the endoscopic surgery system 11000 via the input device 11204. For example, the user inputs instructions for changing the imaging conditions (type of irradiation light, magnification, focal length, etc.) of the endoscope 11100.

[0218] The treatment instrument control device 11205 controls the driving of the energy treatment instrument 11112 for burning or cutting tissues, or sealing blood vessels, etc. The pneumoperitoneum device 11206 injects gas into the body cavity of the patient 11132 through the pneumoperitoneum tube 11111 to expand the body cavity, so as to ensure the field of view of the endoscope 11100 and ensure the working space of the operator. The recorder 11207 is a device capable of recording various information related to the operation. The printer 11208 is a device capable of printing various information related to the operation in various forms such as text, images or charts.

[0219] It should be noted that the light source device 11203 for supplying irradiation light to the endoscope 11100 when imaging the surgical site may include, for example, an LED, a laser light source, or a white light source composed of a combination thereof. In the case where the white light source is composed of a combination of RGB (red, green, and blue) laser light sources, since the output intensity and output timing of each color (various wavelengths) can be controlled with high precision, the white balance of the captured image can be adjusted in the light source device 11203. In addition, in this case, by irradiating the laser light from each of the RGB laser light sources on the observation object in a time-division manner and controlling the drive of the imaging element of the camera head 11102 in synchronization with the irradiation timing. It is possible to capture images corresponding to each of the RGB in a time-division manner. According to this method, a color image can be obtained even when a color filter is not provided in the imaging element.

[0220] In addition, the drive of the light source device 11203 can be controlled so that the light intensity to be output changes at predetermined intervals. By controlling the drive of the imaging element of the camera head 11102 in synchronization with the timing of the change in light intensity, images are acquired in a time-division manner, and the images are synthesized, so that a high dynamic range image without underexposed black spots and overexposed white spots can be generated.

[0221] In addition, the light source device 11203 may be configured to supply light of a predetermined wavelength band corresponding to special light observation. In special light observation, for example, so-called narrow-band light observation (narrow-band imaging) may be performed as follows: that is, by utilizing the wavelength dependence of light absorption in body tissue, light having a narrow band domain compared to the irradiation light (i.e., white light) during ordinary observation is irradiated, thereby imaging predetermined tissues such as blood vessels of the surface layer of the mucosa with high contrast. Alternatively, in special light observation, fluorescence observation may be performed to obtain an image using fluorescence generated by irradiating excitation light. In this fluorescence observation, fluorescence from body tissue can be observed by irradiating excitation light to the body tissue (autofluorescence observation), or a fluorescence image can be obtained by locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the body tissue with excitation light corresponding to the fluorescence wavelength of the reagent. The light source device 11203 may be configured to supply such narrow-band light and / or excitation light suitable for the above-mentioned special light observation.

[0222] Fig.34 It shows Fig.33 A block diagram showing an example of the functional configuration of a camera head 11102 and a CCU (camera control unit) 11201 shown.

[0223] The camera head 11102 includes a lens unit 11401, an imaging unit 11402, a driving unit 11403, a communication unit 11404, and a camera head control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera head 11102 and the CCU 11201 are connected to each other via a transmission cable 11400 so as to be communicable with each other.

[0224] The lens section 11401 is an optical system provided at a connection portion with the lens barrel 11101. Observation light taken in from the distal end of the lens barrel 11101 is guided to the camera head 11102 and enters the lens section 11401. The lens section 11401 includes a combination of a plurality of lenses including a zoom lens and a focus lens.

[0225] The number of imaging elements included in the imaging unit 11402 may be one (so-called single-board type) or multiple (so-called multi-board type). In the case where the imaging unit 11402 is configured as a multi-board type, for example, image signals corresponding to each of RGB are generated by each imaging element, and these image signals can be synthesized to obtain a color image. The imaging unit 11402 may also be configured to have a pair of imaging elements, which are used to respectively obtain an image signal for the right eye and an image signal for the left eye for three-dimensional (3D) display. By performing a 3D display, the operator 11131 can more accurately grasp the depth of the biological tissue in the surgical site. It should be noted that in the case where the imaging unit 11402 is configured as a multi-board type, a plurality of systems of lens units 11401 are provided corresponding to the respective imaging elements.

[0226] In addition, the imaging unit 11402 does not necessarily have to be provided in the camera head 11102. For example, the imaging unit 11402 may be provided inside the lens barrel 11101 and immediately behind the objective lens.

[0227] The driving section 11403 includes an actuator, and moves the zoom lens and the focus lens of the lens section 11401 by a predetermined distance along the optical axis under the control of the camera head control section 11405. Thus, the magnification and focus of the image captured by the imaging section 11402 can be appropriately adjusted.

[0228] The communication unit 11404 includes a communication device for transmitting and receiving various information to and from the CCU 11201. The communication unit 11404 transmits the image signal acquired from the imaging unit 11402 to the CCU 11201 via the transmission cable 11400 as RAW data.

[0229] In addition, the communication unit 11404 receives a control signal for controlling the driving of the camera head 11102 from the CCU 11201, and supplies the control signal to the camera head control unit 11405. For example, the control signal includes the following information related to imaging conditions: information for specifying a frame rate of a captured image; information for specifying an exposure value during imaging; and / or information for specifying a magnification and focus of a captured image, etc.

[0230] It should be noted that the above-mentioned imaging conditions such as frame rate, exposure value, magnification or focus may be appropriately specified by the user, or may be automatically set based on the acquired image signal by the control unit 11413 of the CCU 11201. In the latter case, an automatic exposure (AE: auto exposure) function, an automatic focus (AF: autofocus) function, and an automatic white balance (AWB: auto white balance) function need to be incorporated in the endoscope 11100.

[0231] The camera head control section 11405 controls the driving of the camera head 11102 based on a control signal received from the CCU 11201 via the communication section 11404 .

[0232] The communication unit 11411 includes a communication device for transmitting and receiving various information to and from the camera head 11102. The communication unit 11411 receives an image signal transmitted from the camera head 11102 via the transmission cable 11400.

[0233] Furthermore, the communication unit 11411 transmits a control signal for controlling the driving of the camera head 11102 to the camera head 11102. The image signal and the control signal can be transmitted by means of electrical communication, optical communication, or the like.

[0234] The image processing unit 11412 performs various image processing on the image signal in the RAW data format transmitted from the camera head 11102 .

[0235] The control unit 11413 performs various controls related to imaging of a surgical site, etc., using the endoscope 11100 and display of a captured image obtained by imaging the surgical site, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102 .

[0236] In addition, based on the image signal after image processing has been performed by the image processing unit 11412, the control unit 11413 controls the display device 11202 to display the captured image reflecting the imaging of the surgical site, etc. Thus, the control unit 11413 can use various image recognition technologies to recognize various objects in the captured image. For example, the control unit 11413 can recognize surgical instruments such as forceps, specific biological sites, bleeding, and mist when the energy treatment device 11112 is used, etc. by detecting the edge shape or color of the object contained in the captured image. When the control unit 11413 controls the display device 11202 to display the captured image, the control unit 11413 can use the above-mentioned recognition results to display various surgical auxiliary information superimposed on the image of the surgical site. When the surgical auxiliary information is displayed superimposed and presented to the surgeon 11131, the burden of the surgeon 11131 can be reduced, and the surgeon 11131 can reliably perform the operation.

[0237] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 to each other is an electrical signal cable for communication of electrical signals, an optical fiber for optical communication, or a composite cable for electrical communication and optical communication.

[0238] Here, in the illustrated example, although wired communication is performed by using the transmission cable 11400, communication between the camera head 11102 and the CCU 11201 may be performed by wireless communication.

[0239] An example of an endoscopic surgery system to which the technology according to the present invention is applicable has been described above. The technology according to the present invention is applicable to the imaging unit 11402 in the above-described configuration. By applying the technology according to the present invention to the imaging unit 11402, detection accuracy is improved.

[0240] It should be noted that although an endoscopic surgical system is described here as an example, the technology according to the present invention can be applied to any other system such as a microsurgery system, for example.

[0241] [Application examples for mobile objects]

[0242] The technology according to the present invention can be applied to various products. For example, the technology according to the present invention can also be implemented as a device installed on any type of mobile body including but not limited to automobiles, electric vehicles, hybrid vehicles, motorcycles, bicycles, personal mobility vehicles, airplanes, unmanned aerial vehicles, ships, robots, construction machinery, agricultural machinery (such as tractors), etc.

[0243] Fig.35 It is a block diagram showing an example of a schematic configuration of a vehicle control system as an example of a mobile body control system to which the technology according to the present invention is applicable.

[0244] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig.35 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. In addition, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F: interface) 12053 are shown.

[0245] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 functions as a control device for the following devices: a drive force generating device such as an internal combustion engine, a drive motor, etc. for generating the drive force of the vehicle; a drive force transmitting mechanism for transmitting the drive force to the wheels; a steering mechanism for adjusting the steering angle of the vehicle; and a braking device for generating the braking force of the vehicle.

[0246] The body system control unit 12020 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for devices such as: a keyless entry system; a smart key system; a power window device; or various lights such as headlights, taillights, brake lights, turn signals, fog lights, etc. In this case, radio waves transmitted from a portable device used in place of a key or signals from various switches may be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls the door lock device, power window device, lights, etc. of the vehicle.

[0247] The vehicle exterior information detection unit 12030 detects information on the exterior of the vehicle equipped with the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the camera unit 12031. The vehicle exterior information detection unit 12030 causes the camera unit 12031 to capture an image of the exterior of the vehicle and receive the captured image. Based on the received image, the vehicle exterior information detection unit 12030 can perform processing for detecting objects such as people, vehicles, obstacles, signs, text on the road, etc., or processing for detecting the distance to the object.

[0248] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image, or can output the electrical signal as distance measurement information. In addition, the light received by the imaging unit 12031 can be visible light, or can be non-visible light such as infrared rays.

[0249] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 for detecting the state of the driver. For example, the driver state detection unit 12041 includes a camera for photographing the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue or the driver's concentration, or can determine whether the driver is dozing off.

[0250] Based on the information inside and outside the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, the microcomputer 12051 can calculate the control target value of the driving force generation device, the steering mechanism or the braking device, and can output a control instruction to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control aimed at realizing the functions of ADAS (Advanced Driver Assistance System), the functions of which include: collision avoidance or impact mitigation of the vehicle, following driving based on the distance between vehicles, vehicle constant speed driving, vehicle collision warning, vehicle lane departure warning, etc.

[0251] In addition, based on the information about the vehicle surroundings obtained by the external information detection unit 12030 or the internal information detection unit 12040, the microcomputer 12051 can perform coordinated control such as automatic driving, which enables the vehicle to drive autonomously without relying on the driver's operation, by controlling the driving force generating device, steering mechanism, braking device, etc.

[0252] In addition, based on the information outside the vehicle obtained by the vehicle exterior information detection unit 12030, the microcomputer 12051 can output a control instruction to the body system control unit 12020. For example, the microcomputer 12051 can perform coordinated control aimed at achieving anti-glare, such as by controlling the headlights to switch from high beam to low beam, etc., based on the position of the preceding vehicle or oncoming vehicle detected by the vehicle exterior information detection unit 12030.

[0253] The sound / image output unit 12052 sends an output signal of at least one of sound and image to an output device capable of visually or auditorily notifying the vehicle occupants or the outside of the vehicle of information. Fig.35 In the example of FIG. 1 , as output devices, an audio speaker 12061, a display portion 12062, and an instrument panel 12063 are shown. For example, the display portion 12062 may include at least one of an onboard display and a head-up display.

[0254] Fig.36 This is a diagram showing an example of the installation position of the camera unit 12031.

[0255] exist Fig.36 In the figure, the camera unit 12031 includes camera units 12101, 12102, 12103, 12104 and 12105.

[0256] Camera units 12101, 12102, 12103, 12104 and 12105 are arranged at positions such as the front of the vehicle 12100, the side mirrors, the rear bumper, the trunk door, and the upper part of the windshield in the vehicle compartment. The camera unit 12101 arranged at the front of the vehicle and the camera unit 12105 arranged at the upper part of the windshield in the vehicle compartment mainly obtain images in front of the vehicle 12100. The camera units 12102 and 12103 arranged at the side mirrors mainly obtain images on the sides of the vehicle 12100. The camera unit 12104 arranged at the rear bumper or the trunk door mainly obtains images behind the vehicle 12100. The camera unit 12105 arranged at the upper part of the windshield in the vehicle compartment is mainly used to detect vehicles in front, pedestrians, obstacles, traffic signals, traffic signs, lanes, etc.

[0257] By the way, Fig.36 An example of the imaging range of the imaging units 12101 to 12104 is shown. The imaging range 12111 indicates the imaging range of the imaging unit 12101 disposed at the front of the vehicle. The imaging ranges 12112 and 12113 respectively indicate the imaging ranges of the imaging units 12102 and 12103 disposed at the side mirrors. The imaging range 12114 indicates the imaging range of the imaging unit 12104 disposed at the rear bumper or the trunk door. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image of the vehicle 12100 as seen from above can be obtained.

[0258] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0259] For example, based on the distance information obtained from the camera units 12101 to 12104, the microcomputer 12051 can calculate the distance to each solid object within the camera range 12111 to 12114 and the change in the distance over time (relative speed to the vehicle 12100), thereby extracting the closest solid object on the driving route of the vehicle 12100, and the solid object traveling at a predetermined speed (for example, 0 km / h or more) in the same direction as the vehicle 12100 as the leading vehicle. In addition, the microcomputer 12051 can set the vehicle distance that should be ensured in advance in front of the leading vehicle, and can perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. Therefore, it is possible to perform coordinated control such as automatic driving that enables the vehicle to travel autonomously without relying on the driver's operation.

[0260] For example, based on the distance information obtained from the camera units 12101 to 12104, the microcomputer 12051 can classify the three-dimensional object data of the three-dimensional object into the three-dimensional object data of two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, electric poles and other three-dimensional objects, extract the classified three-dimensional object data, and use the extracted three-dimensional object data to automatically avoid obstacles. For example, the microcomputer 12051 identifies the obstacles around the vehicle 12100 as obstacles that the driver of the vehicle 12100 can visually perceive and obstacles that are difficult to visually perceive. Then, the microcomputer 12051 determines the collision risk used to represent the degree of danger of collision with each obstacle. When the collision risk is equal to or higher than the set value and there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display unit 12062, or performs forced deceleration or evasive steering via the drive system control unit 12010. Thereby, the microcomputer 12051 can provide driving assistance for avoiding collisions.

[0261] At least one of the camera units 12101 to 12104 is an infrared camera capable of detecting infrared rays. For example, the microcomputer 12051 can identify pedestrians by determining whether there are pedestrians in the images captured by the camera units 12101 to 12104. For example, such identification of pedestrians is performed by the following process: a process of extracting feature points in the images captured by the camera units 12101 to 12104 as infrared cameras; and a process of performing pattern matching processing on a series of feature points representing the contour of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that there are pedestrians in the images captured by the camera units 12101 to 12104 and thus identifies the pedestrians, the sound / image output unit 12052 controls the display unit 12062 to display a square contour line for emphasis superimposed on the identified pedestrian. The sound / image output unit 12052 can also control the display unit 12062 to display an icon representing a pedestrian at a desired position.

[0262] Although the present invention has been described with reference to the above-described embodiment, Modification 1 and Modification 2 thereof, applicable examples, and application examples, the present invention is not limited to the above-described embodiment and the like, and may be modified in various ways.

[0263] For example, the above embodiment mentions an example in which the photoelectric conversion unit (photodiode PD) and the pixel circuit (pixel circuit 210) are provided on respective substrates (first substrate 100 and second substrate 200) different from each other; however, this is not restrictive. For example, the pixel circuit 210 may be formed on the surface of the semiconductor layer 100S included in the first substrate 100 together with the transfer transistor TR, and the photodiode PD is formed on the surface. In this case, a similar effect can also be achieved by applying the present technology.

[0264] In addition, the present technology can also be applied to various semiconductor devices and electronic devices other than camera devices. Specifically, it is also applicable to electronic devices having semiconductor elements, including but not limited to light detection elements, light receiving elements, photoelectric conversion elements, ionizing radiation energy conversion elements, semiconductor detectors, integrated circuits and memories. It should be noted that in the case of applying the present technology to a camera device, as in the camera device 1 of the above-mentioned embodiment, in a structure in which the photodiode PD and the pixel circuit 210 are respectively arranged on different substrates (first substrate 100 and second substrate 200), the structure is rarely affected by the p-well layer 112 contained in the photodiode PD, and therefore a greater effect can be achieved.

[0265] It should be noted that the effects described herein are merely examples. The effects of the present invention are not limited to the effects described herein. The present invention may also have effects other than the effects described herein.

[0266] It should be noted that the present invention can also adopt any of the following structures. According to any of the following structures, in the first semiconductor layer in which the first electrode portion and the second electrode portion for forming the gate electrode of the first active element are buried, an undoped first semiconductor region is formed between the first electrode portion and the second electrode portion. As a result, the entire first semiconductor layer between the first electrode portion and the second electrode portion can be used as a channel region. Therefore, the device characteristics can be improved.

[0267] (1) A camera device comprising:

[0268] a photoelectric conversion unit that generates electric charge corresponding to the amount of light received;

[0269] a first active element that performs a predetermined operation on the charge generated by the photoelectric conversion portion, the first active element including a gate electrode including a first electrode portion, a second electrode portion, and a third electrode portion, the first electrode portion and the second electrode portion being arranged side by side in a first direction, the third electrode portion connecting the first electrode portion and the second electrode portion to each other; and

[0270] A first semiconductor layer includes a first surface and a second surface opposite to each other, the first electrode portion and the second electrode portion of the gate electrode are buried on the first surface side of the first semiconductor layer, and the first semiconductor layer includes a first semiconductor region located between the first electrode portion and the second electrode portion, and the first semiconductor region is undoped.

[0271] (2) The imaging device according to (1) above, wherein:

[0272] The photoelectric conversion unit is formed so as to be buried in the first semiconductor layer.

[0273] (3) The imaging device according to (1) or (2) above, further comprising:

[0274] a second semiconductor layer stacked on the second surface side of the first semiconductor layer with a wiring layer sandwiched between the first semiconductor layer and the second semiconductor layer,

[0275] The photoelectric conversion unit is formed in a manner buried in the second semiconductor layer.

[0276] (4) The imaging device according to any one of (1) to (3) above, further comprising:

[0277] a separation portion located outside the first semiconductor region, the separation portion being buried in the first surface of the first semiconductor layer and having an insulating property,

[0278] The first semiconductor layer includes a second semiconductor region, the second semiconductor region is in contact with the separation portion, extends to the second surface, and is doped with impurities of the first conductivity type.

[0279] (5) The imaging device according to (4) above, wherein:

[0280] The second semiconductor region extends over the entire surface of the first semiconductor layer on the second surface side.

[0281] (6) The imaging device according to any one of (1) to (5) above, further comprising:

[0282] A second active element is arranged side by side with the first active element in the first direction, the second active element performs a predetermined operation on the charge generated by the photoelectric conversion unit, and the second active element includes a gate electrode including a first electrode unit, a second electrode unit and a third electrode unit, the first electrode unit of the second active element and the second electrode unit of the second active element are arranged side by side in the first direction, and the third electrode unit of the second active element connects the first electrode unit of the second active element and the second electrode unit of the second active element to each other.

[0283] (7) The imaging device according to (6) above, wherein:

[0284] The first semiconductor layer includes a convex portion located between a first upright portion and a second upright portion, the first upright portion includes the first semiconductor region disposed between the first electrode portion of the first active element and the second electrode portion of the first active element, the second upright portion includes the first semiconductor region disposed between the first electrode portion of the second active element and the second electrode portion of the second active element,

[0285] The convex portion is covered by a separation portion, the separation portion electrically separating the first active element and the second active element from each other, and

[0286] The first standing portion, the second standing portion, and the convex portion have substantially the same width as each other in the first direction, and are arranged at equal intervals.

[0287] (8) The imaging device according to any one of (1) to (7), wherein:

[0288] The first active element comprises:

[0289] a surface channel formed near the first surface of the first semiconductor layer between the first electrode portion and the second electrode portion;

[0290] a sidewall channel extending from the surface channel along each of a first side surface of the first electrode portion and a first side surface of the second electrode portion, the first side surface of the first electrode portion and the first side surface of the second electrode portion being opposite to each other; and

[0291] A bottom channel and a transmission channel, wherein the bottom channel is formed on the bottom surface of the first electrode portion and the bottom surface of the second electrode portion, respectively, and the bottom channel is continuous with the sidewall channel, the transmission channel extends from the vicinity of the surface channel along the second side surface of the first electrode portion and the second side surface of the second electrode portion, respectively, and the transmission channel is continuous with the bottom channel, the second side surface of the first electrode portion is adjacent to the first side surface of the first electrode portion, and the second side surface of the second electrode portion is adjacent to the first side surface of the second electrode portion.

[0292] (9) The imaging device according to (8) above, wherein:

[0293] The width of the sidewall trench narrows from the first surface side toward the second surface side.

[0294] (10) The imaging device according to (8) or (9) above, wherein:

[0295] At least two of the transfer channels are formed for each of the bottom surface channel formed at the bottom surface of the first electrode portion and the bottom surface channel formed at the bottom surface of the second electrode portion.

[0296] (11) The imaging device according to any one of (1) to (10) above, wherein:

[0297] Each of the first electrode portion and the second electrode portion extends in a second direction substantially perpendicular to the first direction in a plan view,

[0298] The first semiconductor layer includes the first semiconductor region in a plan view and has an active region of the first active element in a plan view, the active region has a substantially rectangular shape in a plan view, the substantially rectangular shape includes a pair of first sides opposite in the second direction and a pair of second sides opposite in the first direction, and

[0299] The active region has a cutout portion in at least one of the pair of second sides, and the cutout portion is formed by burying the first electrode portion and / or the second electrode portion.

[0300] (12) The imaging device according to any one of (1) to (11) above, wherein:

[0301] The first active element includes a fourth electrode portion, the fourth electrode portion is disposed between the first electrode portion and the second electrode portion and connected to the third electrode portion, and

[0302] The fourth electrode portion is buried in the first semiconductor region.

[0303] (13) The imaging device according to (12) above, wherein:

[0304] The first electrode portion, the second electrode portion, and the fourth electrode portion have the same width as each other in the first direction.

[0305] (14) The imaging device according to (12) or (13), wherein:

[0306] A width of each of the first electrode portion and the second electrode portion in the first direction is smaller than a width of the fourth electrode portion in the first direction.

[0307] (15) The imaging device according to any one of (1) to (14) above, wherein:

[0308] Each of the first electrode portion and the second electrode portion extends in a second direction substantially perpendicular to the first direction in a plan view,

[0309] The third electrode portion includes a protruding portion formed on the first surface of the first semiconductor layer and protruding outward from both ends of each of the first electrode portion and the second electrode portion in an extending direction, and

[0310] The first extension portion extends from one of the two end portions of each of the first electrode portion and the second electrode portion, and the second extension portion extends from the other of the two end portions of each of the first electrode portion and the second electrode portion, and an extension width of the first extension portion from the one end portion and an extension width of the second extension portion from the other end portion are different from each other.

[0311] (16) The imaging device according to (15) above, wherein:

[0312] The first semiconductor region extends along the second direction between the first electrode portion and the second electrode portion in the plan view, and

[0313] The first semiconductor layer includes third semiconductor regions located at both ends of the first semiconductor region in the extending direction, the third semiconductor regions are each doped with impurities of the second conductivity type.

[0314] (17) The imaging device according to (16) above, wherein:

[0315] Among the third semiconductor regions formed at the two end portions in the extending direction of the first semiconductor region, the third semiconductor region located on the side of one of the two end portions is a source region of the first active element, and the third semiconductor region located on the side of the other of the two end portions is a drain region of the first active element,

[0316] The first extension portion extends outward from the source region side,

[0317] The second extension extends outwardly from the drain region, and

[0318] The extending width of the second extending portion is greater than the extending width of the first extending portion.

[0319] (18) The imaging device according to any one of (1) to (17) above, wherein:

[0320] The first active element includes at least one transistor for constituting a pixel circuit that generates a pixel signal based on the charge generated by the photoelectric conversion portion.

[0321] (19) A camera device comprising:

[0322] a photoelectric conversion unit that generates electric charge corresponding to the amount of light received;

[0323] A first semiconductor layer including a first surface and a second surface opposite to each other; and

[0324] a first active element that performs a predetermined operation on the charge generated by the photoelectric conversion section, the first active element comprising a gate electrode including a first electrode section, a second electrode section, and a third electrode section, the first electrode section and the second electrode section being arranged side by side in a first direction, the third electrode section connecting the first electrode section and the second electrode section to each other,

[0325] wherein each of the first electrode portion and the second electrode portion is buried in the first surface side of the first semiconductor layer, and each of the first electrode portion and the second electrode portion extends in a second direction substantially perpendicular to the first direction in a plan view,

[0326] The third electrode portion includes a protruding portion formed on the first surface of the first semiconductor layer and protruding outward from both ends of each of the first electrode portion and the second electrode portion in an extending direction, and

[0327] The first extension portion extends from one of the two end portions of each of the first electrode portion and the second electrode portion, and the second extension portion extends from the other of the two end portions of each of the first electrode portion and the second electrode portion, and an extension width of the first extension portion from the one end portion and an extension width of the second extension portion from the other end portion are different from each other.

[0328] This application claims the benefit of priority based on U.S. patent application No. 63 / 338,556 filed in the U.S. Patent and Trademark Office on July 12, 2022, the entire contents of which are incorporated herein by reference.

[0329] It should be understood that those skilled in the art may make various modifications, combinations, sub-combinations and changes according to design requirements and other factors, which fall within the protection scope of the appended claims or the equivalents thereof.

Claims

1. A camera device, comprising: a photoelectric conversion unit that generates electric charge corresponding to the amount of light received; a first active element that performs a predetermined operation on the charge generated by the photoelectric conversion section, the first active element comprising a gate electrode including a first electrode section, a second electrode section, and a third electrode section, the first electrode section and the second electrode section being arranged side by side in a first direction, the third electrode section connecting the first electrode section and the second electrode section to each other; as well as A first semiconductor layer includes a first surface and a second surface opposite to each other, the first electrode portion and the second electrode portion of the gate electrode are buried on the first surface side of the first semiconductor layer, and the first semiconductor layer includes a first semiconductor region located between the first electrode portion and the second electrode portion, and the first semiconductor region is undoped.

2. The imaging device according to claim 1, wherein: The photoelectric conversion unit is formed so as to be buried in the first semiconductor layer.

3. The camera device according to claim 1, further comprising: a second semiconductor layer stacked on the second surface side of the first semiconductor layer with a wiring layer sandwiched between the first semiconductor layer and the second semiconductor layer, The photoelectric conversion unit is formed in a manner buried in the second semiconductor layer.

4. The camera device according to claim 1, further comprising: a separation portion located outside the first semiconductor region, the separation portion being buried in the first surface of the first semiconductor layer and having an insulating property, The first semiconductor layer includes a second semiconductor region, the second semiconductor region is in contact with the separation portion, extends to the second surface, and is doped with impurities of the first conductivity type.

5. The imaging device according to claim 4, wherein: The second semiconductor region extends over the entire surface of the first semiconductor layer on the second surface side.

6. The camera device according to claim 1, further comprising: A second active element is arranged side by side with the first active element in the first direction, the second active element performs a predetermined operation on the charge generated by the photoelectric conversion unit, and the second active element includes a gate electrode including a first electrode unit, a second electrode unit and a third electrode unit, the first electrode unit of the second active element and the second electrode unit of the second active element are arranged side by side in the first direction, and the third electrode unit of the second active element connects the first electrode unit of the second active element and the second electrode unit of the second active element to each other.

7. The imaging device according to claim 6, wherein: The first semiconductor layer includes a convex portion located between a first upright portion and a second upright portion, the first upright portion includes the first semiconductor region disposed between the first electrode portion of the first active element and the second electrode portion of the first active element, the second upright portion includes the first semiconductor region disposed between the first electrode portion of the second active element and the second electrode portion of the second active element, The convex portion is covered by a separation portion, the separation portion electrically separating the first active element and the second active element from each other, and The first standing portion, the second standing portion, and the convex portion have substantially the same width as each other in the first direction, and are arranged at equal intervals.

8. The imaging device according to claim 1, wherein: The first active element comprises: a surface channel formed near the first surface of the first semiconductor layer between the first electrode portion and the second electrode portion; a sidewall channel extending from the surface channel along each of a first side surface of the first electrode portion and a first side surface of the second electrode portion, the first side surface of the first electrode portion and the first side surface of the second electrode portion being opposite to each other; and A bottom channel and a transmission channel, wherein the bottom channel is formed on the bottom surface of the first electrode portion and the bottom surface of the second electrode portion, respectively, and the bottom channel is continuous with the sidewall channel, the transmission channel extends from the vicinity of the surface channel along the second side surface of the first electrode portion and the second side surface of the second electrode portion, respectively, and the transmission channel is continuous with the bottom channel, the second side surface of the first electrode portion is adjacent to the first side surface of the first electrode portion, and the second side surface of the second electrode portion is adjacent to the first side surface of the second electrode portion.

9. The imaging device according to claim 8, wherein: The width of the sidewall trench narrows from the first surface side toward the second surface side.

10. The imaging device according to claim 8, wherein: At least two of the transfer channels are formed for each of the bottom surface channel formed at the bottom surface of the first electrode portion and the bottom surface channel formed at the bottom surface of the second electrode portion.

11. The imaging device according to claim 1, wherein: Each of the first electrode portion and the second electrode portion extends in a second direction substantially perpendicular to the first direction in a plan view, The first semiconductor layer includes the first semiconductor region in a plan view and has an active region of the first active element in a plan view, the active region has a substantially rectangular shape in a plan view, the substantially rectangular shape includes a pair of first sides opposite in the second direction and a pair of second sides opposite in the first direction, and The active region has a cutout portion in at least one of the pair of second sides, and the cutout portion is formed by burying the first electrode portion and / or the second electrode portion.

12. The imaging device according to claim 1, wherein: The first active element includes a fourth electrode portion, the fourth electrode portion is disposed between the first electrode portion and the second electrode portion and connected to the third electrode portion, and The fourth electrode portion is buried in the first semiconductor region.

13. The imaging device according to claim 12, wherein: The first electrode portion, the second electrode portion, and the fourth electrode portion have the same width as each other in the first direction.

14. The imaging device according to claim 12, wherein: A width of each of the first electrode portion and the second electrode portion in the first direction is smaller than a width of the fourth electrode portion in the first direction.

15. The imaging device according to claim 1, wherein: Each of the first electrode portion and the second electrode portion extends in a second direction substantially perpendicular to the first direction in a plan view, The third electrode portion includes a protruding portion formed on the first surface of the first semiconductor layer and protruding outward from both ends of each of the first electrode portion and the second electrode portion in an extending direction, and The first extension portion extends from one of the two end portions of each of the first electrode portion and the second electrode portion, and the second extension portion extends from the other of the two end portions of each of the first electrode portion and the second electrode portion, and an extension width of the first extension portion from the one end portion and an extension width of the second extension portion from the other end portion are different from each other.

16. The imaging device according to claim 15, wherein: The first semiconductor region extends along the second direction between the first electrode portion and the second electrode portion in the plan view, and The first semiconductor layer includes third semiconductor regions located at both ends of the first semiconductor region in the extending direction, the third semiconductor regions are each doped with impurities of the second conductivity type.

17. The imaging device according to claim 16, wherein: Among the third semiconductor regions formed at the two end portions in the extending direction of the first semiconductor region, the third semiconductor region located on the side of one of the two end portions is a source region of the first active element, and the third semiconductor region located on the side of the other of the two end portions is a drain region of the first active element, The first extension portion extends outward from the source region side, The second extension extends outwardly from the drain region, and The extending width of the second extending portion is greater than the extending width of the first extending portion.

18. The imaging device according to claim 1, wherein: The first active element includes at least one transistor for constituting a pixel circuit that generates a pixel signal based on the charge generated by the photoelectric conversion portion.

Images