Test time optimization with small number of slow scan pads
By using multiplexer and accumulator technology in integrated circuits, the scanning output frequency is optimized, and the problem of IC test time is solved, and faster scanning shift time is achieved, especially in the presence of slow scanning output pads. In case.
Patent Information
- Application Number
- CN202410945683.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-07-17
- Filing Date
- 2024-07-15
- Publication Date
- 2025-01-17
AI Technical Summary
As the complexity of integrated circuit (IC) design increases, scan test time increases, resulting in increased testing costs and time, especially the slower scan output pads limit the scan shift frequency, increasing testing time and cost.
By introducing multiplexers and accumulators into the scan chain, data shifting is performed using higher frequency scan output pins and temporarily storing data when necessary to move out of lower frequency pins in the next cycle, generating Different scan output data modes, but the pre-known mode will not affect the test results.
Effectively reduces scan test time, especially in the presence of slow scan output pads, saving 25% to 50% of the total test time.
Smart Images
Figure CN119322248A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to optimization of scan shift time in a design for test (DFT) IC, and in particular, to management of slow scan output pads to reduce scan shift time. Background Art
[0002] Scan testing is a hardware-level technique used to evaluate integrated circuits (ICs). Figure 1 As shown, an IC 10 designed to perform scan testing includes n scan chains 13 (1), ..., 13 (n). These chains are sequences of flip-flops with reconfigurable connections that play standard roles within the IC 10, such as maintaining state information. However, when the IC 10 enters a test mode, these flip-flops are logically realigned to form scan chains 13 (1), ..., 13 (n). This allows the state of the flip-flops to be directly manipulated and monitored. By shifting data into and out of the scan chains 13 (1), ..., 13 (n), a process called "scan-shifting", a snapshot of the internal state of the IC 10 can be captured and examined, which is particularly useful in identifying manufacturing defects or design errors.
[0003] As IC designs become increasingly complex, the need for rigorous testing and implementation of new fault models has intensified, especially in industries requiring high reliability, such as the automotive industry. This has led to a significant increase in scan volume (the total data required for scan testing) and, therefore, the need for greater scan compression. Scan compression pertains to on-chip scan decompressor logic 12, which expands the compressed scan pattern (received at the m scan input pads) as it is fed into the scan chains 13(1), ..., 13(n), and scan compression pertains to on-chip compressor logic 14, which compresses data as it is scanned out of the scan chains 13(1), ..., 13(n) (to the m scan output pads).
[0004] As the scan volume grows, the test time for each IC 10 also grows, thereby increasing the cost of testing and the time it takes to perform such testing.
[0005] The test program is shaped by the scan compression process and the number of available I / O pads used as scan input pads and scan output pads. Having more I / O pads can lead to better compression, shorter scan chain length and fewer scan patterns. However, the frequency of data scan shifts of interest to effective testing is usually limited by the use of certain slower scan output pads due to external loads. If some scan output pads have a lower maximum drive capability, they proportionally reduce the entire scan shift frequency. For example, if nine scan output pads can support a maximum scan shift of 100MHz, and one scan output pad can only support a maximum scan shift of 50MHz, the entire scan shift operation is limited to 50MHz. This further increases test time and cost in an undesirable manner. Therefore, further development is needed to address this limitation and increase the scan shift frequency. Summary of the invention
[0006] The design described herein provides efficient processing of slow scan output pads, thereby reducing the time to perform scan tests. It is assumed that some scan data will be shifted by the corresponding scan chain and shifted out by the relevant scan output pins working at a higher frequency, while some data will be shifted by the corresponding scan chain and shifted out by the relevant scan output pins working at a lower frequency. The technology described herein relates to unloading all scan chains at a higher frequency. For those scan chains associated with the scan output pins operating at a lower frequency, the scan data is shifted out by those pins every other cycle instead of every cycle like the scan data from the scan chain associated with the scan output pins operating at a higher frequency. The data that cannot be shifted out by the scan output pins working at a lower frequency is temporarily stored in an accumulator. During the shift period, the accumulated data is shifted out by the scan output pins working at a higher frequency using additional cycles. Although this results in the generation of different scan output data patterns (data pattern), the tester knows in advance what the scan output data pattern expected to be generated will be, so the test will not be negatively affected. BRIEF DESCRIPTION OF THE DRAWINGS
[0007] Figure 1 is a block diagram of a prior art IC including a known scan test circuit.
[0008] Figure 2 is a block diagram of an IC disclosed herein that includes improved scan test circuitry that facilitates scan out at a faster time than otherwise supported by the frequency of the slowest scan out pad.
[0009] Figure 3 It is shown Figure 2 A timing diagram showing the relationship between different clock signals in the scan test circuit of an IC.
[0010] Figure 4 is shown during the initial part of the scan shift process by Figure 2 A table of the data shifted out of the fast and slow scan output pads of the IC and showing the data held in the accumulator during this initial portion of the scan shift process.
[0011] Figure 5 is shown during the last part of the scan shift process by Figure 2 The slow scan output pad of the OC shifts out the data table.
[0012] Figure 6 is a table showing the test time savings of the IC disclosed herein relative to the prior art IC when performing a scan shift process.
[0013] Figure 7 is a block diagram of another IC disclosed herein that includes an improved scan test circuit that scans out pads at a faster time than supported by the frequency of the slowest scan out pad.
[0014] Figure 8 is shown during the last part of the scan shift process by Figure 7 The slow scan output pad of the OC shifts out the data table. DETAILED DESCRIPTION
[0015] The following disclosure enables those skilled in the art to make and use the subject matter described herein. Without departing from the spirit and scope of the present disclosure, the general principles outlined in the present disclosure may be applied to embodiments and applications beyond those described above. It is not intended to limit the present disclosure to the embodiments shown, but rather to conform to the broadest scope consistent with the principles and features disclosed or suggested herein.
[0016] Reference now Figure 2 An integrated circuit 10' is described that includes n scan chains 13(1), ..., 13(n). There are m scan input pads 11(1), ..., 11(m) configured to receive compressed input scan data and provide the compressed input scan data to a scan decompressor 12, which decompresses the compressed input scan data to pass through the scan chains 13(1), ..., 13(n). A scan compressor 14 compresses the scan data into output scan data as it is shifted out through the scan chains 13(1), ..., 13(n), which are clocked by a shift clock signal Shift_CLK.
[0017] There are m scan output pads 21(1), ..., 21(m), where m is less than n. In the integrated circuit 10', the scan output pad 21(m-1) and the scan output pad 21(m) can operate at a maximum frequency equal to a first frequency, while the scan output pad 21(1) and the scan output pad 21(2) can operate at a maximum frequency equal to a second frequency, which is lower than the first frequency. For example, the second frequency can be half of the first frequency.
[0018] The multiplexer 20(m-1) receives the m-1th part of the output scan data from the scan compressor 14 at its first input and receives the output from the accumulator 18 at its second input, and passes the data at its second input to the scan output pad 21(m-1) when the accumulator unload signal Acc_Unload_En is asserted, otherwise passes the data at its first input to the scan output pad 21(m-1). The multiplexer 20(m) receives the m-th part of the output scan data from the scan compressor 14 at its first input and receives the output from the accumulator 18 at its second input, and passes the data at its second input to the scan output pad 21(m) when the accumulator unload signal Acc_Unload_En is asserted, otherwise passes the data at its first input to the scan output pad 21(m).
[0019] The flip-flop 20(1) receives the first portion of the output scan data from the scan compressor 14 at its data input and passes this data to the scan output pad 21(1) when clocked. The flip-flop 20(1) is clocked by the output from the AND gate 19(1). The AND gate 19(1) receives the inverted signal of the accumulator unload signal Acc_Unload_En at its first input and the first clock signal CLK1 at its second input and clocks the flip-flop 20(1) based on performing a logical AND operation on these two logic values. The flip-flop 20(2) receives the second portion of the output scan data from the scan compressor 14 at its data input and passes this data to the scan output pad 21(2) when clocked. The flip-flop 20(2) is clocked by the output from the AND gate 19(2). AND gate 19 ( 2 ) receives the inverted signal of accumulator unload signal Acc_Unload_En at its first input and the first clock signal CLK1 at its second input, and clocks flip-flop 20 ( 2 ) based on performing a logical AND operation on these two logic values.
[0020] It should be understood that for each scan output pad 21(1), ..., 21(m), there is a corresponding logic device that drives the scan output pad. For the slow scan output pads, 21(1) and 21(2) in the example shown, the logic devices that drive these scan output pads are flip-flops 20(1) and 20(2). For the fast scan output pads, 21(m-1) and 21(m) in the example shown, the logic devices that drive these scan output pads are multiplexers 20(m-1) and 20(m). There can be any number of scan output pads, at least one of which is slow, so in any given application, the number of flip-flops like 20(1) and 20(2) corresponds to the number of slow scan output pads, and the number of multiplexers like 20(m-10) and 20(m) corresponds to the number of fast scan output pads.
[0021] The shift clock signal Shift_CLK is generated by an on-chip clock controller (OCC) 15 based on a fast clock signal Fast_CLK used during shifting and an automatic test equipment (ATE) clock signal ATE_CLK.
[0022] The clock gate (CG) 16 passes the shift clock signal Shift_CLK when enabled by the enable signal EN. The multiplexer 17 receives the output of the clock gate 16 at its first input and receives the ATE clock signal ATE_CLK at its second input. When the accumulator unload signal Acc_Unload_En is asserted, the multiplexer 17 passes its second input (the output from the clock gate 16) to its output as the clock signal CLK2, and otherwise passes its first input (ATE clock) to its output.
[0023] The accumulator 18 receives the first and second portions of the output scan data from the scan compressor 14 and is clocked by a second clock signal CLK2 generated as an output of the multiplexer 17 .
[0024] Figure 31 , the relationship between the shift clock Shift_CLK (ATE_CLK during scanning), the first clock signal CLK1 (used to clock the flip-flop associated with the scan output pad that can be operated at a maximum frequency equal to the second frequency), the second clock signal CLK2 (used to clock the flip-flop associated with the scan output pad that can be operated at a maximum frequency equal to the second frequency) when Acc_Unload_En is deasserted during the scan shift, and the second clock signal CLK2 when Acc_Unload_En is asserted to unload the accumulator 18. It is observed that the first clock signal CLK1 is equivalent to the shift clock signal Shift_CLK, but every other pulse is skipped. Similarly, it is observed that during the scan shift (Acc_Unload_En is deasserted), the second clock signal CLK2 is equivalent to the first clock signal CLK1, but a full-cycle phase shift has been applied, whereas during the unloading of the accumulator 18 (Acc_Unload_En is asserted), the second clock signal CLK2 is equivalent to the shift clock signal Shift_CLK.
[0025] Operation is now described. During scan output, each of the scan chains 13(1), ..., 13(n) operates at a first frequency (e.g., ATE_CLK acting as Shift_CLK operates at a higher frequency). Consider dividing the output scan data into m parts, m is 4 in this example, so that the output scan data includes a first part, a second part, an m-1th part, and an mth part.
[0026] During the initial portion of the scan shift, Acc_Unload_En is deasserted, and thus multiplexers 20(m-1) and 20(m) select their second inputs (e.g., those connected to the respective outputs of scan compressor 14) to pass to scan output pads 21(m-1) and 21(m). Thus, during this initial portion of the scan shift in which Acc_Unload_EN is deasserted, the m-1th portion of the output scan data is shifted out through scan output pad 21(m-1) at the first frequency, and the mth portion of the output scan data is shifted out through scan output pad 21(m) at the first frequency.
[0027] Acc_Unload_En being deasserted also has the effect of allowing the outputs of AND gates 19(1) and 19(2), which clock flip-flops 20(1) and 20(2), to follow clock signal CLK1. Thus, since the bits of the first portion of the output scan data are provided to the data input of flip-flop 20(1), but flip-flop 20(1) is clocked by CLK1 (which, as explained, is equivalent to Shift_CLK, but with every other pulse skipped), every other bit of the first portion of the output scan data is output via scan output pad 21(1) during the initial portion of the scan shift.
[0028] Another effect of deasserting Acc_Unload_En is to cause multiplexer 17 to select the output of clock gate 16 as the clock signal CLK2 for passing through accumulator 18. Remember that clock signal CLK2 is considered equivalent to clock signal CLK1 having performed a full cycle shift. Thus, during clock pulses of the shift clock when there are no clock pulses of clock signal CLK1, clock signal CLK2 is pulsed. As a result, accumulator 18 accumulates those bits of the first portion of the output scan data provided to the data input of flip-flop 20(1) during pulses of Shift_CLK where CLK1 was not pulsed. Similarly, since bits of the second portion of the output scan data are provided to the data input of the flip-flop 20(2), but the flip-flop 20(2) is clocked by CLK1, every other bit of the second portion of the output scan data is output via the scan output pad 21(2) during the initial portion of the scan shift, and the accumulator 18 accumulates those bits of the second portion of the output scan data that were provided to the data input of the flip-flop 20(2) during the Shift_CLK pulse when there is no pulse of CLK1.
[0029] Thus, at the end of the initial portion of the scan shift, every bit of the m-1th and mth portions of the output scan data has been shifted out, and every other bit of the first and second portions of the output scan data has been shifted out.
[0030] This is Figure 4. Consider that the first portion of the output scan data includes bits A1-A8, the second portion of the output scan data includes bits B1-B8, the m-1th portion of the output scan data includes bits C1-C8, and the mth portion of the output scan data includes bits D1-D8. Therefore, during the initial portion of the scan shift, bits C1-C8 are shifted out through scan output pad 21(m-1), bits D1-D8 are shifted out through scan output pad 21(m), while bits A1, A3, A5, A7 are shifted out through scan output pad 21(1), and bits B1, B3, B5, B7 are shifted out through scan output pad 21(2). Therefore, at the end of the initial portion of the scan shift, accumulator 18 stores bits A2, A4, A6, A8 and B2, B4, B6, B8.
[0031] The final portion of the scan shift (e.g., unloading of the accelerometer 18) now begins with Acc_Unload_En being asserted, blocking CLK1 from passing through AND gates 19(1) and 19(2) to stop the clocking of flip-flops 20(1) and 20(2), and switching multiplexers 20(m-1) and 20(m) to pass their first inputs (received as the output of accumulator 18) as outputs. The asserted Acc_Unload_En also causes multiplexer 17 to pass the ATE clock ATE_CLK as the second clock CLK2 to clock the accumulator. As a result, accumulator 18 outputs its stored bits at the first frequency to scan output pads 21(m-1) and 21(m) through multiplexers 20(m-1) and 20(m).
[0032] This is Figure 5 . Recall that accumulator 18 has stored bits A2, A4, A6, A8 and B2, B4, B6, B8 at the end of the initial portion of the scan shift. Therefore, during the final portion of the scan shift, bits A2, A4, A6, A8 are shifted out through scan output pad 21(m-1), while bits B2, B4, B6, B8 are shifted out through scan output pad 21(m).
[0033] Although this results in a different scan-out data pattern being generated, the automatic test equipment performing the scan test on the IC knows in advance what the expected generated scan-out data pattern will be, so the test is not negatively impacted.
[0034] The time for performing the last part of the scan shift (e.g., unloading of the accumulator) can be during the scan by adding extra cycles during the scan. The addition of extra shift cycles should not be counterproductive compared to using the prior art scan shift technique (e.g., the addition of extra shift cycles should not generate a total time to unload the scan chain that exceeds the time using the prior art scan shift technique).
[0035] Figure 6 An example of saving scan shift time by using IC 10' as opposed to a prior art design is shown in the diagram of In this example, the length of the scan chain is 100, the maximum operating frequency of the fast scan output pad is 100 mHz, and the maximum operating frequency of at least one slow scan output pad is 50 mHz.
[0036] Using the prior art design, as long as there is at least one slow scan output pad, the time to unload all scan chains 13(1), ..., 13(n) is set by the frequency of the slow scan output pad (i.e., operating at the second frequency). Figure 2 The design of , the time to unload all scan chains 13 (1), ..., 13 (n) is equal to the time to unload the scan chains connected to the fast scan output pad (performed at the maximum frequency of the fast scan output pad) plus the time to unload the accumulator (also via the fast scan output pad and at its maximum frequency), which is substantially less than the time to unload all scan chains at the frequency of the slow scan output pad. It is observed in this chart that when the number of slow scan output pads increases compared to the number of fast scan output pads, the accumulator unloading time increases, however, even in the case where half of the scan output pads are slow pads, the total time is still saved by 25%. In the case of a single slow scan output pad, the total time is saved by almost 50%.
[0037] Variations are within the scope of this disclosure. Figure 7 An embodiment of an integrated circuit 10" is shown in which the accumulator 18 is unloaded via scan output pads 21(1) and 21(2) and scan output pads 21(m-1) and 21(m). To facilitate such operation, flip-flops 20(1) and 20(2) are clocked by the first clock CLK1 even when Acc_Unload_En is asserted. Data input to flip-flop 20(1) is received from the output of multiplexer 22(1), multiplexer 22(1) having a first input receiving the output from accumulator 18, a second input receiving the output from scan compressor 14, and its selection is set by Acc_Unload_En. Similarly, data input to flip-flop 20(2) is received from the output of multiplexer 22(2), multiplexer 22(2) having a first input receiving the output from accumulator 18, a second input receiving the output from scan compressor 14, and its selection is set by Acc_Unload_En.
[0038] In operation, during the initial portion of the scan shift, flip-flops 20(1) and 20(2) will be clocked by the first clock signal CLK1 and will receive their data inputs from scan compressor 14, which is consistent with Figure 2However, during the last portion of the scan shift, flip-flops 20(1) and 20(2) will also be clocked by the first clock signal CLK1 and will receive their data inputs from accumulator 18. Accumulator 18 will therefore output its stored bits to scan output pads 21(m-1) and 21(m) at a rate set by CLK2 (here equal to Shift_CLK) through multiplexers 20(m-1) and 20(m), and to scan output pads 21(1) and 21(2) at a rate set by CLK1 through multiplexers 22(1) and 22(2).
[0039] This is Figure 8 . Recall that accumulator 18 has stored bits A2, A4, A6, A8 and B2, B4, B6, B8 at the end of the initial portion of the scan shift. Therefore, during the final portion of the scan shift, bits A2, A6 are shifted out through scan output pad 21(1), bits A4, A8 are shifted out through scan output pad 21(2), bits B2, B6 are shifted out through scan output pad 21(m-1), and bits B4, B8 are shifted out through scan output pad 21(m).
[0040] Although the present disclosure has been described with a limited number of embodiments, those skilled in the art having benefit of the present disclosure may conceive of other embodiments that do not depart from the scope of the disclosure. In addition, those skilled in the art may conceive of embodiments that represent various combinations of the embodiments disclosed herein made in various ways.
Claims
1. An integrated circuit, comprising: a scan compressor configured to compress the output scan data as it is shifted out of the scan chain; a plurality of scan output pads, wherein a first group of the plurality of scan output pads operates at a first frequency and a second group of the plurality of scan output pads operates at a second frequency lower than the first frequency; a first scan output circuit device configured to shift a first portion of the output scan data out through a first group of the scan output pads at the first frequency; second scan output circuitry configured to shift out every other bit of a second portion of the output scan data through a second group of scan output pads at the second frequency; as well as an accumulator configured to accumulate bits of the second portion of the output scan data that are not shifted out by the second group of scan output pads; The first scan output circuit device is further configured to shift out at least a portion of the accumulated bits through the first group of scan output pads at the first scan frequency after shifting out the first portion of the output data at the first scan frequency.
2. The integrated circuit according to claim 1 further comprises a clock generation circuit device, wherein the clock generation circuit device is configured to generate a shift clock signal for timing the scan chain and a second clock signal for timing the accumulator; and wherein the second scan output circuit device is clocked by the first clock signal.
3. An integrated circuit according to claim 2, wherein when the first scan output circuit device shifts out at least the portion of the accumulated data bits through the first group of the scan output pads, the clock generation circuit device generates the second clock signal equal to the shift clock signal, otherwise generates the second clock signal as a pulse skipped version of the shift clock signal, the pulse skipped version being equivalent to the shift clock signal but in which every other clock pulse or pulses are skipped, and is equivalent to the first clock signal phase-shifted by a full period.
4. An integrated circuit according to claim 2, wherein when the first scan output circuit device shifts out at least the portion of the accumulated data bits through the first group of the scan output pads, the clock generation circuit device generates the second clock signal equal to the shift clock signal, and otherwise generates the second clock signal as a pulse skipped version of the shift clock signal, the pulse skipped version being equivalent to the shift clock signal but in which every other clock pulse is skipped and is equivalent to the first clock signal phase shifted by a full period.
5. The integrated circuit of claim 3, wherein the first scan output circuit means comprises: a multiplexer having a first input coupled to receive the first portion of the output scan data from the scan compressor, a second input coupled to the accumulator to receive the accumulated bits from the accumulator, and outputs coupled to respective scan output pads of a first group of the plurality of scan output pads, wherein selection of which of the first and second inputs of the multiplexer is passed to the output is performed based on an accumulator unload signal asserted when the first scan output circuitry is to shift out at least the portion of the accumulated bits through the first group of scan output pads.
6. The integrated circuit of claim 5, wherein the second scan output circuit means comprises: a flip-flop having a data input coupled to receive the second portion of the output scan data from the scan compressor, and a data output coupled to a corresponding scan output pad in the second group of scan output pads, the flip-flop being clocked by an output from a logic gate.
7. The integrated circuit of claim 6, wherein the logic gate comprises an AND gate having a first input coupled to receive the first clock signal and a second input coupled to receive the accumulator unload signal.
8. The integrated circuit of claim 6, wherein the logic gate comprises an AND gate having a non-inverting input coupled to receive the first clock signal and an inverting input coupled to receive the accumulator unload signal.
9. The integrated circuit of claim 6, wherein the logic gate comprises a clock gating circuit having a first input coupled to receive the first clock signal and a second input coupled to receive the accumulator unload signal.
10. The integrated circuit of claim 1, wherein the first scan output circuit device is further configured to: shift out each of the accumulated bits through the first group of scan output pads at the first scan frequency after shifting out the first portion of the output data at the first scan frequency.
11. The integrated circuit of claim 1, wherein the second frequency is half of the first frequency.
12. A method for performing a scan test on an integrated circuit, comprising: During the first operating period: shifting the scan pattern through the scan chain and out through the scan compressor as output scan data; shifting out a first portion of the output scan data by scanning a first group of output pads at a first scan frequency; shifting out every other bit of a second portion of the output scan data by scanning a second group of output pads at a second scan frequency that is less than the first scan frequency; and accumulating bits of a second portion of the output scan data that are not shifted out by a second group of the scan output pads; as well as During a second operating period immediately following the first operating period: At least a portion of the accumulated bits are shifted out through a first group of scan output pads at the first scan frequency.
13. The method of claim 12, further comprising generating a shift clock signal for clocking the scan chain and a second clock signal for clocking an accumulator performing the accumulation; and wherein the shifting out of the first portion of the output data is performed using a first clock signal.
14. The method of claim 13 , wherein the second clock signal is generated to be equal to the shift clock signal when at least the portion of the accumulated data bits are shifted out through the first group of the scan output pads, and the second clock signal is otherwise generated as a pulse-skipped version of the shift clock signal, the pulse-skipped version being equivalent to the shift clock signal but with every other clock pulse skipped and being equivalent to the first clock signal phase-shifted by a full period.
15. The method of claim 12, wherein each of the accumulated bits is shifted out through a first group of the scan output pads at the first scan frequency. The method of claim 12 , wherein the second scanning frequency is half of the first scanning frequency.