Chip-level integrated circuit fault diagnosis method based on improved wavelet entropy

Abstract

The invention belongs to the technical field of integrated circuits, and particularly relates to a chip-level integrated circuit fault diagnosis method based on improved wavelet entropy, which comprises the following steps: S1, acquiring an original signal of a chip-level integrated circuit, and reconstructing the original signal by using a VMD signal reconstruction technology; s2, performing deep processing on the reconstructed signal by adopting an improved wavelet entropy method, and extracting key features of a fault signal; s3, monitoring the voltage change of each node through the key characteristics of the fault signal, and effectively positioning the fault position; and S4, setting a fault factor which can comprehensively consider the fault position, the attenuation degree and the fault length, comparing the fault factor with a set threshold value, and judging the severity of the fault, thereby realizing the online diagnosis of the fault of the chip-level integrated circuit. According to the invention, by introducing the adaptive wavelet basis selection and multi-scale wavelet entropy fusion technology, the accuracy and efficiency of diagnosis are significantly improved, the repeatability of fault signal feature extraction is reduced, and the real-time performance and stability of a diagnosis system are improved.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a chip-level integrated circuit fault diagnosis method based on improved wavelet entropy. Background Art

[0002] Fault diagnosis of chip-level integrated circuits is not only related to product reliability, but also directly affects production efficiency and cost control. Therefore, developing efficient and accurate fault diagnosis methods has become a hot topic in current research. In recent years, many scholars have conducted relevant research, such as reference [1]: a short-circuit fault diagnosis method for analog integrated circuits based on wavelet neural networks, which extracts features of fault signals through wavelet transform, and then uses neural networks to classify faults. This method improves the accuracy and efficiency of fault diagnosis to a certain extent, but since the parameter selection of wavelet transform and neural network has a great influence on the diagnosis results, a large amount of parameter adjustment and optimization is required in practical applications. Another example is reference [2]: an analog circuit fault diagnosis method based on IWOA-ELM, which uses the IWOA algorithm to optimize the parameters of ELM, thereby improving the generalization ability and stability of ELM in fault diagnosis. However, this method may have certain limitations when processing high-dimensional data and complex fault modes, and cannot fully meet the needs of real-time online diagnosis.

[0003] Chip-level integrated circuits integrate a large number of electronic components on a single piece of semiconductor material, making the circuit structure extremely complex and resulting in the inability to detect complex faults. Summary of the invention

[0004] The purpose of the present invention is to solve the above technical problems and propose a chip-level integrated circuit fault diagnosis method based on improved wavelet entropy.

[0005] In order to achieve the above-mentioned purpose, the present invention adopts the following technical solutions:

[0006] The chip-level integrated circuit fault diagnosis method based on improved wavelet entropy includes the following steps:

[0007] S1, collecting the original signal of the chip-level integrated circuit, and reconstructing the original signal using VMD signal reconstruction technology;

[0008] S2. Use the improved wavelet entropy method to deeply process the reconstructed signal and extract the key features of the fault signal;

[0009] S3, monitor the voltage changes of each node through the key features of the fault signal and effectively locate the fault location;

[0010] S4. Set a fault factor that can comprehensively consider the fault location, attenuation degree and fault length, compare it with the set threshold, and determine the severity of the fault, thereby realizing online diagnosis of chip-level integrated circuit faults.

[0011] Further, as a preferred technical solution of the present invention, S1 includes the following steps: connecting the input end of the signal acquisition card with the signal output end on the target chip, and when collecting the original signal of the chip-level integrated circuit, the original signal data set X of the chip-level integrated circuit is decomposed by using VMD signal reconstruction technology; decomposing the complex original signal into a number of inherent mode functions with different center frequencies, and after one reconstruction and decomposition, the following decomposition results are obtained:

[0012]

[0013] Where: u k (t) represents the kth intrinsic mode function obtained by decomposition, K represents the total number of intrinsic mode functions obtained by decomposition, and t represents the signal decomposition time;

[0014] The original signal of the chip-level integrated circuit processed by VMD signal reconstruction technology obtains multiple time domain component data; since the skewness is extremely sensitive in capturing subtle fluctuations in circuit performance, and the component signal with a larger skewness value often contains more details of circuit performance changes, the skewness is used to analyze the degree of performance fluctuation in the integrated circuit signal before and after optimization. The skewness S is as follows:

[0015]

[0016] Where n represents the number of data points, x i (t) represents domain component data; the components are sorted according to the size of the skewness value, and the components with larger skewness values ​​are selected for further analysis to obtain a reconstructed signal that can better reflect the fluctuation of circuit performance.

[0017] Further, as a preferred technical solution of the present invention, S2 includes the following steps: extracting fault signal features using improved wavelet entropy, selecting appropriate wavelet basis functions and decomposition levels, performing wavelet transform on the fault signal using formula (3), and obtaining wavelet coefficients of each frequency band;

[0018]

[0019] Where: S(t) represents the reconstructed chip-level integrated circuit signal, a represents the scale factor, which controls the expansion and contraction of the wavelet, b represents the translation factor, which controls the translation of the wavelet, and ψ represents the wavelet basis function;

[0020] The wavelet coefficients of each frequency band are normalized, and the formula is:

[0021]

[0022] Where: N represents the total number of points in the frequency band;

[0023] The information entropy of the wavelet coefficients of each frequency band is calculated, and the wavelet energy entropy of the fault signal is obtained as follows:

[0024]

[0025] Where: M represents the total number of decomposition layers, p i Represents the energy proportion of the i-th frequency band.

[0026] As a further preferred technical solution of the present invention, S3 includes the following steps: in the chip-level integrated circuit fault signal characteristics, if an open circuit fault occurs at a certain fault characteristic node f, the voltage value of the node will be significantly abnormal. Assuming that the voltage of the known node f in the non-fault state is V f , after the fault, the voltage of the characteristic node f becomes V f ', and calculate the effect of this change on the voltage V of the characteristic node g g The influence of is calculated as: ΔV g =GHΔV f (6)

[0027] Where: ΔV g Indicates the voltage change at characteristic node g, ΔV f =V f '-V f represents the voltage change of the characteristic node f, and G represents the influence of the voltage change of node f on the voltage of node g;

[0028] Analyze the voltage differences between different nodes and determine the node with the largest voltage change, which is the open circuit fault location;

[0029] In the case of an open circuit fault, the current value near the fault point will also drop significantly. Select a characteristic node g near the fault point to monitor the change of its current value. The current change is expressed by the following formula:

[0030] ΔI g =I g '-I g (7)

[0031] Where: I g ' represents the current value of node g after the fault occurs, I g Indicates the normal current value of node g before the fault occurs; by comparing ΔI g The size of the current near the node g is used to determine whether there is an abnormality;

[0032] Based on the above changes in voltage and current, considering the impact of different fault types on voltage and current, the threshold is set to determine whether the changes in voltage and current are significant enough to determine the fault type. The fault type discrimination formula is expressed as:

[0033]

[0034] Where: V represents the voltage threshold, I represents the current threshold;

[0035] When the voltage changes by ΔV g exceeds V and the current changes by ΔI g When it is lower than I, it is considered that the characteristic node g has failed.

[0036] Further, as a preferred technical solution of the present invention, the S4 includes the following steps: setting a fault factor that can comprehensively consider the fault location, attenuation degree and fault length, and the fault factor is expressed as:

[0037] Y=A0e -αd (1+βL)(9)

[0038] Where: A0 represents the initial amplitude of the characteristic waveform, e represents the base of the natural logarithm, α represents the attenuation rate, d represents the distance between the fault point and the input port, β represents the ratio of the influence of the fault length on the amplitude, and L represents the fault length;

[0039] The set thresholds include a minor fault threshold, a medium fault threshold, and a major fault threshold;

[0040] A minor fault refers to a fault that has little impact on the performance of the integrated circuit and will not cause the integrated circuit to fail immediately; the amplitude range of the characteristic waveform under normal working conditions is [0.8, 1.2], and the minor fault threshold is set to 0.7; when the fault factor value is less than 0.7, the fault is considered to be minor;

[0041] Moderate faults refer to faults that have a certain impact on the performance of the integrated circuit, causing the performance of the integrated circuit to degrade or become unstable; in order to set the medium fault threshold, the transition area between minor faults and serious faults is considered, and the medium fault threshold is set to 0.3; when the fault factor value is between 0.3 and 0.7, the fault is considered to be medium;

[0042] A serious fault refers to a fault that has a serious impact on the performance of the integrated circuit and causes the integrated circuit to fail or be damaged immediately; in order to set the serious fault threshold, the maximum degree of fault that the integrated circuit can tolerate is considered, and the serious fault threshold is set to 0.1; when the fault factor value is less than 0.1, the fault is considered to be serious.

[0043] The chip-level integrated circuit fault diagnosis method based on improved wavelet entropy of the present invention adopts the above technical solution and has the following technical effects compared with the prior art:

[0044] (1) The method of the present invention significantly improves the accuracy and efficiency of diagnosis by introducing adaptive wavelet basis selection and multi-scale wavelet entropy fusion technology.

[0045] (2) The method of the present invention not only reduces the repeatability of fault signal feature extraction, but also improves the real-time performance and stability of the diagnostic system. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 A schematic diagram of the method steps of an embodiment of the present invention;

[0047] Figure 2 A schematic diagram of a chip-level integrated circuit according to an embodiment of the present invention;

[0048] Figure 3 A schematic diagram of current signals corresponding to fault types according to an embodiment of the present invention;

[0049] Figure 4 Schematic diagram of the diagnosis result of an embodiment of the present invention. DETAILED DESCRIPTION

[0050] The present invention is further explained below in detail with reference to the accompanying drawings so that those skilled in the art can more deeply understand the present invention and be able to implement it. However, the following reference examples are only used to explain the present invention and are not intended to limit the present invention.

[0051] like Figure 1 As shown, the chip-level integrated circuit fault diagnosis method based on improved wavelet entropy includes the following steps:

[0052] S1, collecting the original signal of the chip-level integrated circuit, and reconstructing the original signal using VMD signal reconstruction technology;

[0053] S2. Use the improved wavelet entropy method to deeply process the reconstructed signal and extract the key features of the fault signal;

[0054] S3, monitor the voltage changes of each node through the key features of the fault signal and effectively locate the fault location;

[0055] S4. Set a fault factor that can comprehensively consider the fault location, attenuation degree and fault length, compare it with the set threshold, and determine the severity of the fault, thereby realizing online diagnosis of chip-level integrated circuit faults.

[0056] In S1, collecting the original signal of the chip-level integrated circuit is the first step in online fault diagnosis. First, make sure that the oscilloscope, signal acquisition card and connecting wires are in good working condition and are correctly connected as required. Locate the chip-level integrated circuit whose signal needs to be collected. After determining the target chip, determine the type and location of the signal to be collected. Use a test clip to connect the input end of the signal acquisition card to the signal output end on the target chip. After the connection is completed, start the signal acquisition device and set the sampling rate and resolution to 10MHz and 25V / bit respectively. According to actual needs, continuously collect signals for a period of time. After the acquisition is completed, save the data for subsequent analysis and processing.

[0057] When collecting the original signal of chip-level integrated circuits, due to equipment differences and the instability of the external environment, the signal is often mixed with complex and changeable noise and modulation components. In order to extract a purer and more characteristic signal, the present invention uses VMD signal reconstruction technology to decompose the original signal into multiple modal components, and then obtains a more valuable signal through screening and reconstruction, thereby improving the accuracy of signal processing.

[0058] For the original signal data set X of chip-level integrated circuits, VMD signal reconstruction technology is used for decomposition. Through this technical processing, the complex original signal is decomposed into several intrinsic mode functions with different center frequencies. After one reconstruction and decomposition, the following decomposition results are obtained:

[0059]

[0060] Where: u k (t) represents the kth intrinsic mode function obtained by decomposition, K represents the total number of intrinsic mode functions obtained by decomposition, and t represents the signal decomposition time;

[0061] The original signal of the chip-level integrated circuit processed by VMD signal reconstruction technology obtains multiple time domain component data. Since the skewness is extremely sensitive in capturing subtle fluctuations in circuit performance, and the component signal with a larger skewness value often contains more details of circuit performance changes, the skewness can be used to analyze the degree of performance fluctuation in the integrated circuit signal before and after optimization. The skewness S is as follows:

[0062]

[0063] Where n represents the number of data points, x i (t) represents domain component data; the components are sorted according to the size of the skewness value, and the components with larger skewness values ​​are selected for further analysis to obtain a reconstructed signal that can better reflect the fluctuation of circuit performance.

[0064] In S2, in the fault diagnosis of integrated circuits, it is crucial to accurately extract the characteristics of fault signals. Wavelet transform, as an effective time-frequency analysis tool, is widely used in the field of signal processing. In order to further improve the accuracy and efficiency of fault signal feature extraction, the present invention proposes a chip-level integrated circuit fault diagnosis method based on improved wavelet entropy. Wavelet transform is a transformation method that converts chip-level integrated circuit reconstructed signals from the time domain to the time-frequency domain. Compared with the traditional Fourier transform, wavelet transform can provide good localization characteristics in both the time domain and the frequency domain, and is particularly suitable for analyzing non-stationary signals. The basic formula of wavelet transform is:

[0065]

[0066] Where: S(t) represents the reconstructed chip-level integrated circuit signal, a represents the scale factor, which controls the expansion and contraction of the wavelet, b represents the translation factor, which controls the translation of the wavelet, and ψ represents the wavelet basis function;

[0067] The traditional wavelet entropy method is easily affected by the wavelet basis function when processing complex signals, resulting in poor feature extraction. In order to overcome the shortcomings of the traditional wavelet entropy method, the present invention uses improved wavelet entropy to extract fault signal features, selects appropriate wavelet basis functions and decomposition layers, and uses formula (3) to perform wavelet transform on the fault signal to obtain the wavelet coefficients of each frequency band. The wavelet coefficients of each frequency band are normalized, and the formula is:

[0068]

[0069] Where: N represents the total number of points in the frequency band; the information entropy of the wavelet coefficients of each frequency band is calculated, and the wavelet energy entropy of the fault signal is obtained as follows:

[0070]

[0071] Where: M represents the total number of decomposition layers, p i Represents the energy proportion of the i-th frequency band; wavelet energy entropy, as an important fault signal feature extraction method, plays an important role in the fault diagnosis of chip-level integrated circuits. It can comprehensively and accurately reflect the energy distribution characteristics of the fault signal in different frequency bands, providing strong support for fault diagnosis.

[0072] In S3, in the chip-level integrated circuit fault signal characteristics, if an open circuit fault occurs at a fault characteristic node f, the voltage value of the node will be significantly abnormal. Assume that the voltage of the node f in the non-fault state is V f , after the fault, the voltage of the characteristic node f becomes V f ', and want to calculate the effect of this change on the voltage V of the characteristic node g g The influence of is calculated as:

[0073] ΔV g =GHΔV f (6)

[0074] Where: ΔV g Indicates the voltage change at characteristic node g, ΔV f =V f '-V f represents the voltage change of the characteristic node f, and G represents the influence of the voltage change of node f on the voltage of node g.

[0075] By monitoring the voltage changes at each node, the open circuit fault point can be effectively located. Analyze the voltage differences between different nodes and determine the node with the largest voltage change, which is the open circuit fault location. In the case of an open circuit fault, the current value near the fault point will also drop significantly. Select a characteristic node g near the fault point and monitor the change in its current value. The current change can be expressed by the following formula: ΔI g =I g '-I g (7)

[0076] Where: I g ' represents the current value of node g after the fault occurs, I g Indicates the normal current value of node g before the fault occurs; by comparing ΔI g Based on the size of the voltage and current changes, we can determine whether the current near node g is abnormal. Based on the changes in the voltage and current, we can consider the impact of different fault types on the voltage and current. By setting a threshold, we can determine whether the changes in the voltage and current are significant enough to determine the fault type. The fault type discrimination formula can be expressed as:

[0077]

[0078] Where: V represents the voltage threshold, I represents the current threshold; when the voltage change ΔV g exceeds V and the current changes by ΔI g When it is lower than I, it is considered that the characteristic node g has failed.

[0079] In S4, a significant characteristic waveform change pattern was observed in the fault diagnosis of chip-level integrated circuits. As the distance from the fault point to the input port increases, the amplitude of the characteristic waveform decreases significantly. This amplitude reduction follows an approximate exponential decay pattern, but there are differences in the decay rate at different fault distances. For a fixed fault location, the expansion of the fault area will lead to a corresponding increase in the amplitude of the characteristic waveform. Based on these observations, a fault factor is proposed, which can comprehensively consider the fault location, attenuation degree and fault length, so as to accurately evaluate the severity of chip-level integrated circuit faults. The fault factor can be expressed as:

[0080] Y=A0e -αd (1+βL)(9)

[0081] Where: A0 represents the initial amplitude of the characteristic waveform, e represents the base of the natural logarithm, α represents the attenuation rate, d represents the distance between the fault point and the input port, β represents the ratio of the influence of the fault length on the amplitude, and L represents the fault length;

[0082] The fault factor value is a relative quantity that describes the severity of the fault relative to the normal state or the minor fault state. Therefore, setting the threshold is actually defining the boundaries of "minor", "moderate" and "major" faults.

[0083] Minor fault threshold: Minor faults usually refer to those that have little impact on the performance of the integrated circuit and will not cause the integrated circuit to fail immediately. The amplitude range of the characteristic waveform under normal working conditions is [0.8,1.2], and the minor fault threshold is set to 0.7. When the fault factor value is less than 0.7, the fault is considered to be minor.

[0084] Moderate fault threshold: Moderate faults refer to those faults that have a certain impact on the performance of the integrated circuit, causing the performance of the integrated circuit to degrade or become unstable. In order to set the moderate fault threshold, the transition area between minor faults and serious faults is considered, and the moderate fault threshold is set to 0.3. When the fault factor value is between 0.3 and 0.7, the fault is considered moderate.

[0085] Severe fault threshold: Severe faults refer to those faults that have a serious impact on the performance of the integrated circuit and cause the integrated circuit to fail or be damaged immediately. In order to set the severe fault threshold, the severe fault threshold is set to 0.1 considering the maximum degree of fault that the integrated circuit can tolerate. When the fault factor value is less than 0.1, the fault is considered severe. At this time, measures are taken immediately to repair the fault to prevent further damage or failure of the integrated circuit. With the changes in the working environment of the integrated circuit and the diversity of fault types, these thresholds also need to be continuously updated and optimized. Therefore, in practical applications, these thresholds are regularly evaluated and adjusted to ensure that they can accurately reflect the severity of the integrated circuit fault. So far, chip-level integrated circuit fault diagnosis based on improved wavelet entropy is completed.

[0086] In order to further explore and verify the effectiveness of the method of the present invention, a representative chip-level integrated circuit was selected as the experimental object, namely Figure 2 The integrated circuit shown in .

[0087] In terms of hardware, the AMD Ryzen 73700X processor is selected, with a main frequency of up to 3.6GHz, and can be dynamically increased to 4.4GHz when needed. In terms of software, LTspice XVII is selected, which is a powerful circuit simulation software that supports a variety of circuit components and complex circuit topologies, providing great convenience for circuit design and simulation in the experiment. The experimental test environment is shown in Table 1.

[0088] Table 1 Experimental test environment

[0089]

[0090] In the experiment, we first simulated the Figure 2 The chip-level integrated circuit shown in Table 2 is simulated. Through simulation, various possible fault conditions can be simulated and the corresponding current amplitude data are collected. These data directly reflect the performance of the chip under different fault conditions and become an important basis for evaluating the effectiveness of the improved wavelet entropy diagnosis method. By setting the fault type output as shown in Table 2, the severity of the short-circuit fault can be quantitatively analyzed, thereby verifying the accuracy of the diagnosis method.

[0091] Table 2 Fault type output

[0092]

[0093]

[0094] In order to intuitively show the impact of these fault types on the circuit current signal, the respective dynamic current signal waveforms are recorded and presented in the form of graphs, such as Figure 3 shown.

[0095] exist Figure 3 In the figure, the current signal waveforms corresponding to the six fault types show their own unique current change characteristics. The following is a description of the six fault types and their corresponding current changes:

[0096] 1) Transistor short circuit: When a transistor short circuits, its current increases rapidly to a level much higher than normal, forming a steep rising edge. This rapidly increasing current may cause other components in the circuit to overload or damage.

[0097] 2) Open resistor: An open resistor causes the current in the circuit path where it is located to suddenly drop, or even drop to zero. This is usually manifested as a clear falling edge, marking the transition of the current from normal flow to complete interruption.

[0098] 3) Capacitor failure: Capacitor failure is manifested as irregular fluctuations in the current signal.

[0099] 4) Power line short circuit: A power line short circuit usually causes a sharp increase in current, which may far exceed the maximum current value of the circuit design.

[0100] 5) Crystal oscillator failure: Crystal oscillator failure will affect the clock signal in the circuit, causing the current signal to fluctuate periodically or become abnormal. This failure may make the circuit unstable or even unable to work properly.

[0101] 6) Logic gate damage: Logic gate damage causes abnormal current in the circuit path it controls. This abnormal current may appear as continuous, irregular or intermittent current fluctuations.

[0102] According to the above dynamic current signal, more representative transistor short circuit faults, resistor open circuit faults and crystal oscillator faults are selected for subsequent diagnosis experiments. In order to verify the effect of the method of the present invention, reference [1]: Analog integrated circuit short circuit fault diagnosis method based on wavelet neural network and reference [2]: Analog circuit fault diagnosis method based on IWOA-ELM are selected as comparison methods to perform online fault diagnosis on transistor short circuit faults, resistor open circuit faults and crystal oscillator faults. The diagnosis results are as follows: Figure 4 shown.

[0103] according to Figure 4 It can be seen that document [1] can identify transistor short circuit faults and resistor open circuit faults to a certain extent, but when faced with more complex and difficult to detect crystal oscillator faults, document [1] cannot provide effective diagnostic results; document [2] fails to provide accurate diagnostic results for both transistor short circuit faults, resistor open circuit faults and crystal oscillator faults; while the method of the present invention not only successfully identifies transistor short circuit faults and resistor open circuit faults in the circuit, which are common and easy to detect fault types in integrated circuits, but also successfully detects relatively hidden and complex crystal oscillator faults. This proves that the fault diagnosis method proposed in the present invention can not only effectively identify multiple fault types in chip-level integrated circuits, but also exhibits excellent performance when faced with complex and difficult to detect faults.

[0104] The specific implementation scheme described above further describes in detail the purpose, technical scheme and beneficial effects of the present invention. It should be understood that the above is only a specific implementation scheme of the present invention and is not intended to limit the scope of the present invention. Any equivalent changes and modifications made by any technician in the field without departing from the concept and principle of the present invention should fall within the scope of protection of the present invention.

Claims

1. A chip-level integrated circuit fault diagnosis method based on improved wavelet entropy, characterized in that: The following steps are involved: S1, collecting the original signal of the chip-level integrated circuit, and reconstructing the original signal using VMD signal reconstruction technology; S2. Use the improved wavelet entropy method to deeply process the reconstructed signal and extract the key features of the fault signal; S3, monitor the voltage changes of each node through the key features of the fault signal and effectively locate the fault location; S4. Set a fault factor that can comprehensively consider the fault location, attenuation degree and fault length, compare it with the set threshold, and determine the severity of the fault, thereby realizing online diagnosis of chip-level integrated circuit faults.

2. The chip-level integrated circuit fault diagnosis method based on improved wavelet entropy according to claim 1 is characterized in that: The step S1 includes the following steps: connecting the input end of the signal acquisition card with the signal output end of the target chip, and when acquiring the original signal of the chip-level integrated circuit, using the VMD signal reconstruction technology to decompose the original signal data set X of the chip-level integrated circuit; decomposing the complex original signal into a number of intrinsic mode functions with different center frequencies, and after one reconstruction and decomposition, obtaining the following decomposition results: Where: u k (t) represents the kth intrinsic mode function obtained by decomposition, K represents the total number of intrinsic mode functions obtained by decomposition, and t represents the signal decomposition time; The original signal of the chip-level integrated circuit processed by VMD signal reconstruction technology obtains multiple time domain component data; since the skewness is extremely sensitive in capturing subtle fluctuations in circuit performance, and the component signal with a larger skewness value often contains more details of circuit performance changes, the skewness is used to analyze the degree of performance fluctuation in the integrated circuit signal before and after optimization. The skewness S is as follows: Where n represents the number of data points, x i (t) represents domain component data; the components are sorted according to the size of the skewness value, and the components with larger skewness values ​​are selected for further analysis to obtain a reconstructed signal that can better reflect the fluctuation of circuit performance.

3. The chip-level integrated circuit fault diagnosis method based on improved wavelet entropy according to claim 2 is characterized in that: The step S2 comprises the following steps: extracting fault signal features by using improved wavelet entropy, selecting appropriate wavelet basis functions and decomposition levels, performing wavelet transform on the fault signal by using formula (3), and obtaining wavelet coefficients of each frequency band; Where: S(t) represents the reconstructed chip-level integrated circuit signal, a represents the scale factor, which controls the expansion and contraction of the wavelet, b represents the translation factor, which controls the translation of the wavelet, and ψ represents the wavelet basis function; The wavelet coefficients of each frequency band are normalized, and the formula is: Where: N represents the total number of points in the frequency band; The information entropy of the wavelet coefficients of each frequency band is calculated, and the wavelet energy entropy of the fault signal is obtained as follows: Where: M represents the total number of decomposition layers, p i Represents the energy proportion of the i-th frequency band.

4. The chip-level integrated circuit fault diagnosis method based on improved wavelet entropy according to claim 3 is characterized in that: S3 includes the following steps: in the chip-level integrated circuit fault signal characteristics, if an open circuit fault occurs at a certain fault characteristic node f, the voltage value of the node will be significantly abnormal. Assuming that the voltage of the known node f in the non-fault state is V f , after the fault, the voltage of the characteristic node f becomes V f ', and calculate the effect of this change on the voltage V of the characteristic node g g The influence of is calculated as: ΔV g =GHΔV f (6) Where: ΔV g Indicates the voltage change at characteristic node g, ΔV f =V f '-V f represents the voltage change of the characteristic node f, and G represents the influence of the voltage change of node f on the voltage of node g; Analyze the voltage differences between different nodes and determine the node with the largest voltage change, which is the open circuit fault location; In the case of an open circuit fault, the current value near the fault point will also drop significantly. Select a characteristic node g near the fault point to monitor the change of its current value. The current change is expressed by the following formula: ΔI g =I g '-I g (7) Where: I g ' represents the current value of node g after the fault occurs, I g Indicates the normal current value of node g before the fault occurs; by comparing ΔI g The size of the current near the node g is used to determine whether there is an abnormality; Based on the above changes in voltage and current, considering the impact of different fault types on voltage and current, the threshold is set to determine whether the changes in voltage and current are significant enough to determine the fault type. The fault type discrimination formula is expressed as: Where: V represents the voltage threshold, I represents the current threshold; When the voltage changes by ΔV g Exceeds V and current changes by ΔI g When it is lower than I, it is considered that the characteristic node g has failed.

5. The chip-level integrated circuit fault diagnosis method based on improved wavelet entropy according to claim 4 is characterized in that: The S4 comprises the following steps: setting a fault factor that can comprehensively consider the fault location, attenuation degree and fault length, and the fault factor is expressed as: Y=A0e -αd (1+βL)(9) Where: A0 represents the initial amplitude of the characteristic waveform, e represents the base of the natural logarithm, α represents the attenuation rate, d represents the distance between the fault point and the input port, β represents the ratio of the influence of the fault length on the amplitude, and L represents the fault length; The set thresholds include a minor fault threshold, a medium fault threshold, and a major fault threshold; A minor fault refers to a fault that has little impact on the performance of the integrated circuit and will not cause the integrated circuit to fail immediately; the amplitude range of the characteristic waveform under normal working conditions is [0.8, 1.2], and the minor fault threshold is set to 0.7; when the fault factor value is less than 0.7, the fault is considered to be minor; Moderate faults refer to faults that have a certain impact on the performance of the integrated circuit, causing the performance of the integrated circuit to degrade or become unstable; in order to set the medium fault threshold, the transition area between minor faults and serious faults is considered, and the medium fault threshold is set to 0.3; when the fault factor value is between 0.3 and 0.7, the fault is considered to be medium; A serious fault refers to a fault that has a serious impact on the performance of the integrated circuit and causes the integrated circuit to fail or be damaged immediately; in order to set the serious fault threshold, the maximum degree of fault that the integrated circuit can tolerate is considered, and the serious fault threshold is set to 0.1; when the fault factor value is less than 0.1, the fault is considered to be serious.

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