Method for adaptively and dynamically adjusting clock frequency of audio and video equipment

Abstract

The invention provides a method for adaptively and dynamically adjusting the clock frequency of audio and video equipment. The method comprises the following steps: a receiving end FIFO (First In First Out) stores data into the FIFO according to a sending clock and control enabling; detecting empty and full states in real time, and generating an approximate full signal almostfull and an approximate empty signal almostep which correspond to an upper overflow trend and a lower overflow trend of the FIFO respectively; and according to whether the almostfull and the almostep are high or not, calculating a decimal part in a latest PLL decimal frequency division coefficient, sending the decimal part to the PLL, calculating the decimal frequency division coefficient, calculating a new reading frequency, and dynamically adjusting the clock frequency. The invention further provides a circuit for dynamically adjusting the clock frequency of the audio and video equipment. According to the invention, real-time overflow detection is realized, the transmission efficiency is improved, and unnecessary power consumption waste is reduced; one packet of data does not need to be stored in a buffer, so that the size of the buffer is relatively free, and the area cost is saved; successive approximation processing is carried out alternately according to empty and full signals, the sending clock frequency is converged to be consistent with the sampling clock frequency, overflow judgment does not need to be carried out all the time, and efficiency is improved.

Description

Technical Field

[0001] The invention relates to the field of digital signal processing, and in particular to a method for adaptively and dynamically adjusting the clock of audio and video equipment. Background Art

[0002] During the audio and video transmission process, the audio and video transmission clock of the transmitter and the audio and video sampling clock of the receiver are generated by different crystal oscillators and different frequency division coefficients. Therefore, there must be an error between the transmission clock of the transmitter and the sampling clock of the receiver. This error will cause the buffer of the receiver to overflow, resulting in distortion of the received audio and video at the receiver. Therefore, a method for adaptively and dynamically adjusting the clock of audio and video devices is needed to eliminate the clock error between the transmitter and the receiver during the audio and video transmission process.

[0003] Most of the existing methods for dynamically adjusting the frequency of the audio and video device clock mainly detect overflows on a packet-by-packet basis of audio and video data, and adjust the sampling clock frequency of the receiving end through the CPU, which is not conducive to system efficiency and audio and video transmission rate. Patent application 202210095189.1 discloses a method for dynamically adjusting the frequency of the audio and video device clock, which determines one by one whether the amount of data of the currently received audio data packet will cause the buffer of the receiving end to overflow. If an overflow occurs, an overflow interrupt will be returned to the CPU, and then the CPU will adjust the clock frequency of the receiving end so that the receiving buffer will not overflow. However, this method of frequency modulation, which relies on CPU interrupts and overflow judgment for data packets, is not conducive to the overall system efficiency and audio transmission efficiency.

[0004] The solutions for adjusting the audio and video equipment in the prior art have at least the following deficiencies:

[0005] 1. Whether the buffer overflows is determined by the data size of each data packet, making it impossible to transmit multiple data packets in parallel, which affects the transmission efficiency. In addition, packet-by-packet detection requires the buffer to store the data of this packet, and the size of the data packet is difficult for the receiving end to predict. This requires the buffer to be set large enough to store data packets of different sizes, which makes the buffer area cost too high.

[0006] 2. For a data packet, it is not the entire data packet that will cause the buffer to overflow, but the overflow part of the data packet. Originally, the frequency should only be adjusted for the overflow part. If the frequency is adjusted for the entire data packet, the higher the frequency, the more unnecessary the high frequency will be, resulting in waste of power consumption; the lower the frequency, the more unnecessary the low frequency will be, reducing the transmission efficiency of the receiving end.

[0007] 3. The clock frequency of the receiving end is adjusted up and down depending on the size of the data packet and the CPU interrupt. In this process, the clock error problem cannot be solved. As long as the data transmission is received, the overflow judgment will be repeatedly executed, which is inefficient. Secondly, relying on CPU interrupts for frequency adjustment will occupy the CPU's usage resources, and the CPU's response speed is not as timely as the dedicated circuit, which reduces the overall operating efficiency of the system and the transmission efficiency of the received audio and video data. Summary of the invention

[0008] The present invention provides a method for adaptively and dynamically adjusting the clock frequency of audio and video equipment, the method comprising:

[0009] S1: The first-in-first-out audio and video buffer FIFO at the receiving end stores the audio and video data into the buffer FIFO according to the sending clock and control enable of the sending end.

[0010] S2: The buffer FIFO detects the empty and full status in real time, and generates an almost full signal almost_full and an almost empty signal almost_empty, which correspond to the overflow trend and underflow trend of the FIFO respectively;

[0011] S3: If the almost-full signal almost_full is high, the dynamic frequency modulation process is started according to the almost_full signal.

[0012] S4: When the almost_full signal is high, the fractional part FRAC in the fractional frequency division coefficient of the phase-locked loop PLL is adjusted according to the last approximate overflow state.

[0013] S5: If the almost_full signal is not high, further determine whether the almost_empty signal is high. If the almost_empty signal is not high, it means that frequency modulation processing is not required temporarily; if the almost_empty signal is high, start dynamic frequency modulation processing according to the almost_empty signal.

[0014] S6: When the almost_empty signal is high, the adjusted FRAC is calculated based on the last approximate overflow state.

[0015] S7: After processing in steps S4 and S6, the fractional part FRACnew in the latest fractional frequency division coefficient of the phase-locked loop PLL is calculated and sent to the phase-locked loop PLL. The phase-locked loop PLL calculates the fractional frequency division coefficient according to FRACnew, calculates the new read frequency, and dynamically adjusts the clock frequency.

[0016] Step S4 further includes: if the last FIFO overflow state is approximately full, then the fractional part FRAC in the fractional frequency division coefficient of the phase-locked loop PLL is increased by step step; if the last FIFO overflow state is not approximately full, then FRAC is increased by 1 / 2 times step.

[0017] Step S6 further includes: if the last FIFO overflow state is approximately empty, then the fractional part FRAC in the fractional frequency division coefficient of the phase-locked loop PLL is reduced by step step; if the last FIFO overflow state is not approximately empty, then FRAC is reduced by 1 / 2 times step.

[0018] Furthermore, after step S2 is executed, step S8 is also executed to determine whether the sampling frequency matches the transmission frequency. If they match, it means that the sampling frequency has converged. Step S9 is executed to turn off the dynamic frequency modulation circuit and suspend the dynamic frequency modulation. If they do not match, the dynamic frequency modulation circuit is turned on, and subsequent steps are executed according to the judgment results of the approximately full signal almost_full and the approximately empty signal almost_empty.

[0019] Furthermore, it also includes executing step S10 after step S9. After the dynamic frequency modulation circuit is turned off, step S2 is executed again while data is continuously stored in the FIFO. If one of the generated approximately full signal almost_full or approximately empty signal almost_empty is high, it indicates that the previous clock matching failed. After the matching count value is increased, step S8 and subsequent processing are executed sequentially.

[0020] Furthermore, the determination of whether the sampling frequency matches the transmission frequency further includes a counter determining the number of times the read-write pointer difference remains unchanged continuously. When the counter reaches the matching count value, it indicates that the sampling clock frequency of the receiving end has converged to match the transmission clock of the transmitting end.

[0021] A circuit for dynamically adjusting the clock frequency of an audio and video device is also provided, the circuit comprising:

[0022] The splicing module reads the approximately empty and approximately full signals, performs bit splicing, and the splicing result indicates the current approximately empty and full state;

[0023] D flip-flop, when the clock rising edge arrives, if the work enable EN is high, the data at the input end of the D flip-flop is synchronously updated to the output end, and the fractional part FRAC and the step step in the fractional frequency division coefficient of the phase-locked loop PLL are determined according to the approximate empty and full states to determine whether to dynamically adjust the frequency;

[0024] The bit right shift module divides the step length by 2. When the current approximate empty and full state is different from the previous approximate empty and full state, the step length is divided by 2.

[0025] The inequality judgment module judges whether the current approximate empty and full state is the same as the previous approximate empty and full state, and sends the judgment result to the first two-way selector to select the input. If the current approximate empty and full state is not equal to the previous approximate empty and full state, the step length step is adjusted to 1 / 2 of the original; if the current approximate empty and full state is equal to the previous approximate empty and full state, the step length step remains unchanged;

[0026] The second two-way selector adds or subtracts the step length step adjusted by the first two-way selector from FRAC to update FRAC to generate FRACnew;

[0027] When the rising edge of the FIFO read clock rd_clk arrives, the D flip-flop outputs the calculated FRACnew, and the PLL calculates the fractional division coefficient based on FRACnew, calculates the new read frequency, and dynamically adjusts the clock frequency.

[0028] Further, when the first two-way selector adjusts the step length step, if it is currently approximately full and was approximately full last time, then step does not change, if it was not approximately full last time, then step becomes 1 / 2 times; if it is currently approximately empty and was approximately empty last time, then step does not change, if it was not approximately empty last time, then step becomes 1 / 2 times;

[0029] When the second two-way selector adjusts FRAC, if it is currently approximately full, FRAC is updated to FRAC plus the adjusted step; if it is currently approximately empty, FRAC is updated to FRAC minus the adjusted step.

[0030] The technical effects of the present invention are as follows: the processing process does not rely on packet-by-packet overflow detection, but rather performs more precise real-time overflow detection, thereby improving transmission efficiency and reducing unnecessary power consumption waste, and since there is no need to store a packet of data in the buffer, the buffer size can be set relatively freely, reducing the size of the audio and video buffer and saving area cost overhead; the frequency adjustment method is improved, and gradual approximation processing is performed alternately according to the empty and full signals, so that the receiving end's sending clock frequency is converged to be consistent with the sending end's sampling clock frequency, and there is no need to perform overflow judgment all the time, thereby improving efficiency; a special dynamic frequency modulation circuit is designed, and there is no need to return an overflow interrupt to the CPU, thereby reducing the CPU's resource consumption and improving the response speed, thereby improving the system operation efficiency and the audio and video transmission efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a logic block diagram of the clock frequency dynamic adjustment of the present invention;

[0032] Figure 2 is a flow chart of dynamic adjustment of clock frequency of the present invention;

[0033] Figure 3 is a flow chart of another embodiment of the clock frequency dynamic adjustment of the present invention;

[0034] Figure 4 is a structural diagram of a dynamic frequency modulation circuit of the present invention;

[0035] Figure 5 It is a schematic diagram of the dynamic frequency modulation process of the present invention; DETAILED DESCRIPTION

[0036] During the transmission of audio and video signals, the clock difference between the transmitter and the receiver leads to audio and video transmission quality problems. For example, a typical application is a laptop (transmitter) connected to a large-size display (receiver) via an HDMI cable, and the video and audio of the movie are played on the large-size display to obtain a better audio-visual experience. If the clock difference problem between the laptop and the large-size display is not solved, the audio of the laptop movie played on the large-size display will experience audio loss, noise, screen distortion, black screen and other audio and video distortion phenomena.

[0037] The present invention uses a receiving end buffer overflow detection method, cooperates with a dedicated dynamic frequency modulation circuit, alternately performs fractional frequency adjustment according to FIFO approximate empty and full signals, and then gradually approaches the method to realize adaptive dynamic adjustment of the audio and video device clock.

[0038] The present invention adds a dynamic frequency modulation circuit on the basis of a first-in first-out audio and video buffer (FIFO), a phase-locked loop (PLL), and a crystal oscillator. Figure 1 shown. Figure 1 The meanings of the relevant parameters are as follows:

[0039] PLL: Phase-locked loop.

[0040] ref_clk: crystal oscillator output clock.

[0041] tx_clk: The transmit clock from the transmitter.

[0042] tx_data: audio and video data sent by the transmitter.

[0043] din: FIFO data input port.

[0044] wr_clk: FIFO write clock.

[0045] dout: FIFO output data, which means the audio and video data that is cached by FIFO and then output.

[0046] rd_clk: FIFO read clock.

[0047] almost_full: FIFO almost full signal.

[0048] almost_empty: Almost empty signal of FIFO.

[0049] FRAC: The fractional part of the PLL fractional frequency coefficient.

[0050] Figure 2 This is the first embodiment of the present invention for dynamically adjusting the clock frequency. In this embodiment, the dynamic frequency modulation process is not terminated, and the sampling clock frequency of the receiving end is dynamically adjusted in real time. No matter how high the clock frequency accuracy of the transmitting end is, the sampling clock of the receiving end can be dynamically adjusted accordingly. The advantage of this solution is that it can match the transmitting clock of the transmitting end with any accuracy, but because dynamic frequency modulation is always performed, additional power consumption will be generated.

[0051] Figure 2 Dynamically adjusting the clock frequency includes the following steps:

[0052] S1: The first-in-first-out audio and video buffer FIFO at the receiving end stores the audio and video data tx_data from the sending end into the FIFO through the data input port din according to the sending clock tx_clk and related control enable of the sending end.

[0053] S2: In the process of continuously storing tx_data into FIFO, FIFO detects the empty and full status in real time according to the internal write pointer and internal read pointer, and generates the nearly full signal almost_full and the nearly empty signal almost_empty by the hardware circuit according to the set threshold. These two signals represent the full and empty trends inside FIFO, corresponding to the overflow (almost full) and underflow (almost empty) trends. Based on the basic functions of FIFO, by calculating whether the difference between the read and write pointers inside FIFO is greater than the set nearly full and nearly empty thresholds, if it is greater, it indicates that FIFO is currently in the nearly empty and nearly full states.

[0054] S3: If the almost full signal almost_full is high, it means that the FIFO has an overflow trend, and the almost_full signal will be sent to the dynamic frequency modulation circuit to start dynamic frequency modulation processing.

[0055] S4: When the almost_full signal is high, read the current high level of the almost_full signal, and adjust the fractional part FRAC in the fractional frequency division coefficient of the phase-locked loop PLL according to the last approximate overflow state.

[0056] If the last FIFO overflow state is also nearly full, the fractional part FRAC in the fractional frequency coefficient of the phase-locked loop PLL is added with the stepping step. The stepping step is set differently according to different boards to increase the FIFO reading frequency and suppress the FIFO full situation. If the last FIFO trend is not nearly full, FRAC is added with 1 / 2 times the step.

[0057] In step S4, the method of alternating fractional frequency adjustment and then gradually approximating according to the FIFO approximate empty and full signals, and using the last approximate empty and full state to recalculate the step is to achieve a convergence state. For example, if the FIFO has always been generating an approximate full signal, it means that the FIFO read frequency must be actively increased, so FRAC will add a step; but if the last trend of the FIFO is not approximately full, it means that the current approximate full degree is not so urgent, and the FIFO read frequency can be increased less actively, so FRAC will add 1 / 2 times the step, thereby achieving a convergence effect, and finally the sampling clock of the receiving end will be consistent with the sending clock of the sending end.

[0058] S5: If the almost_full signal is not high, it is further determined whether the almost empty signal almost_empty is high. If the almost empty signal almost_empty is not high, it means that the current FIFO is not in an almost overflow state, and no frequency modulation processing is required temporarily. However, it does not mean that the sampling frequency converges to the same as the transmission frequency, and the entire frequency modulation process must continue. If the almost empty signal almost_empty is high, it means that the FIFO has an underflow trend, and the almost_empty signal will be sent to the dynamic frequency modulation circuit to execute the processing of step S6.

[0059] S6: When almost_empty is high, read the current high level of the almost_empty signal and reduce FRAC according to the last approximate overflow state.

[0060] If the last FIFO trend is also approximately empty, the fractional part FRAC in the phase-locked loop PLL fractional division coefficient is subtracted from the step set according to different boards to reduce the FIFO reading frequency and suppress the occurrence of FIFO empty; if the last FIFO trend is not approximately empty, FRAC is subtracted from 1 / 2 times the step.

[0061] Step S6 uses a method of alternating fractional frequency adjustment and then gradually approximating the FIFO's approximately empty and full signals, and recalculates the step using the last approximately empty and full state, in order to reach a convergence state. For example, if the FIFO has always been generating approximately empty signals, it means that the FIFO reading frequency must be actively reduced, so FRAC will subtract step; but if the last trend of the FIFO was not approximately empty, it means that the current approximately empty degree is not so urgent, and the FIFO reading frequency can be reduced less actively, so FRAC will subtract 1 / 2 times the step, thereby achieving a convergence effect, and finally making the sampling clock of the receiving end consistent with the sending clock of the sending end.

[0062] S7: After processing in steps S4 and S6, the dynamic frequency modulation circuit calculates the fractional part FRACnew of the latest phase-locked loop PLL fractional frequency coefficient and sends it to the phase-locked loop. The phase-locked loop calculates the fractional frequency coefficient based on FRACnew, calculates the new read frequency, and dynamically adjusts the clock frequency.

[0063] Figure 3 This is the second embodiment of the present invention for dynamically adjusting the clock frequency. In this embodiment, by setting certain conditions, it is determined whether the sending clock frequency of the sending end and the sampling clock frequency of the receiving end match each other. When the two clocks match, the dynamic frequency modulation circuit is turned off and the dynamic frequency modulation process is ended. Since dynamic frequency modulation is no longer required in the future, power consumption can be saved. The advantage of this solution is that it can end the dynamic frequency modulation process and save power consumption by not having to perform dynamic frequency modulation all the time. However, it can only perform clock matching with a certain accuracy. When the accuracy of the sending clock frequency of the sending end is too high, a matching blind spot is likely to occur, resulting in a certain error. In order to ensure successful matching, additional insurance measures are designed to correct matching errors caused by accuracy problems, and dynamically adjust the matching count value to adapt to higher-precision clock matching.

[0064] The operation flow of the second embodiment is as follows: in the overall flow of the first embodiment, after executing step S2 "FIFO detects the empty and full status in real time, and generates an almost full signal almost_full and an almost empty signal almost_empty", execute step S8.

[0065] S8: Determine whether the sampling frequency has converged to match the transmission frequency. If it matches, it means that the sampling frequency has converged, and execute step S9; if it does not match, turn on the dynamic frequency modulation circuit, and further determine whether the almost full signal almost_full is high. If it is high, execute step S3 and subsequent steps in sequence. If the almost full signal almost_full is not high, determine whether the almost empty signal almost_empty is high, and execute subsequent steps based on the determination result.

[0066] In step S8, it is determined whether the sending clock frequency of the transmitting end matches the sampling clock frequency of the receiving end under a certain accuracy. There are read pointers and write pointers inside the FIFO. If the difference between them is the same for a long period of time, it means that the change rate of the read pointer and the write pointer in the FIFO is consistent. This shows that the read frequency and the write frequency of the FIFO are the same, which also means that the sending clock of the transmitting end matches the sampling clock of the receiving end.

[0067] Therefore, a counter (cnt) is set inside the FIFO to determine the number of times the difference between the read and write pointers remains unchanged. When the counter reaches a certain value (matching count value) (which can be set by software through registers), it means that the sampling clock frequency of the receiving end has converged to match the sending clock of the sending end through dynamic frequency modulation.

[0068] This method can determine whether the clocks within a certain frequency range match. For example:

[0069] 1. If the match count value of the current counter is set to 100, it is necessary to be able to effectively determine whether the frequency matches within 100 cycles. This requires that the ratio of the receiving and sending clock frequencies must be greater than 1.01 and less than 0.99. If the match count value is set to 1000, the ratio between the receiving and sending clocks must be greater than 1.001 and less than 0.999. A simple example is as follows:

[0070] When the match count value is set to 100, the frequency of FIFO write clock A is 1000hz, the frequency of read clock B is 1010hz, and the ratio of the two frequencies is 1.01. Starting from a certain moment, the difference between the read and write pointers does not change, and the counter starts counting from 0 to count the number of times the read and write difference remains unchanged. When the counter counts to 99, if the reading and writing of the intermediate FIFO are not interrupted, the write pointer of clock A increases by 100, the read pointer of clock B increases by 101, and the difference between the read and write pointers increases by 1 and changes. The counter is cleared, and it is correctly detected that A and B have not matched yet.

[0071] If the frequency of FIFO write clock A is 1000hz, and the frequency of read clock B is 1001hz, the ratio of the two frequencies is 1.001. Starting from a certain moment, the difference between the read and write pointers does not change, and the counter starts counting from 0, counting the number of times the difference between the read and write remains unchanged. When the counter counts to 99, if the reading and writing of the intermediate FIFO are not interrupted, the write pointer of clock A increases by 100, and the read pointer of clock B increases by 100.1 (which means that the read pointer is likely to increase by 100 as well), and the difference between the read and write pointers remains unchanged. This leads to the mistaken belief that A and B have matched, but in fact A and B have not matched.

[0072] Combining the above example, we can know that when the match count value is set to 100, when clock A is 1000 Hz, if clock B is at (990, 1000) (1000, 1010) Hz, the method will assume that A and B are matched. This can be called the matching blind spot of the method.

[0073] In this case, the matching count value can be increased, for example, from 100 to 1000. Then, when A is 1000 Hz, the matching blind area becomes (999, 1000) to (1000, 1001). At this time, when B is 1001 Hz, it can be successfully identified as not matching A.

[0074] The difference between B being 1010hz and B being 1001hz can be equivalent to a change in the frequency of the clock precision, that is, the difference between 1.01khz and 1.001khz. Therefore, it can be seen that if the clock precision requirement is higher, the required matching count value is larger. Therefore, under a fixed matching count value, it can only meet the clock frequency matching under a certain precision. In actual applications, the matching count value can be set larger according to the application scenario, so that the transmitter clock frequency with greater precision can be matched. Because the accuracy of the clock frequency is limited, setting a larger matching count value can cover most working conditions. It is also possible to dynamically adapt to working scenarios with greater clock frequency precision by dynamically increasing the matching count value.

[0075] S9: When the sending clock frequency of the sending end is consistent with the sampling clock frequency of the receiving end, the dynamic frequency modulation circuit is turned off and the dynamic frequency modulation process is temporarily stopped.

[0076] S10: After the sending clock matches the sampling clock and the frequency modulation circuit is turned off, step S2 will be executed again as data is continuously stored in the FIFO. If one of the generated nearly full signal almost_full or nearly empty signal almost_empty is high, since these two signals represent the full-empty trend inside the FIFO, corresponding to the overflow (approximately full) and underflow (approximately empty) trends, it means that the FIFO buffer outputs an overflow state, and the occurrence of this overflow state means that the previous clock matching failed. A clock matching failure indicates that the current matching count value cannot meet the current clock frequency accuracy requirements, and the matching count value needs to be increased through software / hardware configuration registers. After increasing the matching count value, step S8 and subsequent processing flow are executed in sequence.

[0077] The dynamic frequency modulation circuit performs gradual approximation processing alternately according to the empty and full signals. Through the current approximate empty and full state and the previous approximate empty and full state, the fractional part FRAC in the fractional frequency division coefficient of the phase-locked loop PLL is added or subtracted by step or 1 / 2 times the step. By adjusting FRAC, FRACnew is obtained and transmitted to PLL. PLL adjusts the reading frequency of the first-in-first-out audio and video buffer FIFO according to FRACnew to realize dynamic frequency modulation.

[0078] Figure 4 , Figure 5 The dynamic frequency modulation circuit structure and method flow chart of the present invention are shown respectively. Figure 4 The meanings and markings of the relevant parameters are as follows:

[0079] rd_clk: FIFO read clock; EN: D flip-flop operation enable; FRACnew: new FRAC value calculated and output by the dynamic frequency modulation circuit. ①: splicing module; ②: D flip-flop; ③: bit right shift module; ④: first two-way selector; ⑤: inequality judgment module; ⑥: adder; ⑦: subtractor; ⑧: second two-way selector; ⑨: port of the dynamic frequency modulation circuit.

[0080] Combination Figure 4-Figure 5 , describe the working process of dynamic frequency modulation circuit.

[0081] The splicing module ① reads in the approximately empty and approximately full signals, performs bit splicing, and the spliced ​​result indicates the current empty and full state. If the current empty and full state is 10, it means the current state is approximately empty; the current empty and full state is 01, which means the current state is approximately full; the current empty and full state is 00, which means there is no approximate overflow and no frequency modulation; there is no situation where the current empty and full state is 11, which means it is both approximately empty and approximately full. Approximate empty and approximately full are mutually exclusive and this situation is impossible, so it will not be discussed here. (S12, S13, S17)

[0082] When the clock rises, if EN is high, the data at the input of the D flip-flop is updated synchronously to the output of the D flip-flop. If the near empty or near full state is not 00 (that is, there is a near empty or near full state, and EN is high at this time), it means that FRAC and step need to be adjusted, so the D flip-flop will be triggered to update FRAC and step.

[0083] The bit right shift module ③ implements the processing of step divided by 2. In binary numbers, the data is shifted right by one bit, indicating that the data is divided by 2. When the current approximate empty and full state is different from the previous approximate empty and full state, step is divided by 2.

[0084] If the current empty and full states are 00, the two D flip-flops with EN will not be enabled, the initial FRAC and step will not change, and frequency modulation will not be performed this time (S21).

[0085] The processing process of the two-way selector is to judge whether the current condition is met. If the current condition is met, one input is selected for output; if the current condition is not met, another input is selected for output. The inequality judgment module ⑤ is used to judge whether the current approximate empty and full state is the same as the previous approximate empty and full state, and the judgment result is sent to the first two-way selector ④ to select the input. If the current approximate empty and full state is not equal to the previous approximate empty and full state, the step is adjusted to 1 / 2 of the original; if the current approximate empty and full state is equal to the previous approximate empty and full state, the step remains unchanged and the step is adjusted. (S14, S15, S18, S19)

[0086] More specifically, (1) if the current state is approximately full and the last time it was approximately full, the step does not change, FRAC+step; (2) if the current state is approximately full and the last time it was approximately empty, the step becomes 1 / 2 times, FRAC+step; (3) if the current state is approximately empty and the last time it was approximately empty, the step does not change, FRAC-step; (4) if the current state is approximately empty and the last time it was approximately full, the step becomes 1 / 2 times, FRAC-step; (5) if the current state is approximately full and there was no approximately empty or full state last time, the step becomes 1 / 2 times, FRAC+step; (6) if the current state is approximately empty and there was no approximately empty or full state last time, the step becomes 1 / 2 times, FRAC-step.

[0087] If the current empty / full state is approximately full (10), then FRAC+step (S14, S15, S16); if the current empty / full state is approximately empty (01), then FRAC-step (S18, S19, S20). The second two-way selector⑧ selects to add / subtract step to FRAC to update FRAC.

[0088] When the rising edge of the rd_clk clock arrives, the D flip-flop will output the calculated FRACnew to ⑨. (S22)

[0089] like Figure 5 As shown:

[0090] S12: Read in the approximately empty and approximately full signals from the FIFO.

[0091] S13: Determine whether the current signal is approximately full.

[0092] S14: If the current state is approximately full and the last state was approximately full, the step does not change, FRAC+step.

[0093] S15: If the current state is approximately full and the last state was approximately empty, the step is increased to 1 / 2, FRAC+step.

[0094] S16: If the current state is approximately full and there was no approximately empty state last time, the step becomes 1 / 2 times, FRAC+step.

[0095] S17: If the current state is not approximately full, determine whether it is approximately empty.

[0096] S18: If the current state is approximately empty and the last state was approximately empty, the step does not change, FRAC-step.

[0097] S19: If the current state is approximately empty and the last state was approximately full, the step is increased by 1 / 2, FRAC-step.

[0098] If S20 is currently in the nearly empty state and was not nearly empty or full last time, the step becomes 1 / 2 times, FRAC-step.

[0099] If S21 is not nearly full or not nearly full, no processing is performed and step and FRAC remain unchanged.

[0100] S22 outputs the adjusted FRACnew.

[0101] The present invention improves the limitations of packet-by-packet overflow detection in previous audio and video dynamic frequency modulation schemes for audio and video transmission, and can achieve multi-packet parallel transmission through real-time frequency adjustment, thereby improving transmission efficiency and reducing unnecessary power consumption, and can reduce the buffer size without the need for a larger buffer to reduce data overflow.

[0102] The present invention proposes a dynamic frequency modulation convergence scheme, which improves the shortcomings of the previous scheme of receiving data and modulating the frequency all the time based on the idea of ​​gradual approximation by alternating empty and full signals, greatly reduces the number of frequency modulations, improves efficiency, and does not generate an excessively large frequency division coefficient through progressive adjustment of fractional frequency division, so that the phase-locked loop can stably enter the locked state without affecting the phase of the clock.

[0103] The present invention proposes a dedicated dynamic frequency modulation circuit for dynamic frequency modulation. This dynamic frequency modulation circuit allows the frequency modulation process to be performed without the involvement of software, reduces interrupt access to the CPU, responds more promptly, and ensures that data at the receiving end will not be interrupted, thereby ensuring that there will be no sound interruption in audio and video, and improving the overall system efficiency and audio and video transmission efficiency.

[0104] The present invention proposes two solutions for matching the sending clock of the sending end with the sampling clock of the receiving end according to different requirements of clock accuracy and power consumption. The present invention is highly adaptable and can be applied to various audio and video transmission protocols with a receiving end buffer.

[0105] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the present invention.

Claims

1. A method for adaptively and dynamically adjusting the clock frequency of an audio and video device, the method comprising: S1: The first-in-first-out audio and video buffer FIFO at the receiving end stores the audio and video data into the buffer FIFO according to the sending clock and control enable of the sending end; S2: The buffer FIFO detects the empty and full status in real time, and generates an almost full signal almost_full and an almost empty signal almost_empty, which correspond to the overflow trend and underflow trend of the FIFO respectively; S3: if the almost_full signal is high, start dynamic frequency modulation processing according to the almost_full signal; S4: when the almost_full signal is high, adjust the fractional part FRAC in the fractional frequency division coefficient of the phase-locked loop PLL according to the last approximate overflow state; S5: if the almost_full signal is not high, further determine whether the almost empty signal almost_empty is high. If the almost empty signal almost_empty is not high, it means that the frequency modulation processing is not needed temporarily; if the almost empty signal almost_empty is high, start the dynamic frequency modulation processing according to the almost_empty signal; S6: When the almost_empty signal is high, the adjusted FRAC is calculated according to the last approximate overflow state; S7: After processing in steps S4 and S6, the fractional part FRACnew in the latest fractional frequency division coefficient of the phase-locked loop PLL is calculated and sent to the phase-locked loop PLL. The phase-locked loop PLL calculates the fractional frequency division coefficient according to FRACnew, calculates the new read frequency, and dynamically adjusts the clock frequency.

2. The method for adaptively and dynamically adjusting the clock frequency of audio and video equipment as described in claim 1, step S4 further includes: if the last FIFO approximate overflow state is approximately full, then the fractional part FRAC in the fractional frequency division coefficient of the phase-locked loop PLL is increased by step step; if the last FIFO approximate overflow state is not approximately full, then FRAC is increased by 1 / 2 times step.

3. The method for adaptively and dynamically adjusting the clock frequency of audio and video equipment as described in claim 1, step S6 further includes: if the last FIFO approximate overflow state is approximately empty, then the fractional part FRAC in the fractional division coefficient of the phase-locked loop PLL is reduced by step step; if the last FIFO approximate overflow state is not approximately empty, then FRAC is reduced by 1 / 2 times step.

4. According to the method for adaptively and dynamically adjusting the clock frequency of audio and video equipment as described in claim 1, after step S2 is executed, step S8 is also executed to determine whether the sampling frequency matches the sending frequency. If they match, it means that the sampling frequency has converged. Step S9 is executed to turn off the dynamic frequency modulation circuit and suspend the dynamic frequency modulation. If they do not match, the dynamic frequency modulation circuit is turned on, and subsequent steps are executed according to the judgment results of the almost full signal almost_full l and the almost empty signal almost_empty.

5. The method for adaptively and dynamically adjusting the clock frequency of audio and video equipment as described in claim 4 further includes executing step S10 after executing step S9, and after the dynamic frequency modulation circuit is turned off, step S2 is executed again during the process of continuously storing data into the FIFO, and if one of the generated almost full signal almost_full or almost empty signal almost_empty is high, it indicates that the previous clock matching failed, and after increasing the matching count value, step S8 and subsequent processing are executed in sequence.

6. The method for adaptively and dynamically adjusting the clock frequency of audio and video equipment as described in claim 4, wherein the determination of whether the sampling frequency matches the transmission frequency further includes a counter determining the number of times the read-write pointer difference remains unchanged continuously, and when the counter reaches the matching count value, it indicates that the sampling clock frequency of the receiving end has converged to match the transmission clock of the transmitting end.

7. A circuit for dynamically adjusting the clock frequency of an audio or video device, the circuit comprising: The splicing module reads the approximately empty and approximately full signals, performs bit splicing, and the splicing result indicates the current approximately empty and full state; D flip-flop, when the clock rising edge arrives, if the work enable EN is high, the data at the input end of the D flip-flop is synchronously updated to the output end, and the fractional part FRAC and the step step in the fractional frequency division coefficient of the phase-locked loop PLL are determined according to the approximate empty and full states to determine whether to dynamically adjust the frequency; The bit right shift module divides the step size by 2. When the current approximate empty and full state is different from the previous approximate empty and full state, the step size is divided by 2. The inequality judgment module judges whether the current approximate empty and full state is the same as the previous approximate empty and full state, and sends the judgment result to the first two-way selector to select the input. If the current approximate empty and full state is not equal to the previous approximate empty and full state, the step length step is adjusted to 1 / 2 of the original; if the current approximate empty and full state is equal to the previous approximate empty and full state, the step length step remains unchanged; The second two-way selector adds or subtracts the step length step adjusted by the first two-way selector from FRAC to update FRAC to generate FRACnew; When the rising edge of the FIFO read clock rd_clk arrives, the D flip-flop outputs the calculated FRACnew, and the PLL calculates the fractional division coefficient based on FRACnew, calculates the new read frequency, and dynamically adjusts the clock frequency.

8. The circuit for dynamically adjusting the clock frequency of audio and video equipment as claimed in claim 7, wherein when the first two-way selector adjusts the step length step, if the current is approximately full and the previous time was approximately full, then step does not change, and if the previous time was not approximately full, then step is multiplied by 1 / 2; if the current is approximately empty and the previous time was approximately empty, then step does not change, and if the previous time was not approximately empty, then step is multiplied by 1 / 2; When the second two-way selector adjusts FRAC, if it is currently approximately full, FRAC is updated to FRAC plus the adjusted step; if it is currently approximately empty, FRAC is updated to FRAC minus the adjusted step.

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