Method and system for designing reusable double-domain multiplier

Abstract

The invention discloses a reusable double-domain multiplier design method and system, and the method comprises the steps: double-domain non-logic base-4Booth coding: setting a coding logic which simultaneously supports the complement operation of a prime number domain and a binary extension domain and a symbol extension bit, and easily realizing the generation of a partial product under double domains through extension; dual-domain partial product generation: generating a partial product array based on the coded values; performing Wallace tree-shaped compression: on the basis of a compressor of a Wallace tree-shaped compression structure, realizing dual-domain compression by introducing a domain control bit; and adder operation: obtaining two partial products based on compression, and adding the two partial products through an adder to obtain a final multiplication result. According to the method, Booth coding, double-domain partial product generation and double-domain compression logic on the prime number domain and the binary extension domain are designed, the symbol extension bit preprocessing technology and the complement plus one-bit optimization technology are combined, multiplication on the double domains can be supported at the same time, and the method has the remarkable advantages of being small in resource occupation and high in performance.

Description

Technical Field

[0001] The present invention relates to the field of information security and integrated circuit technology, and in particular to a reusable dual-domain multiplier design method and system. Background Art

[0002] At present, elliptic curve cryptography is mainly used in two special finite fields, namely the prime field GF(p) and the binary extension field GF(2 m ). Application protocols such as key exchange, encryption and decryption, and digital signatures on elliptic curves are all based on operations on coordinate points on different finite fields, mainly including modular operations such as modular addition and subtraction, modular squaring, modular multiplication, and modular inverse. Dual finite field multiplication operations are the key components of dual field modular multiplication operations. The circuit structure design of dual field multipliers has a direct impact on the area, speed, and other performance of the entire system.

[0003] (1) Prime field GF(p)

[0004] Let p be a prime number. With p as the modulus, the set of all non-negative integers less than p, {0,1,2,3,...,p-1}, with respect to addition and multiplication modulo p, constitutes the prime field, denoted by the symbol GF(p). Addition of field elements is addition modulo p of integers, and multiplication of field elements is multiplication modulo p of integers.

[0005] (2) Binary extension GF(2 m )

[0006] A finite field of order 2m is called a binary field and is denoted by GF(2 m ) represents the binary extension domain GF(2 m ) can be viewed as an m-dimensional vector space over GF(2), whose elements can be represented by bit strings of length m. The two most commonly used methods are polynomial basis and normal basis. The addition of two field elements is the bitwise XOR operation of the bit strings. The multiplication of field elements a and b is defined as follows: Let the polynomials corresponding to a and b be a(x) and b(x), then a·b is defined as the bit string corresponding to the polynomial (a(x)b(x))modf(x), and f(x) is the reduced polynomial.

[0007] The multiplier is the core of digital signal processing and a key component of data processing and public key cryptography. Large number high-speed multipliers usually adopt a parallel structure, which is generally divided into three stages: partial product generation, partial product compression and final carry propagation addition. In the partial product generation stage, the Booth coding algorithm compresses and encodes the multiplier to reduce the number of partial products generated and speed up the compression of partial products. Higher-order Booth algorithms have a higher partial product compression rate, but more odd-multiplied multiplicands need to be pre-calculated, and additional binary complement conversion circuits are required, which limits the application of high-order Booth coding algorithms. Therefore, the most commonly used radix-4 Booth coding structure in actual design is the radix-4 Booth coding structure.

[0008] The conventional radix-4 Booth coding algorithm re-encodes the multiplier and generates three corresponding control signals, fills a 0 in the lowest bit, and groups the signals in a manner of three bits as a group and two groups overlapping by one bit.

[0009]

[0010]

[0011] Among them, b -1 =0.

[0012] It can be seen that by preprocessing -2·b 2i+1 +b 2i +b 2i-1 , the number of partial products can be reduced by about half. The encoding rules are shown in the following table:

[0013] Table 1 Conventional base-4 Booth coding table

[0014]

[0015]

[0016] However, Booth coding involves complement operations and sign extension bit conversion, and conventional radix-4 Booth coding is not easily extended to support radix-4 multiplication in binary fields and complement operations in prime fields. Summary of the invention

[0017] In order to solve the above problems, the present invention proposes a reusable dual-field multiplier design method and system. The present invention designs a prime field GF(p) and a binary extension field GF(2 m ) The Booth encoding on the dual domain, the dual domain partial product generation and the dual domain compression logic, combined with the sign extension bit preprocessing technology and the complement plus 1 bit optimization technology, can simultaneously support multiplication operations on the dual domain. Compared with the conventional dual domain multiplier implementation, it has the significant advantages of less resource occupation and higher performance.

[0018] The technical solution adopted by the present invention is as follows:

[0019] A reusable dual-domain multiplier design method, comprising:

[0020] Dual-field non-logical basis-4Booth coding: According to the binary extension field GF(2 m ), by introducing the domain control bit gfp_en and the non-logical auxiliary coding bit Z, a radix-4 Booth coding logic that supports both prime domain and binary extended domain complement operations and sign extension bits is set to expand the partial product generation under dual domains;

[0021] Dual-field partial product generation: generating a partial product array based on a dual-field non-logical base-4 Booth coded value, the partial product array including partial products generated by decoding logic, sign extension bit preprocessing generation parameters, and complement plus 1 bit optimization parameters;

[0022] Wallace tree compression: Based on the Wallace tree compression structure, the field control bit gfp_en is introduced to realize the prime field GF(p) and the binary extension field GF(2 m )'s dual domain compression;

[0023] Adder operation: After Wallace tree compression, two partial products are obtained and added together through an adder to obtain the final multiplication result.

[0024] Furthermore, in the dual-field partial product generation, the sign extension bit preprocessing includes: processing the sign bit extension array separately, the starting column of the sign extension bit is the 0th column, the odd bits of the array sum are equal to the 'OR' operation of the bits involved in the column, and the even bits are equal to the 'XOR' operation of the bit associated with the bit and the odd column of the lower bit.

[0025] Furthermore, in the dual-domain partial product generation, the two's complement plus 1 bit optimization includes: in the Booth-coded partial product generation, negative numbers are processed in the form of two's complement, that is, all the bits of the multiplicand are inverted and added by 1; the added 1 bit is adjusted to the next row of partial products that are aligned with the lowest bit of the current partial product, thereby reducing the generation logic of the partial products.

[0026] Furthermore, in the dual-field non-logical base-4 Booth encoding and Wallace tree compression, when the gfp_en signal is 1, it is a multiplication operation on the prime field GF(p); when the gfp_en signal is 0, it is a multiplication operation on the binary extended field GF(2 m ) on .

[0027] Furthermore, in the adder operation, the method for selecting the adder includes: selecting a corresponding addition structure according to the frequency and area requirements of the design, and the addition structure includes a serial carry adder and a carry look-ahead adder.

[0028] A reusable dual-domain multiplier system, comprising:

[0029] The dual-domain non-logical basis-4Booth encoding module is configured according to the binary extended domain GF(2 m ), by introducing the domain control bit gfp_en and the non-logical auxiliary coding bit Z, a radix-4 Booth coding logic that supports both prime domain and binary extended domain complement operations and sign extension bits is set to expand the partial product generation under dual domains;

[0030] a dual-field partial product generation module configured to generate a partial product array based on the dual-field non-logical base-4 Booth coded values, the partial product array comprising partial products generated by decoding logic, sign extension bit preprocessing generation parameters, and complement plus 1 bit optimization parameters;

[0031] The Wallace tree compression module is configured as a compressor based on the Wallace tree compression structure, and implements the prime field GF(p) and the binary extension field GF(2 m )'s dual domain compression;

[0032] The adder operation module is configured to obtain two partial products based on Wallace tree compression, and add them together through the adder to obtain the final multiplication result.

[0033] Furthermore, in the dual-field partial product generation module, the sign extension bit preprocessing includes: processing the sign bit extension array separately, the starting column of the sign extension bit is the 0th column, the odd bits of the array sum are equal to the 'OR' operation of the bits involved in the column, and the even bits are equal to the 'XOR' operation of the bits associated with the bit and the odd column of the lower one.

[0034] Furthermore, in the dual-domain partial product generation module, the two's complement plus 1 bit optimization includes: in the Booth-coded partial product generation, negative numbers are processed in the form of two's complement, that is, all the bits of the multiplicand are inverted and added by 1; the added 1 bit is adjusted to the next row of partial products that are aligned with the lowest bit of the current partial product, thereby reducing the generation logic of the partial products.

[0035] Furthermore, in the dual-field non-logical basis-4 Booth encoding module and the Wallace tree compression module, when the gfp_en signal is 1, it is a multiplication operation on the prime field GF(p); when the gfp_en signal is 0, it is a multiplication operation on the binary extension field GF(2 m ) on .

[0036] Furthermore, in the adder operation module, the method for selecting the adder includes: selecting a corresponding addition structure according to the frequency and area requirements of the design, and the addition structure includes a serial carry adder and a carry look-ahead adder.

[0037] The beneficial effects of the present invention are:

[0038] The present invention aims at supporting both prime field GF(p) and binary extension field GF(2 m ) multiplication and modular multiplication, a reusable dual-field multiplier based on non-logical radix-4 Booth coding is designed to realize the prime field GF(p) and the binary extension field GF(2 m ) The Booth encoding on the dual domain, the dual domain partial product generation and the dual domain compression logic, combined with the sign extension bit preprocessing technology and the complement plus 1 bit optimization technology, can simultaneously support multiplication operations on the dual domain. Compared with the conventional dual domain multiplier implementation, it has the significant advantages of less resource occupation and higher performance.

[0039] 1. Support multiplication operations on dual fields

[0040] The present invention introduces the domain control bit gfp_en, which can support both the prime domain GF(p) and the binary extension domain GF(2 m ). When gfp_en is high, it is a multiplication operation on the prime field GF(p). When gfp_en is low, it is a multiplication operation on the binary extension field GF(2 m In terms of circuit design, the two share a set of hardware logic, which not only saves hardware resources but also has the flexibility of dual-domain use.

[0041] 2. Less resource usage and high performance

[0042] In the implementation of dual-field multiplier, based on the idea of ​​Booth coding to reduce partial products, a non-logical radix-4 Booth coding algorithm is designed to support the generation of partial products of dual fields. Combining dual-field compression logic, sign extension bit preprocessing technology and complement plus 1 bit optimization technology, the multiplier supports prime field GF(p) and binary extension field GF(2 m ), compared with the conventional dual-domain multiplier, it can effectively reduce the hardware implementation area while maintaining higher performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 The figure is a flow chart of the design method of the reusable dual-domain multiplier of the present invention.

[0044] Figure 2 Schematic diagram of the partial product array after 8x8-bit multiplication sign extension bit preprocessing.

[0045] Figure 3 Schematic diagram of the partial product array after complement bit optimization.

[0046] Figure 4 Schematic diagram of the area of ​​a dual-field non-logical base-4 Booth coded multiplier.

[0047] Figure 5 This is a schematic diagram of the area of ​​a conventional dual-domain multiplier. DETAILED DESCRIPTION

[0048] In order to have a clearer understanding of the technical features, purposes and effects of the present invention, the specific implementation methods of the present invention are now described. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention, that is, the embodiments described are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present invention.

[0049] Example 1

[0050] like Figure 1 As shown, this embodiment provides a reusable dual-domain multiplier design method, including:

[0051] Dual-field non-logical basis-4Booth coding: According to the binary extension field GF(2 m ), by introducing the domain control bit gfp_en and the non-logical auxiliary coding bit Z, a radix-4 Booth coding logic that supports both prime domain and binary extended domain complement operations and sign extension bits is set to expand the partial product generation under dual domains;

[0052] Dual-field partial product generation: generating a partial product array based on a dual-field non-logical base-4 Booth coded value, the partial product array including partial products generated by decoding logic, sign extension bit preprocessing generation parameters, and complement plus 1 bit optimization parameters;

[0053] Wallace tree compression: Based on the Wallace tree compression structure, the field control bit gfp_en is introduced to realize the prime field GF(p) and the binary extension field GF(2 m )'s dual domain compression;

[0054] Adder operation: After Wallace tree compression, two partial products are obtained and added together through an adder to obtain the final multiplication result.

[0055] Specifically, the dual-domain multiplier design method of this embodiment can be implemented by the following steps:

[0056] 1. Dual-domain non-logical base-4Booth encoding

[0057] Elliptic curve encryption algorithms are usually defined on two finite fields: the prime field GF(p) and the binary extension field GF(2 m ). Among them, GF(2 m ) domain can be represented by polynomials, and its addition and subtraction are binary XOR, and no carry signal is generated; compared with the GF(p) domain, it can be found that the addition and subtraction of the prime domain is also an XOR circuit, and carry and borrow will be generated according to the situation. Improvements on the traditional multiplier can realize GF(2 m ) domain multiplier, thereby forming a dual-domain multiplier.

[0058] Since GF(2 m ) domain operation is special. The addition operation of the domain is a bitwise XOR operation, so the summation of the partial products is completed by XOR operation. In addition, GF(2 m ) domain multiplication does not involve the operation of the sign bit, so the sign bit does not need to be considered when encoding. m ) domain, the partial product generation circuit is adjusted accordingly to enable it to support both GF(p) and GF(2 m ) domain, a unified non-logical base-4 Booth encoding method is used to implement the multiplication operation of the dual domain. The specific encoding method is as follows, where the gfp_en signal is 1 for GF(p) domain and 0 for GF(2 m )domain.

[0059] Table 2 Dual-domain non-logical base-4 Booth encoding

[0060]

[0061]

[0062] The logical expression corresponding to the dual-domain non-logical base-4Booth encoding value is as follows:

[0063] NEG=(b 2i+1 &~(b 2i &b 2i-1 )&gfp_en)|(b 2i+1 &(b 2i |gfp_en))

[0064] B1=(b 2i-1 &gfp_en)⊙b 2i

[0065]

[0066] Z=~(b 2i+1 |b 2i )|(b2i+1 &b 2i &gfp_en)

[0067] 2. Dual-domain partial product generation

[0068] Based on the dual-field non-logical base-4 Booth coded value, the final generated partial product array consists of three parts: the partial product generated by the decoding logic, the sign extension bit preprocessing generation parameter, and the complement plus 1 bit parameter.

[0069] (1) Partial Product Decoding Logic

[0070] According to the control signal of the encoding logic, the decoding circuit is designed to generate the partial product under the dual domain. The corresponding partial product bit generation logic is as follows:

[0071]

[0072] (2) Sign extension bit preprocessing

[0073] The accumulation operation of the partial products after Booth coding is a signed number operation, so the data in the partial products are in the form of complement. In the addition operation of the partial products, the extended sign bit consumes some hardware resources. The use of sign extension bit preprocessing technology can effectively solve the sign bit extension array problem.

[0074] The sign bit extension array is processed separately. The starting column of the sign extension bit is column 0. The odd bits of the array sum are equal to the 'OR' operation of the bits involved in the column, and the even bits are equal to the 'XOR' operation of the bits associated with the bit and the odd columns with the lower one. Let ri represent the accumulated sum of the sign bit array, sign[i] is the sign bit of the partial product corresponding to each row, i = 0, 1, 2, ..., then And so on.

[0075] To illustrate with 8x8 bit multiplication: r0~r6 are the accumulated sum of the sign bit array, L0~L3 represent the 0th to 3rd rows of the array, and the partial product array after preprocessing is as follows Figure 2 shown.

[0076] After preprocessing, the setting of the sign extension bit can be effectively reduced, and the hardware implementation resources can be reduced. When the multiplier bit width is larger, the reduction is greater and the effect is better.

[0077] (3) Optimization of adding 1 bit to the complement code

[0078] In the partial product generation of Booth coding, negative numbers are processed in the form of complement, that is, all the bits of the multiplicand are inverted and added. If the addition operation is performed immediately after the multiplicand is inverted, it will increase the delay and resources of the partial product generation, thereby affecting the speed and area of ​​the entire multiplication. The addition bit can be adjusted to the next row of partial products that are aligned with the lowest bit of the partial product, reducing the logic of partial product generation. Figure 3 As shown, rc0 is the L0 row partial product plus 1 bit, adjusted to the L1 row partial product, rc1 is the L2 row partial product plus 1 bit, adjusted to the L2 row partial product, and so on.

[0079] 3. Wallace tree compression

[0080] Booth coding reduces the number of partial product terms of the multiplier, and the tree compressor reduces the number of cascaded adder stages. When the number of partial product terms of the multiplier is constant, the delay of the multiplier is mainly caused by the cascade of the compressor. The core of the Wallace tree compression structure is the compressor. Common ones include the 3-2 compressor, namely the carry save adder CSA (Carry Save Adder) and the 4-2 compressor with a compression ratio of two to one. Based on the traditional 3-2 compressor and 4-2 compressor, the gfp_en field control bit is introduced to support GF(p) and GF(2 m )Compression of dual domains.

[0081] (1) Dual-domain 4-2 compressor

[0082] The function of the 4-2 compressor is to compress 4 inputs into two outputs, thereby speeding up the operation. Combined with the gfp_en control bit, its logical expression is as follows, where a, b, c, d are data inputs, WIDTH is the data bit width, s is the sum, and co is the carry.

[0083]

[0084] ti={ti1[WIDTH-2:0],1'b0}

[0085]

[0086]

[0087] co=gfp_en&{co1[WIDTH-2:0],1'b0}

[0088] (2) Dual-domain 3-2 compressor

[0089]

[0090]

[0091] co=gfp_en&{co1[WIDTH-2:0],1'b0}

[0092] 4. Adder

[0093] After tree compression, two partial products are obtained, which are added by an adder to obtain the final multiplication result. In the selection of adders, an addition structure such as a serial carry adder and a carry lookahead adder can be selected according to the frequency and area requirements of the specific design.

[0094] More specifically, this embodiment takes a 64x64 bit dual-domain multiplier as an example, adopts a chip 28nm process library, and uses Synopsys's DC (Design Complier) logic synthesis tool to evaluate the multiplier area and frequency. Under the frequency constraint of 1GHz, the dual-domain non-logic base-4 Booth coded multiplier area of ​​this embodiment is about 13257um 2 ,like Figure 4 As shown; the area of ​​a conventional dual-domain multiplier is about 15533um 2 ,like Figure 5 As shown, it can be seen that the design of the present invention effectively reduces the multiplier area by about 15% while having high performance.

[0095] Example 2

[0096] This embodiment provides a reusable dual-domain multiplier system, including:

[0097] The dual-field non-logical basis-4Booth encoding module is configured according to the binary extended field GF(2 m ), by introducing the domain control bit gfp_en and the non-logical auxiliary coding bit Z, a radix-4 Booth coding logic that supports both prime domain and binary extended domain complement operations and sign extension bits is set to expand the partial product generation under dual domains;

[0098] a dual-field partial product generation module configured to generate a partial product array based on the dual-field non-logical base-4 Booth coded values, the partial product array comprising partial products generated by decoding logic, sign extension bit preprocessing generation parameters, and complement plus 1 bit optimization parameters;

[0099] The Wallace tree compression module is configured as a compressor based on the Wallace tree compression structure, and implements the prime field GF(p) and the binary extension field GF(2 m )'s dual domain compression;

[0100] The adder operation module is configured to obtain two partial products based on Wallace tree compression, and add them together through the adder to obtain the final multiplication result.

[0101] Preferably, in the dual-field partial product generation module, the sign extension bit preprocessing includes: processing the sign bit extension array separately, the starting column of the sign extension bit is the 0th column, the odd bits of the array sum are equal to the 'OR' operation of the bits involved in the column, and the even bits are equal to the 'XOR' operation of the bits associated with the bit and the odd column of the lower one.

[0102] Preferably, in the dual-domain partial product generation module, the two's complement plus 1 bit optimization includes: in the Booth-coded partial product generation, negative numbers are processed in the form of two's complement, that is, all the bits of the multiplicand are inverted and added by 1; the added 1 bit is adjusted to the next row of partial products that are aligned with the lowest bit of the current partial product, thereby reducing the generation logic of the partial products.

[0103] Preferably, in the dual-field non-logical base-4 Booth encoding module and the Wallace tree compression module, when the gfp_en signal is 1, it is a multiplication operation on the prime field GF(p); when the gfp_en signal is 0, it is a multiplication operation on the binary extension field GF(2 m ) on .

[0104] Preferably, in the adder operation module, the method for selecting the adder includes: selecting a corresponding addition structure according to the frequency and area requirements of the design, and the addition structure includes a serial carry adder and a carry look-ahead adder.

[0105] Example 3

[0106] This embodiment is based on embodiment 1:

[0107] This embodiment provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the steps of the reusable dual-domain multiplier design method of Embodiment 1 are implemented. The computer program may be in source code form, object code form, executable file, or some intermediate form.

[0108] Example 4

[0109] This embodiment is based on embodiment 1:

[0110] This embodiment provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the reusable dual-domain multiplier design method of Embodiment 1. The computer program may be in source code form, object code form, executable file, or some intermediate form. The storage medium includes: any entity or device capable of carrying computer program code, recording medium, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signal, telecommunication signal, and software distribution medium. It should be noted that the content contained in the storage medium may be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, the storage medium does not include electric carrier signals and telecommunication signals.

[0111] It should be noted that, for the aforementioned method embodiments, for the sake of simplicity of description, they are expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the order of the actions described, because according to the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

Claims

1. A method for designing a reusable dual-domain multiplier, characterized in that: include: Dual-field non-logical basis-4Booth coding: According to the binary extension field GF(2 m ), by introducing the domain control bit gfp_en and the non-logical auxiliary coding bit Z, a radix-4 Booth coding logic that supports both prime domain and binary extended domain complement operations and sign extension bits is set to expand the partial product generation under dual domains; Dual-field partial product generation: generating a partial product array based on a dual-field non-logical base-4 Booth coded value, the partial product array including partial products generated by decoding logic, sign extension bit preprocessing generation parameters, and complement plus 1 bit optimization parameters; Wallace tree compression: Based on the compressor of Wallace tree compression structure, by introducing the field control bit gfp_en, the prime field GF(p) and the binary extension field GF(2 m )'s dual-domain compression; Adder operation: After compression based on the Wallace tree, two partial products are obtained and added together through the adder to obtain the final multiplication result.

2. The method for designing a reusable dual-domain multiplier according to claim 1, characterized in that: In the dual-field partial product generation, the sign extension bit preprocessing includes: processing the sign bit extension array separately, the starting column of the sign extension bit is the 0th column, the odd bits of the array sum are equal to the 'OR' operation of the bits involved in the column, and the even bits are equal to the 'XOR' operation of the bits associated with the bit and the odd column of the lower one.

3. The method for designing a reusable dual-domain multiplier according to claim 1, characterized in that: In the dual-domain partial product generation, the optimization of the complement plus 1 bit includes: in the Booth-coded partial product generation, negative numbers are processed in the form of complement, that is, all the bits of the multiplicand are inverted and added by 1; the added 1 bit is adjusted to the next row of partial products that are aligned with the lowest bit of the current partial product, thereby reducing the generation logic of the partial products.

4. The method for designing a reusable dual-domain multiplier according to claim 1, wherein: In the dual-field non-logical base-4 Booth encoding and Wallace tree compression, when the gfp_en signal is 1, it is a multiplication operation on the prime field GF(p); when the gfp_en signal is 0, it is a multiplication operation on the binary extended field GF(2 m ) on .

5. The method for designing a reusable dual-domain multiplier according to claim 1, characterized in that: In the adder operation, the method for selecting the adder includes: selecting a corresponding addition structure according to the frequency and area requirements of the design requirements, and the addition structure includes a serial carry adder and a carry look-ahead adder.

6. A reusable dual-domain multiplier system, characterized in that: include: The dual-domain non-logical basis-4Booth encoding module is configured according to the binary extended domain GF(2 m ), by introducing the domain control bit gfp_en and the non-logical auxiliary coding bit Z, a radix-4 Booth coding logic that supports both prime domain and binary extended domain complement operations and sign extension bits is set to expand the partial product generation under dual domains; a dual-field partial product generation module configured to generate a partial product array based on the dual-field non-logical base-4 Booth coded values, the partial product array comprising partial products generated by decoding logic, sign extension bit preprocessing generation parameters, and complement plus 1 bit optimization parameters; The Wallace tree compression module is configured to implement the prime field GF(p) and the binary extension field GF(2 m )'s dual-domain compression; The adder operation module is configured to obtain two partial products based on Wallace tree compression, and add them together through the adder to obtain the final multiplication result.

7. A multiplexable dual-domain multiplier system according to claim 6, characterized in that: In the dual-field partial product generation module, the sign extension bit preprocessing includes: processing the sign bit extension array separately, the starting column of the sign extension bit is the 0th column, the odd bits of the array sum are equal to the 'OR' operation of the bits involved in the column, and the even bits are equal to the 'XOR' operation of the bits associated with the bit and the odd column of the lower one.

8. The multiplexable dual-domain multiplier system according to claim 6, characterized in that: In the dual-domain partial product generation module, the two's complement plus 1 bit optimization includes: in the Booth-coded partial product generation, negative numbers are processed in the form of two's complement, that is, all the bits of the multiplicand are inverted and added by 1; the added 1 bit is adjusted to the next row of partial products that are aligned with the lowest bit of the current partial product, thereby reducing the generation logic of the partial products.

9. The multiplexable dual-domain multiplier system according to claim 6, characterized in that: In the dual-field non-logical base-4 Booth encoding module and the Wallace tree compression module, when the gfp_en signal is 1, it is a multiplication operation on the prime field GF(p); when the gfp_en signal is 0, it is a multiplication operation on the binary extension field GF(2 m ) on .

10. The multiplexable dual-domain multiplier system according to claim 6, characterized in that: In the adder operation module, the method for selecting the adder includes: selecting a corresponding addition structure according to the frequency and area requirements of the design requirements, and the addition structure includes a serial carry adder and a carry look-ahead adder.

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