Reset circuit, chip and reset method

Abstract

The invention discloses a reset circuit, a chip and a reset method, the reset circuit comprises a reset control unit and an arithmetic unit, the reset control unit generates a trigger value based on an initial value, a first input end of the arithmetic unit is used for receiving a control signal, and a second input end of the arithmetic unit is connected with an output end of the reset control unit to receive the trigger value; the arithmetic unit generates a reset signal based on the control signal and the trigger value to reset at least part of the registers to be reset. According to the reset circuit, the chip and the reset method, the reset level of the control signal can be improved through the reset control unit and the arithmetic unit, and when all registers need to be reset, the circuit function can be restarted without power failure, so that other items can be continuously tested without power failure after scan test is finished, and the test efficiency is improved. And the chip can be reset without power failure in the normal working process of the chip, so that the re-power-on time is saved, and a power failure restarting method in special environments (such as high and low temperatures) does not need to be considered.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a reset circuit, a chip and a reset method. Background Art

[0002] MCU chip testing includes digital scan testing (a testing method used to detect faults in digital integrated circuits), memory bist testing (built-in self-test), flash testing (memory testing) and analog testing. During the testing process, it is necessary to switch between various modes in a cycle.

[0003] Among them, generally after the digital scan test, the value of the digital register in the chip will change. After exiting the scan mode, the MCU chip cannot work normally. All digital registers need to be restored to the reset value to ensure the correct progress of other tests, while the system reset signal can only reset some registers.

[0004] The general method for resetting all registers is to power on the MCU chip again after the digital scan test. On the one hand, this method will take a certain amount of time to power on again, which will increase the test time. On the other hand, power failure also requires additional control, which will increase the complexity of the test.

[0005] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the invention

[0006] The object of the present invention is to provide a reset circuit, a chip and a reset method, which can reset all registers without power failure after a digital scan test and during normal operation of the chip.

[0007] In order to achieve the above-mentioned purpose, a specific embodiment of the present invention provides a reset circuit, including: a reset control unit and an operation unit, wherein the reset control unit generates a trigger value based on an initial value, a first input end of the operation unit is used to receive a control signal, a second input end of the operation unit is connected to an output end of the reset control unit to receive the trigger value, and the operation unit generates a reset signal based on the control signal and the trigger value to reset at least part of the register to be reset.

[0008] In one or more embodiments of the present invention, the reset circuit further includes an assignment unit, an output end of the assignment unit is connected to an input end of the reset control unit, and the assignment unit is used to provide an initial value to the reset control unit.

[0009] In one or more embodiments of the present invention, the value assignment unit includes one or more trigger units, the trigger units are serially connected to a reset control unit, and the trigger units generate initial values ​​based on input signals.

[0010] In one or more embodiments of the present invention, the value assignment unit includes a memory and a digital circuit, the memory is used to store the signal configuration value, and the digital circuit is used to digitally process the signal configuration value to generate an initial value.

[0011] In one or more embodiments of the present invention, the reset control unit includes a reset register, an input end of the reset register is used to receive an initial value, and an output end of the reset register is used to output a trigger value; or

[0012] The reset control unit includes a reset register and a selector, the output end of the selector is connected to the input end of the reset register, the first input end of the selector or the second input end of the selector is used to receive an initial value, and the output end of the reset register is used to output a trigger value.

[0013] In one or more embodiments of the present invention, the operation unit includes a first logic unit, a first input end of the first logic unit is used to receive a control signal, a second input end of the first logic unit is used to receive a trigger value, and an output end of the first logic unit is used to output a reset signal; or

[0014] The operation unit includes a first logic unit and a second logic unit, the first input end of the first logic unit is used to receive a control signal, the second input end of the first logic unit is connected to the output end of the reset control unit to receive a trigger value, the first input end of the second logic unit is connected to the output end of the first logic unit, the second input end of the second logic unit is used to receive a power-on reset signal, and the output end of the second logic unit is used to output a reset signal.

[0015] In one or more embodiments of the present invention, the operation unit also includes a third logic unit, an input end of the third logic unit is connected to the output end of the reset control unit to receive a trigger value, the output end of the third logic unit is connected to the second input end of the first logic unit, and the first input end of the first logic unit is used to receive a control signal.

[0016] In one or more embodiments of the present invention, the control signal is a system reset signal to control some registers to reset.

[0017] The present invention also discloses a chip, comprising one or more trigger units and the reset circuit, wherein the trigger unit comprises a selector and a register, wherein the output end of the selector is connected to the input end of the register, the output end of the register of each trigger unit is connected to the first input end of the selector of the downstream trigger unit, the second input end of the selector of each trigger unit is used to receive a selection signal, the control end of the selector of each trigger unit is used to receive a selection control signal, the first input end of the selector of the trigger unit located at the head end is used to receive an input signal, the reset end of each register is connected to the output end of the reset circuit to receive a reset signal, and the reset circuit is serially connected to the trigger unit.

[0018] The present invention also discloses a reset method for resetting each register to be reset. Based on the reset circuit, the reset method includes:

[0019] generating a trigger value based on the initial value by resetting the control unit;

[0020] A reset signal is generated by the operation unit based on the control signal and the trigger value to reset at least part of the registers to be reset.

[0021] Compared with the prior art, the reset circuit, chip and reset method of the present invention can improve the reset level of the control signal through the reset control unit and the operation unit. When all registers need to be reset, the circuit function can be restarted without powering off, so that other items can be tested without powering off after the scan test, and the chip can be reset without powering off during normal operation, saving the time of powering on again and eliminating the need to consider the power-off restart method in special environments (such as high and low temperatures). BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0023] Figure 1 This is a circuit schematic diagram of a chip with a reset circuit in Embodiment 1.

[0024] Figure 2 4 is a circuit schematic diagram of the reset circuit in the first embodiment.

[0025] Figure 3 This is a circuit schematic diagram of the value assignment unit in the second embodiment. DETAILED DESCRIPTION

[0026] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0027] "Coupled" or "connected" or "connected" in the specification includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrically conductive medium, which may have parasitic inductance or parasitic capacitance; indirect connection may also include connection through other active or passive devices on the basis of achieving the same or similar functional purposes, such as connection through circuits or components such as switches and follower circuits. In addition, in the invention, words such as "first" and "second" are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply that there is a certain actual relationship, quantity or order between these technical features.

[0028] In the detailed description of the specification, reference is made to the accompanying drawings forming a part thereof, wherein like reference numerals refer to like parts throughout, and wherein are shown by way of exemplary embodiments that may be implemented. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be considered in a limiting sense.

[0029] The various operations in the specification may be described in turn as multiple discrete actions or operations in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be interpreted as implying that these operations must be order-dependent. Specifically, these operations may not be performed in the order presented. The described operations may be performed in an order different from the described embodiments. Various additional operations may be performed and / or the described operations may be omitted in additional embodiments.

[0030] For purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0031] Various components and devices may be referred to or shown in the singular form herein (e.g., "transistor," "transistor," "switch," etc.), but this is merely for ease of discussion, and any element referred to in the singular form may include multiple such elements in accordance with the teachings herein.

[0032] The specification describes the use of the phrases "in one embodiment" or "in other embodiments" or "in some embodiments", which may each refer to one or more of the same or different embodiments. In addition, the terms "including", "comprising", "having", etc. used in relation to the embodiments of the present disclosure are synonymous.

[0033] Example 1

[0034] like Figure 1 As shown, a reset circuit in an embodiment of the present invention includes: a reset control unit 10 and an operation unit 20.

[0035] In one embodiment, the digital scan test is a fault detection method for digital integrated circuits. It builds a scan chain to connect multiple trigger units in the chip in series. Each trigger unit includes a register and a selector. The multiple trigger units include registers D1, D2~Dn and selectors S1, S2~Sn. The registers D1, D2~Dn are connected in series through the corresponding selectors S1, S2~Sn (e.g. Figure 1 As shown), the states of these registers D1, D2~Dn can be easily controlled and observed.

[0036] Specifically, the first input end of the selector S1 of the trigger unit located at the head end is used to receive the input signal scan_in, the output end of each selector S1, S2~Sn is connected to the input end of the corresponding register D1, D2~Dn, the output end of the register of each trigger unit is connected to the first input end of the selector of the downstream trigger unit (such as the output end of the register D1 is connected to the first input end of the downstream selector S2), the second input end of the selector S1, S2~Sn of each trigger unit is used to receive the corresponding selection signal, the control end of the selector S1, S2~Sn of each trigger unit is used to receive the selection control signal shift_enable, and the clock end of each register D1, D2~Dn is used to receive the clock signal clock.

[0037] A reset control unit 10 is provided, and the reset control unit 10 is connected in series with the trigger unit. The reset end of each register D1, D2 to Dn is connected to the output end of the reset circuit.

[0038] The reset control unit 10 can be connected in series between two trigger units, or in series at the end of the circuit. The position of the reset control unit 10 can be adjusted as needed. The reset object of the reset circuit is registers D1, D2~Dn. During the digital Scan test, the control signal shift_enable is selected to control the selectors S1, S2~Sn, so that the input end of each register D1, D2~Dn receives the signal from the first input end of the corresponding selector S1, S2~Sn, and serial communication is realized.

[0039] The reset control unit 10 generates a trigger value DK based on the initial value, the first input end of the operation unit 20 is used to receive the control signal re, the second input end of the operation unit 20 is connected to the output end of the reset control unit 10 to receive the trigger value DK, and the operation unit 20 generates a reset signal reset based on the control signal re and the trigger value DK to reset at least part of the registers to be reset. In one embodiment, the reset signal reset is transmitted to the reset ends of all registers D1, D2~Dn, so that all registers D1, D2~Dn can be reset.

[0040] like Figure 1 As shown, the reset control unit 10 includes a reset register level_reg and a selector SK. The reset control unit 10 has a similar structure to the trigger unit, so that it can be better connected in series with the trigger unit for serial communication. The first input end of the selector SK is connected to the output end of the register of the upstream trigger unit to receive the initial value, the second input end of the selector SK is used to receive the selection signal, the control end of the selector SK is used to receive the selection control signal shift_enable, the output end of the selector SK is connected to the input end of the reset register level_reg, the clock end of the reset register level_reg is used to receive the clock signal clock, and the output end of the reset register level_reg is used to output the trigger value DK. In other embodiments, the selector SK may not be set.

[0041] like Figure 2 As shown, the operation unit 20 includes a first logic unit OR, a second logic unit AND and a third logic unit N.

[0042] The first input end of the first logic unit OR is used to receive the control signal re, the input end of the third logic unit N is connected to the output end of the reset register level_reg of the reset control unit 10 to receive the trigger value DK, the second input end of the first logic unit OR is connected to the output end of the third logic unit N, the first input end of the second logic unit AND is connected to the output end of the first logic unit OR, the second input end of the second logic unit AND is used to receive a power-on reset signal, and the output end of the second logic unit AND is used to output a reset signal reset.

[0043] In one embodiment, the first logic unit OR is an OR gate, the second logic unit AND is an AND gate, and the third logic unit N is a NOT gate. The control signal re is a system reset signal, which is correspondingly output by the reset port IO of the chip and can only reset some registers. The reset register level_reg is reset by the power-on reset signal, that is, the reset register level_reg is reset by the power-on reset signal only during the power-on phase. After the power-on is completed, the power-on reset signal is 1. In other embodiments, the control signal re can be other signals and output by the general port IO.

[0044] The input control signal re can be connected to the reset terminals of all registers D1, D2~Dn (except the reset register level_reg) through the control of the reset circuit. When the reset register level_reg outputs 1, the third logic unit N outputs 0, and a control signal re of 0 is input through the reset port IO, the first logic unit OR outputs 0, and the second logic unit AND outputs 0, which will reset all registers D1, D2~Dn except the reset register level_reg.

[0045] The specific implementation method includes, after all scan mode tests of the digital Scan test are completed, using the serial communication scan structure constructed by registers D1, D2~ and selectors S1, S2~, the trigger value DK output by the reset register level_reg can be set to 1 through the input signal scan_in.

[0046] It can be seen that at least part of the scan chain constructed by the digital Scan test constitutes the assignment unit, that is, the reset circuit and the scan chain constructed by the digital Scan test share at least part of the scan chain, and the shared scan chain constitutes the assignment unit. The trigger unit of the assignment unit located upstream of the reset control unit 10 provides an initial value to the input end of the reset control unit 10 by setting the corresponding input signal scan_in and coordinating the clock signal clock. The position of the reset control unit 10 determines the number of trigger units located upstream of the reset control unit 10. Of course, in other embodiments, the reset control unit 10 can also be set as the first one. In this case, the assignment unit can be a circuit that generates the input signal scan_in, or a register can be set separately as an assignment unit to provide an initial value to the input end of the reset control unit 10.

[0047] After the digital Scan test is completed, if a reset is required, a valid control signal re (in one embodiment, a low level is valid) is input through the reset port IO. Since the trigger value DK is 1, the reset signal reset output by the second logic unit AND is finally 0, so there is no need to power off. All registers D1, D2~Dn can be restored to the power-on restart state by giving a low-level control signal re through the reset port IO.

[0048] As can be seen from the above, since the registers can be reset only when the level is low, in order to realize the power-on reset stage, the power-on reset signal can reset all the registers D1, D2~Dn. After the power-on is completed, when all the registers D1, D2~Dn need to be reset, when the control signal re is 0, the control signal re can be transmitted to all the registers D1, D2~Dn, and when all the registers D1, D2~Dn do not need to be reset, some registers can also be reset by the control signal re, so the operation circuit 20 composed of the first logic unit OR, the second logic unit AND and the third logic unit N is reasonably set.

[0049] In one embodiment, only when the trigger value DK is 1, can the effective control signal re be transmitted to all registers D1, D2 to Dn. In other embodiments, the structure of the operation circuit 20 can also be changed as needed. For example, when the trigger value DK is 0, the third logic unit N may not be set, and when the power-on reset signal is not required, the second logic unit AND may not be set. Of course, there are many kinds of digital logic circuits, which will not be described here, as long as the purpose is achieved.

[0050] This embodiment also discloses a chip, comprising one or more trigger units connected in series, a reset control unit 10 and an operation unit 20. The trigger unit is connected in series with the reset control unit 10.

[0051] This embodiment also discloses a reset method for resetting each register to be reset after the digital Scan test is completed. Based on the above reset circuit, the reset method includes:

[0052] The initial value is provided to the reset control unit 10 by the value assignment unit. In one embodiment, the value assignment unit is formed by at least a part of the scan chain used for the digital Scan test construction.

[0053] The trigger value DK is generated by resetting the control unit 10 based on the initial value.

[0054] The operation unit 20 generates a reset signal reset based on the control signal re and the trigger value DK to reset at least part of the registers to be reset.

[0055] For detailed reset method, please refer to the description of the above circuit.

[0056] Example 2

[0057] In the first embodiment, after the digital Scan test, the existing scan chain composed of trigger units is used as the assignment unit to set the trigger value DK of the reset control unit 10. Figure 1 As shown, the trigger value DK is set by additionally setting a value assignment unit 30 .

[0058] The output end of the assignment unit 30 is connected to the second input end of the selector SK of the reset control unit 10. The assignment unit 30 is used to provide an initial value to the reset control unit 10. The usage scenario of the assignment unit 30 is mainly for the reset requirements when the chip is working normally. Of course, it can also be used for the reset requirements after the digital Scan test.

[0059] Specific as Figure 2 As shown, the assignment unit 30 includes a memory flash and a digital circuit, the memory flash is used to store the signal configuration value, and the digital circuit is used to digitally process the signal configuration value to generate an initial value. The output end of the digital circuit is connected to the second input end of the selector SK. If the selector SK is not set, the output end of the digital circuit is connected to the input end of the reset register level_reg.

[0060] In one embodiment, during the power-on process, the digital circuit will enter normal initialization. During the initialization process, the digital circuit will load an initial value into the reset register level_reg to set the trigger value DK.

[0061] During user use, the signal configuration value can be configured as needed to determine the initial value. For example, if only some registers need to be reset, the trigger value DK can be set to 0 by configuring the signal configuration value. If all registers D1, D2~Dn need to be reset, the trigger value DK can be set to 1 by configuring the signal configuration value. The specific reset control principle performed by the operation unit 20 can be referred to Example 1, and will not be repeated here.

[0062] In other embodiments, referring to the trigger units connected in series in Embodiment 1, several trigger units are set as assignment units, and the assignment units are connected to the second input terminal of the selector SK to provide an initial value for the reset register level_reg.

[0063] This embodiment also discloses a chip, comprising one or more trigger units and a reset circuit connected in series. The trigger unit and the reset circuit are connected in series.

[0064] This embodiment further discloses a reset method for resetting each register to be reset during normal operation of the chip. Based on the above reset circuit, the reset method includes:

[0065] The initial value is provided to the reset control unit 10 by the value assignment unit 30. In one embodiment, the structure of the value assignment unit 30 is as shown above.

[0066] The trigger value DK is generated by resetting the control unit 10 based on the initial value.

[0067] The operation unit 20 generates a reset signal reset based on the control signal re and the trigger value DK to reset at least part of the registers to be reset.

[0068] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0069] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A reset circuit, characterized in that: include: A reset control unit and an operation unit, wherein the reset control unit generates a trigger value based on an initial value, a first input end of the operation unit is used to receive a control signal, a second input end of the operation unit is connected to an output end of the reset control unit to receive the trigger value, and the operation unit generates a reset signal based on the control signal and the trigger value to reset at least part of the register to be reset.

2. The reset circuit according to claim 1, characterized in that: The reset circuit further comprises a value assignment unit, an output end of the value assignment unit is connected to an input end of the reset control unit, and the value assignment unit is used to provide an initial value to the reset control unit.

3. The reset circuit according to claim 2, characterized in that: The assignment unit includes one or more trigger units, the trigger units are serially connected to a reset control unit, and the trigger units generate initial values ​​based on input signals.

4. The reset circuit according to claim 2, characterized in that: The assignment unit includes a memory and a digital circuit, wherein the memory is used to store signal configuration values, and the digital circuit is used to digitally process the signal configuration values ​​to generate initial values.

5. The reset circuit according to claim 1, characterized in that: The reset control unit includes a reset register, an input end of the reset register is used to receive an initial value, and an output end of the reset register is used to output a trigger value; or The reset control unit includes a reset register and a selector, the output end of the selector is connected to the input end of the reset register, the first input end of the selector or the second input end of the selector is used to receive an initial value, and the output end of the reset register is used to output a trigger value.

6. The reset circuit according to claim 1, characterized in that: The operation unit includes a first logic unit, a first input end of the first logic unit is used to receive a control signal, a second input end of the first logic unit is used to receive a trigger value, and an output end of the first logic unit is used to output a reset signal; or The operation unit includes a first logic unit and a second logic unit, the first input end of the first logic unit is used to receive a control signal, the second input end of the first logic unit is connected to the output end of the reset control unit to receive a trigger value, the first input end of the second logic unit is connected to the output end of the first logic unit, the second input end of the second logic unit is used to receive a power-on reset signal, and the output end of the second logic unit is used to output a reset signal.

7. The reset circuit according to claim 6, characterized in that: The operation unit also includes a third logic unit, the input end of the third logic unit is connected to the output end of the reset control unit to receive the trigger value, the output end of the third logic unit is connected to the second input end of the first logic unit, and the first input end of the first logic unit is used to receive the control signal.

8. The reset circuit according to claim 1, characterized in that: The control signal is a system reset signal to control some registers to reset.

9. A chip, characterized in that: comprising one or more trigger units and a reset circuit as claimed in any one of claims 1 to 8, The trigger unit includes a selector and a register, the output end of the selector is connected to the input end of the register, the output end of the register of each trigger unit is connected to the first input end of the selector of the downstream trigger unit, the second input end of the selector of each trigger unit is used to receive a selection signal, the control end of the selector of each trigger unit is used to receive a selection control signal, the first input end of the selector of the trigger unit located at the head end is used to receive an input signal, the reset end of each register is connected to the output end of the reset circuit to receive a reset signal, and the reset circuit is serially connected to the trigger unit.

10. A resetting method, characterized in that: For resetting each register to be reset, based on the reset circuit according to any one of claims 1 to 9, the reset method comprises: generating a trigger value based on the initial value by resetting the control unit; A reset signal is generated by the operation unit based on the control signal and the trigger value to reset at least part of the registers to be reset.

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