Board-level fan-out packaging structure and preparation method thereof

Abstract

The invention discloses a board-level fan-out type packaging structure and a preparation method thereof, the board-level fan-out type packaging structure comprises a first passivation layer, a chip or a rimless device is inversely arranged on the first passivation layer, the chip or the rimless device and the first passivation layer are externally coated with a plastic packaging layer, a first rewiring layer is arranged on the first passivation layer, a rewiring structure is arranged on the first rewiring layer, and a second rewiring layer is arranged on the second passivation layer. And a ball grid array structure for external interconnection is arranged on the rewiring structure. According to the invention, the forming step of the first passivation layer is advanced before the flip mounting of the chip or the passive device, and the chip or the passive device is firmly fixed by using the adhesion of the first passivation layer, so that additional auxiliary adhesive materials or process steps such as dispensing in the prior art can be replaced, the offset problem of the chip or the passive device is solved, and the production efficiency is improved. And no new process step is introduced, the product production cycle is not influenced, the product yield is guaranteed, the cost is low, and the method is suitable for industrial popularization and application.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor packaging, and in particular relates to a board-level fan-out packaging structure and a preparation method thereof. Background Art

[0002] As an advanced packaging technology, board-level fan-out packaging technology has always been known for its cost advantage, and it has been continuously optimized, designed and improved in terms of process structure, process flow, etc., in order to further expand its scale economy advantage. At present, the mainstream fan-out packaging process includes but is not limited to wafer grinding, chip singulation, chip mounting, wafer / large board reorganization, insulation layer molding, redistribution layer molding, solder mask molding, metal pad molding and other steps. During the mounting process, chips or passive devices usually need to be fixed on a temporary bonding layer and then plastic-sealed for protection. During the plastic-sealing process, due to the influence of factors such as film flow impact, the mounted chips or passive devices often have drift problems, resulting in unacceptable yield loss in the later stage. In order to solve the drift problem of chips or passive devices, auxiliary methods such as dispensing are often used to strengthen the bonding strength between chips or passive devices and the underlying bonding layer to effectively resist the drift problem caused by plastic sealing, but this method requires additional processes and materials, which not only increases the cost, but also greatly prolongs the product packaging cycle. Summary of the invention

[0003] In order to solve the technical problems existing in the prior art, an object of the present invention is to provide a board-level fan-out packaging structure and a preparation method thereof.

[0004] In order to achieve the above purpose and the above technical effect, the technical solution adopted by the present invention is:

[0005] A board-level fan-out packaging structure includes a first passivation layer, a chip or a non-edge device is flip-chip placed on the first passivation layer and both are coated with a plastic layer on the outside, a first redistribution layer is arranged on the first passivation layer, a redistribution structure is arranged on the first redistribution layer, and a ball grid array structure for external interconnection is arranged on the redistribution structure.

[0006] Furthermore, a lead-out port is provided on a side of the first passivation layer away from the chip or the edgeless device, and a first redistribution layer is provided at the lead-out port.

[0007] Furthermore, the redistribution structure includes a second passivation layer, a second redistribution layer and a third passivation layer, and the second passivation layer, the second redistribution layer and the third passivation layer are sequentially arranged on the first redistribution layer.

[0008] Furthermore, a ball grid array structure for external interconnection is provided on the third passivation layer.

[0009] Furthermore, the third passivation layer forms a ball grid array structure for external interconnection through the metal pad layer.

[0010] The present invention also discloses a method for preparing a board-level fan-out packaging structure, comprising the following steps:

[0011] Step 1: prepare a temporary carrier, and apply a thermal bonding film or temporary bonding glue on the temporary carrier by slit coating, spin coating, spraying, etc.;

[0012] Step 2: forming a temporary bonding layer on the temporary carrier to temporarily fix the chip or passive device to be packaged;

[0013] Step 3: forming a first passivation layer on the temporary bonding layer;

[0014] Step 4: placing the chip or passive device flip-chip on the first passivation layer, with the signal pin of the chip or passive device in direct contact with the first passivation layer, and using the bonding effect of the first passivation layer to firmly fix the chip or passive device;

[0015] Step 5: Plastic-encapsulate the chip or the non-edge device and the first passivation layer as a whole to form a plastic-encapsulation layer;

[0016] Step 6: remove the temporary carrier and the temporary bonding layer, and form a lead-out port for signal interconnection on the first passivation layer, wherein the lead-out port corresponds to the position of the signal pin;

[0017] Step 7, forming a first redistribution layer at the lead-out port to lead the signal of the signal pin outward;

[0018] Step 8: forming a redistribution structure on the first redistribution layer;

[0019] Step nine: forming a ball grid array structure for external interconnection on the redistribution structure.

[0020] Furthermore, the thickness of the first passivation layer is 5 to 100 micrometers.

[0021] Further, in step eight, the redistribution structure includes a second passivation layer, a second redistribution layer and a third passivation layer;

[0022] The step of forming a redistribution structure on the first redistribution layer comprises:

[0023] Repeat step three to form a second passivation layer; repeat step seven to form a second redistribution layer; repeat step three again to form a third passivation layer, the second passivation layer is used to insulate and isolate the first redistribution layer and the second redistribution layer, and the third passivation layer is used to isolate the second redistribution layer and the subsequent metal pad layer.

[0024] Furthermore, in step nine, the step of forming a ball grid array structure for external interconnection on the redistribution structure includes:

[0025] Ball planting or printed solder paste reflow is directly performed on the third passivation layer to form a final ball grid array structure for external interconnection.

[0026] Furthermore, in step nine, the step of forming a ball grid array structure for external interconnection on the redistribution structure includes:

[0027] A metal pad layer is first formed on the third passivation layer, and then ball planting or printed solder paste reflow is performed on the metal pad layer to form a final ball grid array structure for external interconnection.

[0028] Compared with the prior art, the present invention has the following beneficial effects:

[0029] The present invention discloses a board-level fan-out packaging structure and a preparation method thereof, wherein the step of forming a first passivation layer is advanced to before flip-chip mounting of a chip or a passive device, and the chip or the passive device is firmly fixed by utilizing the adhesion of the first passivation layer, which can replace additional auxiliary adhesive materials or process steps such as glue dispensing in the prior art, and not only solves the problem of chip or passive device offset, but also does not introduce new process steps, does not affect the product production cycle, and the product yield is guaranteed, and the cost is low, so the structure is suitable for industrial promotion and use. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a structural schematic diagram of step 1 of the present invention;

[0031] Figure 2 It is a structural schematic diagram of step 2 of the present invention;

[0032] Figure 3 It is a structural schematic diagram of step three of the present invention;

[0033] Figure 4 It is a structural schematic diagram of step 4 of the present invention;

[0034] Figure 5 This is a schematic diagram of the structure of step five of the present invention;

[0035] Figure 6 This is a structural schematic diagram of step six of the present invention;

[0036] Figure 7 It is a schematic diagram of step seven of the present invention;

[0037] Figure 8 This is a schematic diagram of the structure of step eight of the present invention;

[0038] Fig. 9 This is a schematic diagram of the structure of step nine of embodiment 1 of the present invention;

[0039] Fig.10 This is a structural diagram of step nine of embodiment 2 of the present invention. DETAILED DESCRIPTION

[0040] The present invention is described in detail below so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more definite definition of the protection scope of the present invention.

[0041] A brief summary of one or more aspects is given below to provide a basic understanding of these aspects. This summary is not an exhaustive overview of all conceived aspects, and is neither intended to identify the key or critical elements of all aspects nor to define the scope of any or all aspects. Its only purpose is to give some concepts of one or more aspects in a simplified form as a prelude to a more detailed description that will be given later.

[0042] like Figure 1-10 As shown, the present invention discloses a board-level fan-out packaging structure, including a chip or a non-edge device 400, which is flipped and placed on a first passivation layer 300 and both are coated with a plastic packaging layer 500 on the outside, and a lead-out port 310 is opened on the first passivation layer 300, and a first redistribution layer 610 is arranged at the lead-out port 310 to lead out the signal of a signal pin 410 of the chip or non-edge device 400, and a second passivation layer 700, a second redistribution layer 900, and a third passivation layer 800 are sequentially arranged on the first redistribution layer 610, and a ball grid array structure 1000 that is ultimately interconnected to the outside is formed on the third passivation layer 800 with or without a metal pad layer 1100.

[0043] The present invention also discloses a method for preparing a board-level fan-out packaging structure, comprising the following steps:

[0044] Step 1: If Figure 1 As shown, a temporary carrier 100 is prepared, the size of which is larger than the required plastic packaging size, and a layer of thermal bonding film is attached to the temporary carrier 100 or a layer of temporary bonding glue is spread by slit coating, spin coating, spraying, etc., for subsequent fixing of the chip or passive device 400 to be packaged. The temporary carrier 100 can be any supportive carrier, such as a stainless steel carrier or other metal alloy carrier, a glass carrier, a copper clad plate, a high-temperature polymer plate, etc.;

[0045] Step 2: If Figure 2 As shown, a temporary bonding layer 200 is formed on the temporary carrier 100 to temporarily fix the chip or passive device 400 to be packaged. The forming method may be roller lamination, vacuum lamination, steel mesh screen printing, spraying, slit coating, etc., depending on the material. The temporary bonding layer 200 may be a film material with a certain adhesiveness, or may be a liquid or semi-solid glue with a certain fluidity, etc.;

[0046] Step 3: If Figure 3 As shown, a first passivation layer 300 is formed on the temporary bonding layer 200. The first passivation layer 300 includes but is not limited to a passivation photosensitive dry film, a passivation non-photosensitive dry film, a passivation resin, a passivation photosensitive photoresist, a passivation non-photosensitive photoresist, etc. The formation method can be vacuum lamination, roller lamination, steel mesh screen printing, spraying, slit coating, etc. The thickness of the first passivation layer 300 is 5 to 100 microns, which can be flexibly selected according to product needs;

[0047] Step 4: If Figure 4 As shown, the chip or passive device 400 is flipped and placed on the first passivation layer 300. The chip or passive device 400 has two opposite surfaces, and the active surface includes a signal pin 410. The so-called flip-chip is to place the signal pin 410 downward on the first passivation layer 300, and the two are in direct contact. Then, according to the different materials of the first passivation layer 300, selective baking is performed after the flip-chip process is completed to give full play to the bonding effect of the first passivation layer 300 and firmly fix the chip or passive device 400;

[0048] Step 5: If Figure 5 As shown, after the chip or passive device 400 is flip-chip placed on the first passivation layer 300, it is plastic-sealed as a whole to form a plastic-sealing layer 500. The plastic-sealing layer 500 fully or partially covers the entire temporary carrier 100 and encapsulates the chip or passive device 400;

[0049] Step 6: If Figure 6 As shown, the bonding effect of the temporary bonding layer 200 is released, the temporary carrier 100, the temporary bonding layer 200 and the thermal bonding film or temporary bonding glue are removed, the assembly after the bonding is released is turned over, and a lead-out port 310 for signal interconnection is formed on the first passivation layer 300. The lead-out port 310 corresponds to the position of the signal pin 410. According to the different materials of the first passivation layer 300, the lead-out port 310 can be formed by laser drilling, photolithography, physical mechanical processing, etc.;

[0050] Step 7: Figure 7 As shown, a first redistribution layer 610 is formed at the lead-out port 310 by sputtering a titanium copper seed layer or electroplating a copper seed layer, coating or laminating, exposure, development, and electroplating, for leading the signal of the signal pin 410 outward. The first redistribution layer 610 can be made of conductive metal materials or alloys such as metal copper and conductive silver paste;

[0051] Step 8: If Figure 8As shown, step 3 is repeated to form a second passivation layer 700; step 7 is repeated to form a second redistribution layer 900; and step 3 is repeated again to form a third passivation layer 800. The second passivation layer 700 is used to insulate and isolate the first redistribution layer 610 and the second redistribution layer 900. The third passivation layer 800 is used to isolate the second redistribution layer 900 and the subsequent metal pad layer 1100;

[0052] Step 9: If Fig. 9 As shown, ball planting or printed solder paste reflow is performed on the third passivation layer 800 to form a final ball grid array structure 1000 for external interconnection;

[0053] Or, if Fig.10 As shown, a metal pad layer 1100 is first formed on the third passivation layer 800 in the same manner as step seven, and then ball planting or printed solder paste reflow is performed on the metal pad layer 1100 to form a final ball grid array structure 1000 for external interconnection.

[0054] Example 1

[0055] like Figure 1-9 As shown, a board-level fan-out packaging structure includes a chip or a non-edge device 400, which is flipped and placed on a first passivation layer 300 and both are coated with a plastic packaging layer 500 on the outside, a lead-out port 310 is opened on the first passivation layer 300, and a first redistribution layer 610 is arranged at the lead-out port 310 to lead out the signal of the signal pin 410 of the chip or non-edge device 400, a second passivation layer 700, a second redistribution layer 900, and a third passivation layer 800 are sequentially arranged on the first redistribution layer 610, and a ball grid array structure 1000 that is ultimately interconnected to the outside is formed on the third passivation layer 800.

[0056] A method for preparing a board-level fan-out packaging structure comprises the following steps:

[0057] Step 1: If Figure 1 As shown, a temporary carrier 100 is prepared, the size of which is larger than the required plastic packaging size, and a layer of thermal bonding film is attached to the temporary carrier 100 for subsequent fixing of the chip or passive device 400 to be packaged. The temporary carrier 100 is a stainless steel carrier with support;

[0058] Step 2: If Figure 2 As shown, a temporary bonding layer 200 is formed on the temporary carrier 100 for temporarily fixing the chip or passive device 400 to be packaged. The formation method is roller lamination. The temporary bonding layer 200 is a film material with a certain adhesiveness, and an existing conventional product can be used;

[0059] Step 3: If Figure 3As shown, a first passivation layer 300 is formed on the temporary bonding layer 200. The first passivation layer 300 is a passivation photosensitive dry film formed by vacuum lamination. The thickness of the first passivation layer 300 is 10 microns.

[0060] Step 4: If Figure 4 As shown, the chip or passive device 400 is flipped and placed on the first passivation layer 300. The chip or passive device 400 has two opposite surfaces, and the active surface includes a signal pin 410. The so-called flip-chip is to place the signal pin 410 downward on the first passivation layer 300, and the two are in direct contact. Then, according to the different materials of the first passivation layer 300, selective baking is performed after the flip-chip process is completed. The existing technology can be used to give full play to the bonding effect of the first passivation layer 300 and firmly fix the chip or passive device 400;

[0061] Step 5: If Figure 5 As shown, after the chip or passive device 400 is flip-chip placed on the first passivation layer 300, it is plastic-sealed as a whole to form a plastic-sealing layer 500. The plastic-sealing layer 500 fully or partially covers the entire temporary carrier 100 and encapsulates the chip or passive device 400;

[0062] Step 6: If Figure 6 As shown, the bonding effect of the temporary bonding layer 200 is released, the temporary carrier 100, the temporary bonding layer 200, and the thermal bonding film are removed, and the assembly after the bonding is released is turned over, and a lead-out port 310 for signal interconnection is formed on the first passivation layer 300. The lead-out port 310 corresponds to the position of the signal pin 410. According to the different materials of the first passivation layer 300, the lead-out port 310 is formed by laser drilling;

[0063] Step 7: Figure 7 As shown, a first redistribution layer 610 is formed at the lead-out port 310 by sequentially sputtering a titanium copper seed layer, coating, exposure, development, and electroplating, for leading the signal of the signal pin 410 outward. The first redistribution layer 610 is made of metal copper;

[0064] Step 8: If Figure 8 As shown, step 3 is repeated to form a second passivation layer 700; step 7 is repeated to form a second redistribution layer 900; and step 3 is repeated again to form a third passivation layer 800. The second passivation layer 700 is used to insulate and isolate the first redistribution layer 610 and the second redistribution layer 900. The third passivation layer 800 is used to isolate the second redistribution layer 900 and the subsequent metal pad layer 1100;

[0065] Step 9: If Fig. 9 As shown, ball planting is performed on the third passivation layer 800 to form a ball grid array structure 1000 that is ultimately interconnected to the outside.

[0066] Example 2

[0067] like Figure 1-8 As shown in Figure 10, a board-level fan-out packaging structure includes a chip or a non-edge device 400, which is flipped and placed on a first passivation layer 300 and both are coated with a plastic packaging layer 500. A lead-out port 310 is opened on the first passivation layer 300, and a first redistribution layer 610 is arranged at the lead-out port 310 to lead out the signal of the signal pin 410 of the chip or non-edge device 400. A second passivation layer 700, a second redistribution layer 900, and a third passivation layer 800 are sequentially arranged on the first redistribution layer 610, and a ball grid array structure 1000 that is ultimately interconnected to the outside is formed through a metal pad layer 1100 on the third passivation layer 800.

[0068] A method for preparing a board-level fan-out packaging structure comprises the following steps:

[0069] Step 1: If Figure 1 As shown, a temporary carrier 100 is prepared, the size of which is larger than the required plastic packaging size, and a layer of thermal bonding film is attached to the temporary carrier 100 for subsequent fixing of the chip or passive device 400 to be packaged. The temporary carrier 100 is a stainless steel carrier with support;

[0070] Step 2: If Figure 2 As shown, a temporary bonding layer 200 is formed on the temporary carrier 100 to temporarily fix the chip or passive device 400 to be packaged. The forming method can be roller lamination, vacuum lamination, steel mesh screen printing, spraying, slit coating, etc. according to different materials. The temporary bonding layer 200 is a film material with certain adhesiveness;

[0071] Step 3: If Figure 3 As shown, a first passivation layer 300 is formed on the temporary bonding layer 200. The first passivation layer 300 includes but is not limited to a passivation photosensitive dry film, a passivation non-photosensitive dry film, a passivation resin, a passivation photosensitive photoresist, a passivation non-photosensitive photoresist, etc. The formation method can be vacuum lamination, roller lamination, steel mesh screen printing, spraying, slit coating, etc. The thickness of the first passivation layer 300 is 100 microns;

[0072] Step 4: If Figure 4 As shown, the chip or passive device 400 is flipped and placed on the first passivation layer 300. The chip or passive device 400 has two opposite surfaces, and the active surface includes a signal pin 410. The so-called flip-chip is to place the signal pin 410 downward on the first passivation layer 300, and the two are in direct contact. Then, according to the different materials of the first passivation layer 300, selective baking is performed after the flip-chip process is completed to give full play to the bonding effect of the first passivation layer 300 and firmly fix the chip or passive device 400;

[0073] Step 5: If Figure 5 As shown, after the chip or passive device 400 is flip-chip placed on the first passivation layer 300, it is plastic-sealed as a whole to form a plastic-sealing layer 500. The plastic-sealing layer 500 fully or partially covers the entire temporary carrier 100 and encapsulates the chip or passive device 400;

[0074] Step 6: If Figure 6 As shown, the bonding effect of the temporary bonding layer 200 is released, the temporary carrier 100, the temporary bonding layer 200, and the thermal bonding film are removed, and the assembly after the bonding is released is turned over, and a lead-out port 310 for signal interconnection is formed on the first passivation layer 300, and the lead-out port 310 corresponds to the position of the signal pin 410. According to the different materials of the first passivation layer 300, the lead-out port 310 can be formed by laser drilling, photolithography, physical mechanical processing, etc.;

[0075] Step 7: Figure 7 As shown, a first redistribution layer 610 is formed at the lead-out port 310 by sputtering a titanium copper seed layer or electroplating a copper seed layer, coating or laminating, exposure, development, and electroplating, for leading the signal of the signal pin 410 outward. The first redistribution layer 610 can be made of conductive metal materials or alloys such as metal copper and conductive silver paste;

[0076] Step 8: If Figure 8 As shown, step 3 is repeated to form a second passivation layer 700; step 7 is repeated to form a second redistribution layer 900; and step 3 is repeated again to form a third passivation layer 800. The second passivation layer 700 is used to insulate and isolate the first redistribution layer 610 and the second redistribution layer 900. The third passivation layer 800 is used to isolate the second redistribution layer 900 and the subsequent metal pad layer 1100;

[0077] Step 9: If Fig.10 As shown, a metal pad layer 1100 is first formed on the third passivation layer 800 in the same manner as step seven, and then balls are planted on the metal pad layer 1100 to form a final ball grid array structure 1000 for external interconnection.

[0078] The rest is the same as in Example 1.

[0079] Parts or structures not specifically described in the present invention may adopt existing technologies or existing products and will not be described in detail here.

[0080] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A board-level fan-out packaging structure, characterized in that: It includes a first passivation layer, a chip or a non-edge device is flip-chip placed on the first passivation layer and both are covered with a plastic packaging layer on the outside, a first redistribution layer is arranged on the first passivation layer, a redistribution structure is arranged on the first redistribution layer, and a ball grid array structure for external interconnection is arranged on the redistribution structure.

2. A board-level fan-out packaging structure according to claim 1, characterized in that: A lead-out port is provided on a side of the first passivation layer away from the chip or the edgeless device, and a first redistribution layer is arranged at the lead-out port.

3. A board-level fan-out packaging structure according to claim 1, characterized in that: The redistribution structure comprises a second passivation layer, a second redistribution layer and a third passivation layer, wherein the second passivation layer, the second redistribution layer and the third passivation layer are sequentially arranged on the first redistribution layer.

4. A board-level fan-out packaging structure according to claim 4, characterized in that: A ball grid array structure for external interconnection is arranged on the third passivation layer.

5. A board-level fan-out packaging structure according to claim 4, characterized in that: The third passivation layer forms a ball grid array structure for external interconnection through the metal pad layer.

6. A method for preparing a board-level fan-out packaging structure according to any one of claims 1 to 5, characterized in that: The following steps are involved: Step 1: Prepare a temporary carrier board; Step 2: forming a temporary bonding layer on the temporary carrier to temporarily fix the chip or passive device to be packaged; Step 3: forming a first passivation layer on the temporary bonding layer; Step 4: placing the chip or passive device flip-chip on the first passivation layer, with the signal pin of the chip or passive device in direct contact with the first passivation layer, and using the bonding effect of the first passivation layer to firmly fix the chip or passive device; Step 5: Plastic-encapsulate the chip or the non-edge device and the first passivation layer as a whole to form a plastic-encapsulation layer; Step 6: remove the temporary carrier and the temporary bonding layer, and form a lead-out port for signal interconnection on the first passivation layer, wherein the lead-out port corresponds to the position of the signal pin; Step 7, forming a first redistribution layer at the lead-out port to lead the signal of the signal pin outward; Step 8: forming a redistribution structure on the first redistribution layer; Step nine: forming a ball grid array structure for external interconnection on the redistribution structure.

7. The method for preparing a board-level fan-out packaging structure according to claim 6, characterized in that: The thickness of the first passivation layer is 5 to 100 micrometers.

8. The method for preparing a board-level fan-out packaging structure according to claim 6, characterized in that: In step eight, the redistribution structure includes a second passivation layer, a second redistribution layer and a third passivation layer; The step of forming a redistribution structure on the first redistribution layer comprises: Repeat step three to form a second passivation layer; repeat step seven to form a second redistribution layer; repeat step three again to form a third passivation layer, the second passivation layer is used to insulate and isolate the first redistribution layer and the second redistribution layer, and the third passivation layer is used to isolate the second redistribution layer and the subsequent metal pad layer.

9. The method for preparing a board-level fan-out packaging structure according to claim 8, characterized in that: In step nine, the step of forming a ball grid array structure for external interconnection on the redistribution structure includes: Ball planting or printed solder paste reflow is directly performed on the third passivation layer to form a final ball grid array structure for external interconnection.

10. The method for preparing a board-level fan-out packaging structure according to claim 8, characterized in that: In step nine, the step of forming a ball grid array structure for external interconnection on the redistribution structure includes: A metal pad layer is first formed on the third passivation layer, and then ball planting or printed solder paste reflow is performed on the metal pad layer to form a final ball grid array structure for external interconnection.

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