Static switch control circuit of power frequency inverter power supply

Abstract

The invention discloses a static switch control circuit of a power frequency inverter power supply, the control circuit is used for controlling the power frequency inverter power supply comprising at least two inverters and at least one static switch, the input of the control circuit is respectively connected with a main inverter and an auxiliary inverter, and the output of the control circuit is connected to the static switch. The control circuit includes a first connector and a second connector. According to the static switch control circuit, parallel control can be achieved through the two inverters, when any inverter breaks down, non-delay switching is carried out, communication between the two inverters is not needed, and voltage fluctuation caused by communication delay in a double-inverter control circuit is avoided.

Description

Technical Field

[0001] The invention relates to the field of uninterruptible power supplies, and in particular to a static switch control circuit of an industrial frequency inverter power supply. Background Art

[0002] The industrial frequency inverter power supply consists of an inverter, a static switch, etc. The inverter converts the DC input of the battery pack into AC power to provide AC power to the load. The static switch collects AC input, DC input information, and inverter information to determine the input and inversion status and control the inverter power output.

[0003] When DC input is used, the inverter converts the DC input of the battery pack into AC power to provide AC power to the load. Usually, in order to ensure the stability of the power frequency inverter power supply, a bypass AC input is also set.

[0004] The traditional power frequency inverter power supply consists of a set of inverters and a set of static switches. If the inverters need to be connected in parallel to increase the reliability of power supply, two sets of power frequency inverter power supplies are required. In this solution, the two sets of power frequency inverter power supplies occupy a large space, and there are many wirings between the two sets of power frequency inverter power supplies, which are all outside the power supply and are easily interfered by the environmental magnetic field. Once the communication between the two sets of power frequency inverter power supplies fails, it is likely to cause the power supplies to affect each other and generate circulating currents to damage the inverter power supply and affect the back-end load. Summary of the invention

[0005] The purpose of the present invention is to solve the problem of parallel connection of industrial frequency inverter power supplies and propose a static switch control circuit for an inverter power supply. The control circuit can adapt to two scenarios: shared bypass and separate bypass of inverter power supplies. The application is simple and the system reliability can be improved. When the bypass input is abnormal or an inverter fails, the static switch is guaranteed to work normally. In addition, during the failure of one of the inverters, even if the communication fails, smooth switching can still be guaranteed.

[0006] Principle

[0007] For two or more sets of power frequency inverter power supplies, or a set of power frequency inverter power supplies with a common bypass and multiple sets of inverters, the most important thing is to solve the control problem of the static switch output. For a single set of inverters, the control signals of the inverter output and the bypass output are interlocked, and only one control signal is sent to the static switch, and the other control signal will be blocked; for multiple sets of inverters in parallel, the control signals of all static switches are consistent. If the static switch control signal of a set of inverters is wrong, both control signals will be blocked. Due to the delay of signal interaction, after the main control inverter is damaged, there may be a delay in the process of switching from the standby inverter to the main control inverter, resulting in power failure at the load end.

[0008] In view of the above problems, the present invention provides a static switch control circuit of an industrial frequency inverter power supply, wherein the control circuit is used to control an industrial frequency inverter power supply including at least two inverters and at least one static switch, wherein the input of the control circuit is respectively connected to a main inverter and a sub-inverter, and the output of the control circuit is connected to the static switch, wherein the control circuit comprises a first connector and a second connector, wherein the first connector is powered by a first inverter, and the second connector is powered by a second inverter, and the DC power supply of the first inverter is divided into two branches, wherein the first branch is input to a first input of a controlled connector via a diode D1, and the second branch is input to a second input of a controlled connector via a diode D3. Input, the DC power supply of the second inverter is divided into two branches, the third branch is connected in parallel with the first branch through a diode D4 and then input to the first input of the controlled connector, the fourth branch is connected in parallel with the second branch through a diode D6 and then input to the second input of the controlled connector, the first connector has a first main control inverter signal output and a first bypass control signal output; the second connector has a second main control inverter signal output and a second bypass control signal output; the first main control inverter signal output and the second main control inverter signal output are respectively connected in parallel through diodes to form an inverter control signal; the first bypass control signal output and the second bypass control signal output are respectively connected in parallel through diodes to form a bypass control signal,

[0009] The inverter control signal is input to the base of transistor Q4, the collector of transistor Q4 is connected to the base of transistor Q5 via a diode, the collector of transistor Q5 is powered by a low-voltage power supply via a voltage-dividing resistor and connected to the second input of NAND gate U2A, the first input of NAND gate U2A is connected to the periodically changing PWM drive signal, and the output of NAND gate U2A is used as the output of the inverter control signal.

[0010] The bypass control signal is input to the base of the transistor Q7, the collector of the transistor Q7 is connected to the base of the transistor Q6 via a diode, the collector of the transistor Q6 is powered by a low-voltage power supply via a voltage-dividing resistor and is connected to the second input of the NAND gate U2B, the first input of the NAND gate U2B is connected to the periodically changing PWM drive signal, the output of the NAND gate U2A serves as the output of the bypass control signal, and the collector of the transistor Q5 is connected to the base of the transistor Q6 via a diode.

[0011] Further, the output of the controlled connector is connected to a static switch, and the controlled connector controls the static switch to switch between the bypass input and the inverter input.

[0012] Furthermore, a chip UC3845 is included for generating a PWM driving signal with the same period as the inverter.

[0013] Further, the bypass input is connected to the mains, and the first inverter and the second inverter are respectively connected to respective battery groups.

[0014] Further, the number of the controlled static switches is one or two.

[0015] The present invention can realize that in the control process of two or more sets of industrial frequency inverter power supplies, when the main inverter fails and the inverter communication is delayed, the static switch can still be effectively controlled to avoid the back-end power outage. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a schematic diagram of the framework when the static switch control circuit of the present invention is applied to static switch control;

[0017] Figure 2 1 is an internal circuit diagram of the static switch control circuit of the present invention.

[0018] Figure 3 The present invention is applied to a static switch control circuit to be controlled.

[0019] Figure 4 This is a diagram showing the actual application effect of the circuit of the invention. Channel 1 (yellow) is the sampling of the total output voltage of the inverter power supply, channel 2 (green) is the sampling of the BAPASS signal, and channel 3 (purple) is the sampling of the INVERNT signal. It simulates when one of the inverter power supplies fails. Combined with the analysis of the working process, the BAPASS signal of channel 2 changes from a low level to a high level. During this failure process, it can be observed that the total output voltage sampling of the inverter power supply of channel 1 has no abnormal conditions such as fluctuations, spikes, faults, etc., and the output is stable. DETAILED DESCRIPTION

[0020] The present invention is further described in detail below in conjunction with embodiments and drawings, but the embodiments of the present invention are not limited thereto.

[0021] like Figure 1 As shown, it is a circuit diagram of an application scenario of the control circuit of the present invention. The circuit of the present invention is applied in the case of controlling a static switch using a dual inverter. In order to avoid that two static switches are controlled by a single inverter respectively, once the inverter fails, it will cause irreparable losses. Therefore, a dual inverter is used for redundancy setting. However, considering that in the traditional dual inverter control process, it is necessary to coordinate between the dual inverters based on the communication between the dual inverters. Once the communication between the two is delayed or fails, when a certain inverter fails, the control signal output to the static switch will be disordered.

[0022] In order to avoid the above-mentioned control signal disorder problem, such as Figure 1As shown, in this embodiment, two inverters, inverter No. 1 and inverter No. 2, are used to jointly control the two static switches, and the two inverters are powered by their own battery packs, that is, the present invention adds an additional coordination control circuit, which is hereinafter referred to as a static switch control circuit.

[0023] The static switch control circuit of this embodiment is used to control an industrial frequency inverter power supply including two inverters and two static switches, and the input of the control circuit is connected to inverter No. 1 and inverter No. 2 respectively.

[0024] like Figure 2 As shown, the control circuit includes a first connector CN1 (FKV10VR) and a second connector CN2 (FKV10VR). The first connector is powered by the first inverter (inverter No. 1 in the figure), and the inverter separates a 12V DC signal to power the corresponding connector. Inverter No. 1 outputs a first main control inverter signal and a first bypass control signal to the first connector CN1. Similarly, the second inverter (inverter No. 2 in the figure) outputs a second main control inverter signal and a second bypass control signal to the second connector CN2, and the second connector CN2 is powered by inverter No. 2.

[0025] The first connector CN1 is connected to the static switch control signal of inverter No. 1, and the second connector CN2 is connected to the static switch control signal of inverter No. 2. +12B and +12B' are isolated by diodes D1 and D4 respectively to prevent backflow. In the figure, INV CTRL and INV CTRL' are the control signals of the inverter outputs of the two sets of inverters, which are output through two connectors and isolated by diode D2 to prevent backflow. R1 is the signal grounding resistor to prevent the signal from being suspended and generating virtual voltage.

[0026] In the figure, BY CTRL and BY CTRL' are the control signals of the bypass output of the two sets of inverters, which are output through two connectors and isolated by diode D5 to prevent backflow. R2 is the signal grounding resistor to prevent the signal from being suspended and generating virtual voltage; GND is the signal ground; +12 and +12' are isolated by diodes D3 and D6 respectively to prevent backflow. Pins 1 and 2 of the first connector CN1 are 12V power supply, pins 9 and 10 are 12VB power supply, and pins 3 and 4 are power ground. The two power supplies jointly provide power for the static switch; pins 5 and 6 are the control signals of the bypass output, and pins 7 and 8 are the control signals of the forwarding inverter output. In a single connector, the control signal is an interlocking signal. When pins 5 and 6 output control signals, pins 7 and 8 have no control signals. At this time, the static switch of the inverter power supply is in the bypass output state; when pins 7 and 8 output control signals, pins 5 and 6 have no control signals. At this time, the static switch of the inverter power supply is in the inverter output state.

[0027] The DC power supply input of inverter No. 1 is divided into two branches after being input to connector CN1. The first branch is input to the first input of controlled connector CN1 via diode D1, and the second branch is input to the second input of controlled connector CN3 via diode D3. The DC power supply input of inverter No. 2 is divided into two branches after being input to connector CN2. The third branch is connected in parallel with the first branch via diode D4 and then input to the first input of controlled connector CN3. The fourth branch is connected in parallel with the second branch via diode D6 and then input to the second input of controlled connector CN3. The first connector CN1 has a first main control inverter signal output and a first bypass control signal output, which are mutually inverse, that is, when the first main control inverter signal output is high level, the first bypass control signal output must be low level, and vice versa.

[0028] The second connector has a second main control inverter signal output and a second bypass control signal output, which are mutually inverse, that is, when the second main control inverter signal output is high level, the second bypass control signal output must be low level, and vice versa; the first main control inverter signal output and the second main control inverter signal output are respectively connected in parallel through diodes to form an inverter control signal; the first bypass control signal output and the second bypass control signal output are respectively connected in parallel through diodes to form a bypass control signal.

[0029] The combined inverter control signal is input to the base of transistor Q4, the collector of transistor Q4 is connected to the base of transistor Q5 via a diode, and the emitter of transistor Q4 is grounded. The collector of transistor Q5 is powered by a low-voltage power supply via a voltage-dividing resistor and connected to the second input of NAND gate U2A, and the emitter of transistor Q5 is grounded. The first input of NAND gate U2A is connected to the periodically changing PWM drive signal, and the output of NAND gate U2A is used as the output of the inverter control signal.

[0030] The combined bypass control signal is input to the base of transistor Q7, the collector of transistor Q7 is connected to the base of transistor Q6 via a diode, the emitter of transistor Q7 is grounded, the collector of transistor Q6 is powered by a low-voltage power supply via a voltage-dividing resistor and is connected to the second input of NAND gate U2B, the first input of NAND gate U2B is connected to a periodically changing PWM drive signal, the output of NAND gate U2B serves as the output of the bypass control signal, and the collector of transistor Q5 is connected to the base of transistor Q6 via a diode.

[0031] The periodically changing PWM drive signal is a drive signal generated by an independent chip UC3845, which generates a PWM signal with a corresponding duty cycle according to the control requirements of the static switch. The PWM signal here uses a 50Hz alternating pulse signal to match the output of the inverter, and the period and phase of the two are matched.

[0032] In the circuit, the working process of CD40107 is as follows: Pin 3 of CD40107 outputs to the INV STS DRV signal, which is used to control the inverter output function in the static switch. If the INV STSDRV signal is a high-level signal, the inverter output function stops. If the INV STSDRV signal is a high-low alternating level signal, the inverter output function starts. Pin 5 of CD40107 outputs to the BYSTSDRV signal, which is used to control the bypass output function in the static switch. If the BY STSDRV signal is a high-level signal, the bypass output function stops. If the INV STSDRV signal is a high-low alternating level signal, the bypass output function starts.

[0033] The control process of the static switch is as follows:

[0034] If the static switches of the two inverters are to work in bypass state, they will send high level to BY CTRL and BY CTRL' (the connector forwards through the corresponding port), and if the static switches are to work in inversion state, they will send high level to INV CTRL and INV CTRL' (the connector forwards through the corresponding port, the same below). Under normal circumstances, the signals sent by the two inverters are consistent, so that only one of the BYPASS and INVERNT signals is high level. At this time, the inverter power supply will output in bypass state or inversion state according to normal control requirements. If one of the inverters fails or the information exchange between the two inverters fails, the signals sent by the two inverters will be inconsistent, so that both BYPASS and INVERNT signals are high level. At this time, after passing through the circuit of the present invention, the inverter power supply will output in the inversion state.

[0035] The following is a further detailed explanation of the working process of the inverter power supply:

[0036] When both inverters are working normally, the main control signals (INV CTRL) output by inverter No. 1 and inverter No. 2 to the corresponding connectors are both high level, and the bypass control signals (BY CTRL) are both low level. The corresponding interfaces in CN1 and CN2 output high level, D2 is turned on, and the high level is output to the base of transistor Q4. Q4 is turned on, Q5 is turned off, and the 2nd pin of the NAND gate U2A (CD40107) is high level, the PWM signal of the 1st pin of U2A is a high-low alternating level signal, and the 3rd pin of U2A will output a high-low alternating level signal; Q7 is turned off, Q6 is turned on, the 6th pin of U2B is low level, the PWM signal of the 7th pin of U2B is a high-low alternating level signal, and the 5th pin of U2B will output a high level signal. Since the bypass input and the inverter main control input require alternating signals, the bypass input is not turned on when it is a long high level. The two static switches are output by the inverter under the control of the main control signal.

[0037] When inverter No. 1 or inverter No. 2 fails, the description is made taking the fault No. 1 as an example. The main control signal output (INV CTRL) of connector CN1 connected to inverter No. 1 is low level, and the main control signal of connector CN2 connected to inverter No. 2 is high level. The main control signal output and bypass signal output in the connector are opposite to each other. The bypass signal output of CN2 is low level, and the bypass output of CN1 is high level. The two are high level after being connected in parallel. The INVERNT signal is high level, the BAPASS signal is high level, Q4 is turned on, Q5 is cut off, pin 2 of NAND gate U2A is high level, and the PWM signal of pin 1 of NAND gate U2A is a high-low alternating level signal, and pin 3 of NAND gate U2A will output a high-low alternating level signal; Q7 is turned on, Q6 is turned on, pin 6 of NAND gate U2B is low level, and the PWM signal of pin 7 of NAND gate U2B is a high-low alternating level signal, and pin 5 of NAND gate U2B will output a high-level signal. The static switch is controlled by inverter 2 alone, and there will be no control disorder.

[0038] When both inverters fail, the main control signal output (INVCTRL) of the connector connected to inverter No. 1 is low, the main control signal of the connector connected to inverter No. 2 is low, the main control signal output and bypass signal output in the connector are mutually inverse, the bypass signal output of the connector connected to inverter No. 1 and inverter No. 2 is high, the INVERNT signal is low, and the BAPASS signal is high, Q4 is cut off, Q5 is turned on, the 2nd foot of the NAND gate U2A is low, the 1st foot PWM signal of the NAND gate U2A is a high-low alternating level signal, and the 3rd foot of the NAND gate U2A will output a high-level signal; Q7 is turned on, Q6 is cut off, the 6th foot of the NAND gate U2B is high, the 7th foot PWM signal of the NAND gate U2B is a high-low alternating level signal, and the 5th foot of the NAND gate U2B will output a high-low alternating level signal. A smooth transition from inverter power supply to bypass power supply is achieved.

[0039] When the circuit of the present invention is used for control, the circuit simulation situation after encountering a fault is as follows Figure 4 As shown. Among them, channel 1 (yellow) is the total output voltage sampling of the inverter power supply, channel 2 (green) is the BAPASS signal sampling, and channel 3 (purple) is the INVERNT signal sampling. When one of the inverter power supplies fails, combined with the working process analysis and restraint, the BAPASS signal of channel 2 changes from a low level to a high level. During this fault process, it can be observed that the total output voltage sampling of the inverter power supply of channel 1 has no abnormal conditions such as fluctuations, spikes, faults, etc., and the output is stable.

[0040] Although the principles of the present invention are described in detail above in conjunction with the preferred embodiments of the present invention, those skilled in the art should understand that the above embodiments are merely explanations of the exemplary implementations of the present invention, and are not intended to limit the scope of the present invention. The details in the embodiments do not constitute limitations on the scope of the present invention, and any obvious changes such as equivalent transformations, simple replacements, etc. based on the technical solution of the present invention, without departing from the spirit and scope of the present invention, fall within the protection scope of the present invention.

Claims

1. A static switch control circuit for an industrial frequency inverter power supply, characterized in that: The control circuit is used to control an industrial frequency inverter power supply including at least two inverters and at least one static switch. The input of the control circuit is respectively connected to the main inverter and the auxiliary inverter, and the output of the control circuit is connected to the static switch. The control circuit includes a first connector and a second connector. The first connector is powered by the first inverter, and the second connector is powered by the second inverter. The DC power supply of the first inverter is divided into two branches. The first branch is input to the first input of the controlled connector via a diode D1, and the second branch is input to the second input of the controlled connector via a diode D3. The DC power supply of the second inverter is divided into Two branches, the third branch is connected in parallel with the first branch through a diode D4 and then input to the first input of the controlled connector, the fourth branch is connected in parallel with the second branch through a diode D6 and then input to the second input of the controlled connector, the first connector has a first main control inverter signal output and a first bypass control signal output; the second connector has a second main control inverter signal output and a second bypass control signal output; the first main control inverter signal output and the second main control inverter signal output are respectively connected in parallel through diodes to form an inverter control signal; the first bypass control signal output and the second bypass control signal output are respectively connected in parallel through diodes to form a bypass control signal, The inverter control signal is input to the base of transistor Q4, the collector of transistor Q4 is connected to the base of transistor Q5 via a diode, the collector of transistor Q5 is powered by a low-voltage power supply via a voltage-dividing resistor and connected to the second input of NAND gate U2A, the first input of NAND gate U2A is connected to the periodically changing PWM drive signal, and the output of NAND gate U2A is used as the output of the inverter control signal. The bypass control signal is input to the base of the transistor Q7, the collector of the transistor Q7 is connected to the base of the transistor Q6 via a diode, the collector of the transistor Q6 is powered by a low-voltage power supply via a voltage-dividing resistor and is connected to the second input of the NAND gate U2B, the first input of the NAND gate U2B is connected to the periodically changing PWM drive signal, the output of the NAND gate U2A serves as the output of the bypass control signal, and the collector of the transistor Q5 is connected to the base of the transistor Q6 via a diode.

2. The static switch control circuit according to claim 1, characterized in that: The output of the controlled connector is connected to a static switch, and the controlled connector controls the static switch to switch between the bypass input and the inverter input.

3. The static switch control circuit according to claim 1, characterized in that: The chip UC3845 is also included to generate a PWM drive signal with the same cycle as the inverter.

4. The static switch control circuit according to claim 1, characterized in that: The bypass input is connected to the mains, and the first inverter and the second inverter are respectively connected to their own battery groups.

5. The static switch control circuit according to claim 1, characterized in that: The number of controlled static switches is one or two.

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