Reading circuit and image sensor

Abstract

The invention provides a readout circuit and an image sensor, and the readout circuit comprises a sampling and integrating circuit module which is used for carrying out the m-time sampling and integrating of a pixel signal, so as to obtain an analog pixel signal, an effective signal in the analog pixel signal is amplified by m times compared with an effective signal in the pixel signal, and the effective signal in the analog pixel signal is amplified by m times; the noise signal in the analog pixel signal is amplified by multiple times compared with the noise signal in the pixel signal, and m is a positive integer greater than 1; and the reading circuit module is used for performing analog-to-digital conversion on the analog pixel signal to obtain a digital pixel signal. The pixel signal is sampled and integrated for multiple times through the sampling and integrating circuit module, so that an effective signal in the analog pixel signal is amplified compared with a noise signal, namely, the noise signal is correspondingly reduced, and therefore, when the reading circuit is applied to the image sensor, the noise signal in the image sensor can be effectively reduced, and the image sensor reliability is improved. The problem that an existing image sensor is large in pixel noise is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of image processing and circuit design, and in particular to a readout circuit and an image sensor. Background Art

[0002] Image sensors use the photoelectric conversion function of photoelectric devices to convert the light image on the photosensitive surface into an electrical signal that is proportional to the light image. They are divided into two categories: CCD structure and CMOS structure. With the continuous improvement of various application requirements, image sensors not only need to have high resolution and high frame rate, but also better image quality, which puts higher requirements on the noise characteristics of image sensors.

[0003] However, due to the influence of the manufacturing process, image sensors will inevitably have pixel noise, which appears as isolated pixels or pixel blocks with strong visual effects on the image, seriously affecting the image quality. At present, the common practice to reduce pixel noise is to improve the process technology of the transistors in the pixel array of the image sensor. However, as the area of ​​the image sensor continues to decrease, the size of the transistors in the pixel array is also decreasing, making it difficult to improve the process technology of the transistors and difficult to achieve, and the effect of improving pixel noise is not ideal. Summary of the invention

[0004] The object of the present invention is to provide a readout circuit and an image sensor to solve the problem of how to reduce pixel noise of the image sensor.

[0005] In order to solve the above technical problems, the present invention provides a readout circuit, comprising: The sampling and integration circuit module is used to sample and integrate the pixel signal m times to obtain an analog pixel signal, wherein the effective signal in the analog pixel signal is amplified m times compared to the effective signal in the pixel signal, and the noise signal in the analog pixel signal is amplified m times compared to the noise signal in the pixel signal. times, where m is a positive integer greater than 1; The readout circuit module is used to perform analog-to-digital conversion on the analog pixel signal to obtain a digital pixel signal.

[0006] Optionally, in the readout circuit, the sampling and integration circuit module includes a reset signal sampling unit, a photosensitive signal sampling unit and an integration unit; the reset signal sampling unit is used to sample the pixel signal m times when the pixel signal is a reset signal to output a reset sampling signal; the photosensitive signal sampling unit is used to sample the pixel signal m times when the pixel signal is a photosensitive signal to output a photosensitive sampling signal; the integration unit is used to integrate the reset sampling signal and the photosensitive sampling signal respectively to output a reset integral signal and a photosensitive integral signal, wherein the analog pixel signal includes a reset integral signal and a photosensitive integral signal.

[0007] Optionally, in the readout circuit, the reset signal sampling unit and the photosensitive signal sampling unit each include m parallel signal sampling branches; each of the signal sampling branches includes a sampling switch and a control switch connected in series in sequence, and the sampling switch and the control switch are grounded via a sampling capacitor.

[0008] Optionally, in the readout circuit, only one of the sampling switches is in a closed state at the same time; and all of the control switches are in the same state at the same time.

[0009] Optionally, in the readout circuit, the integration unit includes an integrator; a first reset switch and a first integration capacitor are connected in parallel between the first input port and the first output port of the integrator; a second reset switch and a second integration capacitor are connected in parallel between the second input port and the second output port of the integrator; the first input port is connected to a reset sampling signal, the second input port is connected to a photosensitivity sampling signal, the first output port outputs a reset integration signal, and the second output port outputs a photosensitivity integration signal.

[0010] Optionally, in the readout circuit, at the same time, the states of the first reset switch and the second reset switch are consistent.

[0011] Optionally, in the readout circuit, the readout circuit module includes a comparator and a counter; the first input port of the comparator receives a reset integral signal through a first capacitor, and the second input port receives a photosensitivity integral signal through a second capacitor, the first capacitor and the first input port are grounded through a third capacitor, and the second capacitor and the second input port are connected to a ramp signal through a fourth capacitor; the first input port and the first output port are connected through a third reset switch, and the second input port and the second output port are connected through a fourth reset switch; the second output port is connected to the input port of the counter, and the output port of the counter outputs a digital pixel signal.

[0012] Optionally, in the readout circuit, the states of the third reset switch and the fourth reset switch are consistent.

[0013] Optionally, in the readout circuit, the second output port of the comparator is connected to the input port of the counter via a buffer and an inverter in sequence.

[0014] Optionally, in the readout circuit, the readout circuit also includes a pixel module; the pixel module includes a light emitting diode, a charge transfer tube, a reset tube, an amplifier tube and a gate tube; the positive electrode of the photosensitive diode is grounded, and the negative electrode is connected to the source of the charge transfer tube; the gate of the charge transfer tube is used to receive the transfer tube control signal, the drain is connected to the source of the reset tube and leads to a floating node; the gate of the reset tube is used to receive the reset tube control signal, the drain is connected to the power supply, the drain of the amplifier tube is connected to the power supply, the gate is connected to the floating node, and the source is connected to the drain of the gate tube; the gate of the gate tube is used to receive the pixel control signal, and the source is the output end for outputting the pixel signal.

[0015] In order to solve the above technical problem, the present invention further provides an image sensor, comprising the readout circuit as described in any one of the above items.

[0016] The readout circuit and image sensor provided by the present invention include: a sampling integration circuit module, which is used to sample and integrate the pixel signal m times to obtain an analog pixel signal, wherein the effective signal in the analog pixel signal is amplified m times compared with the effective signal in the pixel signal, and the noise signal in the analog pixel signal is amplified m times compared with the noise signal in the pixel signal. times, where m is a positive integer greater than 1; a readout circuit module is used to perform analog-to-digital conversion on the analog pixel signal to obtain a digital pixel signal. The pixel signal is sampled and integrated multiple times by the sampling and integration circuit module, so that the effective signal in the analog pixel signal is amplified compared with the noise signal, that is, the noise signal is correspondingly reduced, so that when the readout circuit is applied to the image sensor, the noise signal in the image sensor can be effectively reduced, solving the problem of large pixel noise in the existing image sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A structural block diagram of a readout circuit provided in this embodiment; Figure 2 A basic circuit diagram of a readout circuit provided in this embodiment; Figure 3 A circuit schematic diagram of a readout circuit module with a buffer and an inverter provided in this embodiment; Figure 4 A complete circuit schematic diagram of a readout circuit with a pixel module provided in this embodiment; Figure 5 A timing control diagram of a readout circuit with a pixel module provided in this embodiment. DETAILED DESCRIPTION

[0018] The readout circuit and image sensor proposed in the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the accompanying drawings is often a part of the actual structure. In particular, the emphasis of each accompanying drawing is different, and sometimes different proportions are used.

[0019] It should be noted that the terms "first", "second", etc. in the specification, claims and drawings of the present invention are used to distinguish similar objects in order to describe the embodiments of the present invention, rather than to describe a specific order or sequence. It should be understood that the structures used in this way can be interchanged under appropriate circumstances. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0020] This embodiment provides a readout circuit such as Figure 1 As shown, it includes: a sampling integration circuit module, which is used to sample and integrate the pixel signal m times to obtain an analog pixel signal, wherein the effective signal in the analog pixel signal is amplified m times compared to the effective signal in the pixel signal, and the noise signal in the analog pixel signal is amplified m times compared to the noise signal in the pixel signal. times, where m is a positive integer greater than 1; a readout circuit module is used to perform analog-to-digital conversion on the analog pixel signal to obtain a digital pixel signal.

[0021] The readout circuit provided in this embodiment samples and integrates the pixel signal multiple times through the sampling and integration circuit module, so that the effective signal in the analog pixel signal is amplified compared with the noise signal, that is, the noise signal is correspondingly reduced. Therefore, when the readout circuit is applied to the image sensor, the noise signal in the image sensor can be effectively reduced, solving the problem of large pixel noise in the existing image sensor.

[0022] Specifically, in the present embodiment, the sampling and integration circuit module includes a reset signal sampling unit, a photosensitive signal sampling unit and an integration unit; the reset signal sampling unit is used to sample the pixel signal m times when the pixel signal is a reset signal to output a reset sampling signal; the photosensitive signal sampling unit is used to sample the pixel signal m times when the pixel signal is a photosensitive signal to output a photosensitive sampling signal; the integration unit is used to integrate the reset sampling signal and the photosensitive sampling signal respectively to output a reset integration signal and a photosensitive integration signal, wherein the analog pixel signal includes a reset integration signal and a photosensitive integration signal.

[0023] In a specific embodiment, the reset signal sampling unit and the photosensitive signal sampling unit each include m parallel signal sampling branches; each of the signal sampling branches includes a sampling switch and a control switch connected in series in sequence, and the sampling switch and the control switch are grounded via a sampling capacitor.

[0024] like Figure 2 As shown, the reset signal sampling unit includes m parallel signal sampling branches, wherein the sampling switch of each signal sampling branch is denoted as Sri, and the sampling capacitor is denoted as Cri, where i=1, 2, ..., m; the photosensitive signal sampling unit also includes m parallel signal sampling branches, wherein the sampling switch of each signal sampling branch is denoted as Ssj, and the sampling capacitor is denoted as Csj, where j=1, 2, ..., m; the control switch of each branch is denoted as Sc, and its closing or opening is controlled by the same control signal.

[0025] During the sampling process, the control signal of the control switch controls Sc to close; when the pixel signal is the reset signal Vrst, the sampling switch control signal controls Sr1 to Srm to be turned on in sequence, thereby completing m samplings of the reset signal, and the reset sampling signal after each sampling is input to the integration unit for integration processing to obtain the reset integration signal Vritg; similarly, when the pixel signal is the photosensitive signal Vsig, the sampling switch control signal controls Ss1 to Ssm to be turned on in sequence, thereby completing m samplings of the photosensitive signal, and the photosensitive sampling signal after each sampling is input to the integration unit for integration processing to obtain the photosensitive integration signal Vsitg. That is to say, during the sampling process, at the same time, only one of the sampling switches is in a closed state; at the same time, the states of all the control switches are consistent.

[0026] Of course, in other embodiments, the sampling switch and the control switch on each signal sampling branch can also be controlled to be in the same state through the switch control signal, that is, the switch control signal controls the sampling switch and the control switch on the same signal sampling branch to be closed at the same time, and the sampling switches and control switches on other signal sampling branches are opened at the same time, so that when sampling, it can be ensured that only one signal sampling branch is turned on, thereby completing the sampling of the pixel signal. The present application does not limit the control method of the sampling switch and the control switch, as long as the successive sampling of the pixel signal can be completed.

[0027] Furthermore, in this embodiment, the integration unit includes an integrator; a first reset switch RST1 and a first integration capacitor Cf1 are connected in parallel between the first input port inp and the first output port outp of the integrator; a second reset switch RST2 and a second integration capacitor Cf2 are connected in parallel between the second input port inm and the second output port outm of the integrator; the first input port inp is connected to a reset sampling signal, the second input port inm is connected to a photosensitivity sampling signal, the first output port outputs a reset integration signal Vritg, and the second output port outputs a photosensitivity integration signal Vsitg.

[0028] During the integration process, the integrator can not only integrate the reset sampling signal output by the reset signal sampling unit, but also integrate the photosensitive sampling signal output by the photosensitive signal sampling unit. In order to ensure the normal integration process of the integrator while minimizing the generation of control signals, in this embodiment, an integral reset signal is used to control the first reset switch RST1 and the second reset switch RST2, that is, at the same time, the states of the first reset switch and the second reset switch are consistent.

[0029] Furthermore, in the present embodiment, the readout circuit module includes a comparator and a counter; the first input port inp of the comparator receives a reset integral signal through a first capacitor C1, and the second input port inm receives a photosensitivity integral signal through a second capacitor C2; the first capacitor C1 and the first input port inp are grounded through a third capacitor C3, and the second capacitor C2 and the second input port inm are connected to a ramp signal Vramp through a fourth capacitor C4; the first input port inp and the first output port outp are connected through a third reset switch RST3, and the second input port inm and the second output port outm are connected through a fourth reset switch RST4; the second output port outm is connected to the input port of the counter as the output end of the comparator, and the output port of the counter outputs a digital pixel signal Dout.

[0030] In practical applications, in order to ensure that the comparator can compare the two signals normally and reduce the generation of control signals as much as possible, in this embodiment, a comparison reset signal is used to control the third reset switch RST3 and the fourth reset switch RST4, that is, at the same time, the states of the third reset switch and the fourth reset switch are consistent. In addition, the ramp signal Vramp can be provided by a ramp generator.

[0031] Preferably, in order to buffer and increase the driving of the comparison signal output by the comparator, in this embodiment, Figure 3 As shown, the second output port of the comparator is connected to the input port of the counter through a buffer and an inverter in sequence, that is, the second output port of the comparator is connected to the input end of the buffer, the output end of the buffer is connected to the input end of the inverter, and the output end of the inverter is connected to the input port of the counter.

[0032] Furthermore, in this embodiment, if Figure 4 As shown, the readout circuit also includes a pixel module; the pixel module includes a light emitting diode PD, a charge transfer tube Mtg, a reset tube Mrst, an amplifier tube Msf and a gate tube Msel; the positive electrode of the photosensitive diode PD is grounded, and the negative electrode is connected to the source of the charge transfer tube Mtg, the gate of the charge transfer tube Mtg is used to receive the transfer tube control signal TX, the drain is connected to the source of the reset tube Mrst and leads to a floating node FD, the gate of the reset tube Mrst is used to receive the reset tube control signal RX, the drain is connected to the power supply PVDD, the drain of the amplifier tube Msf is connected to the power supply PVDD, the gate is connected to the floating node FD, and the source is connected to the drain of the gate tube Msel, the gate of the gate tube Msel is used to receive the pixel control signal SEL, and the source is connected to the input end of the multiple sampling unit of the noise reduction circuit as the output end, providing the input signal Vp of the multiple sampling unit.

[0033] The working principle of the pixel module provided in this embodiment is roughly as follows: the photosensitive diode PD is sensitive to light and generates photoelectrons that are proportional to the light intensity; the function of the charge transfer tube Mtg is to transfer the photoelectrons in the photosensitive diode PD. When the transfer tube control signal TX is a high voltage, the charge transfer tube Mtg is turned on, and the photoelectrons in the photosensitive diode PD are transferred to the floating node FD, and there is a floating voltage Vfd at the floating node FD; the function of the reset tube Mrst is to reset the floating node FD when the reset tube control signal RX is a high potential; Msf is an amplifier tube. When the pixel control signal SEL is a high potential and the selection tube Msel is turned on, the amplifier tube Msf, the selection tube Msel and the current source to the ground form a path. At this time, the amplifier tube Msf follows the change of the potential of the floating node FD and finally outputs the pixel signal Vp.

[0034] Of course, in other embodiments, pixel modules of other structures may be selected to provide the input signal Vp of the multi-sampling unit, and this application does not limit this. The selection of other pixel module structures without violating the purpose of this application should also fall within the protection scope of this application.

[0035] In a specific application, the readout circuit further includes a decoding driver, and the decoding driver is used to provide a transmission tube control signal TX, a reset tube control signal RX and a pixel control signal SEL.

[0036] The following, combined Figure 4 and Figure 5 , the working principle of the readout circuit proposed in this embodiment is described. Among them, RST_COUNT represents the counter reset signal, EN_COUNT represents the counter enable signal, Vinm and Vinp represent the signals at the two input terminals of the integrator respectively, and Vcom_out represents the comparator output signal.

[0037] When the integrator reset signal is high, the first reset switch RST1 and the second reset switch RST2 are closed to reset the integrator; when the comparator reset signal is high, the third reset switch RST3 and the fourth reset switch RST4 are closed to reset the comparator.

[0038] When the integrator reset signal and the comparator reset signal are low, the integrator performs normal integration operation and the comparator performs normal comparison operation.

[0039] When the pixel signal output by the pixel module is the reset signal Vrst, the sampling switch Sri and the control switch Sc in the reset signal sampling unit sample the reset signal m times in sequence according to the control of the control signal (for example, when the control signal of Sr1 is at a high level, Sr1 is closed, and Cr1 samples the reset signal Vrst for the first time; when the control signal of Srm is at a high level, Srm is closed, and Crm samples the reset signal Vrst for the mth time). When the control signal of the control switch Sc is at a high level, the multi-sampled signals are transmitted to the integrator inp input port, and each output of the integrator is Vcm+Vinp, Vcm+2Vinp, ..., Vcm+m×Vinp in sequence, where Vcm is the reset level of the integrator. Since the reset signal Vrst includes a valid signal and a noise signal, in an ideal state, when the valid signal is 0, the reset signal Vrst at this time only includes a noise signal. Therefore, by sampling the reset signal Vrst multiple times and integrating it with an integrator, when the intensity ratio (signal-to-noise ratio) of the valid signal and the noise signal in the reset signal Vrst is 1:1, the intensity ratio (signal-to-noise ratio) of the valid signal and the noise signal in the reset integrated signal output by the integrator is That is, in a specific application, if the signal-to-noise ratio of the reset signal Vrst is 1:1, then the signal-to-noise ratio of the reset integral signal is In this way, the noise signal in the reset signal Vrst can be effectively reduced. At this time, the first capacitor Cc1 stores the reset integral signal; when the counter enable signal EN_COUNT is at a high level, the counter starts counting, and when the comparator output flips, the counter stops counting, and the counter outputs a digital signal D0.

[0040] Similarly, when the pixel signal output by the pixel module is the photosensitive signal Vsig, the sampling switch Ssi and the control switch Sc in the photosensitive signal sampling unit sample the photosensitive signal m times in sequence according to the control signal (e.g., when the control signal of Ss1 is high, Ss1 is closed, and Cs1 samples the photosensitive signal Vsig for the first time; when the control signal of Ssm is high, Ssm is closed, and Csm samples the photosensitive signal Vsig for the mth time). When the control signal of the control switch Sc is high, the multi-sampled signal is transmitted to the integrator inm input port, and each output of the integrator is Vcm+Vinm, Vcm+2Vinm, ..., Vcm+m×Vinm, where Vcm is the reset level of the integrator. Similarly, when the intensity ratio (signal-to-noise ratio) of the effective signal and the noise signal in the photosensitive signal Vsig is 1:1, the intensity ratio (signal-to-noise ratio) of the effective signal and the noise signal in the photosensitive integrated signal output by the integrator is That is, in a specific application, if the signal-to-noise ratio of the photosensitive signal Vsig is 1:1, then the signal-to-noise ratio of the photosensitive integral signal is In this way, the noise signal in the photosensitive signal Vsig can be effectively reduced. At this time, the second capacitor Cc2 stores the photosensitive integral signal; when the counter enable signal EN_COUNT is at a high level, the counter starts counting, and when the comparator output sends a flip, the counter stops counting, and the counter outputs a digital signal D1.

[0041] In the digital domain, the difference between D1 and D0 is m×(Vrst-Vsig). Since the signal output by the pixel module is sampled m times, the final signal is m times the original pixel photosensitive signal. At the same time, the noise signal in the final signal is m times the original noise signal. By averaging the final signal, we can get a signal that is consistent with the original pixel light-sensitive signal intensity, that is, the final signal is Vrst-Vsig, and the noise signal is the original noise signal. times, effectively reducing the noise signal in the pixel photosensitive signal.

[0042] The readout circuit provided in this embodiment can significantly improve the signal-to-noise ratio, especially in a low-light environment, so that when the image sensor uses the readout circuit provided in this embodiment, the image quality of the image sensor can be effectively improved.

[0043] The present embodiment also provides an image sensor, including the readout circuit as described above. The image sensor provided by the present embodiment samples and integrates the pixel signal multiple times through the sampling and integration circuit module, so that the effective signal in the analog pixel signal is amplified compared with the noise signal, that is, the noise signal is correspondingly reduced, so that when the readout circuit is applied to the image sensor, the noise signal in the image sensor can be effectively reduced, solving the problem of large pixel noise in the existing image sensor.

[0044] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other. In addition, the different parts between the various embodiments can also be used in combination with each other, and the present invention is not limited to this.

[0045] The readout circuit and image sensor provided in this embodiment include: a sampling integration circuit module, which is used to sample and integrate the pixel signal m times to obtain an analog pixel signal, wherein the effective signal in the analog pixel signal is amplified m times compared with the effective signal in the pixel signal, and the noise signal in the analog pixel signal is amplified m times compared with the noise signal in the pixel signal. times, where m is a positive integer greater than 1; a readout circuit module is used to perform analog-to-digital conversion on the analog pixel signal to obtain a digital pixel signal. The pixel signal is sampled and integrated multiple times by the sampling and integration circuit module, so that the effective signal in the analog pixel signal is amplified compared with the noise signal, that is, the noise signal is correspondingly reduced, so that when the readout circuit is applied to the image sensor, the noise signal in the image sensor can be effectively reduced, solving the problem of large pixel noise in the existing image sensor.

[0046] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A readout circuit, characterized in that: include: The sampling and integration circuit module is used to sample and integrate the pixel signal m times to obtain an analog pixel signal, wherein the effective signal in the analog pixel signal is amplified m times compared to the effective signal in the pixel signal, and the noise signal in the analog pixel signal is amplified m times compared to the noise signal in the pixel signal. times, where m is a positive integer greater than 1; The readout circuit module is used to perform analog-to-digital conversion on the analog pixel signal to obtain a digital pixel signal.

2. The readout circuit according to claim 1, characterized in that: The sampling and integration circuit module includes a reset signal sampling unit, a photosensitive signal sampling unit and an integration unit; the reset signal sampling unit is used to sample the pixel signal m times when the pixel signal is a reset signal to output a reset sampling signal; the photosensitive signal sampling unit is used to sample the pixel signal m times when the pixel signal is a photosensitive signal to output a photosensitive sampling signal; the integration unit is used to integrate the reset sampling signal and the photosensitive sampling signal respectively to output a reset integration signal and a photosensitive integration signal, wherein the analog pixel signal includes a reset integration signal and a photosensitive integration signal.

3. The readout circuit according to claim 2, characterized in that: The reset signal sampling unit and the photosensitive signal sampling unit both include m parallel signal sampling branches; each of the signal sampling branches includes a sampling switch and a control switch connected in series in sequence, and the sampling switch and the control switch are grounded via a sampling capacitor.

4. The readout circuit according to claim 3, characterized in that: At the same time, only one of the sampling switches is in a closed state; at the same time, the states of all the control switches are consistent.

5. The readout circuit according to claim 2, characterized in that: The integration unit includes an integrator; a first reset switch and a first integration capacitor are connected in parallel between the first input port and the first output port of the integrator; a second reset switch and a second integration capacitor are connected in parallel between the second input port and the second output port of the integrator; the first input port is connected to a reset sampling signal, the second input port is connected to a photosensitivity sampling signal, the first output port outputs a reset integration signal, and the second output port outputs a photosensitivity integration signal.

6. The readout circuit according to claim 5, characterized in that: At the same time, the states of the first reset switch and the second reset switch are consistent.

7. The readout circuit according to claim 2, characterized in that: The readout circuit module includes a comparator and a counter; the first input port of the comparator receives a reset integral signal through a first capacitor, and the second input port receives a photosensitivity integral signal through a second capacitor; the first capacitor and the first input port are grounded through a third capacitor, and a ramp signal is connected between the second capacitor and the second input port through a fourth capacitor; the first input port and the first output port are connected through a third reset switch, and the second input port and the second output port are connected through a fourth reset switch; the second output port is connected to the input port of the counter, and the output port of the counter outputs a digital pixel signal.

8. The readout circuit according to claim 7, characterized in that: The states of the third reset switch and the fourth reset switch are consistent.

9. The readout circuit according to claim 7, characterized in that: The second output port of the comparator is connected to the input port of the counter via a buffer and an inverter in sequence.

10. The readout circuit according to claim 1, characterized in that: The readout circuit also includes a pixel module; the pixel module includes a light-emitting diode, a charge transfer tube, a reset tube, an amplifier tube and a gate tube; the positive electrode of the photosensitive diode is grounded, and the negative electrode is connected to the source of the charge transfer tube; the gate of the charge transfer tube is used to receive the transfer tube control signal, the drain is connected to the source of the reset tube and leads to a floating node; the gate of the reset tube is used to receive the reset tube control signal, the drain is connected to the power supply, the drain of the amplifier tube is connected to the power supply, the gate is connected to the floating node, and the source is connected to the drain of the gate tube; the gate of the gate tube is used to receive the pixel control signal, and the source is the output end for outputting the pixel signal.

11. An image sensor, characterized in that: Comprising a readout circuit as described in any one of claims 1 to 10.

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