Multi-time programmable memory device and preparation method thereof
By adopting specific structural design and preparation methods in MTP devices, the voltage difference during programming, erasing and writing is reduced, the problem of device failure caused by the increase in oxide layer traps is solved, and the long-term effectiveness and high reliability of the device are achieved.
Patent Information
- Application Number
- CN202411385295.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-30
- Publication Date
- 2025-01-17
AI Technical Summary
After multiple high-voltage programming erases in existing MTP devices, traps in the oxide layer under the control gate increase, resulting in short circuits in the control gate and channel and device failure.
By adopting specific structural design and preparation methods in multi-times programmable memory devices, including setting P-type light doping and heavy doping on intrinsic semiconductor silicon, forming oxide layers and insulating dielectric layers, and etching on these layers Etch grooves and groove isolation, fill metal to form source and drain regions, and reduce the voltage difference required during programming and erasing.
It achieves that only a small voltage difference between the source and drain is required during programming and erasing, and only a small voltage is applied to the control gate to complete the programming and erasing action, thus avoiding the problem of device failure caused by an increase in oxide layer traps. Extends the service life of the device.
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Figure CN119325233A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a multi-time programmable memory device and a preparation method thereof. Background Art
[0002] MTP (Multi-time Programmable Cell) technology occupies an important position in the semiconductor field and is one of the indispensable key technologies in modern integrated circuit design. This technology allows precision adjustment or customization according to customer needs after the chip leaves the factory, thereby significantly improving the flexibility and adaptability of semiconductor devices. As the storage memory module of the chip, MTP captures or releases the charge in the storage medium, accurately adjusts the key parameters such as the threshold voltage of the device, thereby affecting the output current value and realizing precise control of the circuit behavior. This process not only ensures the reliable storage and management of data, but also supports a variety of application scenarios such as firmware upgrades, configuration parameter storage, and user data preservation.
[0003] In the semiconductor manufacturing process, the introduction of MTP technology enables the chip to be programmed and erased multiple times in the later stage, greatly extending the service life and functional expansion capabilities of the device; in addition, MTP has non-volatile characteristics, and the stored data can still be retained even in the case of power failure, ensuring the long-term stability and security of the data. With the continuous advancement of semiconductor technology, MTP devices have achieved significant improvements in storage density, programming speed and power consumption control, further promoting its wide application in embedded systems, IoT devices, high-performance computing and smart terminals.
[0004] In the prior art, conventional MTP device structures are as follows Figure 8 As shown, the floating gate (FG) stores data. When performing a programming operation ( Figure 8 Path ①) and erase operation ( Figure 8 In the middle path ②), in order to make the carriers in the channel enter the floating gate FG, a large voltage difference needs to be applied to the source (S) and the drain (D), usually a voltage difference of about 4V is required, and the control gate (CG) often applies a voltage of at least 8V to allow the carriers to enter or move out of the floating gate layer; this method places high demands on the quality of the oxide layer under the control gate, requiring very few traps and sufficient thickness, but as the number of device programming and erasing increases, the oxide layer under the control gate will have more and more traps under the action of a higher electric field, eventually leading to a short circuit between the control gate and the active channel and device failure, which seriously limits the service life and application range of the device.
[0005] Currently, no effective solution has been proposed for the problems in the related technologies. Summary of the invention
[0006] In response to the problems in the related art, the present invention proposes a multi-time programmable memory device and a preparation method thereof, which has the advantages that during programming and erasing, only a small voltage difference is required between the source and the drain, and only a small voltage needs to be applied to the control gate to complete the programming and erasing operations, thereby solving the problem in the prior art that the oxide layer under the control gate has more and more traps in the oxide layer with multiple high-voltage programming and erasing, which eventually leads to a short circuit between the control gate and the channel and device failure.
[0007] To this end, the specific technical solution adopted by the present invention is as follows:
[0008] According to one aspect of the present invention, a multi-time programmable memory device is provided, which includes intrinsic semiconductor silicon, wherein the bottom surface of the intrinsic semiconductor silicon is provided with P-type light doping, the bottom of the P-type light doping is provided with P-type heavy doping, a first shallow trench isolation is opened on one side of the top of the intrinsic semiconductor silicon, and a second shallow trench isolation is opened on the other side of the top of the intrinsic semiconductor silicon.
[0009] Furthermore, the trench etching depths of the first shallow trench isolation and the second shallow trench isolation extend to the top surface of the P-type lightly doped layer.
[0010] Furthermore, an oxide layer is disposed on the top surface of the intrinsic semiconductor silicon, a control gate and a floating gate region are disposed in the middle of the top of the oxide layer, and an insulating dielectric layer is disposed on the top of the oxide layer.
[0011] Furthermore, a first groove and a second groove are respectively formed on both sides of the top of the insulating dielectric layer, and a barrier layer metal is provided on the inner surfaces of the first groove and the second groove.
[0012] Furthermore, the etching depths of the first groove and the second groove extend to the top surface of the P-type lightly doped layer, and an insulating dielectric layer is separated between the first groove and the control gate, and an insulating dielectric layer is separated between the second groove and the floating gate region.
[0013] Furthermore, a source region is disposed inside the first groove, a drain region is disposed inside the second groove, and a cross section of the source region is configured as an L-shaped structure, with one end of the L-shaped structure extending toward the floating gate region.
[0014] Furthermore, an interlayer dielectric layer is disposed on the top surface of the insulating dielectric layer, and a polysilicon region is disposed in the middle of the top of the interlayer dielectric layer.
[0015] Furthermore, the polysilicon region is located above the floating gate region, and the top of the polysilicon region is located at the same level as the tops of the source region and the drain region.
[0016] Furthermore, an insulating layer is disposed on the top surface of the interlayer dielectric layer, and a source electrode and a drain electrode are respectively disposed through both sides of the top of the insulating layer, and the source electrode is connected to the source region, and the drain electrode is connected to the drain region.
[0017] According to another aspect of the present invention, a method for preparing a multi-time programmable memory device is provided, and the method for preparing a multi-time programmable memory device comprises the following steps:
[0018] S1. Based on the intrinsic semiconductor silicon, the bottom of the intrinsic semiconductor silicon is lightly doped and heavily doped with a P conductive type, and trench etching is performed on both sides of the top of the intrinsic semiconductor silicon to generate a first shallow trench isolation and a second shallow trench isolation;
[0019] S2, thermally oxidize the top of the intrinsic semiconductor silicon to form an oxide layer, use a mask to deposit and etch the middle of the top of the oxide layer to generate a control gate and a floating gate region, and deposit the top of the oxide layer to form an insulating dielectric layer;
[0020] S3, based on the insulating dielectric layer, etching from the top to the bottom using a mask to obtain a first groove and a second groove;
[0021] S4, depositing a barrier layer metal based on the inner surfaces of the first groove and the second groove;
[0022] S5. Filling the first groove and the second groove with metal by a deposition process to generate a source region and a drain region, and setting a longitudinal distance between the source region and the floating gate region to a first spacing, and setting a longitudinal distance between the drain region and the floating gate region to a second spacing, wherein the first spacing is within a range of 2 / 5 to 2 / 3 of the second spacing;
[0023] S6, forming an interlayer dielectric layer based on the top of the insulating dielectric layer, and etching the middle of the top of the interlayer dielectric layer to obtain a polysilicon region;
[0024] S7. Based on the interlayer dielectric layer, an insulating layer is formed, and holes are etched above the source region and the drain region respectively, and contact holes are filled and metal is deposited on the surface to form metal electrode connections to obtain source and drain electrodes.
[0025] The beneficial effects of the present invention are:
[0026] (1) Compared with the conventional multi-time programmable memory device, the present invention utilizes the FN tunneling principle so that when programming and erasing the memory device, only a small voltage difference between the source and drain is required, and only a small voltage is applied to the control gate to complete the programming and erasing operations.
[0027] (2) The memory device prepared by the preparation method provided by the present invention avoids the situation where the oxide layer under the control gate is programmed and erased multiple times at high voltage, resulting in an increasing number of traps in the oxide layer, which eventually leads to a short circuit between the control gate and the channel and device failure. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0029] Figure 1 is a schematic structural diagram of a multi-time programmable memory device according to an embodiment of the present invention;
[0030] Figure 2 is a schematic structural diagram of a multi-time programmable memory device obtained in step S1 of a method for preparing a multi-time programmable memory device according to an embodiment of the present invention;
[0031] Figure 3 is a schematic structural diagram of a multi-time programmable memory device obtained in step S2 of a method for preparing a multi-time programmable memory device according to an embodiment of the present invention;
[0032] Figure 4 is a schematic structural diagram of a multi-time programmable memory device obtained in step S3 of a method for preparing a multi-time programmable memory device according to an embodiment of the present invention;
[0033] Figure 5 is a schematic structural diagram of a multi-time programmable memory device obtained in step S4 of a method for preparing a multi-time programmable memory device according to an embodiment of the present invention;
[0034] Figure 6 is a schematic structural diagram of a multi-time programmable memory device obtained in step S5 of a method for preparing a multi-time programmable memory device according to an embodiment of the present invention;
[0035] Figure 7 is a schematic structural diagram of a multi-time programmable memory device obtained in step S6 of a method for preparing a multi-time programmable memory device according to an embodiment of the present invention;
[0036] Figure 8 It is a schematic diagram of the structure of a traditional multi-time programmable device;
[0037] Fig. 9 The figure is a flow chart of a method for preparing a multi-time programmable memory device according to an embodiment of the present invention.
[0038] In the figure:
[0039] 100, intrinsic semiconductor silicon; 101, P-type light doping; 102, P-type heavy doping; 1031, first shallow trench isolation; 1032, second shallow trench isolation; 104, oxide layer; 105, control gate; 1061, floating gate region; 1062, polysilicon region; 107, insulating dielectric layer; 1081, first groove; 1082, second groove; 109, barrier metal layer; 110, interlayer dielectric layer; 201, source region; 201M, source; 202, drain region; 202M, drain. DETAILED DESCRIPTION
[0040] To further illustrate each embodiment, the present invention provides drawings, which are part of the disclosure of the present invention and are mainly used to illustrate the embodiments and can be used in conjunction with the relevant descriptions in the specification to explain the operating principles of the embodiments. With reference to these contents, ordinary technicians in the field should be able to understand other possible implementations and advantages of the present invention. The components in the figures are not drawn to scale, and similar component symbols are generally used to represent similar components.
[0041] According to an embodiment of the present invention, a multi-time programmable memory device and a method for manufacturing the same are provided.
[0042] The present invention is further described with reference to the accompanying drawings and specific embodiments. Figure 1 As shown, according to one embodiment of the present invention, a multi-time programmable memory device is provided, which includes an intrinsic semiconductor silicon 100, a P-type lightly doped 101 is arranged on the bottom surface of the intrinsic semiconductor silicon 100, a P-type heavily doped 102 is arranged on the bottom of the P-type lightly doped 101, a first shallow trench isolation 1031 is opened on one side of the top of the intrinsic semiconductor silicon 100, and a second shallow trench isolation 1032 is opened on the other side of the top of the intrinsic semiconductor silicon 100.
[0043] Specifically, Figure 1 As shown, a multi-time programmable device proposed by the present invention includes intrinsic semiconductor silicon 100, P-type lightly doped 101, P-type heavily doped 102, a first shallow trench isolation 1031, a second shallow trench isolation 1032, a control gate 105, a floating gate region 1061, a polysilicon region 1062, a source 201M and a drain 202M.
[0044] In one embodiment, the trench etching depths of the first shallow trench isolation 1031 and the second shallow trench isolation 1032 extend to the top surface of the P-type lightly doped layer 101 .
[0045] In one embodiment, an oxide layer 104 is disposed on the top surface of the intrinsic semiconductor silicon 100 , a control gate 105 and a floating gate region 1061 are disposed in the middle of the top of the oxide layer 104 , and an insulating dielectric layer 107 is disposed on the top of the oxide layer 104 .
[0046] In one embodiment, a first groove 1081 and a second groove 1082 are respectively formed on two sides of the top of the insulating dielectric layer 107 , and a barrier metal layer 109 is disposed on the inner surfaces of the first groove 1081 and the second groove 1082 .
[0047] In one embodiment, the trench etching depths of the first groove 1081 and the second groove 1082 extend to the top surface of the P-type lightly doped 101, and the first groove 1081 and the control gate 105 are separated by an insulating dielectric layer 107, and the second groove 1082 and the floating gate region 1061 are separated by an insulating dielectric layer 107.
[0048] In one embodiment, a source region 201 is disposed inside the first groove 1081 , a drain region 202 is disposed inside the second groove 1082 , and a cross section of the source region 201 is configured as an L-shaped structure, one end of the L-shaped structure extending toward the floating gate region 1061 .
[0049] In one embodiment, an interlayer dielectric layer 110 is disposed on the top surface of the insulating dielectric layer 107 , and a polysilicon region 1062 is disposed in the middle of the top of the interlayer dielectric layer 110 .
[0050] In one embodiment, the polysilicon region 1062 is located above the floating gate region 1061 , and the top of the polysilicon region 1062 is located at the same level as the tops of the source region 201 and the drain region 202 .
[0051] In one embodiment, an insulating layer 111 is disposed on the top surface of the interlayer dielectric layer 110 , and a source 201M and a drain 202M are respectively disposed on both sides of the top of the insulating layer 111 , and the source 201M is connected to the source region 201 , and the drain 202M is connected to the drain region 202 .
[0052] like Fig. 9 According to another embodiment of the present invention, a method for preparing a multi-time programmable memory device is provided. The method for preparing a multi-time programmable memory device comprises the following steps:
[0053] S1, based on the intrinsic semiconductor silicon 100, lightly doping and heavily doping of P conductivity type are performed on the bottom of the intrinsic semiconductor silicon 100, and trench etching operations are performed on both sides of the top of the intrinsic semiconductor silicon 100 to generate a first shallow trench isolation 1031 and a second shallow trench isolation 1032;
[0054] Specifically, the preparation method step S1: Figure 2As shown, an intrinsic semiconductor silicon 100 is provided, and a P-conductivity type light doping is first performed on the back side thereof, marked as P-type light doping 101, and then a P-conductivity type heavy doping is performed, marked as P-type heavy doping 102, wherein the doping depth of 101 is greater than the doping depth of 102, returning to the front side of the intrinsic semiconductor silicon 100, a shallow trench isolation (STI) is formed downwardly in the left and right areas of the front side through groove etching, oxide filling, oxide polishing, nitride removal and other process steps, including a first shallow trench isolation 1031 and a second shallow trench isolation 1032, and the groove etching depths of the first shallow trench isolation 1031 and the second shallow trench isolation 1032 extend all the way to the upper surface of 101.
[0055] S2, thermally oxidizing the top of the intrinsic semiconductor silicon 100 to form an oxide layer 104, using a mask to deposit and etch the middle of the top of the oxide layer 104 to generate a control gate 105 and a floating gate region 1061, and depositing the top of the oxide layer 104 to form an insulating dielectric layer 107;
[0056] Specifically, the preparation method step S2: Figure 3 As shown, thermal oxidation is performed on the surface of the device to form an oxide layer 104, and then deposition and etching steps are performed through a mask to form a control gate 105 and a floating gate region 1061. The control gate 105 is connected to an external electrode by forming a contact hole and a local interconnection process (only for explanation here, not shown in the figure), and finally an insulating dielectric layer 107 is deposited on the surface of the device.
[0057] S3, based on the insulating dielectric layer 107, etching from the top to the bottom using a mask to obtain a first groove 1081 and a second groove 1082;
[0058] Specifically, the preparation method step S3: Figure 4 As shown, the left area of the control gate 105 and the right area of the floating gate region 1061 are etched downward through a mask to form a first groove 1081 and a second groove 1082. The etching depth of the first groove 1081 and the second groove 1082 reaches the upper surface of 101, and the first groove 1081 and the control gate 105 are separated by an insulating dielectric layer 107. Similarly, the second groove 1082 and the floating gate region 1061 are separated by an insulating dielectric layer 107.
[0059] S4, depositing a barrier metal 109 based on the inner surfaces of the first groove 1081 and the second groove 1082;
[0060] Specifically, the preparation method step S4: Figure 5 As shown, a barrier metal layer 109 is deposited on the surface of the device, and then the excess barrier metal is removed, leaving only the inner surfaces of the grooves 1081 and 1082 described in step S3.
[0061] S5. Filling the first groove 1081 and the second groove 1082 with metal by a deposition process to generate a source region 201 and a drain region 202, and setting a first spacing La as the longitudinal distance between the source region 201 and the floating gate region 1061, and setting a second spacing Lb as the longitudinal distance between the drain region 202 and the floating gate region 1061, and the first spacing La is within a range of 2 / 5 to 2 / 3 of the second spacing Lb;
[0062] Specifically, the preparation method step S5: Figure 6 As shown, metal is continuously deposited on the device surface and filled in the first groove 1081 and the second groove 1082, and then the excess metal is removed to finally form the source region 201 and the drain region 202. The metal material for filling can be selected with relatively low resistivity. In this embodiment, aluminum, copper, tungsten, molybdenum, platinum, etc. are selected; wherein the source region 201 will extend to the right close to the floating gate region 1061, and the distance from the longitudinal left side surface of the floating gate region 1061 is La, and the distance from the drain region 202 to the longitudinal right side surface of the floating gate region 1061 is Lb, and La is in the range of 2 / 5Lb to 2 / 3Lb, and the longitudinal height of the source region 201 and the drain region 202 exceeding the insulating dielectric layer 107 is h.
[0063] S6, forming an interlayer dielectric layer 110 based on the top of the insulating dielectric layer 107, and etching the middle of the top of the interlayer dielectric layer 110 to obtain a polysilicon region 1062;
[0064] Specifically, the preparation method step S6: Figure 7 As shown, an interlayer dielectric layer 110 is formed on the surface of the device, and the area above the floating gate region 1061 is etched downward, and a polysilicon region 1062 is formed through a deposition process, wherein the upper surface of the polysilicon region 1062 is on the same horizontal plane as the source region 201 and the drain region 202, and the polysilicon region 1062 is isolated from the floating gate region 1061 by an insulating dielectric layer 107. Since the interlayer dielectric layer 110 has holes inside, when a voltage difference is applied to the source and drain, electrons can tunnel or move out of the polysilicon region 1062 more easily. At the same time, since La is in the range of 2 / 5Lb to 2 / 3Lb, a certain amount of static charge can be maintained in the polysilicon region 1062.
[0065] S7. Based on the interlayer dielectric layer 110, an insulating layer 111 is formed, and holes are etched above the source region 201 and the drain region 202 respectively, and contact holes are filled and metal is deposited on the surface to form metal electrode connections, thereby obtaining the source 201M and the drain 202M.
[0066] Specifically, the preparation method step S7: Figure 1As shown, an insulating layer 111 is formed on the surface of the device, and then holes are etched above the source region 201 and the drain region, contact holes are filled in the holes, and then metal is deposited on the surface to finally form metal electrode connections, namely the source 201M and the drain 202M.
[0067] In order to facilitate understanding of the above technical solution of the present invention, the actual programming and erasing operations of the multi-time programmable memory device prepared by the present invention in the binary storage mode are taken as an example to specifically describe the working principle as follows:
[0068] When programming "1": when a forward voltage is applied between the source and the drain (i.e., the preferred range of Vd-Vs is 0.4V-1V, where Vd is the drain voltage and Vs is the source voltage), since La is smaller than Lb, the number of electrons from the source 201M tunneling to the polysilicon region 1062 is greater than the number of electrons flowing out of the polysilicon region 1062 to the drain 202M, so there is a net positive charge in the polysilicon region 1062. At this time, due to the action of the electric field, electrons near the drain region 202 in the intrinsic semiconductor silicon 100 are attracted into the channel, and a positive voltage is applied to the control gate 105; thereby, under the action of the electric field, electrons near the source region 201 of the intrinsic semiconductor silicon 100 are attracted into the channel. As the forward voltage applied to the control gate 105 increases to about 1V, electrons are prompted to tunnel into the floating gate region 101. At this time, the threshold voltage of the entire device is reduced, and it can be easily read when reading the drain voltage.
[0069] When programming "0": when a reverse voltage is applied between the source and the drain (i.e., the preferred range of Vs-Vd is 0.4V-1V), since La is smaller than Lb, the number of electrons from the drain 202M that tunnel to the polysilicon region 1062 is less than the number of electrons that flow out of the polysilicon region 1062 from the source 201M, so there is a net negative charge in the polysilicon region 1062. Due to the action of the electric field, holes near the drain region 202 in the intrinsic semiconductor silicon 100 are attracted into the channel. A negative voltage is applied to the control gate 105. Under the action of the electric field, holes near the source region 201 of the intrinsic semiconductor silicon 100 are attracted into the channel. As the negative voltage applied to the control gate 105 increases to about 1V, holes are forced to tunnel into the floating gate region 101. At this time, the threshold voltage of the entire device increases, and it can be easily read when reading the drain voltage.
[0070] When erasing "1": when a reverse voltage is applied between the source and the drain (i.e., the preferred range of Vs-Vd is 0.4V-1V), since La is smaller than Lb, the number of electrons from the drain 202M tunneling to the polysilicon region 1062 is less than the number of electrons flowing out of the polysilicon region 1062 from the source 201M, so there is a net negative charge in the polysilicon region 1062. Due to the action of the electric field, the electrons near the drain region 202 in the intrinsic semiconductor silicon 100 are prevented from approaching the channel. A negative voltage is applied to the control gate 105. Under the action of the electric field, the electrons near the source region 201 of the intrinsic semiconductor silicon 100 are prevented from approaching the channel. As the negative voltage applied to the control gate 105 increases to about 1V, the electrons in the floating gate region 101 are caused to return to the channel.
[0071] When erasing "0": when a forward voltage is applied between the source and the drain (i.e., the preferred range of Vd-Vs is 0.4V-1V), since La is smaller than Lb, the number of electrons from the source 201M tunneling to the polysilicon region 1062 is greater than the number of electrons flowing out of the polysilicon region 1062 to the drain 202M, so there is a net positive charge in the polysilicon region 1062. Due to the action of the electric field, the holes near the drain region 202 in the intrinsic semiconductor silicon 100 are prevented from approaching the channel. A positive voltage is applied to the control gate 105. Under the action of the electric field, the holes near the source region 201 of the intrinsic semiconductor silicon 100 are prevented from approaching the channel. As the positive voltage applied to the control gate 105 increases to about 1V, the holes in the floating gate region 101 are caused to return to the channel.
[0072] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims
1. A multi-time programmable memory device, characterized in that: The multi-time programmable memory device comprises an intrinsic semiconductor silicon (100), wherein the bottom surface of the intrinsic semiconductor silicon (100) is provided with a P-type light doping (101), the bottom of the P-type light doping (101) is provided with a P-type heavy doping (102), a first shallow trench isolation (1031) is opened on one side of the top of the intrinsic semiconductor silicon (100), and a second shallow trench isolation (1032) is opened on the other side of the top of the intrinsic semiconductor silicon (100).
2. The multi-time programmable memory device according to claim 1, characterized in that: The trench etching depths of the first shallow trench isolation (1031) and the second shallow trench isolation (1032) extend to the top surface of the P-type lightly doped (101).
3. The multi-time programmable memory device according to claim 1, characterized in that: An oxide layer (104) is provided on the top surface of the intrinsic semiconductor silicon (100), a control gate (105) and a floating gate region (1061) are provided in the middle of the top of the oxide layer (104), and an insulating dielectric layer (107) is provided at the top of the oxide layer (104).
4. The multi-time programmable memory device according to claim 3, characterized in that: A first groove (1081) and a second groove (1082) are respectively provided on both sides of the top of the insulating dielectric layer (107), and a barrier layer metal (109) is provided on the inner surfaces of the first groove (1081) and the second groove (1082).
5. The multi-time programmable memory device according to claim 4, characterized in that: The etching depths of the first groove (1081) and the second groove (1082) extend to the top surface of the P-type lightly doped (101), and an insulating dielectric layer (107) is between the first groove (1081) and the control gate (105), and an insulating dielectric layer (107) is between the second groove (1082) and the floating gate region (1061).
6. The multi-time programmable memory device according to claim 4, characterized in that: A source region (201) is arranged inside the first groove (1081), a drain region (202) is arranged inside the second groove (1082), and a cross section of the source region (201) is arranged as an L-shaped structure, one end of the L-shaped structure extends toward the floating gate region (1061).
7. The multi-time programmable memory device according to claim 6, characterized in that: An interlayer dielectric layer (110) is disposed on the top surface of the insulating dielectric layer (107), and a polysilicon region (1062) is disposed in the middle of the top of the interlayer dielectric layer (110).
8. The multi-time programmable memory device according to claim 7, characterized in that: The polysilicon region (1062) is located above the floating gate region (1061), and the top of the polysilicon region (1062) is located at the same level as the tops of the source region (201) and the drain region (202).
9. The multi-time programmable memory device according to claim 7, characterized in that: An insulating layer (111) is provided on the top surface of the interlayer dielectric layer (110), and a source electrode (201M) and a drain electrode (202M) are respectively provided on both sides of the top of the insulating layer (111), and the source electrode (201M) is connected to the source region (201), and the drain electrode (202M) is connected to the drain region (202).
10. A method for preparing a multi-time programmable memory device, used for preparing the multi-time programmable memory device according to any one of claims 1 to 9, characterized in that: The method for preparing a multi-time programmable memory device comprises: S1, based on the intrinsic semiconductor silicon (100), lightly doping and heavily doping of P conductivity type are performed on the bottom of the intrinsic semiconductor silicon (100), and trench etching operations are performed on both sides of the top of the intrinsic semiconductor silicon (100) to generate a first shallow trench isolation (1031) and a second shallow trench isolation (1032); S2, thermally oxidizing the top of the intrinsic semiconductor silicon (100) to form an oxide layer (104), using a mask to deposit and etch the middle of the top of the oxide layer (104) to generate a control gate (105) and a floating gate region (1061), and depositing the top of the oxide layer (104) to form an insulating dielectric layer (107); S3, based on the insulating dielectric layer (107), etching from the top to the bottom using a mask to obtain a first groove (1081) and a second groove (1082); S4, depositing a barrier metal (109) based on the inner surfaces of the first groove (1081) and the second groove (1082); S5. Using a deposition process, fill the first groove (1081) and the second groove (1082) with metal to generate a source region (201) and a drain region (202), and set the longitudinal distance between the source region (201) and the floating gate region (1061) to be a first spacing (La), and set the longitudinal distance between the drain region (202) and the floating gate region (1061) to be a second spacing (Lb), and the first spacing (La) is 1 / 2 of the second spacing (Lb). 2 / 5~ 2 / 3 range; S6, forming an interlayer dielectric layer (110) based on the top of the insulating dielectric layer (107), and etching the middle of the top of the interlayer dielectric layer (110) to obtain a polysilicon region (1062); S7. Based on the interlayer dielectric layer (110), an insulating layer (111) is formed, and holes are etched above the source region (201) and the drain region (202), respectively, and contact holes are filled and metal is deposited on the surface to form metal electrode connections, thereby obtaining a source electrode (201M) and a drain electrode (202M).