Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. Forming a first photoresist layer with a storage gate pattern on the substrate; etching the substrate by taking the first photoresist layer as a mask to form a plurality of discrete openings; forming a storage gate in the opening, wherein the top surface of the storage gate is flush with the top surface of the substrate; forming a selection gate layer on the surface of the substrate and the surface of the storage gate; forming a second photoresist layer with a selection gate pattern on the selection gate layer; and etching the selection gate layer by taking the second photoresist layer as a mask to form a plurality of discrete selection gates. An opening is formed in a substrate, a storage gate is formed in the opening, the storage gate is located in the substrate, and a selection gate is formed on the substrate, so that the selection gate and the storage gate have no overlapping area in the projection direction parallel to the substrate, that is, the selection gate and the storage gate have no electric contact in the pressurization process; the crosstalk effect between the storage gate and the selection gate is avoided, and the performance of the memory is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] The storage unit of a SONOS device is usually composed of a SONOS storage transistor (referred to as a storage tube) and a high-voltage selection transistor (referred to as a selection tube). The storage tube is used to store data, and the selection tube is used to complete the selection of the data address. Both transistors are in the same well area.

[0003] However, in the existing SONOS device, when a memory cell is operated, the word line BL of the memory cell will be selected, and the select gate (SG) of this row will be pressurized and selected, and the adjacent memory gate (MG) will be sensed at this time. Similarly, when the memory gate (MG) of this row is pressurized and selected, the adjacent select gate (SG) will also be sensed, resulting in a crosstalk effect between the memory gate and the select gate, which affects the performance of the memory. Summary of the invention

[0004] The technical problem solved by the present invention is how to improve the performance of the memory.

[0005] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a first photoresist layer having a storage gate pattern on the substrate; etching the substrate using the first photoresist layer as a mask to form a plurality of discrete openings; forming a storage gate in the opening, wherein the top surface of the storage gate is flush with the top surface of the substrate; forming a selection gate layer on the surface of the substrate and the surface of the storage gate; forming a second photoresist layer having a selection gate pattern on the selection gate layer; etching the selection gate layer using the second photoresist layer as a mask to form a plurality of discrete selection gates.

[0006] Optionally, the process for forming a number of discrete openings is: a dry etching process, the process parameters of the dry etching process are that the etching gas is a combination of one or more of H2, CF4, CHF3, CH2F2, C4F8 and Ar, the gas flow rate of the etching gas is 30sccm to 80sccm, the source power is 800W to 1200W, the bias power is 100W to 400W, the etching pressure is 10mTorr to 50mTorr, and the etching time is 30 seconds to 70 seconds; the process parameters for etching the substrate are that the chamber pressure is 5mT to 15mT, the source power is 350W to 1200W, the bias voltage is 150V to 600V, the gas flow rate is 20sccm to 200sccm, and the etching time is 8s to 60s.

[0007] Optionally, the method for forming the semiconductor structure also includes: before forming the selection gate layer, forming a storage gate dielectric layer on the opening surface and the substrate surface; after forming the storage gate, etching and removing the storage gate dielectric layer on the substrate surface until the substrate surface is exposed to form a dielectric layer.

[0008] Optionally, the step of forming the storage gate dielectric layer includes: forming a charge tunneling layer on the surface of the opening and the surface of the substrate; forming a charge trapping layer on the surface of the charge tunneling layer; and forming a charge blocking layer on the surface of the charge trapping layer.

[0009] Optionally, the method for forming the semiconductor structure further includes: before the step of forming the selection gate layer, forming a gate oxide layer on the substrate and the storage gate; after the step of forming the selection gate, forming a sidewall spacer on the sidewall of the selection gate.

[0010] Optionally, the step of forming a sidewall spacer on the sidewall of the select gate includes: forming a first silicon oxide layer on the sidewall of the select gate; forming a silicon nitride layer on a surface of the first silicon oxide layer; and forming a second silicon oxide layer on a surface of the silicon nitride layer.

[0011] Optionally, after the step of forming a plurality of discrete selection gates, the method further includes: performing ion implantation on the substrate between the selection gates and the storage gates to form source / drain regions.

[0012] Optionally, after the step of forming the source / drain region, it also includes: forming an interlayer dielectric layer on the substrate, the interlayer dielectric layer covering the source / drain region, the storage gate and the select gate; etching the interlayer dielectric layer and the gate oxide layer in sequence until the top of the storage gate, the top of the select gate and the top of the source / drain region are exposed to form a contact hole.

[0013] Optionally, after the step of forming the contact hole, it also includes: depositing a metal layer on the bottom surface of the contact hole; performing an annealing process to react the metal layer with the top surface of the source / drain region, the top surface of the storage gate and the top surface of the select gate to form a metal silicide layer.

[0014] Correspondingly, the present invention also provides a semiconductor structure, comprising: a substrate; an opening, a plurality of the openings being discretely located in the substrate; a storage gate, located in the opening, and a top surface of the storage gate being flush with a top surface of the substrate; a selection gate, a plurality of the selection gates being discretely located on the substrate, and the selection gate being adjacent to the storage gate in a projection direction perpendicular to the substrate.

[0015] Optionally, the semiconductor structure further includes: a dielectric layer located on the surface of the opening, the dielectric layer including a charge tunneling layer, a charge trapping layer located on the surface of the charge tunneling layer, and a charge blocking layer located on the surface of the charge trapping layer.

[0016] Optionally, the semiconductor structure also includes: a gate oxide layer located on the bottom surface of the selection gate, and a side wall located on the side wall surface of the selection gate, the side wall including a first silicon oxide layer, a silicon nitride layer located on the surface of the first silicon oxide layer, and a second silicon oxide layer located on the surface of the silicon nitride layer.

[0017] Optionally, the semiconductor structure further includes: a source / drain region located in the substrate between the select gate and the storage gate.

[0018] Optionally, the semiconductor structure further includes: a metal silicide layer located on the top surface of the source / drain region, the top surface of the storage gate, and the top surface of the select gate, an interlayer dielectric layer located on the substrate, and a contact hole located in the interlayer dielectric layer.

[0019] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0020] The present invention forms an opening in a substrate and forms a storage gate in the opening so that the storage gate is located in the substrate, and then forms a selection gate on the substrate, so that the selection gate and the storage gate have no overlapping area in a projection direction parallel to the substrate, that is, the selection gate and the storage gate have no electrical contact during the pressurization process, thereby avoiding the crosstalk effect between the storage gate and the selection gate, and improving the performance of the memory; in addition, the storage gate in the present invention is located in the substrate, so that the distance of the channel between the source and the drain is increased from the horizontal distance to the sum of the length along the surface of the storage gate in the substrate and the width of the selection gate, so that when the distance between the source and the drain in the horizontal direction remains unchanged, the carrier channel length becomes longer, thereby reducing the storage unit area and improving the performance of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a schematic diagram of the structure of a semiconductor structure;

[0022] Figures 2 to 16 is a schematic diagram of a process for forming a semiconductor structure in one embodiment of the present invention. DETAILED DESCRIPTION

[0023] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.

[0024] Please refer to Figure 1 In the current SONOS device, when a memory cell is operated, the word line BL of the memory cell will be selected, and the select gate 101 (select gate, SG) of this row will be pressurized and selected. At this time, the adjacent memory gate 102 (memory gate, MG) will be sensed. Similarly, when the memory gate 102 (memory gate, MG) of this row is pressurized and selected, the adjacent select gate 101 (select gate, SG) will also be sensed, resulting in a crosstalk effect between the memory gate 102 and the select gate 101, which affects the performance of the memory.

[0025] In addition, since the storage gate and the select gate are both located on the substrate, the channel length between the source and the drain is the horizontal distance between the source and the drain. If the carrier channel length is to be lengthened, the distance between the source and the drain must be increased, which in turn increases the storage unit area.

[0026] In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure and a method for forming the same, by forming a buried storage gate in the substrate and forming a selection gate on the surface of the substrate, so that the selection gate and the storage gate have no overlapping area in the projection direction parallel to the substrate, that is, the selection gate and the storage gate have no electrical contact during the pressurization process, thereby avoiding the crosstalk effect between the storage gate and the selection gate, and improving the performance of the memory.

[0027] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0028] Please refer to Figure 2 , providing a substrate 200; forming an isolation region 201 in the substrate 200; and forming a protective layer 202 on the surface of the substrate 200.

[0029] In this embodiment, the material of the substrate 200 is silicon.

[0030] In other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium; in other embodiments, the substrate may also be a silicon on insulator substrate or a germanium on insulator substrate.

[0031] The method for forming the isolation region 201 includes: etching the substrate 200 to form a shallow trench; and forming the isolation region 201 in the shallow trench.

[0032] In this embodiment, the material of the isolation region 201 is silicon oxide.

[0033] In this embodiment, the isolation region 201 is in an inverted trapezoidal shape.

[0034] The isolation region 201 is used to avoid electrical crosstalk between adjacent active devices.

[0035] In this embodiment, the method further includes: removing the isolation region 201 higher than the surface of the substrate 200 through a planarization process.

[0036] In this embodiment, the planarization process adopts a chemical mechanical polishing process.

[0037] In this embodiment, by adjusting the process parameters of chemical mechanical polishing, it is possible to ensure that during the polishing process, the isolation region 201 above the surface of the substrate 200 is removed and stops at a surface flush with the substrate 200 .

[0038] In other embodiments, the thickness of the isolation region 201 above the surface of the substrate 200 is 0 angstroms to 80 angstroms.

[0039] In this embodiment, the material of the protection layer 202 is silicon oxide or silicon oxynitride.

[0040] In this embodiment, the thickness of the protection layer 202 is in a range of 30 angstroms to 50 angstroms.

[0041] In some embodiments, the protection layer 202 is a single layer or multiple layers.

[0042] When the protection layer 202 is a single layer, the material of the protection layer 202 is silicon nitride.

[0043] When the protective layer 202 is a multi-layer stack, the material of the protective layer 202 is a combination of one or more of silicon nitride, silicon oxide, and carbon-rich silicon nitride.

[0044] The protection layer 202 is used to protect the surface of the substrate 200 from being damaged during the subsequent process of forming the opening 203 .

[0045] It can be seen that, by forming the protection layer 202 on the substrate 200 , the present invention avoids etching damage to the substrate 200 when the opening 203 is subsequently formed by etching, thereby ensuring the integrity of the substrate 200 .

[0046] Please refer to Figure 3 , forming a first photoresist layer having a storage gate 205 pattern on the substrate 200; using the first photoresist layer as a mask, etching the substrate 200 to form a plurality of discrete openings 203.

[0047] In this embodiment, the process for forming a plurality of discrete openings 203 is: a dry etching process, wherein the process parameters of the dry etching process are that the etching gas is a combination of one or more of H2, CF4, CHF3, CH2F2, C4F8 and Ar, the gas flow rate of the etching gas is 30sccm to 80sccm, the source power is 800W to 1200W, the bias power is 100W to 400W, the etching pressure is 10mTorr to 50mTorr, and the etching time is 30 seconds to 70 seconds; the process parameters for etching the substrate 200 are that the chamber pressure is 5mT to 15mT, the source power is 350W to 1200W, the bias voltage is 150V to 600V, the gas flow rate is 20sccm to 200sccm, and the etching time is 8s to 60s.

[0048] Please refer to Figure 4 A storage gate 205 dielectric layer is formed on the surface of the opening 203 and the surface of the substrate 200.

[0049] The step of forming a storage gate dielectric layer includes: forming a charge tunneling layer (not shown in the figure) on the surface of the opening 203 and the surface of the substrate 200; forming a charge trapping layer (not shown in the figure) on the surface of the charge tunneling layer; forming a charge blocking layer (not shown in the figure) on the surface of the charge trapping layer.

[0050] In this embodiment, the storage gate dielectric layer is an "ONO" structure, that is, a "sandwich structure" formed by silicon oxide, silicon nitride and silicon oxide.

[0051] Please refer to Figure 5 A storage gate layer 2051 is formed in the opening 203 and on the surface of the substrate 200 .

[0052] In this embodiment, the material of the storage gate layer 2051 is single crystal silicon or polycrystalline silicon.

[0053] Please refer to Figure 6 , the storage gate layer 2051 is planarized to form a storage gate 205 , and the top surface of the storage gate 205 is flush with the top surface of the substrate 200 .

[0054] After the storage gate 205 is formed, the storage gate dielectric layer on the surface of the substrate 200 is removed by etching until the surface of the substrate 200 is exposed, thereby forming a dielectric layer 204 .

[0055] In this embodiment, after the storage gate 205 is formed, the process further includes: forming a gate oxide layer 206 on the substrate 200 and the storage gate 205 .

[0056] In the above scheme, the storage gate 205 is located in the substrate 200, so that the distance of the channel between the source and the drain is increased from the horizontal distance to the sum of the length along the surface of the storage gate 205 located in the substrate 200 and the width of the selection gate 207, so that the carrier channel length becomes longer when the distance between the source and the drain in the horizontal direction remains unchanged, thereby reducing the storage unit area and improving the performance of the memory.

[0057] Please refer to Figure 7 , a selection gate layer 2071 is formed on the surface of the gate oxide layer 206 .

[0058] In this embodiment, the material of the gate oxide layer 206 is silicon oxide.

[0059] Please refer to Figure 8 , forming a second photoresist layer having a pattern of the select gate 207 on the select gate layer 2071 ; and etching the select gate layer 2071 using the second photoresist layer as a mask to form a plurality of discrete select gates 207 .

[0060] In the above scheme, an opening 203 is formed in the substrate 200, and a storage gate 205 is formed in the opening 203, so that the storage gate 205 is located in the substrate 200, and then a selection gate 207 is formed on the substrate 200, so that the selection gate 207 and the storage gate 205 have no overlapping area in the projection direction parallel to the substrate 200, that is, the selection gate 207 and the storage gate 205 have no electrical contact during the pressurization process, thereby avoiding the crosstalk effect between the storage gate 205 and the selection gate 207, thereby improving the performance of the memory.

[0061] Please refer to Fig. 9 After the step of forming the select gate 207 , a spacer 2072 is formed on the sidewall of the select gate 207 .

[0062] The step of forming a sidewall spacer 2072 on the sidewall of the select gate 207 includes: forming a first silicon oxide layer on the sidewall of the select gate 207; forming a silicon nitride layer on the surface of the first silicon oxide layer; and forming a second silicon oxide layer on the surface of the silicon nitride layer.

[0063] Please refer to Fig.10 , an interlayer dielectric layer 2073 is formed on the substrate 200 , and the interlayer dielectric layer 2073 covers the source / drain region 2074 , the storage gate 205 and the selection gate 207 .

[0064] After the step of forming a plurality of discrete selection gates 207 , the method further includes: performing ion implantation on the substrate 200 between the selection gates 207 and the storage gates 205 to form source / drain regions 2074 .

[0065] Please refer to Fig.11 as well as Fig.12 , Fig.11 It is a top view. Fig.11 Only the substrate 200, the storage gate 205 and the selection gate 207 are shown. Fig.12 is along Fig.11 In the cross-sectional schematic diagram along the AA1 direction, the interlayer dielectric layer 2073 and the gate oxide layer 206 are sequentially etched until the top of the source / drain region 2074 is exposed to form a first contact hole (not shown in the figure).

[0066] After the step of forming the first contact hole, it also includes: depositing a first metal layer (not shown in the figure) on the bottom surface of the first contact hole; performing an annealing process to react the first metal layer with the top surface of the source / drain region 2074 to form a first metal silicide layer 2081.

[0067] The process for etching the interlayer dielectric layer 2073 is dry etching, and the process parameters of the dry etching include: the chamber pressure is 20mT to 100mT, the source power is 500W to 2800W, the bias power is 30W to 2800W, the gas flow rate is 20sccm to 200sccm, and the etching time is 8s to 20s.

[0068] After the step of forming the first contact hole, it also includes: forming a first metal layer (not shown in the figure) at the bottom of the first contact hole; performing an annealing process to react the first metal layer with the top surface of the source / drain region 2074 to form a first metal silicide layer 2081.

[0069] After forming the first metal silicide layer 2081 , the method further includes: filling the first contact hole with a conductive material to form a first conductive plug 208 .

[0070] In this embodiment, the first conductive plug 208 is formed by using a chemical vapor deposition process or a physical vapor deposition process.

[0071] In this embodiment, the material of the first conductive plug 208 is copper, aluminum or tungsten.

[0072] In this embodiment, the method for forming the first metal layer is a chemical vapor deposition process, the material of the first metal layer is a nickel-platinum alloy, titanium or cobalt, and the thickness of the first metal layer ranges from 80 angstroms to 130 angstroms.

[0073] In this embodiment, the steps of performing annealing process treatment include: performing a first sub-annealing process treatment on the top surface of the first metal layer and a portion of the source / drain region 2074 to cause the first metal layer and the top surface of a portion of the source / drain region 2074 to react to form a high-resistance metal silicide layer (not shown in the figure); performing a second sub-annealing process treatment on the high-resistance metal silicide layer to cause a phase change reaction of the high-resistance metal silicide layer to form a first metal silicide layer 2081.

[0074] In this embodiment, the first annealing process adopts a rapid thermal annealing furnace, and the process parameters of the first annealing process are: annealing temperature is 200° C. to 350° C., and annealing time is 15 seconds to 45 seconds.

[0075] In this embodiment, the second annealing process adopts a rapid thermal annealing furnace, and the process parameters of the second annealing process are: annealing temperature is 300° C. to 600° C., and time is 15 seconds to 45 seconds.

[0076] In this embodiment, after the first partial annealing process, the method further includes: removing the first metal layer that does not react with silicon by wet etching to prevent a circuit short circuit caused by bridging.

[0077] The temperature of the first sub-annealing process is lower than the temperature of the second sub-annealing process. In the first sub-annealing process, the annealing temperature is 200°C to 350°C. The first metal layer will only react with a portion of the top surface of the source / drain region 2074102 to form a high-resistance metal silicide layer. If the annealing temperature is outside the range of 200°C to 350°C, it will cause the first metal layer to have an incomplete reaction or over-reaction with a portion of the top surface of the source / drain region 2074102.

[0078] In the second annealing process, the annealing temperature is 300°C to 600°C, which converts the high-resistance metal silicide layer into a low-resistance metal silicide layer. If the annealing temperature is outside the range of 300°C to 600°C, the high-resistance metal silicide layer will not be completely converted into the low-resistance metal silicide layer.

[0079] In the above scheme, two annealing processes are used to form the first metal silicide layer 2081, avoiding the problem of short circuit caused by generating a low-resistance metal silicide layer through only one annealing process. Specifically, the process temperature under the one annealing process will be very high. In such a high temperature environment, silicon can diffuse along the grain boundaries of the first metal silicide layer 2081, causing excessive growth of the first metal silicide layer 2081 above the silicon oxide boundary, and subsequent wet etching cannot remove the first metal silicide layer 2081 on the oxide, causing a short circuit.

[0080] In this embodiment, the material of the first metal silicide layer 2081 is: NiSi containing Pt.

[0081] Please refer to Fig.13 as well as Fig.14 , Fig.13 It is a top view. Fig.13 Only the substrate 200, the storage gate 205 and the selection gate 207 are shown. Fig.14 is along Fig.13 In the cross-sectional view along the BB1 ​​direction, the interlayer dielectric layer 2073 and the gate oxide layer 206 are sequentially etched until the top of the storage gate 205 is exposed, thereby forming a second contact hole (not shown in the figure).

[0082] After the step of forming the second contact hole, the method further includes: depositing a second metal layer on the bottom surface of the second contact hole; and performing an annealing process to react the second metal layer with the top surface of the storage gate 205 to form a second metal silicide layer 2091 .

[0083] After forming the second metal silicide layer 2091 , the method further includes: filling the second contact hole with a conductive material to form a second conductive plug 209 .

[0084] In this embodiment, the second conductive plug 209 is formed by using a chemical vapor deposition process or a physical vapor deposition process.

[0085] In this embodiment, the second conductive plug 209 is made of copper, aluminum or tungsten.

[0086] In this embodiment, the method for forming the second metal silicide layer 2091 and the second conductive plug 209 is the same as the method for forming the second metal silicide layer 2091 and the second conductive plug 209 described above, and will not be repeated herein.

[0087] Please refer to Fig.15 as well as Fig.16 , Fig.15 It is a top view. Fig.15 Only the substrate 200, the storage gate 205 and the selection gate 207 are shown. Fig.16 is along Fig.15 The cross-sectional view along CC1 direction shows that the interlayer dielectric layer 2073 is etched sequentially until the top of the select gate 207 is exposed, thereby forming a third contact hole (not shown in the figure).

[0088] After the step of forming the third contact hole, the method further includes: depositing a third metal layer on the bottom surface of the third contact hole; and performing an annealing process to react the third metal layer with the top surface of the selection gate 207 to form a third metal silicide layer 2101.

[0089] After forming the third metal silicide layer 2101 , the method further includes: filling the third contact hole with a conductive material to form a third conductive plug 210 .

[0090] In this embodiment, the third conductive plug 210 is formed by a chemical vapor deposition process or a physical vapor deposition process.

[0091] In this embodiment, the third conductive plug 210 is made of copper, aluminum or tungsten.

[0092] In this embodiment, the method for forming the third metal silicide layer 2101 and the third conductive plug 210 is the same as the method for forming the third metal silicide layer 2101 and the third conductive plug 210 described above, and will not be described in detail herein.

[0093] Accordingly, please continue to refer to Fig.10An embodiment of the present invention further provides a semiconductor structure, comprising a substrate 200; an opening 203, wherein a plurality of the openings 203 are separately located in the substrate 200; a storage gate 205, which is located in the opening 203 and wherein the top surface of the storage gate 205 is flush with the top surface of the substrate 200; and a selection gate 207, wherein a plurality of the selection gates 207 are separately located on the substrate 200 and the selection gates 207 are adjacent to the storage gates 205 in a projection direction perpendicular to the substrate 200.

[0094] In this embodiment, it further includes: a dielectric layer located on the surface of the opening 203, wherein the dielectric layer includes a charge tunneling layer, a charge trapping layer located on the surface of the charge tunneling layer, and a charge blocking layer located on the surface of the charge trapping layer.

[0095] In this embodiment, it also includes: a gate oxide layer 206 located on the bottom surface of the selection gate 207, and a side wall 2072 located on the side wall surface of the selection gate 207, the side wall 2072 includes a first silicon oxide layer, a silicon nitride layer located on the surface of the first silicon oxide layer, and a second silicon oxide layer located on the surface of the silicon nitride layer.

[0096] In this embodiment, the device further includes a source / drain region 2074 located in the substrate 200 between the select gate 207 and the storage gate 205 .

[0097] In this embodiment, it also includes: a metal silicide layer located on the top surface of the source / drain region 2074, the top surface of the storage gate 205 and the top surface of the selection gate 207, an interlayer dielectric layer 2073 located on the substrate 200, and a contact hole located in the interlayer dielectric layer 2073.

[0098] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a first photoresist layer having a storage gate pattern on the substrate; Using the first photoresist layer as a mask, etching the substrate to form a plurality of discrete openings; forming a storage gate in the opening, wherein a top surface of the storage gate is flush with a top surface of the substrate; forming a selection gate layer on the surface of the substrate and the surface of the storage gate; forming a second photoresist layer having a select gate pattern on the select gate layer; The select gate layer is etched using the second photoresist layer as a mask to form a plurality of discrete select gates.

2. The method for forming a semiconductor structure according to claim 1, wherein: The process for forming a number of discrete openings is: a dry etching process, the process parameters of the dry etching process are that the etching gas is a combination of one or more of H2, CF4, CHF3, CH2F2, C4F8 and Ar, the gas flow rate of the etching gas is 30sccm to 80sccm, the source power is 800W to 1200W, the bias power is 100W to 400W, the etching pressure is 10mTorr to 50mTorr, and the etching time is 30 seconds to 70 seconds; the process parameters for etching the substrate are that the chamber pressure is 5mT to 15mT, the source power is 350W to 1200W, the bias voltage is 150V to 600V, the gas flow rate is 20sccm to 200sccm, and the etching time is 8s to 60s.

3. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: Before forming the selection gate layer, forming a storage gate dielectric layer on the opening surface and the substrate surface; After forming the storage gate, the storage gate dielectric layer on the surface of the substrate is removed by etching until the surface of the substrate is exposed to form a dielectric layer.

4. The method for forming a semiconductor structure according to claim 3, wherein: The steps of forming a storage gate dielectric layer include: forming a charge tunneling layer on the opening surface and the substrate surface; forming a charge trapping layer on the surface of the charge tunneling layer; A charge blocking layer is formed on the surface of the charge trapping layer.

5. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: Before the step of forming the selection gate layer, forming a gate oxide layer on the substrate and on the storage gate; After the step of forming the selection gate, a spacer is formed on the sidewall of the selection gate.

6. The method for forming a semiconductor structure according to claim 5, wherein: The step of forming a sidewall spacer on the sidewall of the select gate comprises: forming a first silicon oxide layer on the sidewalls of the select gate; forming a silicon nitride layer on a surface of the first silicon oxide layer; A second silicon oxide layer is formed on the surface of the silicon nitride layer.

7. The method for forming a semiconductor structure according to claim 1, wherein: After the step of forming a plurality of discrete selection gates, the method further includes: performing ion implantation on the substrate between the selection gates and the storage gates to form source / drain regions.

8. The method for forming a semiconductor structure according to claim 7, wherein: After the step of forming the source / drain region, the method further comprises: forming an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer covers the source / drain region, the storage gate and the select gate; The interlayer dielectric layer and the gate oxide layer are sequentially etched until the top of the storage gate, the top of the selection gate and the top of the source / drain region are exposed to form contact holes.

9. The method for forming a semiconductor structure according to claim 8, wherein: After the step of forming the contact hole, the method further comprises: Depositing a metal layer on the bottom surface of the contact hole; An annealing process is performed to react the metal layer with the top surface of the source / drain region, the top surface of the storage gate, and the top surface of the select gate to form a metal silicide layer.

10. A semiconductor structure, characterized in that: include: substrate; openings, a plurality of the openings being discretely located in the substrate; A storage gate is located in the opening, and a top surface of the storage gate is flush with a top surface of the substrate; A selection gate is provided, wherein a plurality of the selection gates are separately located on the substrate, and the selection gates are adjacent to the storage gate in a projection direction perpendicular to the substrate.

11. The semiconductor structure according to claim 10, characterized in that: Also includes: A dielectric layer is located on the surface of the opening, wherein the dielectric layer comprises a charge tunneling layer, a charge trapping layer located on the surface of the charge tunneling layer, and a charge blocking layer located on the surface of the charge trapping layer.

12. The semiconductor structure according to claim 10, wherein: Also includes: A gate oxide layer located on the bottom surface of the selection gate, and a sidewall located on the sidewall surface of the selection gate, wherein the sidewall includes a first silicon oxide layer, a silicon nitride layer located on the surface of the first silicon oxide layer, and a second silicon oxide layer located on the surface of the silicon nitride layer.

13. The semiconductor structure according to claim 10, wherein: Also includes: A source / drain region is located in the substrate between the select gate and the storage gate.

14. The semiconductor structure according to claim 13, wherein: Also includes: A metal silicide layer located on the top surface of the source / drain region, the top surface of the storage gate and the top surface of the selection gate, an interlayer dielectric layer located on the substrate, and a contact hole located in the interlayer dielectric layer.

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