Regenerative annealing of metal oxide thin film transistors

Abstract

A method of forming a TFT is provided. The method includes forming a buffer layer over a substrate. A metal oxide channel layer is formed over the buffer layer, and the channel layer is annealed. A gate insulator layer is formed over the channel layer, and an ILD is deposited over the gate insulator layer to form a TFT. The TFT is annealed at a first annealing condition to form an annealed TFT. The annealed TFT is shorted or includes a first threshold voltage of about 0 volts or less. The annealed TFT is annealed at a second annealing condition to form a regenerated TFT, the regenerated TFT having a second threshold voltage greater than the first threshold voltage, the second annealing condition including a temperature of about 150 DEG C to about 275 DEG C.

Description

Background Art

[0001] field

[0002] Embodiments of the present disclosure relate generally to thin film transistor (TFT) devices and methods for processing the devices to achieve enhanced electrical performance and device stability.

[0003] Related technical description

[0004] A thin film transistor (TFT) is formed by depositing a thin film of an active semiconductor layer, a dielectric layer and metal contacts over a supporting substrate such as glass. In particular, the TFT may be a metal oxide semiconductor field effect transistor (MOSFET).

[0005] TFT has aroused great interest in display applications due to their high resolution, low power consumption and high-speed operation for liquid crystal display (LCD) and organic light emitting diode (OLED) displays. TFT is embedded in the panel of the display. The data line voltage signal from the source driver IC in the display module and the scan line voltage signal from the gate driver circuit in the peripheral display panel area in the display panel are delivered to the TFT in the pixel circuit to control the display image by opening and closing the TFT in the active display panel area. By improving the response of TFT with higher mobility and / or by reducing the crosstalk between pixels, image distortion is reduced. Most display products, including LCD or OLED televisions (TV) and monitors, include TFT in the panel. Many modern high-resolution and high-quality electronic visual display devices use OLED displays based on active matrices with a large number of TFTs as components of pixel circuits. One beneficial aspect of TFT technology is that it uses a separate TFT for each pixel on the display. Each TFT acts as a switch or current source in the pixel circuit or gate driver circuit to realize increased control of the display image by controlling the voltage and current through the data signal line and the gate signal line. Higher on-current from high-mobility TFTs allows for faster refresh of displayed images and better image quality by minimizing distortion of data and gate signal voltages.

[0006] During the manufacture of TFTs in certain devices, such as low temperature polycrystalline oxide (LTPO) displays, the TFTs may be sensitive to the integration process, resulting in poor uniformity, excessive conductivity, or electrical shorts. Some techniques have been used to enhance device performance; however, conventional techniques are often only applicable to certain integration processes and have other drawbacks.

[0007] Therefore, there is a need for a method of manufacturing a stable TFT that can be widely deployed for a wide range of TFTs with different integration processes. Summary of the invention

[0008] In some embodiments, a method for forming a thin film transistor (TFT) is provided. The method includes forming a buffer layer over a substrate. A metal oxide channel layer is formed over the buffer layer. The method includes annealing the metal oxide channel layer after forming the metal oxide channel layer. A gate insulator layer is formed over the metal oxide channel layer. The method includes depositing an interlayer dielectric (ILD) over the gate insulator layer to form a TFT. The method includes annealing the TFT for a first annealing condition to form an annealed TFT. The method includes annealing the annealed TFT for a second annealing condition to form a regenerated TFT, the regenerated TFT having a second threshold voltage greater than the first threshold voltage, the second annealing condition including a temperature of about 150°C to about 275°C.

[0009] In some embodiments, a method for forming a thin film transistor (TFT) is provided. The method includes forming a buffer layer over a substrate and forming a metal oxide channel layer over the buffer layer. The method includes annealing the metal oxide channel layer at a temperature of about 140°C to about 240°C for about 5 minutes to about 30 minutes after forming the metal oxide channel layer. A gate insulator layer is formed over the metal oxide channel layer. The gate insulator layer is annealed. The method includes depositing an interlayer dielectric (ILD) over the gate insulator layer and annealing the TFT for a first annealing condition to form an annealed TFT. The method includes annealing the annealed TFT for a second annealing condition in the presence of air to form a regenerated TFT, the regenerated TFT having a second threshold voltage greater than the first threshold voltage. The second annealing condition includes annealing at a temperature of about 150°C to about 275°C.

[0010] In some embodiments, a method for processing a thin film transistor (TFT) is provided. The method includes providing a TFT, the TFT including a silicon-containing buffer layer, a metal oxide channel layer, a gate insulator layer, and an interlayer dielectric (ILD). The TFT is annealed for a first annealing condition to form an annealed TFT. The annealed TFT is annealed for a second annealing condition to form a regenerated TFT. The second annealing condition includes a temperature of about 150°C to about 275°C. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order that the above-stated features of the present disclosure may be understood in detail, a more particular description of the present disclosure briefly summarized above may be made with reference to embodiments, some of which are illustrated in the accompanying drawings. However, it is to be noted that the drawings illustrate only exemplary embodiments and are therefore not to be considered limiting of the scope, and other equally effective embodiments may be admitted.

[0012] Figure 1 A process flow diagram depicts an example method of forming a thin film transistor according to some embodiments.

[0013] Figure 2 Depicted is a schematic cross-sectional side view of a thin film transistor at a stage of fabrication, according to some embodiments.

[0014] Figure 3 Depicted is a schematic cross-sectional side view of a thin film transistor at a stage of fabrication after etching certain portions of a gate insulator layer, in accordance with some embodiments.

[0015] Figure 4 Depicted is a schematic cross-sectional side view of a top gate thin film transistor in accordance with some embodiments.

[0016] Figure 5 Depicted is a schematic cross-sectional side view of a thin film transistor after an implantation process, according to some embodiments.

[0017] Figure 6 Depicted is a schematic cross-sectional side view of a top gate thin film transistor in accordance with some embodiments.

[0018] Figure 7 Depicted is a schematic cross-sectional side view of a TFT after implantation, according to some embodiments.

[0019] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation. DETAILED DESCRIPTION

[0020] Embodiments of the present disclosure generally provide TFT device structures with enhanced electrical performance and stability for display devices and methods of forming the TFT structures. In particular, top gate TFT devices are sensitive to conventional integration processes. Small process variations in operating parameters may result in considerable non-uniformity in the film deposited above the substrate. Forming a low temperature polycrystalline silicon oxide (LTPO) includes forming an interlayer dielectric and annealing the interlayer dielectric. Annealing the TFT may cause the TFT to electrically short or increase the conductivity to a value that makes the TFT unusable for the intended application of the TFT. Conventional methods for solving, preventing or overcoming the TFT short circuit problem have been integration specific, such as modifying the film properties of certain individual layers to achieve uniform and acceptably stable final TFT performance.

[0021] In contrast, the method described herein provides a process for regenerating a short circuit or high conductivity TFT into a TFT usable for LTPO products. Regardless of the process used to integrate the TFT, the regeneration process restores the voltage threshold of the short circuit or high conductivity TFT. In addition, the entire TFT is processed in the process described herein without adjusting the individual layers. The regeneration process includes annealing the TFT at a temperature of about 275°C or lower (such as about 200°C to about 250°C) for 30 minutes to 12 hours (such as about 60 minutes to about 120 minutes).

[0022] Gate insulator layer cutting integration

[0023] Figure 1 A process flow diagram of an example method 100 of forming a thin film transistor according to some embodiments is depicted. Method 100 includes forming a buffer layer over a substrate in activity 102. As used herein, the term "substrate" includes any suitable material, such as a silicon-based substrate, a semiconductor-based substrate, an insulating-based substrate, and a germanium-based substrate. In some embodiments, the substrate includes one or more layers present in an LTPO device. The substrates described herein may include a transparent material, such as rigid glass or flexible polyimide, or other materials useful for displays. In some embodiments, the buffer layer includes an insulating material, such as a silicon-containing material, such as silicon nitride (SiN x ), silicon oxide (SiO x ), multilayer silicon nitride / silicon oxide (SiN x / SiO y ), silicon oxynitride (SiON), other insulating materials, or combinations thereof. Any of the deposited layers herein may be deposited using conventional processes such as chemical vapor deposition, such as plasma enhanced chemical vapor deposition.

[0024] Method 100 includes forming a metal oxide channel layer over the buffer layer in activity 104, and annealing the metal oxide channel layer after forming the metal oxide channel layer in activity 106. The metal oxide channel layer may include InGaZnO, InZnO, InSnO, InGaO, InGaSnO, InGaZnSnO, InGaZnON, ZnO, ZnON, ZnSnO, CdSnO, GaSnO, TiSnO, CuAlO, SrCuO, LaCuOS, GaN, InGaN, AlGaN, InGaAlN, or a combination thereof. In some embodiments, the metal oxide channel layer includes a single layer or multiple sublayers. In some embodiments, the metal oxide channel layer is annealed at a temperature of about 130° C. to about 500° C., such as about 140° C. to about 400° C., for about 5 minutes to about 60 minutes, such as about 10 minutes to about 20 minutes. In some embodiments, the channel layer is deposited to about to about In some embodiments, forming the metal oxide channel layer includes flowing a gas mixture at a pressure of about 0.1 Pa to about 0.8 Pa, such as about 0.2 Pa to about 0.5 Pa. The gas mixture includes about 2% to about 80% by volume, such as about 10% to about 50% by volume, such as about 20% to about 40% by volume, of oxygen.

[0025] In activity 108, a gate insulator layer is formed over the metal oxide channel layer. The gate insulator layer may be formed to be approximately to about The gate insulator layer may include an insulating material such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof. In some embodiments, the gate insulator layer is formed by co-flowing a silicon-containing gas (such as silane) and a nitrogen-containing gas (such as nitrogen oxide). In some embodiments, such as for a 680 mm×880 mm substrate, the silicon-containing gas flows at a rate of about 100 sccm to about 250 sccm (such as about 150 sccm to about 170 sccm), and the nitrogen-containing gas flows at a rate of about 5000 sccm to about 15000 sccm (such as about 10000 sccm).

[0026] The method includes etching a portion of a gate insulator layer in activity 110. In some embodiments, etching the portion of the gate insulator layer includes forming a gate over an inner portion of the gate insulator layer and exposing an outer portion of the gate insulator layer to a plasma, such as a helium-containing plasma. The outer portion of the gate insulator layer is etched to expose portions of a channel layer. These portions of the channel layer are exposed to the plasma.

[0027] In activity 112, an interlayer dielectric is deposited over the gate insulator layer to form a TFT. The interlayer dielectric may be approximately to about In activity 114, the TFT is annealed at a first annealing condition to form an annealed TFT. In activity 116, the annealed TFT can be annealed at a second annealing condition to form a regenerated TFT.

[0028] Figure 2 Depicted is a schematic cross-sectional side view of a thin film transistor at a stage of fabrication, according to some embodiments. Figure 2The TFT can be formed using a method of forming a TFT, such as method 100. The TFT includes a substrate 202, a buffer layer disposed over the substrate 204, such as the buffer layer described in activity 102 of method 100, a channel layer 206, such as the channel layer described in activity 104 of method 100, a gate insulator layer 208, such as the gate insulator layer described in activity 106 of method 100, and a gate electrode 210 disposed over the gate insulator layer 208.

[0029] Figure 3 1. A schematic cross-sectional side view of a TFT is depicted after etching a portion of the gate insulator layer 208 as described in activity 110 of method 100. The portion of the gate insulator layer 208 is etched to expose a portion 306 of the channel layer 206. Figure 4 As shown, interlayer dielectric 412 is deposited over gate electrode 210. A portion of interlayer dielectric 412 is etched to form a connection between portion 306 of channel layer and source electrode 414A and drain electrode 414B. In some embodiments, Figure 4 The depicted TFT is considered to be a top gate TFT formed by a gate insulator cut integration process. In some embodiments, the deposited TFT includes a post-deposition threshold voltage (Vth) of about -5V to about 20V (such as about 0.5V to about 2V, such as about 1V to about 1.5V). In some embodiments, the deposited TFT includes a post-deposition threshold voltage (Vth) of about 12cm 2 / (V·s) to about 14cm 2 The post-deposition electron mobility (μ) of about 100 V·s and the post-deposition subthreshold slope (SS) of about 0.1 V / decade (V / decade) to about 0.6 V / decade (such as about 0.18 V / decade to about 0.25 V / decade).

[0030] After depositing the interlayer dielectric 412, the TFT is annealed with a first annealing condition, as described in activity 112 of method 100. In some embodiments, the first annealing condition includes a first temperature of about 250°C or higher (such as about 260°C to about 280°C), a first duration of about 5 minutes to about 90 minutes (such as about 20 minutes to about 40 minutes). The first annealing condition includes annealing the TFT in the presence of nitrogen. After the first duration, the TFT threshold voltage is reduced to a threshold voltage lower than the post-deposition TFT before the first annealing condition. In some embodiments, after the first duration, the TFT is electrically shorted, or the threshold voltage is negative.

[0031] After annealing the TFT with the first annealing condition, the annealed TFT is transferred to a furnace and heated to a second annealing condition, as described in activity 114 of method 100. The second annealing condition includes annealing the annealed TFT at a second temperature lower than the first temperature. In some embodiments, the second annealing condition includes a temperature of about 275°C or lower (such as about 150°C to about 260°C, such as about 250°C). The second annealing condition includes a second duration of about 30 minutes or longer (such as about 45 minutes to about 12 hours, such as about 60 minutes to about 180 minutes, such as about 90 minutes to about 120 minutes). The second annealing condition includes the presence of air (such as more than 90% air by volume). In some embodiments, the second annealing condition includes a nitrogen-containing gas, an oxygen-containing gas, or a combination thereof. In some embodiments, the second annealing condition includes a vacuum condition. The regenerated TFT includes a threshold voltage greater than the threshold voltage of the annealed TFT, such as about -2.5V to about 1V, such as about -1V to about 0.5V. In some embodiments, the threshold voltage is about 0, such as within about 0.25 V of nearly 0. The regenerated TFT includes an electron mobility substantially the same as after deposition (such as within about 10% of the electron mobility after deposition, such as about 13 cm 2 (V·s) to about 14cm 2 The regenerated TFT includes a subthreshold slope that is substantially the same as the post-deposition subthreshold slope (such as within about 10% of the post-deposition subthreshold slope, such as about 0.1 V / decade to about 0.6 V / decade, such as about 0.18 V / decade to about 0.25 V / decade).

[0032] Ion implantation integration

[0033] Figure 5 A process flow diagram of an example method 500 for forming a thin film transistor using an ion implantation integration process according to some embodiments is depicted. Method 500 includes forming a buffer layer over a substrate in activity 502. In some embodiments, forming the buffer layer in activity 502 is substantially the same as forming the buffer layer as described in activity 102 of method 100.

[0034] Method 500 includes forming a metal oxide channel layer over the buffer layer in activity 504, similar to activity 104, and annealing the metal oxide channel layer after forming the metal oxide channel layer in activity 506, similar to activity 106 of method 100. In some embodiments, the metal oxide channel layer is annealed at a temperature of about 300° C. to about 400° C., such as about 300° C. to about 350° C., for about 30 minutes to about 90 minutes, such as about 30 minutes to about 60 minutes. In some embodiments, the channel layer is deposited to about to about In some embodiments, forming the metal oxide channel layer includes flowing a gas mixture at a pressure of about 0.1 Pa to about 0.8 Pa, such as about 0.2 Pa to about 0.5 Pa. The gas mixture includes about 2% to about 80% by volume, such as about 10% to about 50% by volume, such as about 20% to about 40% by volume, of oxygen.

[0035] In activity 508, a gate insulator layer is formed over the metal oxide channel layer, similar to activity 108 of method 100. The gate insulator layer may be formed to be approximately to about The gate insulator layer may include an insulating material such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof. In some embodiments, the gate insulator layer is formed by co-flowing a silicon-containing gas (such as silane) and a nitrogen-containing gas (such as oxynitride). In some embodiments, such as for a 680 mm by 880 mm substrate, the silicon-containing gas flows at a rate of about 100 sccm to about 250 sccm (such as about 150 sccm to about 170 sccm), and the nitrogen-containing gas flows at a rate of about 5000 sccm to about 15000 sccm (such as about 10000 sccm).

[0036] Method 500 includes implanting ions (such as boron ions) into the metal oxide channel layer in activity 510. In some embodiments, the ions penetrate the gate insulator layer 608, such as Figure 6 As shown, and implanted into the metal oxide channel layer 606 after forming a gate electrode over the gate insulator layer. In some embodiments, the gate insulator layer is annealed at a temperature of about 300° C. to about 360° C. for about 30 minutes to about 90 minutes, such as about 60 minutes, prior to implantation.

[0037] In activity 512, an interlayer dielectric is deposited over the gate insulator layer to form a TFT. In some embodiments, the gate insulator layer is exposed to ions at an implantation energy of about 20 keV to about 60 keV, such as about 30 keV to about 40 keV, wherein the implantation dose is about 10 14 cm 2 to about 10 16 cm 2 In some embodiments, the interlayer dielectric is approximately to about (such as about to about ). In some embodiments, the interlayer dielectric includes multiple layers, such as about to about (such as about to about ) of the first sublayer, about to about The second sublayer (such as about to about ) to about (such as about to about ) of the third sublayer. In activity 514, the TFT is annealed at a first annealing condition to form an annealed TFT. In activity 516, the annealed TFT can be annealed at a second annealing condition to form a regenerated TFT.

[0038] Figure 6 Depicted is a schematic cross-sectional side view of a thin film transistor at a stage of fabrication, according to some embodiments. Figure 6 The TFT can be formed using a method of forming a TFT, such as method 500. The TFT includes a substrate 202, a buffer layer 204 disposed over the substrate 202 (such as the buffer layer 204 described in activity 502 of method 500), a channel layer 206 (such as the channel layer described in activity 504 of method 500), a gate insulator layer 608 (such as the gate insulator layer described in activity 508 of method 500), and a gate electrode 210 disposed over the gate insulator layer 208. A portion 606 of the channel layer 206 includes ions implanted into the portion, such as boron ions.

[0039] Figure 7 5 illustrates a schematic cross-sectional side view of a TFT after implantation as described in method 500. This portion of the gate insulator layer 208 is etched to expose a portion 706 of the channel layer 206. Figure 7 As shown, interlayer dielectric 712 is deposited over gate electrode 210. A portion of interlayer dielectric 412 is etched to form a connection between portion 706 of the channel layer and source electrode 714A and drain electrode 714B. In some embodiments, Figure 7 The depicted TFT is considered to be a top gate TFT formed by an injection integration process. In some embodiments, the deposited TFT includes a post-deposition threshold voltage of about -5V to about 20V (such as about -2.5V to about 1V for an injection TFT without annealing the gate insulator layer, such as about -2.1V to about -1V for a TFT formed by annealing the gate insulator layer, such as about 0.25V to about 0.6V). In some embodiments, the deposited TFT includes about 2.5cm 2 (V·s) to about 15cm 2 (V·s) (such as about 3.0 cm 2 (V·s) to about 3.5cm 2 (V·s), or about 12.0 cm 2(V·s) to about 13.0cm 2 In some embodiments, the post-deposition subthreshold slope (SS) is about 0.1 V / decade to about 0.6 V / decade, such as about 0.15 V / decade to about 0.40 V / decade, such as about 0.18 V / decade to about 0.35 V / decade.

[0040] After depositing the interlayer dielectric 712, the TFT is annealed with a first annealing condition, as described in activity 514 of method 500. In some embodiments, such as for a TFT whose gate insulator layer is not annealed, the first annealing condition includes a first temperature of about 250°C or higher (such as about 300°C to about 380°C), and a first duration of about 5 minutes to about 90 minutes (such as about 20 minutes to about 40 minutes). The first annealing condition includes annealing the TFT in the presence of nitrogen. After the first duration, the TFT threshold voltage is reduced to a threshold voltage lower than the threshold voltage of the TFT after deposition. In some embodiments, after the first duration, the threshold voltage is less than zero, such as about -2V or less, such as about -5V or less, such as about -10V or less. Alternatively, after the first duration, the TFT is electrically shorted.

[0041] After annealing the TFT (wherein the gate insulating layer is not annealed) with the first annealing condition, the annealed TFT is transferred to a furnace and heated to a second annealing condition, as described in activity 516 of method 500. The second annealing condition includes annealing the annealed TFT at a second temperature lower than the first temperature of the first annealing condition. In some embodiments, the second annealing condition includes a temperature of about 275°C or less (such as about 225°C to about 260°C, such as about 250°C). The second annealing condition includes a second duration of about 30 minutes or longer (such as about 45 minutes to about 12 hours, such as about 60 minutes to about 3 hours). In some embodiments, the second annealing condition includes the presence of air (such as more than 90% air by volume). In some embodiments, the second annealing condition includes a nitrogen-containing gas, an oxygen-containing gas, or a combination thereof. In some embodiments, the second annealing condition includes a vacuum condition. The regenerated TFT includes a threshold voltage greater than the threshold voltage of the annealed TFT, such as about -2.5V to about 1V, such as about -1V to about 0.5V. In some embodiments, the threshold voltage is about 0, such as within about 0.25 V of nearly 0. The regenerated TFT includes an electron mobility substantially the same as after deposition (such as within about 10% of the electron mobility after deposition, such as about 12 cm 2 (V·s) to about 14cm 2The regenerated TFT includes a subthreshold slope that is substantially the same as the post-deposition subthreshold slope (such as within about 10% of the post-deposition subthreshold slope, such as about 0.08 V / decade to about 0.25 V / decade).

[0042] In some embodiments, such as for a TFT in which the gate insulator layer is annealed, the first annealing condition includes a single temperature of about 300° C. or higher (such as about 320° C. to about 360° C.) for a single duration of about 5 minutes to about 90 minutes (such as about 10 minutes to about 20 minutes). The first annealing condition includes annealing the TFT in the presence of nitrogen. After the single duration, the TFT is electrically shorted.

[0043] After annealing the TFT with the first annealing condition, the annealed TFT is transferred to a furnace and heated to a second annealing condition, as described in activity 516 of method 500. The second annealing condition includes annealing the annealed TFT at a third temperature lower than the first temperature, the second temperature, a single temperature, or both. In some embodiments, the second annealing condition includes a temperature of about 275°C or lower (such as about 225°C to about 260°C, such as about 250°C). The second annealing condition includes a duration of about 30 minutes or longer (such as about 45 minutes to about 12 hours, such as about 1 hour to about 3 hours, such as about 60 minutes to about 90 minutes). In some embodiments, the second annealing condition includes the presence of air (such as more than 90% air by volume). In some embodiments, the second annealing condition includes a vacuum condition. The regenerated TFT includes a threshold voltage greater than the threshold voltage of the annealed TFT, such as about -2V to about 0.5V, such as about -1V to about 0V. In some embodiments, the threshold voltage is about 0, such as within about 0.5V of almost 0. The regenerated TFT includes an electron mobility substantially the same as after deposition (such as within about 10% of the electron mobility after deposition, such as about 13 cm 2 (V·s) to about 15cm 2 The regenerated TFT includes a subthreshold slope that is substantially the same as the post-deposition subthreshold slope (such as within about 10% of the post-deposition subthreshold slope, such as about 0.1 V / decade to about 0.3 V / decade).

[0044] Example

[0045] For each of the integration processes described in Table 1, several samples were formed.

[0046] Table 1 - Integration details

[0047]

[0048] Each of the integration types B1, B2 and B3 is formed by depositing a layer having a thickness of about A silicon nitride layer having a thickness of about 100 mm is formed on the silicon nitride layer. The integrated type B1 and B2 substrates further include a silicon oxide layer having a thickness of about 1000 nm deposited at a pressure of 0.2 Pa. IGZO channel layer. The integrated type B3 substrate further includes an IGZO channel layer deposited at a pressure of about 0.4 Pa. For each of the integrated types B1, B2 and B3, depositing the channel layer includes exposing the substrate to a gas mixture comprising argon, oxygen, or a combination thereof. In some embodiments, one or more target materials are sputtered by oxygen or argon in the gas mixture. In some embodiments, the target materials to be sputtered include indium, gallium, zirconium, and a combination thereof. For integrated types B1 and B2, the mixture contains approximately 20% oxygen by volume. For integrated type B3, the mixture contains approximately 50% oxygen by volume. For integrated types B1 and B2, the IGZO channel layer is annealed at approximately 350°C for 1 hour. For integrated type B3, the IGZO channel layer is annealed at approximately 141°C for 10 minutes. For each of B1, B2 and B3, a gate insulator layer is deposited over the IGZO layer at a temperature of approximately 270°C to approximately 280°C. The gate insulator layer is deposited to approximately The gate insulator was deposited to a thickness of . The gate insulator was deposited by co-flowing silane and nitrous oxide. For B3, the gate insulator was annealed at about 330° C. for 1 hour. For integration types B2 and B3, the samples were exposed to boron ion implantation as described in method 500. For integration type B1, the samples were formed using the gate insulator cut integration process described in method 100. The samples formed using integration types B1 and B2 included The samples formed using the integrated B3 include an interlayer dielectric having a thickness of about (e.g., SiO sublayer), (e.g., SiO sublayer) and Three sub-layers (e.g., SiN sub-layers) with a thickness of 100 Å.

[0049] Table 2 - Properties before and after regeneration annealing

[0050]

[0051] Table 2 summarizes the threshold voltage, electron mobility, and subthreshold voltage values ​​of substrates formed using integration type B1 before ILD annealing. The substrate formed using integration type B1 was shorted after ILD annealing at a temperature of about 300°C for 15 minutes. The shorted TFT was then annealed at a lower temperature of about 250°C in the presence of air for about one hour. The TFT was regenerated with a negative threshold voltage. The TFT was further annealed for an additional hour and the threshold voltage was increased to near zero.

[0052] Table 2 summarizes the threshold voltage values ​​of substrates formed using integration type B2 after deposition and before ILD annealing. Table 2 also summarizes the current, gate voltage values ​​of sample TFTs after ILD annealing at 275°C for about 30 minutes in the presence of a nitrogen-containing gas. The threshold voltage values ​​of the annealed substrates shift to a more negative threshold voltage compared to the samples before annealing. Highly conductive TFTs are unusable for the intended purpose of the TFTs. Typically, short-circuited or highly conductive TFTs are discarded as unusable. The highly conductive TFTs are then annealed at a lower temperature of about 250°C in the presence of air for about one hour, and the threshold voltage is shown to be regenerated to near zero, as shown in Table 2.

[0053] The threshold voltage values ​​of the substrate formed using the integrated type B3 after deposition and before ILD annealing are summarized in Table 2. Table 2 summarizes the threshold voltage, electron mobility, and subthreshold voltage. The TFT was ILD annealed at 340°C for about 15 minutes in the presence of a nitrogen-containing gas and short-circuited. The short-circuited TFT was then annealed at a lower temperature of about 250°C in the presence of air for about one hour, as shown in Table 2. The TFT was regenerated with a threshold voltage close to zero.

[0054] As shown by the examples, it has been found that the low temperature annealing method described herein is effective for a wide variety of TFTs, regardless of how the TFTs are integrated. In addition, the annealing method described herein exhibits higher threshold voltage uniformity on several samples of TFTs formed using the same process than the threshold voltage uniformity of the TFTs before the low temperature annealing. In particular, a bias temperature stress test can be performed on the post-deposition TFT before regeneration, and the post-deposition TFT shows more variation between TFTs integrated using the same integration process. The same bias temperature stress test can be performed on the regenerated TFT. The regenerated TFT treated using any of the methods described herein exhibits less variation and higher stability than the post-deposition TFT. The stability test may include applying a gate voltage, such as a voltage of about 10V to about 30V, to the gate electrode of the TFT. The TFT may be heated to about 50°C to about 70°C for a predetermined duration, such as about 300 seconds, 600 seconds, 900 seconds, 1800 seconds, or 3600 seconds, to observe whether the TFT transfer curve moves within one or more of the predetermined durations, such as each of the durations 300 seconds, 600 seconds, 900 seconds, 1800 seconds, and 3600 seconds. Less movement indicates stability, while more movement indicates lower stability. Both negative and positive voltages may be used to test the TFT.

Claims

1. A method for forming a thin film transistor (TFT), the method comprising: forming a buffer layer over the substrate; forming a metal oxide channel layer above the buffer layer; annealing the metal oxide channel layer after forming the metal oxide channel layer; forming a gate insulator layer over the metal oxide channel layer; depositing an interlayer dielectric (ILD) over the gate insulator layer to form the TFT; annealing the TFT for a first annealing condition to form an annealed TFT, wherein the annealed TFT is a short circuit or includes a first threshold voltage; as well as The annealed TFT is annealed for a second annealing condition to form a regenerated TFT, the regenerated TFT having a second threshold voltage greater than the first threshold voltage, the second annealing condition comprising a temperature of about 150°C to about 275°C. 2 . The method of claim 1 , further comprising annealing the gate insulator layer at a temperature of about 200° C. to about 350° C. for about 60 minutes to about 120 minutes after forming the gate insulator layer.

3. The method of claim 1, wherein the first annealing condition comprises annealing in the presence of a nitrogen-containing gas.

4. The method of claim 1, wherein forming the metal oxide channel layer comprises flowing a gas mixture at a pressure of about 0.1 Pa to about 0.8 Pa, the gas mixture comprising about 2% to about 80% oxygen by volume.

5. The method of claim 1, wherein the metal oxide is selected from indium gallium zinc oxide (IGZO), InGaZnON, ZnO, ZnON, ZnSnO, CdSnO, GaSnO, TiSnO, CuAlO, SrCuO, LaCuOS, GaN, InGaN, AlGaN, InGaAlN, or a combination thereof. The method of claim 1 , wherein the buffer layer comprises silicon nitride, silicon oxide, or a combination thereof.

7. The method of claim 1, wherein the first annealing condition comprises annealing the TFT at a temperature of about 250°C or higher for a first duration.

8. The method of claim 1, wherein the second annealing condition comprises annealing for about 30 minutes to about 12 hours.

9. The method of claim 1, further comprising doping the metal oxide channel layer with ions.

10. A thin film transistor (TFT), comprising: a buffer layer, the buffer layer being above the substrate; a metal oxide channel layer, the metal oxide channel layer being disposed above the buffer layer; a gate insulator layer disposed over the metal oxide channel layer; as well as An interlayer dielectric (ILD) is disposed over the gate insulator layer, wherein the TFT is annealed for a first annealing condition to reduce a threshold voltage of the TFT and then annealed for a second annealing condition to increase the threshold voltage of the TFT to about 0V or more.

11. The TFT of claim 10, wherein the metal oxide channel layer is deposited to about to about Thickness.

12. The TFT of claim 10, further comprising an interlayer dielectric, the interlayer dielectric having a first sublayer, a second sublayer and a third sublayer, the first sublayer having a thickness of about to about The first sublayer has a thickness of about to about The second thickness of the third sublayer is about to about The thickness of the third sublayer is .

13. The TFT of claim 10, further comprising an interlayer dielectric having a dielectric thickness of about Peace Thickness.

14. The TFT of claim 10, wherein the first annealing condition comprises annealing the TFT at a temperature of about 300°C or higher for about 5 minutes to about 90 minutes.

15. The TFT of claim 10, wherein the second condition comprises a duration of about 30 minutes to about 12 hours.

16. A method for processing a TFT, the method comprising: providing the TFT, the TFT comprising a silicon-containing buffer layer, a metal oxide channel layer, a gate insulator layer, and an interlayer dielectric (ILD); annealing the TFT at a first annealing condition to form an annealed TFT, the annealed TFT having a first threshold voltage; as well as The annealed TFT is annealed for a second annealing condition to form a regenerated TFT, the regenerated TFT having a second threshold voltage greater than the first threshold voltage, the second annealing condition comprising a temperature of about 150°C to about 275°C.

17. The method of claim 16, wherein the annealed TFT is either an electrical short or at the first threshold voltage of about 0 volts or less.

18. The method of claim 16, wherein the first annealing condition comprises annealing the TFT at a temperature of about 250°C or higher.

19. The method of claim 16, wherein the second threshold voltage of the regenerated TFT is about 0V or greater.

20. The method of claim 16, wherein an electron mobility of the regenerated TFT is equal to or greater than an electron mobility of the TFT before annealing.

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