Stress calibration method and corresponding electronic equipment

Abstract

The embodiment of the invention relates to a stress calibration method and corresponding electronic equipment. A test circuit includes a set of electronic switches having a current path between a first node and a ground node, where each electronic switch has a respective control node. A set of coupling channels has one end coupled to a common test node and another end coupled to a respective control node of the electronic switch. A stress voltage supply is coupled to the common test node. A set of comparator circuits includes a comparator circuit having a first input node coupled to a control node of a respective electronic switch of the set of electronic switches via a sense circuitry and having a second node coupled to a threshold voltage node. A method of operating a test circuit is also disclosed.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Italian Patent Application No. 102023000015036, filed on Jul. 18, 2023, which is incorporated herein by reference. Technical Field

[0003] The present invention relates to a stress calibration method and corresponding electronic equipment. Background Art

[0004] ECU or engine control module (ECM for short) is an electronic control unit that is configured to process signals from sensors and is configured to control a series of actuators equipped on an (e.g., internal combustion or electric) engine based on signals received from sensors equipped on the engine. ECU may include electrical loads such as sensors, light emitting diodes, and other loads such as resistive load circuits and / or inductive load circuits.

[0005] The power transistors used in the half-bridge arrangement can be reliability tested during their manufacture. For example, a pulsed gate stress test (gate stress for short) method includes a method for identifying defects that may appear during the use of the IC or even after a period of time if the test is not performed and / or the test is invalid. For example, the gate stress method is performed at the wafer level for quality inspection. The application of gate stress can include a test circuit that uses a dedicated pad coupled to the internal gate of the power MOSFET under test.

[0006] The gate stress test includes, for example, measuring a first gate leakage current before applying voltage stress to the transistor. -3 s), a stress voltage equal to or higher than an absolute maximum rating (AMR parameter), which is the maximum voltage that an electronic component can withstand between its (e.g., gate-source) terminals without damage, is applied. When the test time interval elapses, a second gate leakage current is measured, and a comparison of the first gate leakage current and the second gate leakage current is performed.

[0007] In the event that the comparison results in the second current being greater than the first current, this may indicate the presence of a latent gate oxide defect in the transistor, not visible during normal operation at room temperature, which is activated, for example, in response to stress voltage application. Thus, the transistor under test may be flagged as faulty.

[0008] The device including the integrated power MOSFET may also include a gate-source voltage comparator configured to generate a first (e.g., "high" or "1") state in response to the voltage across the gate and source terminals of the power transistor being above a threshold during the on-phase. The output of the comparator may be used for different purposes in the functional mode (such as overload diagnostic structure, dead time management, etc.).

[0009] During the gate stress process, the current drawn by the low-side driver circuit device (especially a multi-channel device) can be considerable (e.g., in the range of 10 mA, 1 mA = 10 mA = 10 mA). -3 A).

[0010] This can result in a similarly significant voltage drop across internal metal connections, for example between the pad used to apply the stress voltage with an EWS probe (testing at wafer level) and the effective gate-source voltage applied during stress.

[0011] Such conditions can be difficult to detect and may result in a lack of effective pressure on all or some drivers. Also at the analog level, this phenomenon can be difficult to understand without taking into account metal connections and parasitic components.

[0012] Any discrepancies between simulation results and automated test equipment (ATE)-level measurements may indicate a significant risk of underperforming parts during pre-production steps (eg, due to failures such as "burn-in" testing or field returns). Summary of the invention

[0013] The present description relates to methods and systems for testing circuits, such as low-side driver circuits including, for example, metal oxide semiconductor field effect (MOS-FET) transistors.

[0014] One or more embodiments may be applied to an integrated circuit (IC) including a power MOSFET, such as, for example, an engine control unit (ECU) of an automotive engine management system (EMS).

[0015] One or more embodiments can help alleviate the above problems. For example, the proposed solution can better control the stress voltage applied during the gate stress process.

[0016] One or more embodiments may relate to a corresponding test circuit.

[0017] One or more embodiments may relate to a corresponding vehicle.

[0018] One or more embodiments include comparing a stress voltage applied during testing to an internal threshold.

[0019] One or more embodiments may result in improved control of the gate stress process.

[0020] One or more embodiments overcome the risk of undesirably stressing the power MOSFET gate during the testing phase.

[0021] One or more embodiments help reduce the probability of aging failures and / or field returns related to gate oxide defects.

[0022] One or more embodiments facilitate obtaining quick feedback from test equipment indicating the effective gate voltage applied to a single power (eg, MOSFET) transistor under test. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] One or more embodiments will now be described, by way of non-limiting example only, with reference to the accompanying drawings, in which:

[0024] Figure 1 is an exemplary diagram of a circuit according to the present disclosure,

[0025] Figure 2 is an exemplary diagram of a circuit according to the present disclosure,

[0026] Figure 3 is an exemplary diagram of a test device according to the present disclosure,

[0027] Figure 4 is an exemplary diagram of a vehicle according to the present disclosure.

[0028] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated.

[0029] The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale. The edges of features drawn in the figures do not necessarily indicate the end of the extent of the features. DETAILED DESCRIPTION

[0030] In the subsequent description, one or more specific details are illustrated to provide a deeper understanding of the embodiments of the present description. These embodiments can be obtained without one or more specific details, or using other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not illustrated or described in detail so that certain aspects of the embodiments will not be obscure.

[0031] References to "an embodiment" or "one embodiment" in the framework of this specification are intended to indicate that a particular configuration, structure, or characteristic described with respect to the embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in one embodiment" that may appear in one or more points of this specification do not necessarily refer to the same embodiment.

[0032] Furthermore, particular configurations, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0033] The references used herein are provided for convenience only and therefore do not limit the scope of protection or the scope of the embodiments.

[0034] For simplicity, in the following detailed description, the same reference numerals may be used to represent both a node / line in a circuit and a signal that may appear at the node or line.

[0035] like Figure 1 As illustrated, a circuit 10 for performing a stress test at a control terminal GQ (e.g., gate terminal) of a (e.g., MOSFET) transistor Q includes a test input node TEST_PAD configured to be coupled to a power supply configured to generate a stress voltage to perform a test of the circuit 10. For example, a total current equal to the sum Igs1+Igs2+…+Igsn may be provided. The currents Igs1,…,Igsn flowing in a set of test channels 101,…,10n for electronic switches Q1,…,Qn are discussed below.

[0036] A group of electronic switches Q1, ..., Qn has a corresponding control node G1, ..., Gn, which is configured to be coupled to a test input node TEST_PAD to be tested. A group of test channels 101, ..., 10n couples the test input node TEST_PAD to the control node G1, ..., Gn of the corresponding electronic switch in the group of electronic switches Q1, ..., Qn. For example, each test channel in the group of test channels 101, ..., 10n may include a series arrangement of a resistor element and a diode of a resistor element R1, ..., Rn and a diode D1, ..., Dn belonging to the corresponding group.

[0037] A set of driver circuits 121, ..., 12n is provided. Each driver circuit in the set of driver circuits 121, ..., 12n is configured to provide a respective control signal to a respective control terminal G1, ..., Gn of a respective electronic switch in the set of electronic switches Q1, ..., Qn at a respective driver output node in a set of driver output nodes 1211, ..., 121n.

[0038] A set of (e.g., voltage) comparator circuits 141, ..., 14n are coupled to a reference node V_REF to receive a reference (e.g., voltage) value V_REF therefrom and are coupled to the set of electronic switches Q1, ..., Qn. Each comparator circuit in the set of comparator circuits 141, ..., 14n includes a respective first input node 1411, ..., 14n1 coupled to a respective output node 1211, ..., 12n1 of a respective driver circuit in the set of driver circuits 121, ..., 12n and a second input node 1412, ..., 14n2 coupled to the reference node V_REF.

[0039] A set of coupling circuit blocks 161, ..., 16n is disposed between first input nodes 1411, ..., 14n1 of the comparator circuits in the set of comparator circuits 141, ..., 14n and control nodes G1, ..., Gn of the electronic switches in the set of electronic switches Q1, ..., Qn. The coupling circuit blocks in the set of coupling circuit blocks 161, ..., 16n include circuit devices configured to selectively couple the control nodes G1, ..., Gn of the electronic switches in the set of electronic switches Q1, ..., Qn to the comparator circuits in the set of comparator circuits 141, ..., 14n.

[0040] For example, each comparator circuit in the set of comparator circuits 141, ..., 14n is configured to be coupled to each corresponding control node of the electronic switch via a coupling circuit block in the set of coupling circuit blocks 161, ..., 16n, and perform a comparison between a reference value V_REF and a (e.g., voltage) signal sensed at a control node of a corresponding device under test Q1, ..., Qn. The comparator circuits 141, ..., 14n are also configured to generate a corresponding comparison signal VGS_COMP1, ..., VGS_COMPn as a result.

[0041] like Figure 1 As illustrated, the reference value V_REF is greater than a minimum stress voltage (eg, V_REF>V_STRESS_MIN) that the circuit 10 is designed to deliver to the device under test in the set of electronic switches Q1 , . . . , Qn.

[0042] As illustrated herein, each comparator in the group of comparators is configured to detect whether an actual signal sensed at a corresponding control node (e.g., G1) of a corresponding device under test (e.g., Q1) in the group of electronic switches Q1, …, Qn exceeds or does not exceed (in other words, reaches or does not reach) a reference voltage value V_REF in response to a stress test voltage V_STRESS_MIN being applied at a test input node TEST_PAD.

[0043] For example, when it is compared that the sensed signal does not exceed the reference value V_REF, the stress test voltage V_TEST_MIN is repeatedly applied to the i-th switch (eg, the first switch Q) in the group of electronic switches Q1 , . . . , Qn.

[0044] Figure 2 An alternative circuit 10' is shown in which a single comparator 140 is used for an electronic switch (e.g., the first electronic switch Q1) in the group of electronic switches Q1, ..., Qn. Such examples are merely exemplary and are by no means limiting, otherwise it should be understood that Figure 2 The embodiment shown can be used with Figure 1 The implementation method is combined with Figure 2 The channel-specific blocks shown are repeated for a subset or all channels of the electronic switch under test.

[0045] The circuit 10' is configured to facilitate applying a stress voltage at a control terminal GQ of at least one transistor under test Q1. The driver circuit 120 is configured to provide a corresponding control signal to a corresponding control terminal G1 of the first electronic switch Q1 at a corresponding driver output node 1201. The comparator circuit 140 includes a first input node 1401 and a second input node 1402, the first input node 1401 is coupled to the output node 1201 of the driver circuit 120, and the second input node 1402 is coupled to a reference node V_REF. The comparator circuit 140 is configured to generate a comparison signal VGS_COMP based on a comparison of the signals received at the input nodes 1401, 1402.

[0046] The coupling circuit 160 is disposed between the first input node 1401 of the comparator circuit 140 and the control node G1 of the first electronic switch Q1. The coupling circuit 160, which comprises a circuit arrangement, is configured to selectively couple the control node G1 of the first electronic switch Q1 to the comparator circuit 140.

[0047] The supply voltage node V3V3 is configured to provide a supply voltage level, for example 2.7 volts. The voltage threshold generator circuit block 22 includes (e.g., resistor) voltage dividers R4, R5 placed between the supply voltage V3V3 and the ground GND. The voltage threshold source 22 is coupled to the second input node 1402 of the voltage comparator 140 to provide a voltage threshold level V_REF thereto.

[0048] like Figure 2As shown in the example of FIG. 1 , the coupling circuit 160 includes a first switch SW1 and a second switch SW2, the first switch SW1 being placed between the output node 1201 of the driver circuit 120 and the first input node 1401 of the voltage comparator 140, and the second switch SW2 being placed between the first input node 1401 of the comparator 140 and a group of resistor elements R1, R2 (which includes a first resistor element R1 connected in series with a second resistor element R2). The group of resistor elements R1, R2 is arranged between the control node G1 of the first electronic switch Q1 and the output node 1201 of the driver circuit 120.

[0049] The third switch SW3 is disposed between the third resistor element R3 and the ground GND, and the third resistor element R3 has one end coupled to the set of resistor elements R1, R2 (specifically, between the first resistor element and the second resistor element). The inverter circuit 1601 is coupled to the first switch SW1 and is configured to receive the calibration enable signal TS to operate the switch SW1.

[0050] like Figure 2 As shown, the first SW1, the second SW2, and the third SW3 switches are each configured to switch between a first (“closed” or “ON”) state and a second (“disconnected” or “OFF”) state based on the calibration enable signal TS. In the first state, they are conductive, and in the second state, they are not conductive. Specifically, due to the presence of the inverter circuit 1601, only one of the first SW1 and the second SW2 can be conductive at the same time.

[0051] In one or more embodiments, using a portion of the supply voltage V3V3 as a reference voltage facilitates the calibration process to define a minimum stress voltage level.

[0052] In one embodiment, a method for calibrating a gate stress process includes asserting a calibration enable signal TS with a first logic value (e.g., "1" or "true"), thereby switching the first switch SW1 to a second off state, while simultaneously switching the second switch SW2 and the third switch SW3 to a first on state. A calibration voltage level (e.g., a multiple of about 100 mV step size) is applied to a test pad node, the test pad node is coupled to a first test channel 101, and the first test channel is coupled to a first electronic switch Q1.

[0053] After applying the stress test voltage, the control voltage sensed at the control node G1 of the first electronic switch Q1 is received at the first input node 1401 of the comparator 140 through the resistor divider formed by the resistor elements R1 , R2 , R3 .

[0054] A threshold reference voltage V_REF is provided at a second input node 1402 of the comparator circuit 140. A comparison of the sensed control voltage with the threshold reference voltage V_REF is performed, and a comparison signal VGS_COMP is generated, as a result, having a first logic value (e.g., "1" or "high") in response to the sensed control voltage exceeding the threshold reference voltage V_REF, and a second logic value (e.g., "0" or "low") in response to the sensed control voltage not exceeding the threshold reference voltage V_REF.

[0055] In response to the comparison signal VGS_COMP having the second logic value, the calibration voltage level is increased (e.g., in steps of about 100 mV), and the operations of the method discussed above are repeated until the comparison signal VGS_COMP has reached the first logic value. This operation provides an indication of an effective stress voltage level V_STRESS_MIN equal to the calibration voltage that produces the first logic value of the comparison signal VGS_COMP, which is provided, for example, to a user circuit device such as an engineering workstation (EWS).

[0056] At the end of the calibration process, ie, after obtaining the value of the effective stress voltage level V_STRESS_MIN, the calibration enable signal TS is asserted to a second logic level (eg, “0” or “low”) to couple the first input node 1401 of the comparator circuit 140 to the output node 1201 of the driver circuit 12 .

[0057] like Figure 2 As shown, the resistance elements R1, R2, R3 of the coupling circuit 160 and the resistance elements R4, R5 in the threshold voltage generator circuit block 22 may have resistance values ​​linked by a certain relationship between them. For example, the first resistance element R1 and the second resistance element R2 may have resistance values ​​equal to the resistance value of the fourth resistance element R4 in the threshold voltage generator circuit block 22. The third resistance element R3 may have a resistance value equal to the resistance value of the fifth resistance element R5 connected in series with the fourth resistance element in the threshold voltage generator circuit block 22.

[0058] As described herein, the resistor elements R1, R2, R3 of the coupling circuit 160 are designed to protect the CMOS driver from excessive stress voltages during the test phase. For example, for a 4.6 volt AMR, the maximum voltage applicable to the driver may be about 3.6 volts, while during the gate stress process, the voltage may reach a value of about 6 volts.

[0059] Thanks to the use of the coupling circuit 160 , it is possible to utilize a reference voltage VREF which is a fraction of the internal supply voltage V3V3 (eg 3.3 Volts) without risking having to use a higher value (eg 6 Volts).

[0060] like Figure 3 As shown in the example, an electronic device 30 (for example, to be used in the test production phase) includes an internal power supply source 20, which is configured to be coupled to a voltage generator to apply a stress voltage V_STRESS_MIN (obtained as a result of a calibration process) to the circuit 10, 10' through the TEST_PAD node thereof to verify its state.

[0061] Figure 4 An example of one or more embodiments of a (e.g., wheeled and / or electric) vehicle V is provided, the vehicle V comprising a set of electronic control units 40, 50 coupled to a set of devices 30 according to the present disclosure, for example, equipped with a set of power MOSFETs that have been tested according to the methods of the present disclosure.

[0062] like Figure 3 As illustrated, the device 30 includes the circuit 10, 10' according to the present disclosure, and a power supply V_STRESS_MIN configured to provide a stress voltage. Figure 4 As shown, the electronic device 30 may be equipped on an autonomous vehicle V (eg, an electric autonomous vehicle).

[0063] Thus, one or more embodiments may provide improved robustness against failures of power MOSFETs utilized by an on-vehicle ECU 40, 50. This may be beneficial in meeting safety requirements in the automotive field.

[0064] For example, in accordance with the present disclosure, an energy management system (EMS) unit 40 configured to manage energy of the vehicle V is coupled to the device 30 .

[0065] The method exemplified herein includes providing a set of electronic switches Q1, ..., Qn having a current line passing between a power supply node VDD and a ground GND. Each electronic switch in the set of electronic switches includes a corresponding control node G1, ..., Gn to receive a calibrated stress test voltage V_STRESS_MIN.

[0066] One end of a coupling channel in a group of coupling channels 101, ..., 10n is coupled to a common test node TEST_PAD, and the other end of a coupling channel in a group of coupling channels is coupled to a corresponding control node of an electronic switch in the group of electronic switches. The group of coupling channels is configured to propagate the application of a test voltage V_STRESS_MIN from the common test node to the corresponding control node of the electronic switch in the group of electronic switches. Based on an enable calibration signal TS having a first logic value, a first input node of a comparator circuit in a group of comparator circuits 140; 141, ..., 14n is coupled to a control node of a corresponding electronic switch in the group of electronic switches.

[0067] The threshold voltage level V_REF is provided to the second input node of the comparator circuit in the group of comparator circuits. The test voltage is applied to the common node TEST_PAD. A set of control voltages is sensed at the first input node of the group of comparators. The set of control voltages includes a control voltage sensed at the control node of the electronic switch in the group of electronic switches.

[0068] A set of comparisons 140; 141, ..., 14n of the group of sensed control voltages and a threshold reference voltage are performed to generate a set of comparison signals VGS_COMP; VGS_COMP1, ..., VGS_COMP2, the set of comparison signals having a first logic value in response to a sensed control voltage in the sensed group of control voltages exceeding the threshold reference voltage, and a second logic value in response to a sensed control voltage in the sensed group of control voltages not exceeding the threshold reference voltage.

[0069] In response to at least one comparison signal VGS_COMP in the set of comparison signals VGS_COMP1, ..., VGS_COMP2 having a second logic value, increasing the test voltage applied at the common test node. In response to each comparison signal in the set of comparison signals having a first logic value, interrupting the set of comparisons and increasing the test voltage applied at the common test node. The value reached by the test voltage applied at the common test node is provided to the user circuit as a calibrated stress test voltage value.

[0070] For example, in response to a calibration enable signal having a first logic value, at least one resistor divider R1, R2, R3 is coupled (e.g., via switch SW2) to a control node of an electronic switch in the group of control switches. As a result, a sensed control voltage is sensed via at least one resistor divider. A supply voltage level V3V3 is coupled at one end of a series arrangement of resistor elements referenced to grounds R4, R5, resulting in a threshold reference voltage being provided at a node in the middle of the series arrangement. The resistor elements in the resistor divider have resistance values ​​based on the resistance values ​​of the resistor elements in the series arrangement of the resistor elements coupled to the supply voltage level.

[0071] As illustrated herein, the set of electronic switches is coupled to a set of drive circuits 120; 121, ..., 12n. The control nodes of the electronic switches in the set of electronic switches are coupled to the output nodes 1201; 1211, ..., 121n of the corresponding drive circuits in the set of drive circuits. Each control node is configured to receive a control signal from the corresponding drive circuit. The current line is configured to be at least partially conductive or non-conductive based on the logic value of the control signal.

[0072] As illustrated herein, the electronic switches of the set of electronic switches comprise transistors, preferably MOSFET transistors.

[0073] For example, increasing the test voltage includes gradually increasing the test voltage from a minimum voltage level to a maximum voltage level, preferably increasing the test voltage in steps of about 100 mV.

[0074] Figures 1 to 3 The test circuit 10, 10', 30 illustrated in any one of the examples includes a set of electronic switches Q1, ..., Qn, which are configured to have a current line passing between a first node VDD and a ground GND. Each electronic switch in the set of electronic switches includes a corresponding control node to receive a calibrated stress test voltage V_STRESS_MIN.

[0075] A set of coupling channels 101, ..., 10n has one end coupled to a common test node TEST_PAD and another end coupled to respective control nodes G1, ..., Gn of electronic switches in the set of electronic switches. The set of coupling channels 101, ..., 10n is configured to propagate the application of a test voltage V_STRESS_MIN from the common test node to respective control nodes G1, ..., Gn of electronic switches in the set of electronic switches.

[0076] The threshold voltage node is configured to receive a threshold voltage V_REF, and the stress voltage supply source is configured to apply a calibrated stress test voltage to the common node. A set of comparator circuits 140; 141, ..., 14n includes a comparator circuit having a first input node coupled to a control node of a corresponding electronic switch in the set of electronic switches via a sensing circuit device (e.g., R1, R2, R3). The comparator circuit has a second node coupled to the threshold voltage node.

[0077] The sensing circuit device is configured to sense a set of control voltages at control nodes of the electronic switches in the set of electronic switches. The set of comparator circuits is configured to perform a set of comparisons of the sensed set of control voltages with a threshold reference voltage and generate a set of comparison signals, the set of comparison signals having a first logic value in response to the sensed control voltages in the sensed set of control voltages exceeding the threshold reference voltage, and a second logic value in response to the sensed control voltages in the sensed set of control voltages not exceeding the threshold reference voltage, the set of comparators being configured to provide the set of comparison signals VGS_COMP; VGS_COMP1, ..., VGS_COMP2 to the user circuit.

[0078] like Figures 1 to 3 As exemplified in any one of the embodiments, the sensing circuit device includes at least one resistor divider R1, R2, R3 referenced to ground, the resistor divider being coupled to the control node of the electronic switch in the group of control switches, resulting in the sensed control voltage being sensed via the at least one resistor divider. The threshold voltage node is coupled to a supply voltage level V3V3 at one end of the series arrangement of resistor elements referenced to ground R4, R5, resulting in a threshold reference voltage V_REF being provided at a node in the middle of the series arrangement. The resistor elements in the resistor divider have resistance values ​​based on the resistance values ​​of the resistor elements in the series arrangement of the resistor elements.

[0079] like Figures 1 to 3 As illustrated in any one of the examples, the group of electronic switches is coupled to a group of drive circuits 120; 121, ..., 12n, and the control nodes of the electronic switches in the group of electronic switches are coupled to the output nodes 1201; 1211, ..., 121n of the corresponding drive circuits in the group of drive circuits. Each control node is configured to receive a control signal from the corresponding drive circuit. The current line is configured to be conductive or non-conductive based on the logic value of the control signal.

[0080] like Figures 1 to 3 As illustrated in any one of the embodiments, the electronic switches in the set of electronic switches include transistors, preferably MOSFET transistors.

[0081] like Figure 4 As illustrated, a vehicle (e.g., a battery-powered wheeled vehicle) may be equipped with Figures 1 to 3 A test circuit 10, 10', 30 of any one of the above.

[0082] It should be understood that the various individual implementation options illustrated in this specification with reference to the accompanying drawings are not necessarily intended to be employed in the same combination illustrated in the accompanying drawings. Therefore, one or more embodiments may employ these (otherwise non-mandatory) options individually and / or in different combinations relative to the combinations illustrated in the accompanying drawings.

[0083] Without prejudice to the essential principles, the details and embodiments may vary, even significantly, with respect to what has been described merely by way of example, without departing from the scope of protection, which is defined by the appended claims.

Claims

1. A method comprising: providing a set of electronic switches having a current path between a supply node and ground, wherein each electronic switch in the set of electronic switches includes a corresponding control node to receive a stress test voltage; coupling one end of a coupling channel in a set of coupling channels to a common test node, and coupling the other end of the coupling channel in the set of coupling channels to respective control nodes of electronic switches in the set of electronic switches, wherein the set of coupling channels is configured to propagate application of a test voltage from the common test node to respective control nodes of the electronic switches in the set of electronic switches; coupling a first input node of a comparator circuit in a group of comparator circuits to the control node of a corresponding electronic switch in the group of electronic switches based on an enable calibration signal having a first logic value; providing a threshold voltage level to a second input node of a comparator circuit in the set of comparator circuits; applying the test voltage to the common test node; sensing a set of control voltages at the first input nodes of the set of comparators, the set of control voltages comprising control voltages sensed at the control nodes of the electronic switches in the set of electronic switches; performing a set of comparisons of the sensed set of control voltages with the threshold voltage level, thereby generating a set of comparison signals having the first logic value in response to a sensed control voltage of the sensed set of control voltages exceeding the threshold voltage level and a second logic value in response to a sensed control voltage of the sensed set of control voltages not exceeding the threshold voltage level; In response to at least one comparison signal of the set of comparison signals having the second logic value, increasing the test voltage applied at the common test node; in response to each comparison signal in the set of comparison signals having the first logic value, interrupting execution of the set of comparisons and increasing a test voltage applied at the common test node; as well as A value reached by the test voltage applied at the common test node is provided to the user circuit as a calibrated stress test voltage value.

2. The method according to claim 1, comprising: coupling at least one resistor divider to a control node of the electronic switch in the set of control switches to sense the sensed control voltage via the at least one resistor divider in response to the calibration enable signal having the first logic value; as well as A supply voltage level is coupled at one end of a series arrangement of ground-referenced resistor elements, thereby providing the threshold voltage level at a node in the middle of the series arrangement as a result, wherein the resistor elements in the resistor divider have resistance values ​​based on the resistance values ​​of the resistor elements in the series arrangement of the resistor elements that are coupled to the supply voltage level.

3. The method of claim 1 , wherein the set of electronic switches is coupled to a set of drive circuits, and wherein control nodes of electronic switches in the set of electronic switches are coupled to output nodes of corresponding drive circuits in the set of drive circuits, each control node being configured to receive a control signal from a corresponding drive circuit in the set of drive circuits, wherein the current path is configured to be at least partially conductive or non-conductive based on a logic value of the control signal. The method of claim 1 , wherein the electronic switches in the set of electronic switches comprise transistors.

5. The method of claim 1, wherein the electronic switches in the set of electronic switches comprise MOSFET transistors.

6. The method of claim 1 , wherein increasing the test voltage comprises: The test voltage is gradually increased starting from a minimum voltage level to a maximum voltage level.

7. The method of claim 1 , wherein gradually increasing the test voltage comprises: The test voltage was increased in steps of approximately 100 mV.

8. A test circuit comprising: a set of electronic switches having a current path between a first node and a ground node, wherein each electronic switch includes a respective control node; a set of coupling channels, the set of coupling channels having one end and another end, the one end being coupled to a common test node, the other end being coupled to the corresponding control node of the electronic switch; a stress voltage supply source coupled to the common test node; threshold voltage node; Sensing circuit device; as well as A set of comparator circuits, the set of comparator circuits including comparator circuits having a first input node coupled to the control nodes of corresponding electronic switches in the set of electronic switches via the sensing circuit device and having a second node coupled to the threshold voltage node.

9. The test circuit of claim 8 , wherein each electronic switch comprises a corresponding control node for receiving a calibrated stress test voltage, and wherein the set of coupling channels is configured to propagate application of the test voltage from the common test node to the corresponding control nodes of the electronic switches in the set of electronic switches.

10. The test circuit of claim 8, wherein the sensing circuit arrangement comprises at least one resistor divider, the at least one resistor divider being referenced to ground, the at least one resistor divider being coupled to a control node of the electronic switch in the set of control switches; and Wherein the threshold voltage node is coupled to a supply voltage level at one end of a series arrangement of resistive elements referenced to ground. 11 . The test circuit of claim 10 , wherein a resistive element in the resistive divider has a resistance value that is based on a resistance value of a resistive element in the series arrangement of the resistive elements.

12. The test circuit of claim 8 , wherein the set of electronic switches is coupled to a set of drive circuits, and wherein control nodes of electronic switches in the set of electronic switches are coupled to output nodes of corresponding drive circuits in the set of drive circuits, each control node being configured to receive a control signal from the corresponding drive circuit.

13. The test circuit of claim 8, wherein the electronic switches in the set of electronic switches comprise MOSFET transistors.

14. A method of operating the test circuit according to claim 8, the method comprising: providing a threshold voltage level to a second input node of a comparator circuit in the set of comparator circuits; applying a test voltage to the test common node; sensing a set of control voltages at the first input nodes of the set of comparators; performing a set of comparisons of the sensed set of control voltages to a threshold voltage level, thereby generating a set of comparison signals having a first logic value in response to a sensed control voltage of the sensed set of control voltages exceeding the threshold voltage level and a second logic value in response to a sensed control voltage of the sensed set of control voltages not exceeding the threshold voltage level; In response to at least one comparison signal of the set of comparison signals having the second logic value, increasing the test voltage applied at the test common node; as well as In response to each comparison signal in the set of comparison signals having the first logic value, increasing the test voltage applied at the common test node, wherein a value reached by the test voltage applied at the common test node is determined as a calibrated stress test voltage value.

15. A test circuit comprising: a set of electronic switches configured to have a current path passing between a first node and ground, wherein each electronic switch in the set of electronic switches includes a respective control node to receive a calibrated stress test voltage; a set of coupling channels, the set of coupling channels having one end coupled to a common test node and another end coupled to respective control nodes of electronic switches in the set of electronic switches, wherein the set of coupling channels is configured to propagate application of a test voltage from the common test node to respective control nodes of the electronic switches in the set of electronic switches; a threshold voltage node configured to receive a threshold voltage; a stress voltage supply source configured to apply a calibrated stress test voltage to the common test node; Sensing circuit device; as well as a set of comparator circuits, the set of comparator circuits comprising comparator circuits having a first input node coupled to the control node of a respective one of the set of electronic switches via the sensing circuitry, and having a second node coupled to the threshold voltage node; wherein the sensing circuitry is configured to sense a set of control voltages at the control nodes of the electronic switches in the set of electronic switches; and wherein the set of comparator circuits is configured to perform a set of comparisons of the sensed set of control voltages with the threshold voltage and to generate a set of comparison signals having a first logic value in response to a sensed control voltage in the sensed set of control voltages exceeding the threshold voltage and a second logic value in response to a sensed control voltage in the sensed set of control voltages not exceeding the reference voltage.

16. The test circuit of claim 15, wherein the set of comparators is configured to provide the set of comparison signals to a user circuit.

17. The test circuit of claim 15 , wherein the set of electronic switches is coupled to a set of drive circuits, wherein control nodes of electronic switches in the set of electronic switches are coupled to output nodes of corresponding drive circuits in the set of drive circuits, each control node is configured to receive a control signal from a corresponding drive circuit, and wherein the current path is configured to be conductive or non-conductive based on a logic value of the control signal.

18. The test circuit of claim 15, wherein the electronic switches in the set of electronic switches comprise transistors.

19. The test circuit of claim 18, wherein the electronic switches in the set of electronic switches comprise MOSFET transistors.

20. A vehicle equipped with the test circuit of claim 15, wherein the vehicle comprises a battery powered wheeled vehicle.

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