Chip module and laser radar

Abstract

The embodiment of the invention provides a chip module and a laser radar, and the chip module comprises a photosensitive chip which is provided with a photosensitive area and comprises a first substrate, at least one photosensitive unit and at least one quenching unit, the photosensitive unit and the quenching unit are located on the first substrate, and the photosensitive unit is located in the photosensitive area; the signal processing chip is electrically connected with the photosensitive chip in a first direction through a hybrid bonding stacking process, is suitable for processing electric signals output by the photosensitive unit and comprises a second substrate, a control circuit, a digital reading circuit and a digital logic circuit, and the control circuit, the digital reading circuit and the digital logic circuit are located on the second substrate. And the projections of the digital logic circuit and the photosensitive area in the direction vertical to the first direction are at least partially overlapped. By adopting the technical scheme, the utilization rate of the photosensitive area in the chip module can be improved.

Description

Technical Field

[0001] The embodiments of this specification relate to the field of optoelectronic technology, and in particular to a chip module and a laser radar. Background Art

[0002] The solution of bonding the photosensitive chip and the signal processing chip together through the hybrid bonding (Hybrid Bonding) 3D stacking process has become a commonly used packaging form. Through the above packaging process, the photosensitive chip and its corresponding signal processing chip can be bonded at the wafer level, and the readout circuit, control switch and quenching unit corresponding to the photosensitive chip are arranged under the photosensitive area of ​​the photosensitive chip.

[0003] Based on the application requirements of laser radar, the signal processing chip not only needs to perform fine-grained drive control, but also needs to complete high-parallelism, uncompressed electrical signal detection, histogram storage accumulation and data processing. That is, on the signal processing chip side, in addition to integrating the readout circuit, control switch and quenching unit corresponding to the photosensitive chip, it is also necessary to integrate the digital logic circuit that implements the above functions, for example, it can include digital signal processing (Digital Signal Processing, DSP) circuit, static random access memory (Static Random Access Memory, SRAM) circuit and sampling (Sampling) circuit. Since the readout circuit, control switch and quenching unit are already set on the lower side of the photosensitive area of ​​the photosensitive chip, the digital logic circuit can only be set outside the photosensitive area of ​​the photosensitive chip. If the digital logic circuit is integrated on the signal processing chip side, it is necessary to increase its corresponding area, resulting in the area of ​​the signal processing chip being much larger than the area of ​​the photosensitive chip. Since the 3D stacking process is a wafer-level packaging process, in order to facilitate cutting after wafer stacking, the area of ​​the photosensitive chip should usually be equal to the area of ​​the corresponding signal processing chip. In order to ensure that the area of ​​the photosensitive chip is equal to the area of ​​the corresponding signal processing chip, the area of ​​the chip with a smaller area (usually the photosensitive chip) needs to be increased. Therefore, it is also necessary to increase the area of ​​the photosensitive chip while keeping the area of ​​the photosensitive area of ​​the photosensitive chip unchanged, resulting in a decrease in the area utilization of the photosensitive area of ​​the photosensitive chip and a corresponding increase in the implementation cost.

[0004] The contents of the background technology section are merely the technologies known to the public and do not represent the existing technologies in the field. Summary of the invention

[0005] In view of this, the embodiments of this specification provide a chip module and a laser radar, which can improve the utilization rate of the photosensitive area in the chip module.

[0006] First, the embodiment of this specification provides a chip module, including:

[0007] A photosensitive chip having a photosensitive area, comprising: a first substrate, at least one photosensitive unit located on the first substrate, and at least one quenching unit, wherein the photosensitive unit is located in the photosensitive area;

[0008] A signal processing chip is electrically connected to the photosensitive chip in a first direction through a hybrid bonding stacking process, and is suitable for processing the electrical signal output by the photosensitive unit, wherein the signal processing chip includes: a second substrate, a control circuit, a digital readout circuit and a digital logic circuit located on the second substrate, and the projections of the digital logic circuit and the photosensitive area in a first direction perpendicular to the first direction at least partially overlap.

[0009] Optionally, the photosensitive unit has a first electrode coupled to the first end of the quenching unit, and a second electrode coupled to a negative power supply;

[0010] The control circuit is coupled to the second end of the quenching unit via a second hybrid bonding point;

[0011] The digital readout circuit is coupled to the first electrode of the photosensitive unit and the first end of the quenching unit through a first hybrid bonding point;

[0012] The digital logic circuit is coupled to the digital readout circuit.

[0013] Optionally, the chip module further includes: a first driving circuit, coupled to one end of the control circuit, suitable for providing an over-driving voltage for the photosensitive unit.

[0014] Optionally, the photosensitive unit has a first electrode coupled to the control circuit via a third hybrid bonding point, and a second electrode coupled to a negative power supply;

[0015] The control circuit is coupled to the first end of the quenching unit via a fourth hybrid bonding point;

[0016] The digital readout circuit is coupled to the first end of the quenching unit and the control circuit respectively through the fourth hybrid bonding point;

[0017] The digital logic circuit is coupled to the digital readout circuit.

[0018] Optionally, the chip module further includes: a second driving circuit coupled to the second end of the quenching unit and suitable for providing an overdriving voltage for the photosensitive unit.

[0019] Optionally, the quenching unit and the photosensitive unit are located in different layers of the first substrate, and their projections on a plane perpendicular to the first direction at least partially overlap.

[0020] Optionally, the digital readout circuit includes: at least one readout capacitor and at least one readout port, wherein one end of each readout capacitor is coupled to the corresponding quenching unit and the photosensitive unit, and the other end is coupled to the corresponding readout port.

[0021] Optionally, the photosensitive chip includes: a plurality of photosensitive units and a plurality of quenching units, and there are at least two photosensitive units sharing one readout port.

[0022] Optionally, the readout capacitor is a metal-oxide-metal capacitor including metal traces.

[0023] Optionally, the photosensitive chip includes a plurality of photosensitive units, the digital readout circuit includes a plurality of logic units, and each of the plurality of logic units performs a logic operation on output signals of some of the plurality of photosensitive units.

[0024] Optionally, the logic unit comprises at least one OR logic gate.

[0025] Optionally, the photosensitive units correspond one-to-one to the OR logic gates.

[0026] Optionally, projections of the logic unit and the corresponding photosensitive unit on a plane perpendicular to the first direction at least partially overlap.

[0027] Optionally, the photosensitive unit includes at least one of the following:

[0028] Single photon avalanche diode;

[0029] Avalanche photodiode;

[0030] Silicon photomultiplier tube.

[0031] Optionally, the digital logic circuit includes: a digital signal processing module, a signal sampling module and a data storage module.

[0032] Accordingly, the embodiment of this specification also provides a laser radar, including:

[0033] A light emission module, adapted to emit laser light and generate a detection signal;

[0034] The chip module described in any of the aforementioned embodiments is suitable for receiving the echo signal obtained after the detection signal is reflected from the target object, and is suitable for measuring the target object information based on the flight time of the detection signal to obtain a measurement result.

[0035] By adopting the chip module provided in the embodiment of the present specification, by setting the quenching unit on the first substrate of the photosensitive chip, the quenching unit no longer occupies the space of the signal processing chip. Therefore, when the control circuit, the digital readout circuit and the digital logic circuit are set on the second substrate of the signal processing chip, the size of the signal processing chip can be effectively reduced, thereby reducing the overall size of the chip module, and then reducing the size of the photosensitive chip. Therefore, while keeping the size of the photosensitive area unchanged, the utilization rate of the photosensitive area in the chip module can be improved; and through a hybrid bonding stacking process, the signal processing chip and the photosensitive chip are electrically connected in a first direction, so that the projections of the digital logic circuit and the photosensitive area in the first direction perpendicular to the first direction at least partially overlap, so that the relative position relationship between the digital logic circuit and the photosensitive area can be flexibly set, further reducing the overall area of ​​the chip module.

[0036] Furthermore, through the first hybrid bonding point and the second hybrid bonding point, on the one hand, the overall size of the chip module can be reduced and the utilization rate of the photosensitive area in the chip module can be improved; on the other hand, the electrical connection between the photosensitive unit, the quenching resistor, the control circuit, the digital readout circuit and the digital logic circuit can be realized, so that the optical signal detected by the photosensitive unit can be processed.

[0037] Furthermore, through the third hybrid bonding point and the fourth hybrid bonding point, on the one hand, the overall size of the chip module can be reduced and the utilization rate of the photosensitive area in the chip module can be improved; on the other hand, the electrical connection between the photosensitive unit, the quenching resistor, the control circuit, the digital readout circuit and the digital logic circuit can be realized, so that the optical signal detected by the photosensitive unit can be processed.

[0038] Furthermore, the quenching unit and the photosensitive unit are formed in different layers of the first substrate, and the quenching unit itself is a passive device. It is easy to implement and can reduce the difficulty of integration by integrating it with the photosensitive unit in different layers of the first substrate. By making the projections of the quenching unit and the photosensitive unit on the plane perpendicular to the first direction at least partially overlap, the influence of the quenching unit on the area of ​​the photosensitive chip can be reduced, which facilitates the control of the area of ​​the photosensitive chip, thereby reducing the overall area of ​​the chip module.

[0039] Furthermore, the digital readout circuit may include: at least one readout capacitor and at least one readout port. Since one end of each readout capacitor is coupled to the corresponding quenching unit and the photosensitive unit, and the other end is coupled to the corresponding readout port, the electrical signal output by the photosensitive unit can be obtained by reading the voltage change on the readout capacitor, and the implementation method is simple; and the readout capacitor occupies a small space, which can reduce the overall area of ​​the chip module.

[0040] Furthermore, the photosensitive chip can have multiple photosensitive units and multiple quenching units. By allowing at least two photosensitive units to share one readout port, the number of readout ports used can be reduced, further reducing the area of ​​the digital readout circuit, thereby reducing the overall area of ​​the chip module and reducing the implementation cost.

[0041] Furthermore, since the readout capacitor is a metal-oxide-metal capacitor and the readout capacitor may include metal wiring, it only needs to occupy part of the metal wiring space of the second substrate. Compared with other forms of capacitors, the required metal wiring space is small, which can further reduce the overall area of ​​the chip module.

[0042] Furthermore, the photosensitive chip includes multiple photosensitive units, and the digital readout circuit includes multiple logic units. By enabling each of the multiple logic units to perform logic operations on output signals of some of the multiple photosensitive units, the electrical signals output by the photosensitive units can be obtained, and the implementation method is simple.

[0043] Furthermore, by making the projections of the logic unit and the corresponding photosensitive unit on the plane perpendicular to the first direction at least partially overlap, the relative position relationship between the logic unit and the photosensitive unit can be flexibly set, thereby reducing the overall area of ​​the chip module. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions of the embodiments of this specification, the drawings required for use in the embodiments of this specification or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0045] Figure 1 A schematic diagram of the structure of a chip module in an embodiment of this specification is shown;

[0046] Figure 2 A schematic diagram showing the relative position distribution of a photosensitive unit and a quenching unit in an embodiment of this specification is shown;

[0047] Figure 3 A schematic diagram of the circuit structure of a chip module in an embodiment of this specification is shown;

[0048] Figure 4 A schematic diagram of the circuit structure of another chip module in the embodiment of this specification is shown;

[0049] Figure 5 A schematic cross-sectional structure diagram of a chip module in an embodiment of this specification is shown;

[0050] Figure 6A schematic diagram of the structure of a digital readout circuit in an embodiment of this specification is shown;

[0051] Figure 7 A schematic diagram showing the structure of another digital readout circuit in an embodiment of this specification is shown;

[0052] Figure 8 A schematic diagram of the structure of a laser radar in an embodiment of this specification is shown. DETAILED DESCRIPTION

[0053] As described in the background technology, the hybrid bonding 3D stacking process can realize the bonding of the photosensitive chip and its corresponding signal processing chip at the wafer level, and the readout circuit, control switch and quenching unit corresponding to the photosensitive chip are arranged under the photosensitive area of ​​the photosensitive chip.

[0054] When the chip module formed by bonding the photosensitive chip and the signal processing chip is applied to the laser radar, the signal processing chip not only needs to perform fine-grained drive control, but also needs to complete processes such as high-parallelism, uncompressed electrical signal detection, histogram storage accumulation and data processing. That is, on the signal processing chip side, in addition to integrating the readout circuit, control switch and quenching unit corresponding to the photosensitive chip, it is also necessary to integrate the digital logic circuit that realizes the above functions.

[0055] Since the readout circuit, control switch and quenching resistor are already arranged at the lower side of the photosensitive area, the space at the lower side of the photosensitive area cannot completely accommodate the digital logic circuit, so part of the digital logic circuit can only be arranged outside the photosensitive area.

[0056] As a specific example, for a single photosensitive unit with a size of 10 μm*10 μm, the corresponding quenching resistor has a projected area of ​​about 20-30 μm. 2 The projected area of ​​the digital readout circuit and control circuit is about 5-10μm 2 That is, the digital readout circuit, control circuit and quenching resistor placed under the photosensitive area need to occupy about 25%-40% of the projected area of ​​the photosensitive area on the signal processing chip. For an area of ​​about 30-40mm 2 For the photosensitive area, the projection area occupied by the digital logic circuit on the signal processing chip is also about 30-40mm 2, that is, the digital logic circuit that realizes the above functions needs to occupy a projection area ratio equivalent to about 100% of the photosensitive area. Therefore, in order to realize the signal detection and processing functions of the chip module, the signal processing chip that integrates the readout circuit, control switch, quenching unit, etc., and the digital logic circuit, must have a projection area of ​​at least 125%-140% of the photosensitive area. Therefore, it is necessary to further increase the area of ​​the signal processing chip to integrate the digital logic circuit, where the projection area refers to the area formed by the circuit or components projected onto the photosensitive area.

[0057] However, since the 3D stacking process is a wafer-level packaging process, the area of ​​the photosensitive chip is usually equal to the area of ​​the signal processing chip. In order to facilitate cutting after wafer stacking, the area of ​​the photosensitive chip should usually be equal to the area of ​​the corresponding signal processing chip. In order to ensure that the area of ​​the photosensitive chip is equal to the area of ​​the corresponding signal processing chip, it is necessary to increase the area of ​​the chip with a smaller area (usually the photosensitive chip). Therefore, it is also necessary to increase the area of ​​the photosensitive chip while keeping the area of ​​the photosensitive area of ​​the photosensitive chip unchanged. The above scheme leads to a decrease in the area utilization of the photosensitive area of ​​the photosensitive chip, and correspondingly increases the implementation cost.

[0058] In order to solve the above technical problems, the embodiment of this specification provides a chip module, which improves the utilization rate of the photosensitive area in the chip module by setting the quenching unit on the photosensitive chip. Specifically, by setting the quenching unit on the first substrate of the photosensitive chip, the quenching unit no longer occupies the area of ​​the signal processing chip, so when the control circuit, the digital readout circuit and the digital logic circuit are set on the second substrate of the signal processing chip, the size of the signal processing chip can be effectively reduced, thereby reducing the overall size of the chip module, and then reducing the size of the photosensitive chip, so that while keeping the size of the photosensitive area unchanged, the utilization rate of the photosensitive area in the chip module can be improved; and through the hybrid bonding stacking process, the signal processing chip is electrically connected to the photosensitive chip in the first direction, so that the relative position relationship between the digital logic circuit and the photosensitive area can be flexibly set, further reducing the overall area of ​​the chip module.

[0059] In order to enable those skilled in the art to better understand the inventive concept, working principle and advantages of the embodiments of this specification, the chip module in the embodiments of this specification is described in detail below.

[0060] First, the hybrid bonding stacking process is briefly described.

[0061] The hybrid bonding stacking process is an advanced packaging process that can vertically connect die to wafer (D2W) or wafer to wafer (W2W) through closely spaced pads. With the development of the hybrid bonding stacking process, heterogeneous integration of different chips and / or devices can be further realized, thereby providing a powerful and flexible method for direct connection between chips with different functions, sizes and design rules.

[0062] Compared to other packaging processes, the hybrid bonding stacking process can achieve high-density connections through micron-level (e.g., less than 10μm) bonding pitch, thereby enabling higher accuracy and alignment during the bonding process.

[0063] Based on this, the signal processing chip and the photosensitive chip in the embodiments of this specification are electrically connected using a hybrid bonding stacking process.

[0064] In order to enable those skilled in the art to better understand and implement, see Figure 1 and Figure 2 The schematic diagram of the structure of a chip module in the embodiment of this specification is shown. In some embodiments of this specification, the chip module 100 may include:

[0065] The photosensitive chip 110 has a photosensitive area A0, including: a first substrate 110, at least one photosensitive unit (such as a photosensitive unit 111) located on the first substrate, and at least one quenching unit (such as Figure 2 Schematic quenching unit 112), wherein the photosensitive unit 111 is located in the photosensitive area A0;

[0066] The signal processing chip 120 is stacked with the photosensitive chip in a first direction by a hybrid bonding process (wherein, Figure 1 The line segment L in the figure can represent an electrical connection (where the photosensitive chip and the signal processing chip are bonded) suitable for processing the electrical signal output by the photosensitive unit 111, wherein the signal processing chip 120 may include: a second substrate 120, a control circuit 121 located on the second substrate 120, a digital readout circuit 122 and a digital logic circuit 123, and the projection of the digital logic circuit 123 and the photosensitive area A0 in the perpendicular first direction at least partially overlap.

[0067] Therefore, by adopting a chip module with the above-mentioned structure, by setting the quenching unit 112 on the first substrate 110 of the photosensitive chip, the quenching unit 112 no longer occupies the space of the signal processing chip 120. Therefore, when the control circuit 121, the digital readout circuit 122 and the digital logic circuit 123 are set on the second substrate 120 of the signal processing chip, the size of the signal processing chip 120 can be effectively reduced, thereby reducing the overall size of the chip module 100, and further reducing the size of the photosensitive chip 110. Therefore, while keeping the size of the photosensitive area A0 unchanged, the utilization rate of the photosensitive area A0 in the chip module 100 can be improved; and through a hybrid bonding stacking process, the signal processing chip and the photosensitive chip are electrically connected in a first direction, so that the projections of the digital logic circuit 123 and the photosensitive area A0 in the first direction perpendicular to the first direction at least partially overlap, so that the relative position relationship between the digital logic circuit 123 and the photosensitive area A0 can be flexibly set, further reducing the overall area of ​​the chip module 100.

[0068] It should be noted that, first of all, Figure 1 The positions of the control circuit 121, the digital readout circuit 122, and the digital logic circuit 123 are only illustrative and simplified descriptions, and are only used to illustrate that the signal processing chip 120 may include the control circuit 121, the digital readout circuit 122, and the digital logic circuit 123, rather than indicating or implying that the control circuit 121, the digital readout circuit 122, and the digital logic circuit 123 in the embodiments of this specification must have specific positions, and therefore cannot be understood as a limitation of the present invention. Secondly, the sizes of the control circuit 121, the digital readout circuit 122, and the digital logic circuit 123 are only used to illustrate their relative areas in the signal processing chip 120. Furthermore, Figure 1 The connection relationship between the control circuit 121, the digital readout circuit 122 and the digital logic circuit 123 is not shown. In actual application, the control circuit 121, the digital readout circuit 122 and the digital logic circuit 123 can be electrically connected through metal wiring.

[0069] Understandably, Figure 1 The shape and quantity of the photosensitive units shown in the figure are only examples. In a specific embodiment, the shape and quantity of the photosensitive units can be flexibly set according to actual detection requirements, and the embodiments of this specification do not impose specific restrictions on this.

[0070] In order to enable those skilled in the art to better understand and implement the embodiments of this specification, some specific examples are given below for the specific implementation of the chip module in the embodiments of this specification.

[0071] In some embodiments of this specification, continue to refer to Figure 2The quenching unit 112 and the photosensitive unit 111 may be located on different layers of the first substrate, and their projections on a plane perpendicular to the first direction at least partially overlap.

[0072] Specifically, since the quenching unit and the photosensitive unit are formed in different layers of the first substrate, and the quenching unit itself is a passive device, it is easy to implement and reduce the difficulty of integration by integrating it with the photosensitive unit in different layers of the first substrate; and by making the projections of the quenching unit and the photosensitive unit on the plane perpendicular to the first direction at least partially overlap, the influence of the quenching unit on the area of ​​the photosensitive chip can be reduced, which facilitates the control of the area of ​​the photosensitive chip, thereby reducing the overall area of ​​the chip module.

[0073] It should be noted that Figure 2 Only one photosensitive unit and a corresponding quenching unit are shown. For other corresponding quenching units and photosensitive units, please refer to Figure 2 The configuration shown will not be elaborated here; and the relative positions of the photosensitive unit and the quenching unit are also illustrative. As long as the quenching unit and the photosensitive unit are located on different layers of the first substrate and there is an overlap in the projected areas of the two, it will be fine.

[0074] In a specific implementation, a photodetector may be used as a photosensitive unit in a chip module. As an optional example, the photodetector may include at least one of an avalanche photodiode (APD), a single photon avalanche diode (SPAD), and a silicon photomultiplier (SiPM). The embodiments of this specification do not limit the specific structure of the photosensitive unit, as long as the photosensitive unit can detect an optical signal.

[0075] In a specific implementation, the quenching unit may be a quenching resistor. By selecting quenching resistors with different resistance values ​​to be connected in series with the photosensitive unit, the electrical pulse width and recovery time of the electrical signal detected by the photosensitive unit can be adjusted.

[0076] It should be noted that the specific parameters of the quenching resistor can be determined according to application requirements, the specific structure or size of the photosensitive unit, etc. This specification does not impose any limitation on the parameters of the quenching resistor.

[0077] In some embodiments of the present specification, the quenching resistor can be made of a variety of different materials. For example, the material used may include germanium, silicon, metal (such as nickel), metal germanide or metal silicide. The type of material used is not limited in the embodiments of the present invention, as long as it can achieve the avalanche process of quenching the photosensitive unit coupled thereto.

[0078] In some embodiments of the present specification, based on actual application requirements, a variety of connection methods can be used to achieve electrical connection between the signal processing chip and the photosensitive chip.

[0079] In a specific implementation, the first electrode of the photosensitive unit can be coupled to the first end of the quenching unit, and the second electrode thereof can be coupled to the negative power supply; the control circuit can be coupled to the second end of the quenching unit through a second hybrid bonding point; the digital readout circuit can be coupled to the first electrode of the photosensitive unit and the first end of the quenching unit through a first hybrid bonding point; and the digital logic circuit can be coupled to the digital readout circuit.

[0080] As a specific example, see Figure 3 The circuit structure diagram of a chip module in the embodiment of this specification is shown in FIG. Figure 3 As shown, the photosensitive unit may be a single photon avalanche diode SPAD, the quenching unit may be a quenching resistor R, and the control circuit 121 may be a field effect transistor, wherein:

[0081] The first electrode (for example, the cathode) of the single-photon avalanche diode SPAD can be coupled to the first end of the quenching resistor R, and its second electrode (for example, the anode) can be coupled to the negative power supply -Bv, and the second end of the quenching resistor R can be coupled to the control circuit 121 through the second hybrid bonding point HB2, that is, the single-photon avalanche diode SPAD, the quenching resistor R and the control circuit 121 are connected in series, so the control circuit 121 can respond to the driving signal input at its control end and select to turn on the corresponding single-photon avalanche diode SPAD through the quenching resistor R.

[0082] The digital readout circuit 122 can be coupled to the first electrode of the photosensitive unit SPAD and the first end of the quenching resistor R through the first hybrid bonding point HB1 to read out the electrical signal sampled by the quenching resistor R.

[0083] Specifically, when the laser radar performs detection, in response to the driving signal input to the control end of the control circuit 121, the corresponding single photon avalanche diode SPAD can be turned on.

[0084] For each single-photon avalanche diode SPAD, when the actual applied reverse bias voltage is greater than its avalanche breakdown voltage, the single-photon avalanche diode SPAD can work in Geiger mode, can detect light signals, and generate a large photocurrent. The quenching resistor R will quench the entire avalanche process and charge the single-photon avalanche diode SPAD. If there is another photon injection, the above avalanche process will be repeated again, forming a cycle of avalanche->quench->charge.

[0085] During this process, the digital readout circuit 122 can read out the electrical signal sampled by the quenching resistor R and process it by the digital logic circuit.

[0086] By adopting the above-mentioned connection method, through the first hybrid bonding point and the second hybrid bonding point, on the one hand, the overall size of the chip module can be reduced and the utilization rate of the photosensitive area in the chip module can be improved; on the other hand, the electrical connection between the photosensitive unit, the quenching resistor, the control circuit, the digital readout circuit and the digital logic circuit can be realized, and the optical signal detected by the photosensitive unit can be processed.

[0087] It should be noted that, firstly, since the digital logic circuit can obtain the light signal output by the photosensitive unit through the digital readout circuit, Figure 3 No digital logic circuits are shown, and Figure 3 The upper and lower sides of the dotted line in the figure represent the circuit components located in the signal processing chip and the photosensitive chip respectively. For the specific distribution, please refer to Figure 5 ; Secondly, Figure 3 The shape of the digital readout circuit 122 in FIG. 1 is only an example. The specific structure of the digital readout circuit can be found in Figure 6 and Figure 7 , which will not be described in detail here.

[0088] Understandably, Figure 3 The conduction process of the photosensitive unit is explained by taking the field effect transistor as an example. In some other embodiments, the control circuit can also be other three-terminal devices or switches. For example, the control circuit can be a transistor. The embodiments of this specification do not impose any restrictions on the specific type of the control circuit, as long as the control circuit can select and conduct the corresponding photosensitive unit.

[0089] In a specific implementation, the control circuit can select and turn on the corresponding single photon avalanche diode SPAD in response to the driving signal input to its control terminal. In actual operation, the single photon avalanche diode SPAD can detect the optical signal only when the reverse bias voltage applied to the single photon avalanche diode SPAD is greater than the avalanche breakdown voltage.

[0090] Based on this, in some embodiments of the present specification, the chip module may further include a first driving circuit, which may be coupled to one end of the control circuit and is suitable for providing an over-driving voltage for the photosensitive unit.

[0091] For example, continue to refer to Figure 3The first driving circuit can be a first driving power supply Vov1, and the first driving power supply Vov1 is coupled to the first end of the control circuit 121. Since the second end of the control circuit 121 is coupled to the second end of the quenching resistor R, the first driving power supply Vov1 can provide an over-driving voltage for the single-photon avalanche diode SPAD, wherein the over-driving voltage is greater than the avalanche breakdown voltage of the single-photon avalanche diode SPAD.

[0092] It is understandable that the first drive circuit can also be other devices or circuits that can provide voltage. For example, the first drive circuit can be a charge pump circuit. The embodiments of this specification do not impose any restrictions on this, as long as the first drive circuit can provide an overdrive voltage for the photosensitive unit.

[0093] In another specific implementation, the first electrode of the photosensitive unit can be coupled to the control circuit through a third hybrid bonding point, and its second electrode can be coupled to a negative power supply; the control circuit can be coupled to the first end of the quenching unit through a fourth hybrid bonding point; the digital readout circuit can be coupled to the first end of the quenching unit and the control circuit respectively through the fourth hybrid bonding point; and the digital logic circuit can be coupled to the digital readout circuit.

[0094] As a specific example, see Figure 4 The circuit structure diagram of another chip module in the embodiment of this specification is shown in FIG. Figure 4 As shown, the first electrode of the single-photon avalanche diode SPAD can be coupled to the first end of the control circuit 121 through the third hybrid bonding point HB3, and its second electrode can be coupled to the negative power supply -Bv, and the first end of the control circuit 121 can be coupled to the first end of the quenching resistor R through the fourth hybrid bonding point HB4, that is, the single-photon avalanche diode SPAD, the quenching resistor R and the control circuit 121 are connected in series, so the control circuit 121 can respond to the driving signal input at its control end and select to turn on the corresponding single-photon avalanche diode SPAD.

[0095] The digital readout circuit 122 may be coupled to the first end of the quenching resistor R and the second end of the control circuit 121 respectively through the fourth hybrid bonding point HB4 .

[0096] in, Figure 4 The specific working principle of the chip module shown can be found in Figure 3 The corresponding description will not be expanded here.

[0097] By adopting the above-mentioned connection method, through the third hybrid bonding point and the fourth hybrid bonding point, on the one hand, the overall size of the chip module can be reduced and the utilization rate of the photosensitive area in the chip module can be improved; on the other hand, the electrical connection between the photosensitive unit, the quenching resistor, the control circuit, the digital readout circuit and the digital logic circuit can be realized, and the optical signal detected by the photosensitive unit can be processed.

[0098] It should be noted that Figure 4 The inside and outside of the dotted box in the figure represent the circuit elements located in the signal processing chip and the photosensitive chip, respectively. The structure in the dotted box is the signal processing chip. For its specific structure, please refer to Figure 6 and Figure 7 .

[0099] use Figure 4 In the chip module shown, when the corresponding single photon avalanche diode SPAD is selected to be turned on, it is still necessary to provide a bias voltage for the single photon avalanche diode SPAD to put the single photon avalanche diode SPAD in an avalanche state.

[0100] Based on this, in some embodiments of the present specification, the chip module may further include a second driving circuit, which may be coupled to the second end of the quenching unit and is suitable for providing an over-driving voltage for the photosensitive unit.

[0101] For example, continue to refer to Figure 4 The second driving circuit can be a second driving power supply Vov2, and the second driving power supply Vov2 can be coupled to the second end of the quenching resistor R. Since the quenching resistor R, the control circuit 121 and the single-photon avalanche diode SPAD are connected in series, the second driving power supply Vov2 can provide an over-driving voltage for the single-photon avalanche diode SPAD, wherein the over-driving voltage is greater than the avalanche breakdown voltage of the single-photon avalanche diode SPAD.

[0102] In order to enable those skilled in the art to better understand the specific structure of the chip module in the embodiments of this specification, a detailed description is given below with reference to the accompanying drawings.

[0103] Reference Figure 5 The cross-sectional structure diagram of a chip module in the embodiment of this specification is shown in FIG. Figure 5 As shown, in some embodiments of the present specification, the chip module may include a photosensitive chip 210 and a signal processing chip 220 .

[0104] like Figure 5As shown, the photosensitive chip 210 can have multiple photosensitive units (for example, photosensitive unit 212, which can specifically be a single photon avalanche diode SPAD), each photosensitive unit can be formed on a corresponding first substrate 211, and the first substrate 211 can be a base, and each photosensitive unit 212 can be coupled to a corresponding quenching resistor R.

[0105] Specifically, the photosensitive chip 210 may include a first semiconductor region 213 of a first conductivity type and a second semiconductor region 214 of a second conductivity type for adjacently forming a PN junction, and the first semiconductor region 213 and the second semiconductor region 214 are formed on a first substrate 211. The second semiconductor region 214 may be located inside the first substrate 211, and the first semiconductor region 213 may be closer to the surface of the first substrate 211.

[0106] In a specific implementation, based on actual needs, the conductivity types of the first semiconductor region 213 and the second semiconductor region 214 can be flexibly set. For example, the first conductivity type can be P type, and the first semiconductor region 213 can be a P++ layer; the second conductivity type can be N type, and the second semiconductor region 214 can be an N-doped region (N-rich region).

[0107] It can be understood that the above description of the first semiconductor region and the second semiconductor region is only an example. In some other embodiments, the first conductivity type may be N-type, and the first semiconductor region 213 may be an N-doped region (N-rich region); the second conductivity type may be P-type, and the second semiconductor region 214 may be a P++ layer. The embodiments of this specification do not impose any restrictions on this, as long as the first semiconductor region and the second semiconductor region are semiconductor regions of opposite types.

[0108] It should be noted that Figure 5 In the description, an example is given in which a photosensitive chip 210 has a first semiconductor region 213 and a second semiconductor region 214. In a specific implementation, a photosensitive chip 210 may also include a plurality of first semiconductor regions 213 and a plurality of second semiconductor regions 214, and this specification does not impose any limitation on this.

[0109] In a specific implementation, the first semiconductor region 213 can be electrically connected to the first end of the corresponding quenching resistor R through the first electrode E1 of the photosensitive unit 212 and the metal wiring layer MW1 located at the photosensitive chip 210 in sequence; the second end of the quenching resistor R can be coupled to the signal processing chip 220 (for example, a control circuit or a digital readout circuit) through the metal wiring layers MW2, MW3, the hybrid bonding point HB, and the metal wiring layers MW6 and MW7 located at the signal processing chip 220 in sequence; the second electrode E2 of the photosensitive unit 212 can be coupled to the negative power supply through the metal wiring layers MW1, MW2 and MW3 in sequence.

[0110] In some embodiments of the present specification, according to the location of the hybrid bonding point, it may include a hybrid bonding point HBP located in the photosensitive chip area, and a hybrid bonding point HBL located in the signal processing chip area.

[0111] The following combination Figure 5 , briefly describe the working principle of the chip module:

[0112] The PN junction formed by the first semiconductor region 213 and the second semiconductor region 214 can be used to operate at an avalanche breakdown voltage, so that under the action of a bias voltage, after the incident photons are absorbed by the PN junction, photogenerated electron-hole pairs can be generated, and the optical signal can be amplified by the avalanche effect. The bias voltage can be applied by connecting the electrodes on both sides of the PN junction respectively. The specific setting method can be referred to Figure 3 and Figure 4 .

[0113] Since the first semiconductor region 213 is electrically connected to one end of the corresponding quenching resistor R, the quenching resistor R can quench the avalanche breakdown process of the corresponding photosensitive unit and can sample the electrical signal output by the corresponding avalanche photodiode according to the optical signal.

[0114] The mutually independent photosensitive chip 210 and signal processing chip 220 are integrated together through a hybrid bonding point HB, so that the signal processing chip 220 can be electrically connected to the photosensitive unit and the corresponding quenching resistor R respectively, so that the signal processing chip 220 can digitally read the electrical signal sampled by the corresponding quenching resistor 120 and can process the electrical signal.

[0115] It should be noted that, first of all, Figure 5 The number and shape of the photosensitive units shown in the figure are only examples, and the embodiments of this specification do not limit this. Figure 5 Among the structures that belong to the same metal routing layer and have the same function, only one of them is shown, for example, Figure 5 The 3 metal wiring layers MW2 may be included, but Figure 5 Only one is shown.

[0116] It should also be noted that, since the present invention mainly disposes the quenching unit originally located in the signal processing chip in the photosensitive chip, the relative position relationship between the control circuit, the digital readout circuit and the digital logic circuit in the signal processing chip does not change. Figure 5 It only shows the internal connection diagram of the quenching unit and the photosensitive unit, but does not show the internal structure of the signal processing chip.

[0117] In some embodiments of this specification, continue to refer to Figure 5The chip module may further include a plurality of isolation regions, wherein the isolation region may include an isolation region WS located on the top of the first substrate 221, and an isolation region LY for isolating each semiconductor region. For example, the isolation region LY may isolate the first semiconductor region 213 and the second semiconductor region 214 and other semiconductor regions 215.

[0118] Therefore, by adopting the chip module in the above embodiment and setting the quenching unit at the photosensitive chip, the utilization rate of the photosensitive area in the chip module can be improved.

[0119] In a specific implementation, when the photosensitive unit detects a light signal, the digital readout circuit can read out the electrical signal sampled by the quenching unit and further process the electrical signal.

[0120] In some embodiments of the present specification, based on actual application requirements, digital readout circuits with different structures can be used to read out the electrical signal.

[0121] As a specific example, refer to Figure 6 A structural diagram of a digital readout circuit in an embodiment of the present specification is described. In some embodiments of the present specification, the digital readout circuit RC1 may include: at least one readout capacitor and at least one readout port (for example, it may include a readout capacitor C11 and a readout port out1), wherein the readout port may be configured to output the response of each of the photosensitive units to the light signal.

[0122] More specifically, one end of each readout capacitor is coupled to the corresponding quenching unit and the photosensitive unit, and the other end is coupled to the corresponding readout port.

[0123] For example, one end of the read capacitor C11 is connected to the quenching unit R Q11 The other end of the photosensitive unit SPAD11 is coupled to the readout port out1; one end of the readout capacitor C12 is coupled to the quenching unit R Q12 The first end is coupled to the photosensitive unit SPAD12, and the other end is coupled to the readout port out2.

[0124] The following is a brief description of the working principle of the above circuit:

[0125] Reference Figure 6 For any photosensitive unit, such as the photosensitive unit SPAD11, when there is no output, the current or charge value on the corresponding readout capacitor C11 is zero, that is, the voltage value is zero; when there is a photon response pulse output, the voltage of the junction capacitor of the photosensitive unit SPAD11 drops below the bias voltage, and the quenching unit R Q11The electrical signal detected by the photosensitive unit SPAD11 can be sampled, and the corresponding readout capacitor C11 integrates the electrical signal. The voltage change across the capacitor C11 can be read out through the readout port out1 to obtain information related to the electrical signal. The implementation method is simple; and the readout capacitor C11 occupies a small space, which can reduce the overall area of ​​the chip module.

[0126] In some embodiments of the present specification, the read-out capacitor can be a metal-oxide-metal capacitor, and the read-out capacitor can include metal routing, so it only needs to occupy part of the metal routing space of the second substrate. Compared with other forms of capacitors, the required metal routing space is small, further reducing the overall area of ​​the chip module.

[0127] In a specific implementation, the photosensitive chip may include: a plurality of photosensitive units and a plurality of quenching units, and each photosensitive unit and each quenching unit may be coupled in a one-to-one correspondence. In this case, there are at least two photosensitive units sharing one readout port.

[0128] Continue to refer to Figure 6 The photosensitive chip may include photosensitive units SPAD11 to SPAD1m, SPAD21 to SPAD2n, and a plurality of quenching units R coupled to each photosensitive unit in a one-to-one correspondence. Q11 To RQ 1m , RQ 21 To RQ 2n , where m and n are both integers greater than 1.

[0129] Correspondingly, the digital readout circuit RC1 may include multiple readout capacitors (for example, readout capacitors C11 to C1m, C21 to C2n) and multiple readout ports (for example, readout ports out1 to outp, where p is an integer greater than 1, and p is related to m and n. In some embodiments, p=m=n).

[0130] like Figure 6 As shown, the photosensitive cells SPAD11 and SPAD21 can share a readout port out1 , the photosensitive cells SPAD12 and SPAD22 can share a readout port out2 , . . . , the photosensitive cells SPAD1m and SPAD2n can share a readout port outp.

[0131] By making at least two photosensitive units share one readout port, the number of readout ports used can be reduced, further reducing the area of ​​the digital readout circuit, thereby reducing the overall area of ​​the chip module and reducing the implementation cost.

[0132] It should be noted that for multiple photosensitive units sharing a readout port, in the actual detection process, each photosensitive unit is turned on in a time-sharing manner, that is, only the electrical signal detected by one of the photosensitive units can be obtained at a time, thereby being able to more accurately obtain the position of the electrical signal, detection time and other information, thereby improving the accuracy of the acquired electrical signal.

[0133] For example, the photosensitive unit SPAD11 and the photosensitive unit SPAD21 share the readout port out1. In a detection process, if the photosensitive unit SPAD11 works, the photosensitive unit SPAD21 does not work; or, the photosensitive unit SPAD21 works, and the photosensitive unit SPAD11 does not work.

[0134] In some embodiments of the present specification, when the photosensitive chip includes multiple photosensitive units and multiple quenching units, different control methods can be used to select and turn on corresponding photosensitive units.

[0135] As a specific example, the signal processing chip may include multiple control circuits, and each photosensitive unit may be coupled to each control circuit in a one-to-one correspondence, that is, one control circuit controls the conduction process of one photosensitive unit, which can improve control accuracy.

[0136] As another specific example, the signal processing chip may include multiple control circuits, and there are at least two photosensitive units coupled to the same control circuit, that is, one control circuit can control the conduction process of at least two photosensitive units, which can reduce the number of control circuits used and reduce the overall area of ​​the chip module.

[0137] It is understandable that other control methods may be used to selectively turn on corresponding photosensitive units. For example, each photosensitive unit is coupled to the same control circuit, and the embodiments of this specification do not impose any restrictions on the turn-on process of the photosensitive units.

[0138] As another specific example, refer to Figure 7 In some embodiments of the present specification, the photosensitive chip may include a plurality of photosensitive units, for example, photosensitive units SPAD11 to SPAD1t, SPAD21 to SPAD2q, and a plurality of quenching units R coupled to each photosensitive unit one by one. Q11 To R Q1t , R Q21 To R Q2q , wherein t and q are both integers greater than 1, and in some embodiments, t may be equal to q.

[0139] Correspondingly, the digital readout circuit RC2 may include: multiple logic units (for example, OR11 to OR1r, OR21 to OR2s, wherein s and r are integers greater than 1, and the values ​​of s and r are related to q and t), and each of the multiple logic units performs a logic operation on the output signals of some of the multiple photosensitive units. For example, the logic unit OR11 can perform a logic operation on the output signal of the photosensitive unit SPAD11.

[0140] More specifically, the first end of each logic unit is coupled to its corresponding quenching unit and photosensitive unit, the second end can be coupled to the output end of another logic unit, and the output end of the logic unit located on the far left (from the current perspective) can serve as a readout port of the digital readout circuit.

[0141] For example, the first end of the logic unit OR11 located on the leftmost side is connected to the quenching unit R Q11 The second end is coupled to the photosensitive unit SPAD11, and the second end can be coupled to the output end of the logic unit OR21, whose output end can be used as a readout port out1 of the digital readout circuit RC2.

[0142] In some embodiments of the present specification, the logic unit may include at least one “OR” logic gate, and the logic unit may perform a logic “OR” operation on output signals of some photosensitive units among the plurality of photosensitive units.

[0143] In a specific implementation, the photosensitive units correspond to the "OR" logic gates one by one, that is, the number of the two is the same. By making the photosensitive units correspond to the "OR" logic gates one by one, by obtaining the output of the "OR" logic gate, the position, detection time and other information of the electrical signal obtained by the corresponding photosensitive unit can be accurately determined, thereby improving the accuracy of the obtained electrical signal.

[0144] In a specific implementation, an "OR" logic gate can be placed in the corresponding area of ​​each SPAD. Since the logic unit usually occupies about 10%-20% of the area of ​​the signal processing module chip, the remaining area can be used to configure the digital logic circuit.

[0145] It should be noted that, for mutually coupled logic units, the photosensitive units corresponding to each logic unit are turned on in time and do not work at the same time. This is because: if the photosensitive units corresponding to each mutually coupled logic unit are turned on at the same time, it is impossible to determine which photosensitive unit detects the light signal based on the output of the logic unit.

[0146] For example, the logic unit OR11 and the logic unit OR21 are coupled to each other. In the same detection process, no matter whether the photosensitive unit SPAD11 coupled to the logic unit OR11 is turned on, or the photosensitive unit SPAD21 coupled to the logic unit OR21 is turned on, when the turned-on photosensitive unit SPAD detects the light signal, the output end of the logic unit OR11 is "1" (which can be considered as a high level), that is, it is impossible to determine whether the photosensitive unit SPAD11 or the photosensitive unit SPAD21 is turned on based on the output of the logic unit OR11.

[0147] The following is a brief description of the working principle of the above circuit:

[0148] Reference Figure 7 For any photosensitive unit, such as the turned-on photosensitive unit SPAD11, when there is no output, the inputs of the first and second terminals of the logic unit OR11 are both "0" (which can be considered as a low level), and its output terminal is also "0"; when there is a photon response pulse output, the voltage of the junction capacitor of the photosensitive unit SPAD11 drops by the bias voltage, and the quenching resistor R Q11 The detected electrical signal can be sampled, and the input of the first end of the corresponding logic unit OR11 is "1", while the output of the output end of the logic unit OR21 coupled to the logic unit OR11 is "0" (this is because the photosensitive unit SPAD21 and the photosensitive unit SPAD11 are turned on in time, and SPAD21 is not turned on at this time), that is, the second end input of the logic unit OR11 is "0", and after the "OR" operation, the logic unit OR11 can output "1", and by measuring the changes in the output end of the reading logic unit OR11, the electrical signal output by the photosensitive unit SPAD11 can be obtained, and the implementation method is simple.

[0149] It should be noted that Figure 6 and Figure 7 Only the case where two SPADs in the same row share one output port is shown. In actual applications, the number of SPADs sharing an output port can be greater. In some embodiments, multiple SPADs in the same column can also share one output port. This specification does not impose any restrictions on this, as long as the SPADs sharing the same port are turned on in time-sharing mode.

[0150] It should also be noted that Figure 6 and Figure 7 The structure of the illustrated digital readout circuit is only an example. In some other embodiments, the digital readout circuit may further include a plurality of inverters, and each inverter in the plurality of logic units performs an inversion operation on the output signals of some of the plurality of photosensitive units. The embodiments of this specification do not limit the specific structure of the digital readout circuit, as long as it can read the electrical signal detected by the photosensitive unit.

[0151] In some embodiments of the present specification, when the digital readout circuit acquires the electrical signal, the digital logic circuit may further process the electrical signal to acquire relevant information.

[0152] In a specific implementation, the digital logic circuit may include: a digital signal processing module, a signal sampling module and a data storage module, wherein the signal sampling module can collect the electrical signal output by the photosensitive unit from the digital readout circuit, the data storage module can store the electrical signal, and the digital signal processing module can obtain the electrical signal from the signal sampling module or the data storage module to process the electrical signal to obtain corresponding information.

[0153] For example, when the laser radar is detecting, the laser can emit a detection signal, and the photosensitive unit can detect the echo signal related to the obstacle (which can also be considered as an electrical signal). After the digital signal processing module obtains the detection signal, it can determine the flight time difference and power and other parameters of the detection signal based on the detection signal and the echo signal, and then obtain relevant information about the obstacle, such as the distance of the obstacle relative to the laser radar, the reflectivity of the obstacle and other parameters, thereby completing the detection, tracking and identification of the obstacle.

[0154] It should be noted that based on different application scenarios, digital logic circuits with different structures can be selected. For example, the digital logic circuit may also include a counter array and / or a time-to-digital converter, etc. The embodiments of this specification do not impose any restrictions on the structure of the digital logic circuit.

[0155] In a specific implementation, the above chip module can be applied to the fields of sensors, cameras, lidar, etc. An example of application in lidar is given below.

[0156] See also Figure 8 The structure diagram of a laser radar is shown in FIG. 1 . In some embodiments of the present specification, the laser radar L may include a light emitting module L1 and a chip module L2 as described in any of the above embodiments, wherein:

[0157] The light emitting module L1 is suitable for emitting laser light and generating detection signals;

[0158] The chip module L2 is suitable for receiving the echo signal obtained by reflecting the detection signal from the target object, and for measuring the target object information based on the flight time of the detection signal to obtain a measurement result.

[0159] Among them, the specific implementation of the chip module L2 can refer to the specific introduction of the aforementioned embodiment, and will not be described in detail here.

[0160] Specifically, the laser in the optical emission module L1 can emit a detection signal (detection beam or laser signal) to the outside world, and then the photosensitive unit in the chip module L2 corresponding to the laser will receive the echo signal (reflection signal) reflected from the obstacle. The chip module L2 can determine the flight time difference and power and other parameters of the detection signal based on the detection signal and the echo signal, and then obtain relevant information about the obstacle C, such as the distance of the obstacle C relative to the laser radar L, the reflectivity of the obstacle C and other parameters, thereby completing the detection, tracking and identification of the obstacle C.

[0161] Although the embodiments of this specification are disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A chip module, characterized in that: include: A photosensitive chip having a photosensitive area, comprising: a first substrate, at least one photosensitive unit located on the first substrate, and at least one quenching unit, wherein the photosensitive unit is located in the photosensitive area; A signal processing chip is electrically connected to the photosensitive chip in a first direction through a hybrid bonding stacking process, and is suitable for processing the electrical signal output by the photosensitive unit, wherein the signal processing chip includes: a second substrate, a control circuit, a digital readout circuit and a digital logic circuit located on the second substrate, and the projections of the digital logic circuit and the photosensitive area in a first direction perpendicular to the first direction at least partially overlap.

2. The chip module according to claim 1, characterized in that: The photosensitive unit has a first electrode coupled to the first end of the quenching unit and a second electrode coupled to a negative power supply; The control circuit is coupled to the second end of the quenching unit via a second hybrid bonding point; The digital readout circuit is coupled to the first electrode of the photosensitive unit and the first end of the quenching unit through a first hybrid bonding point; The digital logic circuit is coupled to the digital readout circuit.

3. The chip module according to claim 2, characterized in that: Also includes: The first driving circuit is coupled to one end of the control circuit and is suitable for providing an over-driving voltage for the photosensitive unit.

4. The chip module according to claim 1, characterized in that: The photosensitive unit has a first electrode coupled to the control circuit via a third hybrid bonding point, and a second electrode coupled to a negative power supply; The control circuit is coupled to the first end of the quenching unit via a fourth hybrid bonding point; The digital readout circuit is coupled to the first end of the quenching unit and the control circuit respectively through the fourth hybrid bonding point; The digital logic circuit is coupled to the digital readout circuit.

5. The chip module according to claim 4, characterized in that: Also includes: The second driving circuit is coupled to the second end of the quenching unit and is suitable for providing an over-driving voltage for the photosensitive unit.

6. The chip module according to claim 1, characterized in that: The quenching unit and the photosensitive unit are located on different layers of the first substrate, and their projections on a plane perpendicular to the first direction at least partially overlap.

7. The chip module according to claim 1, characterized in that: The digital readout circuit comprises: At least one readout capacitor and at least one readout port, wherein one end of each readout capacitor is coupled to the corresponding quenching unit and the photosensitive unit, and the other end is coupled to the corresponding readout port.

8. The chip module according to claim 7, characterized in that: The photosensitive chip comprises: There are a plurality of photosensitive units and a plurality of quenching units, and at least two photosensitive units share one readout port.

9. The chip module according to claim 7 or 8, characterized in that: The readout capacitor is a metal-oxide-metal capacitor including metal traces.

10. The chip module according to claim 1, characterized in that: The photosensitive chip includes a plurality of photosensitive units, and the digital readout circuit includes a plurality of logic units, each of the plurality of logic units performing a logic operation on output signals of some of the plurality of photosensitive units.

11. The chip module according to claim 10, characterized in that: The logic unit includes at least one OR logic gate.

12. The chip module according to claim 11, characterized in that: The photosensitive units correspond to the OR logic gates one by one.

13. The chip module according to claim 12, characterized in that: Projections of the logic unit and the corresponding photosensitive unit on a plane perpendicular to the first direction at least partially overlap.

14. The chip module according to claim 1, characterized in that: The photosensitive unit includes at least one of the following: Single photon avalanche diode; Avalanche photodiode; Silicon photomultiplier tube.

15. The chip module according to claim 1, characterized in that: The digital logic circuit includes: a digital signal processing module, a signal sampling module and a data storage module.

16. A laser radar, characterized in that: include: A light emission module, adapted to emit laser light and generate a detection signal; The chip module described in any one of claims 1 to 15 is suitable for receiving the echo signal obtained after the detection signal is reflected from the target object, and is suitable for measuring the target object information based on the flight time of the detection signal to obtain a measurement result.

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