Method for improving harmonic interference based on clock spread spectrum technology

Abstract

The invention relates to a method for improving harmonic interference based on a clock spread spectrum technology, which comprises the following steps of: in a subarray level radar control system, generating a CLK clock signal as a sampling clock of serial input data and a main frequency clock of chip internal logic processing by a digital component FPGA (Field Programmable Gate Array); and a CLK clock signal with a stable period generated by the FPGA is converted into a pseudo-random period clock signal. According to the invention, the CLK clock signal generated by the FPGA is directly converted into the pseudo-random periodic clock signal, and spectrum spreading is carried out on the CLK clock signal, so that the CLK clock signal has a smaller peak energy value, and the problems of harmonic crosstalk modulation and electromagnetic compatibility in the prior art are solved.

Description

Technical Field

[0001] The invention relates to the field of array control, and in particular to a method for improving harmonic interference based on clock spread spectrum technology. Background Art

[0002] With the continuous improvement of radar technology, large-scale phased array radars are increasingly widely used. Phased array radar antennas are distributed with thousands of antenna radiating units. The beam control system needs to complete the beam control code calculation and distribute the serial control information to each component, and finally realize the serial-to-parallel conversion of the control information to achieve flexible control of the radar beam pointing. At present, in the design of the sub-array-level digital array architecture, the digital component mainly receives the instructions and timing information of the main controller, completes the beam control data calculation, and sends the control information to the T / R component. The multifunctional beam control dedicated chip is integrated in the T / R component to complete all channel controls in the component.

[0003] The multifunctional dedicated wave control chip integrated in the T / R component generally requires input signals including CLK clock signal, DIN serial data signal, DEN data valid enable signal, TR1, TR2 transceiver timing control signal, etc. The wave control chip has serial-to-parallel conversion, drive control and status information upload functions, can collect and report channel and component detection information, and detect and protect key signals. Moreover, its protection threshold can be flexibly configured through serial data to improve the stability of the radar system. Figure 1 The figure shows the timing diagram of the input signal of the multi-function wave control chip.

[0004] The CLK clock input by the multi-function wave control chip is a square wave signal with a 50% duty cycle generated by the digital component FPGA, which ensures that the chip can collect the temperature information of the T / R component in real time and perform over-pulse width and over-duty cycle protection functions on the key transmission signals. Therefore, the CLK chip not only needs to remain continuous during the validity period of the serial data signal, but also needs to remain continuous throughout normal operation to collect and control the chip status in the T / R component.

[0005] As T / R components become highly integrated, miniaturized, and multi-channel, the electromagnetic environment inside the components becomes more severe, and the CLK clock signal input by the multi-functional wave control dedicated chip becomes the main source of electromagnetic radiation interference in the T / R components. The single-frequency CLK clock signal operates at a fixed frequency, causing the energy to be superimposed on the digital intermediate frequency and radio frequency in the form of high-order harmonics or modulation.

[0006] At present, the common practice is to process the CLK clock signal through grounding, shielding and filtering. However, these measures are mostly based on the fact that the interference problem has already occurred and has been finalized, that is, after a quantitative exceeding standard data has appeared, the purpose of suppression is achieved by "encircling and blocking" the interference path, or local containment, etc., which makes it difficult to solve or reduce the interference problem from the source. At the same time, as the number of channels increases, the amount of transmitted data increases, and the beam switching time requirements become faster and faster, the transmission frequency of the CLK clock is also gradually increasing, and the interference caused by the high-order harmonics it generates is becoming more and more serious. The spurious crosstalk of the CLK clock may directly cause the spurious requirements of digital components and T / R components to fail to meet the indicators. Summary of the invention

[0007] In order to solve the existing technical problems, the present invention provides a method for improving harmonic interference based on clock spread spectrum technology.

[0008] The specific contents of the present invention are as follows: A method for improving harmonic interference based on clock spread spectrum technology. In a subarray-level radar control system, a CLK clock signal is generated by a digital component FPGA as a sampling clock for serial input data and a main frequency clock for internal logic processing of the chip. The time-hopping spread spectrum principle is used to transform the stable periodic CLK clock signal generated by the FPGA into a pseudo-random periodic clock signal.

[0009] Furthermore, time hopping spread spectrum includes direct sequence spread spectrum, frequency hopping spread spectrum, time hopping spread spectrum and linear frequency modulation spread spectrum.

[0010] Furthermore, the CLK clock signal generated by the digital component FPGA is divided into N frame time periods, where N is a positive integer, and each frame time period is set to a transmission rate. After the frame ends, it automatically jumps to the next frame, and the N frame time period is cyclically repeated.

[0011] Furthermore, the digital component FPGA generates a serial data signal, and the data signal changes at the falling edge of CLK in each frame time period, and the rising edge of CLK samples the middle of the DIN data.

[0012] Furthermore, when performing clock spread spectrum, the error of the multi-function wave control chip for over-pulse width and over-duty cycle protection is calculated based on the N-frame time period scale, the CLK rate setting value within the frame, and the minimum width of the TR2 transmission signal, and the chip protection threshold is configured to be within a certain range according to product requirements.

[0013] The present invention directly converts the CLK clock signal generated by FPGA into a pseudo-random periodic clock signal, spreads the CLK clock signal to make it have a smaller peak energy value, and solves the harmonic crosstalk modulation and electromagnetic compatibility problems in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The specific implementation of the present invention will be further explained below in conjunction with the accompanying drawings.

[0015] Figure 1 This is the timing diagram of the input signal of the multi-function wave control chip; Figure 2 This is a schematic diagram of clock harmonic crosstalk and modulation spurious; Figure 3 This is the waveform of the CLK clock signal at a rate of 10M; Figure 4 Schematic diagram of pseudo-random rate CLK clock signal waveform; Figure 5 This is the harmonic crosstalk diagram of the 10M rate CLK clock signal at the intermediate frequency; Figure 6 It is the harmonic crosstalk diagram of the CLK clock signal at the intermediate frequency under the spread spectrum rate; Figure 7 A specific implementation flow chart of a method for improving harmonic interference based on clock spread spectrum technology; Figure 8 In accordance with Figure 7 The harmonic crosstalk test diagram of the spread spectrum clock CLK at the intermediate frequency of the method; Fig. 9 This is the harmonic crosstalk test diagram of the 15M continuous clock CLK at the intermediate frequency. DETAILED DESCRIPTION

[0016] The CLK clock input by the multifunctional wave control chip crosstalks to the intermediate frequency or radio frequency of the digital components or T / R components in the form of high-order harmonics or modulation. How to solve the crosstalk problem and hidden dangers at the source has become an important direction of electromagnetic compatibility design research. In the following two situations, the CLK clock signal needs to be specially processed to meet the index requirements: 1. Regarding the general spurious requirements of digital components and T / R components, after the implementation of grounding, shielding and filtering measures, there are still spikes caused by crosstalk and modulation at the clock multiple frequency points, resulting in the spurious requirements of the components not meeting the indicators, such as Figure 2 shown.

[0017] 2. In the electromagnetic compatibility RE102 electric field radiation emission project of digital components and T / R components, the spatial radiation peak values ​​of the multi-function wave control chip input CLK clock frequency and its multiple frequencies are higher than the limit value requirements.

[0018] In order to solve the above harmonic crosstalk modulation and electromagnetic compatibility problems, it is necessary to spread the CLK clock signal so that it has a smaller peak energy value.

[0019] The method for improving harmonic interference based on clock spread spectrum technology of the present invention, in the sub-array radar control system, the digital component FPGA generates a CLK clock signal as the sampling clock of the serial input data and the main frequency clock of the chip internal logic processing, and adopts the principle of time hopping spread spectrum to transform the stable period CLK clock signal generated by the FPGA into a pseudo-random period clock signal. Clock spread spectrum technology is a frequency modulation technology that expands energy to a wider frequency band to reduce the peak value and its harmonic radiation emission. The basic methods include four implementation modes: direct sequence spread spectrum, frequency hopping spread spectrum, time hopping spread spectrum and linear frequency modulation spread spectrum.

[0020] The specific implementation method includes: the CLK clock signal generated by the FPGA on the digital board is divided into N frame time periods, N is a positive integer, each frame time period is set to a transmission rate, and automatically jumps to the next frame after the frame ends, and the N frame time period is cycled; FPGA generates serial data signals. In each frame period, the data signal changes at the falling edge of CLK, and the rising edge of CLK is right in the middle of the DIN data, ensuring that the serial data obtained by the T / R component based on CLK sampling is correct and valid; According to the N-frame time period scale, the CLK rate setting value within the frame and the minimum width of the TR2 transmission signal, the error of the multi-function wave control chip for over-pulse width and over-duty cycle protection is calculated, and the chip protection threshold is configured to be within a certain range according to product requirements.

[0021] Take FPGA generating a continuous and stable CLK clock signal at a rate of 10M as an example, the waveform is as follows Figure 3 As shown. Using the time-hopping spread spectrum principle, the CLK clock signal generated by the FPGA is directly divided into "frame" time periods, and the transmission rate of each frame time period is set to a different value to form a pseudo-random rate transmission, such as Figure 4 Set the frame rates to 10M, 12M, 14M, 8M, etc.

[0022] The Matlab simulation model is used to generate a continuous and stable 10M rate CLK signal under unit scale, and the harmonic interference energy generated near the intermediate frequency 450M. The simulation results are as follows Figure 5 The peak energy of high-order harmonics reaches -46dBm. The method of improving harmonic interference by using the clock spread spectrum technology of the present invention divides the continuous and stable 10M rate CLK signal into 10 frame time periods. The signal rate of the first frame is 5M and lasts for 2us; the signal rate of the second frame is 6M and lasts for 1.667us, ..., the signal rate of the tenth frame is 15M and lasts for 0.667us. After the tenth frame is received, it automatically jumps to the first frame. Similarly, the harmonic interference energy generated near the intermediate frequency 450M is as follows Figure 6As shown in the figure, the harmonic peak energy is reduced to -60dBm. It can be seen that the indicators are greatly improved, and the clock harmonic interference is effectively suppressed.

[0023] like Figure 7 As shown, it is a specific implementation flow chart of the present invention, which includes the following steps: Step 1: The digital board is powered on and the FPGA is running. The CLK clock signal generated by the FPGA is divided into 6 frame time periods. The average frequency of the 6 frame time period, 13.33M, is used to calculate the over-pulse width protection value of the configuration multi-function chip for the key signal TR2; Step 2: The 200M clock of the crystal oscillator on the board is divided by 10, and the CLK outputs the 20M rate clock after the division. The DIN data changes on the falling edge of the clock and lasts for 10 cycles. Step 3, the 200M clock is divided by 12, and CLK outputs the 16.67M rate clock after the division. The DIN data changes on the falling edge of the clock and lasts for 10 cycles; Step 4, the 200M clock is divided by 14, and CLK outputs the 14.28M rate clock after the division. The DIN data changes on the falling edge of the clock and lasts for 10 cycles; Step 5, the 200M clock is divided by 16, and CLK outputs the 12.5M rate clock after the division. The DIN data changes on the falling edge of the clock and lasts for 10 cycles; Step 6, the 200M clock is divided by 18, and CLK outputs the 11.11M rate clock after the division. The DIN data changes on the falling edge of the clock and lasts for 10 cycles; Step 7, the 200M clock is divided by 20, CLK outputs the 10M rate clock after the division, and the DIN data changes on the falling edge of the clock for 10 cycles; Return to step 2 and perform steps 2-7 periodically.

[0024] When the CLK clock signal is transmitted from the digital board to the T / R components, the energy of its high-order harmonics generates harmonic interference glitches within the 450M±25M intermediate frequency signal of the digital board. After the implementation of the method to improve harmonic interference based on clock spread spectrum technology, the high-order harmonic interference of the clock on the digital board is as follows: Figure 8 As shown in the figure, the harmonic energy is dispersed and the harmonic interference peak is -95dBm. The 480M in the figure is the third harmonic component of the 120M clock of the digital system on the board, which is not within the intermediate frequency range of 450±25M and has no impact on the radar system.

[0025] The traditional CLK clock signal is transmitted at a continuous and stable 15M rate. In this case, the high-order harmonic interference of the clock on the digital board is as follows: Fig. 9As shown in the figure, within the intermediate frequency of 450±25M, there are three burr interferences at 450M and 450±15M, with an amplitude of about -79dBm. The spurious indicators do not meet the system requirements.

[0026] It can be seen that the method of the present invention is applied in the sub-array-level digital array, and can greatly improve the high-order harmonic interference of the transmitted CLK clock signal at the intermediate frequency.

[0027] The method for improving harmonic interference based on clock spread spectrum technology of the present invention, the multifunctional wave control chip adopts the pseudo-random periodic clock under time hopping spread spectrum as the main frequency clock for logic processing, and the state acquisition and control protection functions are still reliable and effective. The peak energy of the transmission clock fundamental frequency and harmonic frequency is reduced accordingly, and the harmonic interference and modulation interference peak of the intermediate frequency or radio frequency are greatly reduced, and the spurious indicators of the digital components and T / R components are optimized. The peak value of spatial radiation of the transmission clock frequency and its multiple frequency points is reduced. It also has the characteristics of high versatility, flexible scalability, simple engineering implementation, etc.

[0028] Many specific details are described in the above description to facilitate a full understanding of the present invention. However, the above description is only a preferred embodiment of the present invention. The present invention can be implemented in many other ways different from those described herein, so the present invention is not limited to the specific implementation disclosed above. At the same time, any person familiar with the art can make many possible changes and modifications to the technical solution of the present invention using the methods and technical contents disclosed above without departing from the scope of the technical solution of the present invention, or modify it into an equivalent embodiment of equivalent changes. Any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

Claims

1. A method for improving harmonic interference based on clock spread spectrum technology, characterized in that: In the sub-array-level radar control system, the CLK clock signal generated by the digital component FPGA is used as the sampling clock for the serial input data and the main frequency clock for the internal logic processing of the chip. The time-hopping spread spectrum principle is used to transform the stable periodic CLK clock signal generated by the FPGA into a pseudo-random periodic clock signal.

2. The method for improving harmonic interference based on clock spread spectrum technology according to claim 1 is characterized in that: Time-hopping spread spectrum includes direct sequence spread spectrum, frequency hopping spread spectrum, time-hopping spread spectrum and linear frequency modulation spread spectrum.

3. The method for improving harmonic interference based on clock spread spectrum technology according to claim 1, characterized in that: The CLK clock signal generated by the digital component FPGA is divided into N frame time periods, where N is a positive integer. Each frame time period is set to a transmission rate, and automatically jumps to the next frame after the frame ends, and the N frame time period is cyclically repeated.

4. The method for improving harmonic interference based on clock spread spectrum technology according to claim 3 is characterized in that: The digital component FPGA generates a serial data signal. In each frame period, the data signal changes on the falling edge of CLK, and the rising edge of CLK samples the middle of the DIN data.

5. The method for improving harmonic interference based on clock spread spectrum technology according to claim 3 is characterized in that: When performing clock spread spectrum, the error of the multi-function wave control chip for over-pulse width and over-duty cycle protection is calculated based on the N-frame time period scale, the CLK rate setting value within the frame, and the minimum width of the TR2 transmission signal, and the chip protection threshold is configured to be within a certain range according to product requirements.

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