Clock synchronization method of field programmable system-on-chip

Abstract

The invention relates to the technical field of integrated circuits, and discloses a clock synchronization method of a field programmable system-on-chip. The field programmable system-on-chip comprises a processor system and programmable logic. The clock synchronization method comprises the following steps: the processor system generates a timestamp by using a local timestamp generation module; the processor system carries out frequency division on the timestamp to obtain a timestamp marking signal; the processor system downsamples the timestamp using the timestamp flag signal; the processor system sends the timestamp marking signal and the downsampled timestamp to the programmable logic; the programmable logic generates a local clock; the programmable logic adopts a local clock to sample the timestamp marking signal; the programmable logic device adopts the sampled timestamp marking signal to sample the downsampled timestamp; the programmable logic uses the sampled timestamps. According to the invention, the problem of complex timestamp synchronization can be solved, and the precision of timestamp data is improved.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a clock synchronization method for a field programmable system-on-chip. Background Art

[0002] In Field Programmable SoC (FPSOC) products, the processor system (PS) side can usually run at a relatively high frequency, such as 500MHz to 1GHz, while the programmable logic (PL) side can run at a relatively low frequency, such as 100 to 300MHz. There are two directions for timestamp data synchronization, as follows Figure 1 As shown:

[0003] 1.PL is the source of timestamp generation, PS is the destination of timestamp reception

[0004] At this time, the PL side works in a lower frequency clock domain, and the PS side works in a higher frequency clock domain. The high frequency clock on the PS side can be used to sample the low frequency accompanying clock on the PL side, thereby sampling the low frequency timestamp data.

[0005] 2.PS is the source of timestamp generation, and PL is the destination of timestamp reception

[0006] At this time, the PL side works in a lower frequency clock domain, and the PS side works in a higher frequency clock domain. The PL side cannot use the low frequency clock to sample the high frequency timestamp data on the PS side. At this time, the conventional practice is to use an asynchronous FIFO for data exchange here.

[0007] When PS is the timestamp generation source and PL is the timestamp receiving destination, using asynchronous FIFO for timestamp data synchronization has the following disadvantages:

[0008] Since the timestamp usually has a large data bit width, using FIFO cache for it will inevitably increase resource consumption, increase chip design costs, and be detrimental to chip PPA.

[0009] Since the timestamp is a continuous data type, when the clock domains on both sides of the asynchronous FIFO differ greatly, a complex control logic needs to be added to ensure that the timestamp source can store the latest timestamp data into the FIFO normally and the timestamp receiver can correctly access the latest timestamp data, which increases the design difficulty.

[0010] Due to the particularity of timestamp data, the use of asynchronous FIFO may result in uneven data distribution, which affects the timestamp accuracy.

[0011] This section is intended to provide a background or context for understanding the embodiments of the present application and is for reference only. The applicant should not be considered to admit that this section belongs to the prior art that has been disclosed before the filing date of the present application. Summary of the invention

[0012] The purpose of the present application is to provide a clock synchronization method for a field programmable system-level chip to solve the problem that the PS side (higher frequency) generates a timestamp as a source and transmits it to the PL side (lower frequency) as a destination. Due to the lower frequency of the PL side, the timestamp data synchronization is complicated.

[0013] The present application discloses a clock synchronization method for a field programmable system-on-chip, wherein the field programmable system-on-chip includes a processor system and a programmable logic. The clock synchronization method includes:

[0014] The processor system generates a timestamp using a local timestamp generation module;

[0015] The processor system divides the timestamp to obtain a timestamp mark signal;

[0016] The processor system downsamples the timestamp using the timestamp flag signal;

[0017] The processor system sends the timestamp flag signal and the downsampled timestamp to the programmable logic;

[0018] The programmable logic generates a local clock;

[0019] The programmable logic samples the timestamp signal using the local clock;

[0020] The programmable logic samples the downsampled timestamp using the sampled timestamp flag signal; and

[0021] The programmable logic uses a sampled timestamp.

[0022] In a preferred example, the frequency of the timestamp generated by the processor system is higher than the frequency of the local clock generated by the programmable logic.

[0023] In a preferred example, the frequency range of the timestamp generated by the processor system is 500 MHz to 1 GHz, and the frequency range of the local clock generated by the programmable logic is 100 MHz to 300 MHz.

[0024] In a preferred example, the frequency division ratio of the frequency division is determined according to a frequency ratio relationship between a timestamp of the processor system and a local clock of the programmable logic.

[0025] In a preferred example, a range of the frequency division ratio of the frequency division is less than or equal to the frequency of the timestamp of the processor system divided by half of the local clock of the programmable logic.

[0026] In a preferred example, the processor system also includes any one or more of the following groups: an application processing unit, a real-time processing unit, a neural network processing unit, and an image processing unit; the programmable logic also includes any one or more of the following groups: an embedded memory, a lookup table, a random access memory, and a phase-locked loop.

[0027] The present application also discloses a clock synchronization device for a field programmable system-level chip, comprising:

[0028] a memory for storing computer executable instructions; and,

[0029] A processor, coupled to the memory, is configured to implement the steps in the method described above when executing the computer executable instructions.

[0030] The present application also discloses a non-transitory computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, the steps in the method described above are implemented.

[0031] The present application also discloses a computer program product, which includes computer executable instructions. When the computer executable instructions are executed by a processor, the steps in the method described above are implemented.

[0032] In the implementation of the present application, the processor system generates a timestamp, divides the timestamp to obtain a timestamp flag signal, uses the timestamp flag signal to downsample the timestamp, sends the timestamp flag signal and the downsampled timestamp to the programmable logic, and the programmable logic samples the timestamp flag signal using the local clock, and uses the sampled timestamp flag signal to sample the downsampled timestamp. The present application can reduce the sampling difficulty on the programmable logic side and ensure the integrity of the continuity signal. There is no need for asynchronous FIFO to synchronize the timestamp, which saves logic resources, simplifies the design, and achieves a better PPA (Performance, Power, Area). In addition, the timestamp flag signal is configurable according to the user's application scenario, and flexible configuration of the timestamp accuracy can be achieved.

[0033] Each technical feature disclosed in the above invention content, each technical feature disclosed in each implementation mode and example below, and each technical feature disclosed in the accompanying drawings can be freely combined with each other to form various new technical solutions (these technical solutions should be deemed to have been recorded in this specification), unless such combination of technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed, and features C and D are equivalent technical means that play the same role. Technically, only one of them can be used, and it is impossible to use them at the same time. Feature E can be combined with feature C technically. Then, the solution of A+B+C+D should not be deemed to have been recorded because it is technically infeasible, while the solution of A+B+C+E should be deemed to have been recorded. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 The diagram is a schematic diagram of the time stamp data synchronization of a field programmable system-on-chip in the prior art.

[0035] Figure 2 It is a flowchart of a clock synchronization method for a field programmable system-on-chip according to an embodiment of the present application.

[0036] Figure 3 It is a flowchart of timestamp data synchronization of a field programmable system-on-chip according to one embodiment of the present application.

[0037] Figure 4 It is a timing diagram of timestamp data synchronization of a field programmable system-on-chip according to one embodiment of the present application. DETAILED DESCRIPTION

[0038] In the following description, many technical details are provided to help readers better understand the present application. However, those skilled in the art can understand that the technical solution claimed in the present application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0039] Description of some concepts:

[0040] Field Programmable System on Chip (FPSOC) is a highly integrated chip that integrates programmable logic devices (such as FPGA) with system-level components (such as processors, memory, and peripheral interfaces). FPSOC combines the advantages of system-on-chip (SoC) and field programmable gate array (FPGA). Through the built-in programmable logic unit, developers can dynamically configure and reconfigure hardware functions according to needs to achieve customized application solutions. This makes FPSOC particularly useful in projects with rapid iterations and short development cycles. The integrated dedicated hardware acceleration module can significantly improve the processing speed of specific tasks, such as signal processing, image processing, and encryption operations. Due to programmable logic, FPSOC can adapt to different application requirements, support multiple communication protocols and interface standards, and is suitable for a variety of application scenarios. With the development of emerging technologies such as the Internet of Things (IoT), 5G communications, artificial intelligence (AI), and edge computing, the demand for FPSOC continues to grow. In the future, FPSOC will develop towards higher integration, lower power consumption, and stronger processing capabilities to meet the changing market needs. In addition, the continuous optimization of software tools and development environment will further lower the development threshold of FPSOC and promote its application in more fields.

[0041] Processor Configuration Access Port (PCAP) is an interface used to implement communication and configuration between processors and programmable logic (such as FPGA) in a system-on-chip (SoC). PCAP allows the processor to directly access and control the programmable logic part, realizing dynamic configuration, data exchange and collaborative work.

[0042] Timestamp refers to the precise time information recorded when a specific event occurs. It can be used to identify, synchronize, track and manage the time relationship within an integrated circuit and between it and external devices. Timestamps are usually generated by an internal clock or an external synchronization signal to ensure their accuracy and reliability.

[0043] Frequency Division Ratio is an important concept in electronics and integrated circuit design that involves reducing the frequency of an input signal to a desired lower frequency. The frequency division ratio is usually expressed as the ratio of the input frequency to the output frequency. For example, a frequency division ratio of 4 means that the input frequency is four times the output frequency.

[0044] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0045] An embodiment of the present application relates to a clock synchronization method for a field programmable system-level chip, wherein the field programmable system-level chip includes a processor system (PS) and a programmable logic (PL), and the processor system and the programmable logic are connected via a processor configuration access port (PCAP). In one embodiment, the processor system may include any one or more of the following groups: an application processing unit (Application Processor Unit, APU), a real-time processing unit (Real time Processor Unit, RPU), a neural network processing unit (Neural Processor Unit, NPU), and an image processing unit (JPEG Processor Unit, JPU). In one embodiment, the programmable logic 102 may also include any one or more of the following groups: an embedded RAM, a lookup table (LOTS), a random access memory (RAM), and a phase locked loop (PLL).

[0046] Figure 2 The present invention is a flow chart of a clock synchronization method for a field programmable system-on-chip in an embodiment. The clock synchronization method comprises the following steps:

[0047] Step 101: The processor system generates a timestamp using a local timestamp generation module. In one embodiment, the frequency range of the timestamp generated by the processor system is 500 MHz to 1 GHz.

[0048] In one embodiment, the frequency of the timestamps generated by the processor system is higher than the frequency of the local clock generated by the programmable logic.

[0049] Step 102: The processor system divides the timestamp to obtain a timestamp mark signal.

[0050] In one embodiment, the frequency division ratio of the timestamp signal is determined according to the frequency ratio between the timestamp of the processor system and the local clock of the programmable logic. The timestamp signal is configurable according to the user application scenario, and the timestamp accuracy can be flexibly configured.

[0051] In one embodiment, the range of the frequency division ratio of the timestamp mark signal obtained by frequency division is less than or equal to the frequency of the timestamp of the processor system divided by half of the local clock of the programmable logic.

[0052] Step 103: The processor system downsamples the timestamp using the timestamp flag signal.

[0053] Step 104: The processor system sends the timestamp mark signal and the downsampled timestamp to the programmable logic.

[0054] Step 105: The programmable logic generates a local clock. In one embodiment, the frequency range of the local clock generated by the programmable logic is 100 MHz to 300 MHz.

[0055] In the present application, the frequency range of the timestamp generated by the processor system is, for example, 500MHz to 1GHz, for example, 1000MHz, 5000MHz, 8000MHz, 9000MHz, etc. The frequency range of the local clock generated by the programmable logic is, for example, 100MHz to 300MHz, for example, 150MHz, 100MHz, 250MHz, etc. It should be understood that in this embodiment, the frequency of the timestamp generated by the processor system is higher than the frequency of the local clock generated by the programmable logic when the processor system is used as the timestamp generation source and the programmable logic is used as the timestamp receiving destination, but the frequency range of the timestamp generated by the processor system is not limited to the above range, for example, it can also be greater than 1GHz, for example, 1GHz to 5GHz, for example, 2GHz, 3GHz, 4GHz, etc. The frequency range of the local clock generated by the programmable logic is not limited to the above range, for example, it can also be greater than 300MHz, for example, 300MHz to 500MHz, for example, 400MHz.

[0056] Step 106: The programmable logic samples the timestamp signal using the local clock.

[0057] Step 107: The programmable logic samples the downsampled timestamp using the sampled timestamp flag signal.

[0058] In step 108 , the programmable logic uses the sampled timestamp.

[0059] In this embodiment, the processor system generates a timestamp, divides the timestamp to obtain a timestamp flag signal, uses the timestamp flag signal to downsample the timestamp, sends the timestamp flag signal and the downsampled timestamp to the programmable logic, and the programmable logic samples the timestamp flag signal using the local clock, and uses the sampled timestamp flag signal to sample the downsampled timestamp. This application does not require an asynchronous FIFO for timestamp synchronization, saves logic resources, simplifies the design, can reduce the difficulty of sampling on the programmable logic side, and ensures the integrity of the continuity signal.

[0060] In order to better understand the technical solution of the present application, a specific example is provided below for illustration. The details listed in the example are mainly for ease of understanding and are not intended to limit the scope of protection of the present application.

[0061] Figure 3 The schematic diagram of the structure of a field programmable system-on-chip in one embodiment is shown. The field programmable system-on-chip includes a processor system (PS) 201 and a programmable logic (PL) 202, and the processor system (PS) 201 and the programmable logic (PL) 202 are connected via a processor configuration access port (PCAP).

[0062] The solution disclosed in the present invention mainly solves the problem that the PS side (higher frequency) generates timestamps as the source and transmits them to the PL side (lower frequency) as the destination. Due to the lower frequency of the PL side, the synchronization of timestamp data is complicated. Figure 3 As shown, it is divided into the following steps: Figure 4 The diagram is a timing diagram of timestamp data synchronization in an embodiment.

[0063] 1. The PS side 201 uses the local timestamp generation module to generate the timestamp ps_clk.

[0064] 2. The PS side 201 uses a high-frequency clock to generate a timestamp flag signal ps_timestamp_toggle, which can be obtained by dividing the high-frequency clock ps_clk of the PS side 201. The division coefficient can be configured according to the ratio between the timestamp generation module clock of the PS side 201 and the sampling clock of the PL side 202, and the operation is flexible.

[0065] For example, the timestamp sampling module of the PL side 202 operates at 200 MHz, whose frequency is F1, the timestamp generating module of the PS side 201 operates at 800 MHz, whose frequency is F2, and the timestamp identification signal frequency is F3.

[0066] At this time, for F1, the maximum signal frequency that can be sampled is 100MHz (sampling theorem), then the frequency F3 of the timestamp mark signal ps_timestamp_toggle can be a frequency division of F2 of 8 or more, that is, F3=800 / 8=100MHz, that is, a frequency division of 8 or more can be accepted. The larger the frequency division value, the more data the timestamp loses and the worse the accuracy.

[0067] However, the frequency division value can be flexibly configured according to the user's application. If the user does not need very high precision, it may be sufficient to directly use F2's 100 division value. This can not only meet user needs but also reduce overall power consumption.

[0068] If the user wants high precision, then according to the maximum signal frequency that F1 can sample, F3 = F1 ÷ 2 ≥ F2 ÷ N, so the frequency division coefficient N ≥ F2 ÷ F1 * 2, this is the minimum frequency division number of F2 used to generate the timestamp identification signal. That is, the configuration of the maximum timestamp accuracy that can be given to PL through PS at this PL / PS frequency.

[0069] In short, under different PS / PL working conditions of different users, the best accuracy that PS can provide to PL can be configured according to customer needs.

[0070] 3. Use the flag signal ps_timestamp_toggle generated in step 2 to downsample the timestamp data ps_timestamp to obtain the downsampled timestamp data ps_timestamp_o.

[0071] 4. Output the timestamp flag signal ps_timestamp_toggle generated in step 2 and the down-sampled timestamp data ps_timestamp_o generated in step 3 to the PL side 202.

[0072] 5. The PL side 202 generates a local clock pl_clk.

[0073] 6. The PL side 202 uses the local clock pl_clk to synchronize the received timestamp flag signal ps_timestamp_toggle to obtain ps_timestamp_toggle_sync0. The PL side 202 uses the local clock pl_clk to synchronize ps_timestamp_toggle_sync0 to obtain the synchronized timestamp flag signal ps_timestamp_toggle_sync1.

[0074] 7. The PL side 202 uses the synchronized timestamp flag signal ps_timestamp_toggle_sync1 to sample the received timestamp data ps_timestamp_o to obtain ps_timestamp_sync.

[0075] 8. The PL side 202 uses the sampling completed timestamp data ps_timestamp_sync normally.

[0076] Accordingly, the embodiments of the present application also provide a computer-readable storage medium, in which computer executable instructions are stored, and when the computer executable instructions are executed by the processor, the various method embodiments of the present application are implemented. Computer-readable storage media include permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be a computer-readable instruction, a data structure, a module of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, read-only compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. According to the definition herein, computer-readable storage media do not include transient computer-readable media (transitory media), such as modulated data signals and carriers.

[0077] In addition, the embodiments of the present application also provide a clock synchronization device for a field programmable system-level chip, which includes a memory for storing computer executable instructions, and a processor; the processor is used to implement the steps in the above-mentioned method implementation when executing the computer executable instructions in the memory. Among them, the processor can be a central processing unit (Central Processing Unit, referred to as "CPU"), a graphic processor (Graphic Processing Unit, referred to as "GPU"), a digital signal processor (Digital Signal Processor, referred to as "DSP"), a microcontroller unit (Microcontroller Unit, referred to as "MCU"), a neural network processor (referred to as "NPU"), an application-specific integrated circuit (Application Specific Integrated Circuit, referred to as "ASIC"), a field programmable gate array (Field Programmable Gate Array, referred to as "FPGA") or other programmable logic devices. The aforementioned memory can be a read-only memory (read-only memory, referred to as "ROM"), a random access memory (random access memory, referred to as "RAM"), a flash memory (Flash), a hard disk or a solid-state hard disk, etc. The steps of the method disclosed in each embodiment of the present invention can be directly embodied as a hardware processor execution, or a combination of hardware and software modules in the processor.

[0078] In addition, an embodiment of the present application further provides a computer program product, which includes computer executable instructions, and when the computer executable instructions are executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0079] It should be noted that, in the present application, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements defined by the sentence "include one" do not exclude the existence of other identical elements in the process, method, article or equipment including the elements. In the present application, if it is mentioned that a certain action is performed according to a certain element, it means at least the meaning of performing the action according to the element, which includes two situations: performing the action only according to the element and performing the action according to the element and other elements. Multiple, multiple, multiple, etc. expressions include 2, 2 times, 2 kinds and more than 2, more than 2 times, more than 2 kinds.

[0080] The serial numbers used in describing the steps of the method do not themselves constitute any limitation on the order of these steps. For example, the step with a larger serial number does not necessarily have to be executed after the step with a smaller serial number. The step with a larger serial number may be executed first and then the step with a smaller serial number. They may also be executed in parallel, as long as this execution order is reasonable for those skilled in the art. For another example, multiple steps with consecutive serial numbers (e.g., step 101, step 102, step 103, etc.) do not limit other steps that can be executed in between. For example, there may be other steps between step 101 and step 102.

[0081] This specification includes combinations of the various embodiments described herein. Individual references to embodiments (e.g., "one embodiment" or "some embodiments" or "preferred embodiments"); however, these embodiments are not mutually exclusive unless indicated as mutually exclusive or it is clear to a person skilled in the art that they are mutually exclusive. It should be noted that the word "or" is used in this specification in a non-exclusive sense unless the context clearly indicates or requires otherwise.

[0082] All documents mentioned in this specification are considered to be included in the disclosure of this application as a whole, so that they can be used as a basis for modification when necessary. In addition, it should be understood that the above is only a preferred embodiment of this specification and is not intended to limit the scope of protection of this specification. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of one or more embodiments of this specification should be included in the scope of protection of one or more embodiments of this specification.

[0083] In some cases, the actions or steps described in the claims may be performed in a different order than in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

Claims

1. A clock synchronization method for a field programmable system-on-chip, characterized in that: The field programmable system-level chip includes a processor system and a programmable logic, and the clock synchronization method includes: The processor system generates a timestamp using a local timestamp generation module; The processor system divides the timestamp to obtain a timestamp mark signal; The processor system downsamples the timestamp using the timestamp flag signal; The processor system sends the timestamp flag signal and the downsampled timestamp to the programmable logic; The programmable logic generates a local clock; The programmable logic samples the timestamp signal using the local clock; The programmable logic samples the downsampled timestamp using the sampled timestamp flag signal; and The programmable logic uses a sampled timestamp.

2. The clock synchronization method according to claim 1, characterized in that: The frequency of the timestamp generated by the processor system is higher than the frequency of the local clock generated by the programmable logic.

3. The clock synchronization method according to claim 1, characterized in that: The frequency range of the timestamp generated by the processor system is 500 MHz to 1 GHz, and the frequency range of the local clock generated by the programmable logic is 100 MHz to 300 MHz.

4. The clock synchronization method according to claim 1, characterized in that: The frequency division ratio of the frequency division is determined according to a frequency ratio relationship between a timestamp of the processor system and a local clock of the programmable logic.

5. The clock synchronization method according to claim 1, wherein: The range of the frequency division ratio is less than or equal to the frequency of the timestamp of the processor system divided by half of the local clock of the programmable logic.

6. The clock synchronization method according to claim 1, characterized in that: The processor system also includes any one or more of the following groups: an application processing unit, a real-time processing unit, a neural network processing unit, and an image processing unit. The programmable logic also includes any one or more of the following groups: an embedded memory, a lookup table, a random access memory, and a phase-locked loop.

7. A clock synchronization device for a field programmable system-on-chip, characterized in that: include: A memory for storing computer executable instructions; as well as, A processor, coupled to the memory, configured to implement the steps of the method according to any one of claims 1 to 6 when executing the computer executable instructions.

8. A non-transitory computer-readable storage medium, characterized in that: The non-transitory computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, the steps in the method according to any one of claims 1 to 6 are implemented.

9. A computer program product comprising computer executable instructions, characterized in that: When the computer executable instructions are executed by a processor, the steps in the method described in any one of claims 1 to 6 are implemented.

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