Binary translation method, device, electronic device and readable storage medium

Abstract

The embodiment of the present invention provides a binary translation method, device, electronic device and readable storage medium, the method comprising: if the current instruction translated is a memory access instruction, query whether there is a reusable target cache register in the allocated cache register; the allocated cache register stores the memory access address of the translated memory access instruction; the memory access address in the reusable target cache register is the same as the high bit of the memory access address of the current instruction; if there is a reusable target cache register, obtain a target difference; the target difference is the difference between the memory access address of the current instruction and the memory access address in the target cache register; according to the target difference and the target cache register, translate the current instruction into a target instruction. The embodiment of the present invention can reduce the number of translated instructions, improve the execution efficiency of the translator, and increase the speed at which the translator runs the program.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a binary translation method, device, electronic device and readable storage medium. Background Art

[0002] Binary translation can convert instructions of one ISA (Instruction Set Architecture) into instructions of another ISA. Through binary translation technology, applications of one ISA (source architecture) can be run on another ISA (target architecture).

[0003] As the performance of microprocessors continues to improve, it is increasingly feasible to run source programs of one CPU architecture under another CPU architecture through binary translation, which has led to more development of binary translation technology. However, the technology still has technical problems such as low translation efficiency and too many redundant operations. Summary of the invention

[0004] In view of the above problems, an embodiment of the present invention is proposed to provide a binary translation method that overcomes the above problems or at least partially solves the above problems, which can avoid repeated loading of the same high-order address of the translated instructions, reduce the number of translated instructions, and improve the execution efficiency of the translator, thereby increasing the speed at which the translator runs the program.

[0005] Correspondingly, the embodiment of the present invention also provides a binary translation device, an electronic device, and a computer program product to ensure the implementation and application of the above method.

[0006] In a first aspect, an embodiment of the present invention discloses a binary translation method, the method comprising:

[0007] If the current instruction translated is a memory access instruction, query whether there is a reusable target cache register in the allocated cache register; the allocated cache register stores the memory access address of the translated memory access instruction; the memory access address in the reusable target cache register is the same as the high bit of the memory access address of the current instruction;

[0008] If there is a reusable target cache register, a target difference is obtained; the target difference is the difference between the memory access address of the current instruction and the memory access address in the target cache register;

[0009] The current instruction is translated into a target instruction according to the target difference and the target cache register.

[0010] In a second aspect, an embodiment of the present invention discloses a binary translation device, the device comprising:

[0011] A cache query module, for querying whether there is a reusable target cache register in the allocated cache register if the current instruction translated is a memory access instruction; the allocated cache register stores the memory access address of the translated memory access instruction; the memory access address in the reusable target cache register is the same as the high bit of the memory access address of the current instruction;

[0012] A difference acquisition module, used for acquiring a target difference if there is a reusable target cache register; the target difference is the difference between the memory access address of the current instruction and the memory access address in the target cache register;

[0013] The optimization translation module is used to translate the current instruction into a target instruction according to the target difference and the target cache register.

[0014] In the third aspect, an embodiment of the present invention discloses an electronic device, comprising: a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the steps of the binary translation method as described in any of the above.

[0015] In a fourth aspect, an embodiment of the present invention discloses a readable storage medium, on which a program or instruction is stored, and when the program or instruction is executed by a processor, the binary translation method as described in any of the above can be implemented.

[0016] In a fifth aspect, an embodiment of the present invention discloses a computer program product, including a computer program, which, when executed by a processor, performs the steps of any of the aforementioned binary translation methods.

[0017] The embodiments of the present invention include the following advantages:

[0018] The embodiment of the present invention uses a cache register to cache the memory access address of the translated memory access instruction, and provides a function of reusing the memory access address for subsequent memory access instructions, thereby optimizing the translation of subsequent memory access instructions. Since the memory access addresses of consecutive memory access instructions are usually consecutive and have the same high-order address, the embodiment of the present invention can reuse the memory access address of the translated memory access instruction when translating the current memory access instruction, and based on the memory access address in the reusable target cache register and the target difference (the difference between the memory access address of the current instruction and the memory access address in the target cache register), a memory access instruction of the client platform can be translated into a memory access instruction of the host platform, avoiding the repeated loading of the same high-order address by the translated instruction, greatly reducing the number of translated instructions, and improving the execution efficiency of the translator, thereby improving the speed of the translator running the program. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a schematic diagram of a binary translation architecture of the present invention;

[0020] Figure 2 is a flowchart of a binary translation method embodiment of the present invention;

[0021] Figure 3 It is a schematic diagram of the data structure of a cache item of the present invention;

[0022] Figure 4 is a flow chart of optimizing translation using cache registers in one example of the present invention;

[0023] Figure 5 is a structural block diagram of an embodiment of a binary translation device of the present invention;

[0024] Figure 6 It is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0025] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0026] The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable when appropriate, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In the embodiments of the present invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0027] Binary translation technology can solve the problem of binary-level applications running across instruction set architectures. Specifically, binary translation technology can convert instruction sequences in one instruction set architecture into instruction sequences in another instruction set architecture.

[0028] Reference Figure 1 , shows a schematic diagram of a binary translation architecture, which includes a disassembler, an optimizer, a translator, and an assembler. First, the source program is input into the disassembler for disassembly and cut into basic blocks (TranslationBlock, TB), and the information of each instruction in each basic block is obtained; the optimizer analyzes the information obtained after disassembly, finds out the possible instruction sequences to be optimized, and marks them; the translator translates each instruction according to the information obtained after disassembly, and performs some optimizations during the translation process with the assistance of the marking information provided by the optimizer; the optimized translated instructions are finally sent to the assembler for assembly. A basic block usually ends with a control flow changing instruction (such as a jump instruction, a function call instruction, etc.).

[0029] In an embodiment of the present invention, the source platform is also referred to as a client platform, and the target platform is also referred to as a host platform or a local platform. The processor of the source platform may be a processor based on a first instruction set architecture. The processor of the target platform may be a processor based on a second instruction set architecture. The second instruction set architecture is a different instruction set architecture from the first instruction set architecture.

[0030] Binary translation includes static binary translation and dynamic binary translation. Static binary translation is to translate binary program A (source program) on the source platform before it is executed, so as to translate binary program A into binary program B (target program) on the target platform. Dynamic binary translation is to translate the executed code fragments when the binary program is running. The binary translation method of the embodiment of the present invention can be applied to the scenario of dynamic binary translation.

[0031] User Mode Emulation is a user space translator that can translate instructions from the client platform into instructions from the host platform. For example, it translates instructions from the CISC (Complex Instruction Set Computing) platform into instructions from the RISC (Reduced Instruction Set Computer) platform. When translating to memory access instructions from the CISC (such as x86) platform, the specific address value is calculated by the base register and the offset according to the memory address of the memory access instruction. When translating to instructions from the host platform, the corresponding load instructions are generated according to the current host platform, such as generating load instructions with high addresses and load instructions with low addresses. That is, for a memory access instruction from the client platform, it needs to be translated into multiple load instructions from the host platform. When a large number of continuous memory accesses are made, a large number of instructions for repeatedly loading the same high address will be generated, resulting in too many redundant operations, affecting the translation efficiency and the efficiency of the translator running the program.

[0032] Reference Figure 2 , shows a flowchart of a binary translation method embodiment of the present invention, the method may include the following steps:

[0033] Step 101: If the current instruction translated is a memory access instruction, query whether there is a reusable target cache register in the allocated cache register; the allocated cache register stores the memory access address of the translated memory access instruction; the memory access address in the reusable target cache register is the same as the high bit of the memory access address of the current instruction;

[0034] Step 102: If there is a reusable target cache register, a target difference is obtained; the target difference is the difference between the memory access address of the current instruction and the memory access address in the target cache register;

[0035] Step 103: According to the target difference and the target cache register, translate the current instruction into a target instruction.

[0036] The binary translation method provided by the embodiment of the present invention can be applied to a dynamic binary translator. During the translation process, when a memory access instruction is translated, a physical register is used as a cache register to cache the memory access address of the translated memory access instruction so that the cached memory access address can be reused when translating to subsequent memory access instructions, thereby reducing the number of instructions that repeatedly load the same high-order address and reducing the number of instructions generated after translation, thereby improving the translation efficiency of the translator and the efficiency of the translator running the program.

[0037] The examples in the embodiments of the present invention take the client platform as a CSIC instruction set platform and the host platform as an RSIC instruction set platform as an example. It can be understood that the embodiments of the present invention do not limit the instruction set architecture of the client platform and the host platform.

[0038] The embodiment of the present invention can identify whether the current instruction is a memory access instruction through the instruction code (operation code). For example, the memory access instruction usually contains instruction codes such as mov, lea, or movs. Furthermore, the memory access address of the memory access instruction can be read directly from the register, or it can be obtained by loading an immediate number. In the case of obtaining the memory access address by loading an immediate number, the host platform usually needs to use multiple instructions to implement the operation of loading the immediate number, resulting in a large number of instructions after translation. The embodiment of the present invention optimizes the translation of the memory access instruction that obtains the memory access address by loading an immediate number to reduce the number of instructions after translation.

[0039] In a specific implementation, the memory access instruction may include a load instruction or a store instruction. The load instruction is used to load the data in the memory address into the register. The store instruction is used to write the data in the register into the memory address.

[0040] In Example 1, assume that the following two client platform memory access instructions need to be translated:

[0041] 0x4000001f99 mov dword ptr [rip + 0xFF00],0

[0042] 0x4000001fa0 mov dword ptr [rip + 0xFF10],0

[0043] The two memory access instructions in Example 1 are storage instructions. In the above two memory access instructions, the number in [] is the immediate number to be loaded, and rip is a value that can be directly obtained, which refers to the value of the PC (Program Counter) register.

[0044] In Example 1, when the first memory access instruction is translated, since no other memory access instructions have been translated before, no cache register has been allocated to cache the memory access address of the translated memory access instruction. Therefore, there is no reusable target cache register at this time. Therefore, the first memory access instruction is translated normally without optimization. The translation result of the first memory access instruction is as follows:

[0045] lu12i.w itmp0,0x28

[0046] ori itmp0, itmp0, 0xa48

[0047] lu32.d itmp0,64

[0048] st.w $s0,itmp0,0

[0049] The first memory access instruction is translated into 4 host platform instructions, including 3 instructions for loading the immediate value (0x4000028a48) and 1 instruction for accessing the immediate value. The first two instructions are used to load the lower 32 bits of the immediate value (0x4000028a48), the third instruction is used to load the upper 32 bits of the immediate value, and the last instruction is used to access the immediate value stored in register itmp0.

[0050] If the optimization method of the present invention is not used, the second memory access instruction is also translated normally, and the translation result of the second memory access instruction is as follows:

[0051] lu12i.w itmp0,0x28

[0052] ori itmp0, itmp0, 0xa58

[0053] lu32.d itmp0,64

[0054] st.w $s0,itmp0,0

[0055] The second memory access instruction is also translated into 4 host platform instructions. The first two instructions are used to load the lower 32 bits of the immediate value (0x4000028a58), the third instruction is used to load the upper 32 bits of the immediate value, and the last instruction is used to access the immediate value stored in register itmp0.

[0056] It can be seen that translating these two memory access instructions will generate instructions for repeatedly loading the same high-order address, which in turn affects the translation efficiency and the efficiency of the translator running the program.

[0057] The embodiment of the present invention optimizes the translation of continuous memory access instructions, and the continuous memory access instructions refer to at least two continuous memory access instructions. The continuous memory access instructions can be adjacent memory access instructions in a basic block (TB), that is, the continuous memory access instructions are not separated by other instructions, such as "memory access instruction 1, memory access instruction 2", where memory access instruction 1 and memory access instruction 2 are continuous memory access instructions; or, the continuous memory access instructions can also be memory access instructions separated by other instructions in the same basic block (TB), such as "memory access instruction 1, 1 or more other instructions, memory access instruction 2", where memory access instruction 1 and memory access instruction 2 are also continuous memory access instructions.

[0058] Since consecutive memory access instructions will continuously perform memory access, the memory addresses (memory access addresses) accessed by the consecutive memory access instructions are usually continuous, the high bits of the addresses are the same, and the difference is only in the low bits. Therefore, the embodiment of the present invention can optimize the translation of the current memory access instruction by reusing the memory access address of the translated memory access instruction saved in the cache register, and translate it into a target instruction to reduce the number of translated instructions.

[0059] In an optional embodiment of the present invention, translating the current instruction into a target instruction according to the target difference and the target cache register may include:

[0060] According to the target difference and the target cache register, the current instruction is translated into a load instruction of the host platform, or the current instruction is translated into a store instruction of the host platform; the load instruction is used to load data from the target memory address to the specified register; the store instruction is used to write the data in the specified register to the target memory address; the target memory address is the memory address in the target cache register plus the target difference.

[0061] In an embodiment of the present invention, if the current instruction (memory access instruction) can be optimized and translated, that is, there is a reusable target cache register, the current instruction can be translated into a target instruction based on the target difference and the target cache register, and this target instruction is a memory access instruction of the host platform.

[0062] Furthermore, if the current instruction is a load instruction, the current instruction is translated into a load instruction of the host platform according to the target difference and the target cache register. The load instruction is used to load data from the target memory address into a specified register.

[0063] If the current instruction is a storage instruction, the current instruction is translated into a storage instruction of the host platform according to the target difference and the target cache register; the storage instruction is used to write the data in the specified register into the target memory address.

[0064] The target memory address is the memory address in the target cache register plus the target difference.

[0065] For example, in Example 1, when translating to the second memory access instruction (current instruction at this time), since the first memory access instruction has been translated, the memory access address (0x4000028a48) of the first memory access instruction has been loaded into the cache register itmp0 assigned to it. Since the memory access address (0x4000028a58) of the current instruction (the second memory access instruction) is the same as the high bit of the memory access address (0x4000028a48) stored in the cache register itmp0, and the difference is only 10, when translating to the second memory access instruction, the cache register itmp0 is a reusable target cache register. The embodiment of the present invention utilizes the memory access address (0x4000028a48) stored in the target cache register itmp0 and the target difference (10) to optimize the translation of the second memory access instruction and translate it into the following target instruction:

[0066] st.w $s0,itmp0,10

[0067] This target instruction is a storage instruction of the host platform. This target instruction obtains the memory address (0x4000028a58) of the current instruction by adding the target difference (10) to the memory address in the target cache register itmp0. In this target instruction, $s0 is the specified register, itmp0 is the target cache register, and 10 is the target difference.

[0068] The embodiment of the present invention utilizes a cache register to save the memory access address of the translated memory access instruction so that when translating to a subsequent memory access instruction, the cached memory access address can be reused. Based on the memory access address in the reusable target cache register and the target difference, a memory access instruction of the client platform can be translated into a memory access instruction of the host platform, which greatly reduces the number of translated instructions, improves the execution efficiency of the translator, and thus improves the speed at which the translator runs the program.

[0069] In an embodiment of the present invention, the cache register may be a temporary register used by the translator, and the cache register may be a physical register. Exemplarily, the translator uses physical registers itmp0 to itmp6 as temporary registers, and the temporary registers are allocated in sequence during the translation process. Generally, the temporary registers with higher register numbers are used less frequently. Therefore, an embodiment of the present invention may utilize a portion of the temporary registers as cache registers, and design a corresponding data structure to manage and maintain the corresponding relationship between the cache registers and the access addresses stored therein.

[0070] Furthermore, since the embodiment of the present invention uses the temporary registers of the shared translator as cache registers, and the translator generally uses a total of 7 temporary registers from itmp0 to itmp6. Under normal circumstances, at most 3 temporary registers are used to translate an instruction, that is, the 3 temporary registers from itmp0 to itmp2 may be used frequently during the binary translation process, and the probability of the latter temporary registers being used is relatively small. Therefore, the embodiment of the present invention can use the 4 temporary registers with higher register numbers from itmp3 to itmp6 as cache registers, and when allocating cache registers, priority is given to allocating from the register with the largest number.

[0071] For example, in Example 1, when the first memory access instruction is translated, the cache register itmp6 is allocated to the first memory access instruction, and the translation result of the first memory access instruction is as follows:

[0072] lu12i.w itmp6,0x28

[0073] ori itmp6, itmp6, 0xa48

[0074] lu32.d itmp6,64

[0075] st.w $s0,itmp6,0

[0076] In Example 1, when translating to the second memory access instruction, the target cache register itmp6 can be reused, and the translation result of the second memory access instruction is as follows:

[0077] st.w $s0,itmp6,10

[0078] The embodiment of the present invention orderly allocates temporary registers as cache registers for caching the memory access addresses of translated memory access instructions, thereby realizing that when translating subsequent memory access instructions, the memory access addresses in the existing target cache registers can be reused.

[0079] Furthermore, according to different ways of calculating memory access addresses of memory access instructions, the embodiment of the present invention divides memory access instructions into the following two different memory access types: direct type and indirect type.

[0080] The direct type refers to the memory access address that can be directly calculated during translation. The direct type of memory access address can be in the following forms: [rip+offset] or [offset]. Rip is the PC value, which can be directly obtained during translation; offset is a specific value. The two memory access instructions in Example 1 are both direct type.

[0081] Indirect type means that the memory access address cannot be directly calculated during translation, and can only be calculated dynamically when the program is running. The indirect memory access address can include the following form: [base + index×scale + offset]. Among them, base (base register), index (index register), scale (multiplier) and offset (offset) are four optional parts. Since the values ​​of base and index cannot be determined during translation and can only be determined when the program is running, the specific value of "base + index×scale" cannot be obtained during translation and can only be calculated dynamically when the program is running.

[0082] Furthermore, the embodiment of the present invention divides the memory access address into two parts: static value and dynamic value. The static value refers to the value in the memory access address that can be calculated during translation, and the dynamic value refers to the value in the memory access address that can only be calculated when the program is running. The field used to calculate the dynamic value is called the dynamic value field.

[0083] For example, in Example 1, for the first memory access instruction, the memory access address is [rip + 0xFF00]. Since the value of rip is known during translation, the memory access address [rip + 0xFF00] can be calculated to be 0x4000028a48 during translation. For the first memory access instruction in Example 1, its memory access type is direct, and its memory access address only contains static values, and the static value is the memory access address 0x4000028a48.

[0084] For another example, for the following memory access instruction:

[0085] mov rax,dword ptr [rdi + rcx×4 + 0x1596550]

[0086] The memory access address of this memory access instruction is [rdi + rcx×4 + 0x1596550], base (base register) is rdi, index (index register) is rcx, scale (multiplier) is 4, and offset (offset) is 0x1596550. Among them, the values ​​of rdi and rcx can only be determined when the program is running, so the value of "rdi + rcx×4" cannot be calculated during translation, which is called dynamic value; rdi, rcx and 4 are called dynamic value fields. Offset (offset) 0x1596550 is called static value.

[0087] Since the direct memory access address can be directly calculated during translation, while the indirect memory access address cannot be directly calculated during translation, the memory access address cannot be reused between two memory access instructions of different memory access types. In other words, a prerequisite for the current instruction to reuse the memory access address of the translated memory access instruction is that the memory access type of the current instruction is the same as the memory access type of the translated memory access instruction.

[0088] In an optional embodiment of the present invention, the querying whether there is a reusable target cache register in the allocated cache registers may include:

[0089] Step S11, identifying the memory access type of the current instruction;

[0090] Step S12, querying the saved cache items based on the memory access type of the current instruction; each cache item has a corresponding relationship with each allocated cache register; the cache item includes memory access information of the translated memory access instruction, and the memory access information includes the memory access type;

[0091] Step S13: If a target cache item with the same memory access type as the current instruction is found, determine whether the target cache item meets the reuse condition; if so, determine that the allocated cache register corresponding to the target cache item is a reusable target cache register.

[0092] The embodiment of the present invention manages the mapping relationship between the cache register and the memory access address of the memory access instruction cached therein by establishing a preset data structure (called a cache item), thereby achieving the effect of being able to reuse the memory access address that has been loaded before.

[0093] There is a corresponding relationship between each cache entry and each allocated cache register; each cache entry is used to record the memory access information of a translated memory access instruction, and the memory access information at least includes the memory access type of the memory access instruction. Furthermore, a flag bit (called a type flag bit) can be used in the cache entry to record the memory access type. For example, a type flag bit of 1 indicates a direct type, and a type flag bit of 0 indicates an indirect type.

[0094] For example, in Example 1, when translating to the first memory access instruction (the first memory access instruction is the current instruction at this time), it is identified that the memory access type of the current instruction is direct, and a reusable target cache register has not yet been generated. Therefore, a cache register is allocated to the first memory access instruction (such as allocating itmp6) to cache its memory access address, and the first memory access instruction is translated normally. After allocating itmp6 to the first memory access instruction, a cache entry corresponding to the first memory access instruction (such as cache entry 1) can be created to record the memory access information of the first memory access instruction, and the memory access information includes the memory access type of the first memory access instruction, such as setting the type identification bit in cache entry 1 to 1.

[0095] In Example 1, when translating to the second memory access instruction (the second memory access instruction is the current instruction at this time), it is identified that the memory access type of the current instruction is direct, and it is found that the memory access type recorded in cache item 1 is also direct. Therefore, cache item 1 is the target cache item, and cache item 1 meets the reusable condition. The cache address in the target cache register itmp6 corresponding to cache item 1 can be reused to translate the second memory access instruction into a target instruction.

[0096] Since the direct type of memory access address can be directly calculated during translation, when translating the current instruction, the memory access address of the current instruction and the memory access address in the target cache register can both be calculated, so it is possible to directly determine whether the memory access address in the target cache register is reusable; while the indirect type of memory access address cannot be directly calculated during translation, and the memory access address of the current instruction and the memory access address in the target cache register cannot be directly obtained. Only when the dynamic value fields of the two are completely consistent, that is, the difference between the two is only the change in the static value (offset), can it be determined whether the memory access address in the target cache register is reusable. That is, for different memory access types, there are differences in the way of determining whether the target cache item meets the reuse condition. In order to further determine whether the target cache item meets the reuse condition under different memory access types, the memory access information in each cache item can further include the static value and dynamic value fields in the translated memory access instruction.

[0097] See also Figure 3 , shows a schematic diagram of the data structure of a cache item in an embodiment of the present invention. Figure 3 As shown, a cache entry includes a type identification bit, a static value (offset), and a dynamic value field. The type identification bit is used to identify the memory access type of the memory access instruction, such as direct type (1) or indirect type (0). The static value is the part of the memory access address that can be directly calculated. For direct memory access instructions, the static value is the memory access address of the memory access instruction. For indirect memory access instructions, the static value is the offset part of the memory access instruction used to calculate the memory access address. The dynamic value field includes the base register number, index register number, and scale (multiple). These three dynamic value fields are optional.

[0098] For example, for a direct memory access instruction, the corresponding cache entry includes two parts: type identification bit (value is 1) and offset (static value), and may not include the dynamic value field. For an indirect memory access instruction, the corresponding cache entry includes three parts: type identification bit (value is 0), offset (static value) and dynamic value field, and the three items in the dynamic value field are also optional.

[0099] In an optional embodiment of the present invention, the memory access information further includes a static value and a dynamic value field in the memory access instruction, and the determining whether the target cache item meets the reuse condition may include:

[0100] If the memory access type of the current instruction is identified as indirect, then determine whether the target cache item satisfies a first condition; if the first condition is satisfied, then determine whether the target cache item satisfies a second condition; if the second condition is satisfied, then determine that the target cache item satisfies a reuse condition; otherwise, determine that the target cache item does not satisfy the reuse condition; or

[0101] If the memory access type of the current instruction is identified as a direct type, determining whether the target cache item satisfies a second condition, and if so, determining that the target cache item satisfies a reuse condition, otherwise, determining that the target cache item does not satisfy the reuse condition;

[0102] Among them, the first condition includes: the dynamic value field in the current instruction is consistent with the dynamic value field in the target cache item; the second condition includes: the difference between the static value in the current instruction and the static value in the target cache item is less than or equal to a preset value; the preset value is the maximum value of the immediate number supported by the memory access instruction of the host platform; the preset value may be different depending on the host platform.

[0103] When translating the memory access instruction of the client platform into the memory access instruction of the host platform, if there is a reusable target cache register, the memory address in the target cache register can be reused for optimized translation to avoid using instructions that repeatedly load the memory address, and a memory access instruction of the client platform can be optimized and translated into a memory access instruction of the host platform. For example, the second memory access instruction (which is a storage instruction) in Example 1 can be optimized and translated into an st instruction (storage instruction) of the host platform. For another example, the second memory access instruction (which is a load instruction) in Example 2 can be optimized and translated into an ld instruction (load instruction) of the host platform.

[0104] Furthermore, if the host platform adopts the RISC instruction set, since the RISC instruction set has a limit of 12 on the number of bits of the immediate value, when the embodiment of the present invention optimizes and translates the memory access instruction of the client platform by reusing the target register, the maximum value of the immediate value that can be supported by the translated memory access instruction of the host platform (such as the st series instruction or the ld series instruction) is 2 12 , referred to as si12. When the diff value exceeds si12, an st instruction or an ld instruction cannot be used for optimization translation, and an additional instruction is required to load the diff value, which will result in a small difference before and after optimization. At this time, no optimization translation will be performed.

[0105] In the embodiment of the present invention, different multiplexing conditions are set for direct memory access instructions and indirect memory access instructions.

[0106] When the current instruction translated is a direct memory access instruction, if there is a target cache item of the same type (direct type) in the saved cache items, it is further determined whether the difference between the static value in the current instruction and the static value in the target cache item is less than or equal to a preset value (such as si12). The difference between the static value in the current instruction and the static value in the target cache item is the target difference (such as diff). If diff is less than or equal to the preset value, it is determined that the target cache item meets the reuse condition, otherwise, it is determined that the target cache item does not meet the reuse condition.

[0107] For the current instruction translated, if the memory access type is indirect, the memory access address of the current instruction cannot be calculated during translation. However, if there is a cache register in the allocated cache registers, which stores the memory access address of the previous indirect memory access instruction, and the memory access address stored in the cache register is consistent with the dynamic value field of the memory access address of the current instruction, then it means that the only part of the memory access address of the current instruction that has changed from the memory access address of the previous indirect memory access instruction is the offset (static value). Therefore, it is possible to reuse the memory access address in the cache register.

[0108] When the current instruction translated is an indirect memory access instruction, if there is a target cache item of the same type (indirect type) in the saved cache items, it is necessary to first determine whether the dynamic value field in the current instruction is consistent with the dynamic value field in the target cache item. If they are consistent, it is possible to further determine whether the target cache item meets the reuse conditions.

[0109] Furthermore, judging whether the dynamic value field in the current instruction is consistent with the dynamic value field in the target cache item refers to judging whether the number of dynamic value fields recorded in the current instruction and the target cache item is the same, and whether the value of each dynamic value field contained is the same. Only when the number of dynamic value fields contained in the two is the same and the value of each dynamic value field contained is also the same, the dynamic value fields of the two are considered to be consistent.

[0110] For example, when the current instruction translated is an indirect memory access instruction, if there is a target cache item of the same type (indirect type) in the saved cache items, such as cache item 2, it is necessary to determine whether the dynamic value field in the current instruction is consistent with the dynamic value field in cache item 2. In an example, assuming that the current instruction is "mov rax, dword ptr [rdi +rcx×4 + 0x1596550]", the dynamic value field includes rdi, rcx, and 4. If the dynamic value field recorded in cache item 2 is also rdi, rcx, and 4, then the dynamic value fields of the two are considered to be consistent.

[0111] When it is determined that the dynamic value field in the current instruction is consistent with the dynamic value field in the target cache item, it is further determined whether the difference between the static value in the current instruction and the static value in the target cache item is less than or equal to the preset value (such as si12). The difference between the static value in the current instruction and the static value in the target cache item is the target difference (diff). If diff is less than or equal to the preset value, it is determined that the target cache item meets the reuse condition. Otherwise, if the dynamic value field in the current instruction is inconsistent with the dynamic value field in the target cache item, or the calculated diff is greater than the preset value, it is determined that the target cache item does not meet the reuse condition.

[0112] In Example 2, assume that the following two client platform memory access instructions need to be translated:

[0113] mov rax , dword ptr [rdi + rcx×4 + 0x1596550]

[0114] mov rax , dword ptr [rdi + rcx×4 + 0x1596560]

[0115] The two memory access instructions in Example 2 are load instructions. When the first memory access instruction is translated, the memory access type of the current instruction is identified as indirect, and the saved cache items are queried. If the target cache item does not exist, a cache register (such as itmp6) is allocated for the first memory access instruction to save its memory access address. The first memory access instruction is translated normally, and a cache item (such as cache item 2) is created to record the memory access information of the first memory access instruction, including the type identification bit (0), the offset (static value) of 0x1596550, and the dynamic value field including rdi, rcx, and 4.

[0116] In Example 2, the translation result of the first memory access instruction is as follows:

[0117] alsl.d itmp6 , $s1 , $s7 , 1

[0118] lu12i.w itmp5 , 0x1596

[0119] ori itmp5 , itmp5 , 0x550

[0120] add.d itmp6 , itmp6 , itmp5

[0121] ld.w $s0 , itmp6 , 0

[0122] When translating to the second memory access instruction, it is identified that the memory access type of the current instruction is indirect. The saved cache items are queried and the target cache item (cache item 2) exists. The dynamic value fields (rdi, rcx, and 4) in the current instruction are consistent with the dynamic value fields (rdi, rcx, and 4) recorded in the target cache item (cache item 2). Then, it is further determined that the difference (10) between the static value (0x1596560) in the current instruction and the static value (0x1596550) in the target cache item is less than the preset value (such as si12). Therefore, in this example, the target cache item meets the reuse condition, and the second memory access instruction can be optimized and translated into a target instruction. The translation result of the second memory access instruction is as follows:

[0123] ld.w $s0 , itmp6 , 10

[0124] The target instruction is a load instruction of the host platform, $s0 is the specified register, itmp6 is the target cache register, and 10 is the target difference.

[0125] In an optional embodiment of the present invention, the method may further include:

[0126] Step S21, after querying whether there is a reusable target cache register in the allocated cache registers, if there is no reusable target cache register, a new cache register is allocated for the current instruction to store the memory access address of the current instruction;

[0127] Step S22: creating a new cache entry, and recording the memory access information of the current instruction in the new cache entry;

[0128] Step S23: establishing a corresponding relationship between the new cache item and the new cache register.

[0129] During the binary translation process, when translating to the current instruction, if a reusable target cache register is found, then when loading the memory access address of the current instruction, the current instruction can be optimized and translated into a target instruction by reusing the memory address stored in the target cache register plus the target difference (diff). In this case, there is no need to allocate a cache register for the current instruction or create a new cache entry.

[0130] When translating to the current instruction, if it is found that there is no reusable target cache register, the current instruction is translated normally (without optimization), that is, translated into multiple host platform instructions. At this time, a new cache register needs to be allocated for the current instruction to cache the memory access address of the current instruction, and a new cache entry is created to manage the mapping relationship between the new cache register and the memory access address of the memory access instruction it caches, so as to provide multiplexing function for subsequent memory access instructions.

[0131] In an optional embodiment of the present invention, the method may further include:

[0132] Step S31, before allocating a new cache register for the current instruction, query whether there is an allocable cache register;

[0133] Step S32: If there is no allocatable cache register, remove the cache entry with the least number of uses and release the cache register corresponding to the cache entry.

[0134] The embodiment of the present invention realizes optimized translation of memory access instructions by sharing temporary registers of the translator as cache registers. Furthermore, in order to avoid conflicts with temporary registers used by the translator, the embodiment of the present invention uses part of the temporary registers as cache registers, such as using four temporary registers itmp3 to itmp6 as cache registers.

[0135] During the translation process, before a new cache register needs to be allocated for the current instruction, it is possible to query whether there is an allocatable cache register. If the four cache registers itmp3 to itmp6 are all in use, there is no allocatable cache register. At this time, the LFU (Least Frequently Used) algorithm can be used to remove the cache item with the least number of uses and release the cache register corresponding to the cache item, so that a new cache register can be allocated for the current instruction.

[0136] Reference Figure 4 , shows a schematic diagram of a flow chart of using cache registers for optimized translation in an example of the present invention. Figure 4As shown, the embodiment of the present invention can maintain the saved cache items through a cache management module to manage the mapping relationship between the cache register and the memory access address of the memory access instruction cached by it. When translating to the current instruction, the memory access type of the current instruction is identified, and the cache management module is used to query whether there is a target cache item with the same memory access type. If the target cache item with the same memory access type as the current instruction is queried, it is further determined whether the target cache item meets the reuse condition. If the reuse condition is met, the register number (such as itmp6) of the reusable target cache register is obtained and the target difference diff (such as 0x17) is obtained, and then the current instruction is optimized and translated into a target instruction. If the target cache item with the same memory access type as the current instruction is not queried, or the queried target cache item does not meet the reuse condition, a new cache register is allocated to the current instruction to save the memory access address of the current instruction, and a new cache item is created to record the memory access information of the current instruction, and a mapping relationship between the new cache item and the new cache register is established.

[0137] The embodiment of the present invention uses a cache management module to take over the allocation of temporary registers, and uses a cache replacement algorithm internally to maintain the mapping relationship between cache items and real physical registers. When translating to the current instruction, if there is a reusable target cache, the translator can obtain the register number of the reusable target cache register and the target difference diff from the cache management module. At this time, only one target instruction is needed to complete the translation of the current instruction, which greatly reduces the number of translation instructions, increases the execution efficiency of the binary translator, and thus improves the speed at which the binary translator runs the program.

[0138] In a specific implementation, since the memory access address of a direct memory access instruction can be directly calculated during translation and will not change, the cache items corresponding to the saved direct memory access instructions will not be invalid. The memory access address of an indirect memory access instruction cannot be directly calculated during translation, and the memory access address depends on the dynamic value field, and the base register and index register in the dynamic value field may be modified by other instructions. Therefore, the cache items corresponding to the saved indirect memory access instructions may be invalid.

[0139] In Example 3, assume that the following client platform instructions need to be translated:

[0140] mov rcx, dword ptr [rbx + rax×8 + 0xFF10]

[0141] Instruction 1

[0142] Instruction 2

[0143] Directive 3

[0144] mov rcx , dword ptr [rbx + rax×8 + 0xFF20]

[0145] In Example 3, the memory access types of the two consecutive memory access instructions are both indirect. The memory access address of the first memory access instruction depends on rbx (base register), rax (index register) and 8 (scale multiple). Assume that the memory access address of the first memory access instruction has been saved in a cache register (such as itmp6), and a cache entry corresponding to the first memory access instruction has been created (such as cache entry 3). The cache address stored in itmp6 is the calculation result of "rbx + rax×8 + 0xFF10". The memory access information recorded in cache entry 3 includes: type identification bit (0), static value (0xFF10), and dynamic value fields including rbx, rax and 8.

[0146] If any instruction among instruction 1, instruction 2 and instruction 3 will modify the value in register rbx or rax, and the memory access address recorded in cache register itmp6 corresponding to cache item 3 is calculated using the values ​​in unmodified rbx and rax, it will cause an error in the memory access address recorded in itmp6. In this embodiment of the present invention, cache item 3 is said to be invalid, and the invalid cache item cannot meet the reuse condition.

[0147] In order to prevent indirect memory access instructions from reusing cache registers corresponding to invalid cache items, resulting in memory access address errors, the embodiment of the present invention adds a tag to each indirect cache item to identify whether the cache item is valid (or invalid). The embodiment of the present invention does not limit the method of marking whether the cache item is valid (or invalid).

[0148] In an optional embodiment of the present invention, querying the saved cache item based on the memory access type of the current instruction may include:

[0149] If the memory access type of the current instruction is identified as indirect, then the saved and marked valid cache items are queried based on the memory access type of the current instruction; the marked valid cache items mean that after the cache item is created and before the current instruction is translated, the register on which the memory access address of the memory access instruction corresponding to the cache item depends has not been modified by other instructions.

[0150] For example, in Example 3, when the second memory access instruction is translated, it is identified that the memory access type of the memory access instruction is indirect, then a query is made as to whether there is an indirect cache item with a valid mark in the saved cache items. If so, it is determined that the target cache item is found; otherwise, it is determined that the target cache item is not found.

[0151] In an optional embodiment of the present invention, the method may further include:

[0152] Step S41: after creating a new cache item, mark the new cache item as valid;

[0153] Step S42: Create a dependency array corresponding to the new cache item; the dependency array records the registers that the dynamic value field in the new cache item depends on;

[0154] Step S43: If it is detected that an instruction modifies the register recorded in the dependency array, the cache entry corresponding to the dependency array is marked as invalid.

[0155] In an embodiment of the present invention, after a new cache entry is created for an indirect memory access instruction, the new cache entry is initially marked as valid, and a dependency array corresponding to the new cache entry is created; the dependency array records the register numbers of each register that the dynamic value field in the new cache entry depends on.

[0156] For example, in Example 3, after cache item 3 is created, cache item 3 is initially marked as valid, and a dependency array corresponding to cache item 3 is created as shown in Table 1.

[0157] Table 1

[0158]

[0159] The dependency array records the register numbers of the registers that the dynamic value field in cache item 3 depends on, such as rbx and rax. During the binary translation process, when executing instructions 1, 2, and 3, if it is detected that an instruction modifies the register recorded in the dependency array shown in Table 1, the cache item 3 corresponding to the dependency array is marked as invalid. When the second cache instruction is translated, cache item 3 cannot be used as the target cache item to further determine whether it can be reused. If no instruction is detected to modify the register recorded in the dependency array shown in Table 1, when the second cache instruction is translated, cache item 3 is still marked as valid, and cache item 3 can be used as the target cache item to further determine whether it can be reused.

[0160] Furthermore, in order to improve the utilization rate of the cache register, the cache item marked as invalid may be removed and the cache register corresponding to the cache item may be released.

[0161] In summary, the embodiment of the present invention uses a cache register to cache the memory access address of the translated memory access instruction, and provides a function of reusing the memory access address for subsequent memory access instructions, thereby optimizing the translation of subsequent memory access instructions. Since the memory access addresses of consecutive memory access instructions are usually consecutive and have the same high-order address, the embodiment of the present invention can reuse the memory access address of the translated memory access instruction when translating the current memory access instruction, and based on the memory access address in the reusable target cache register and the target difference (the difference between the memory access address of the current instruction and the memory access address in the target cache register), a memory access instruction of the client platform can be translated into a memory access instruction of the host platform, avoiding repeated loading of the same high-order address, greatly reducing the number of translated instructions, and improving the execution efficiency of the translator, thereby improving the speed at which the translator runs the program.

[0162] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0163] Reference Figure 5 , shows a structural block diagram of a binary translation device embodiment of the present invention, the device can be applied to a binary translator, and the device may include:

[0164] The cache query module 201 is used to query whether there is a reusable target cache register in the allocated cache register if the current instruction translated is a memory access instruction; the allocated cache register stores the memory access address of the translated memory access instruction; the memory access address in the reusable target cache register is the same as the high bit of the memory access address of the current instruction;

[0165] A difference acquisition module 202, configured to acquire a target difference if there is a reusable target cache register; the target difference is the difference between the memory access address of the current instruction and the memory access address in the target cache register;

[0166] The optimization translation module 203 is used to translate the current instruction into a target instruction according to the target difference and the target cache register.

[0167] Optionally, the cache query module includes:

[0168] A type identification submodule, used to identify the memory access type of the current instruction;

[0169] A cache query submodule, used for querying the saved cache items based on the memory access type of the current instruction; each cache item has a corresponding relationship with each allocated cache register; the cache item includes the memory access information of the translated memory access instruction, and the memory access information includes the memory access type;

[0170] The conditional judgment submodule is used to judge whether the target cache item meets the reuse condition if a target cache item with the same memory access type as the current instruction is queried; if so, determine that the allocated cache register corresponding to the target cache item is a reusable target cache register.

[0171] Optionally, the memory access information further includes static value and dynamic value fields in the memory access instruction, and the condition judgment submodule includes:

[0172] A first judgment unit is used to judge whether the target cache item satisfies a first condition if the memory access type of the current instruction is identified as an indirect type, and if the first condition is satisfied, judge whether the target cache item satisfies a second condition, and if the second condition is satisfied, determine that the target cache item satisfies a reuse condition, otherwise, determine that the target cache item does not satisfy the reuse condition;

[0173] A second judgment unit is used to judge whether the target cache item satisfies a second condition if the memory access type of the current instruction is identified as a direct type, and if so, determine that the target cache item satisfies a reuse condition; otherwise, determine that the target cache item does not satisfy the reuse condition;

[0174] Among them, the first condition includes: the dynamic value field in the current instruction is consistent with the dynamic value field in the target cache item; the second condition includes: the difference between the static value in the current instruction and the static value in the target cache item is less than or equal to a preset value; the preset value is the maximum value of the immediate value supported by the memory access instruction of the host platform.

[0175] Optionally, the cache query submodule is specifically used to:

[0176] If the memory access type of the current instruction is identified as indirect, then the saved and marked valid cache items are queried based on the memory access type of the current instruction; the marked valid cache items mean that after the cache item is created and before the current instruction is translated, the register on which the memory access address of the memory access instruction corresponding to the cache item depends has not been modified by other instructions.

[0177] Optionally, the device further comprises:

[0178] A register allocation module, configured to allocate a new cache register for the current instruction to store the memory access address of the current instruction if there is no reusable target cache register after querying whether there is a reusable target cache register in the allocated cache registers;

[0179] A cache entry creation module, used to create a new cache entry and record the memory access information of the current instruction in the new cache entry;

[0180] The mapping establishment module is used to establish a corresponding relationship between the new cache item and the new cache register.

[0181] Optionally, the device further comprises:

[0182] An initial marking module, used for marking the new cache item as valid after the new cache item is created;

[0183] An array creation module, used to create a dependency array corresponding to the new cache item; the dependency array records the registers that the dynamic value field in the new cache item depends on;

[0184] The marking modification module is used to mark the cache item corresponding to the dependency array as invalid if it is detected that an instruction modifies the register recorded in the dependency array.

[0185] Optionally, the device further comprises:

[0186] An allocation query module, used for querying whether there is an allocatable cache register before allocating a new cache register for the current instruction;

[0187] The cache replacement module is used to remove the cache item with the least number of uses and release the cache register corresponding to the cache item if there is no allocatable cache register.

[0188] Optionally, the optimized translation module is specifically used to:

[0189] According to the target difference and the target cache register, the current instruction is translated into a load instruction of the host platform, or the current instruction is translated into a store instruction of the host platform; the load instruction is used to load data from the target memory address to the specified register; the store instruction is used to write the data in the specified register to the target memory address; the target memory address is the memory address in the target cache register plus the target difference.

[0190] The binary translation device provided by the embodiment of the present invention can be applied to a binary translator, wherein the binary translator uses a cache register to cache the memory access address of the translated memory access instruction, and provides a function of reusing the memory access address for subsequent memory access instructions, thereby optimizing the translation of subsequent memory access instructions. Since the memory access addresses of consecutive memory access instructions are usually consecutive and have the same high-order address, the embodiment of the present invention can reuse the memory access address of the translated memory access instruction when translating the current memory access instruction, and based on the memory access address in the reusable target cache register and the target difference (the difference between the memory access address of the current instruction and the memory access address in the target cache register), a memory access instruction of the client platform can be translated into a memory access instruction of the host platform, avoiding repeated loading of the same high-order address, greatly reducing the number of translated instructions, and improving the execution efficiency of the translator, thereby improving the speed at which the translator runs the program.

[0191] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0192] Reference Figure 6 , is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Figure 6 As shown, the electronic device includes: a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the steps of the binary translation method of the above-mentioned embodiment.

[0193] An embodiment of the present invention provides a non-transitory computer-readable storage medium. When instructions in the storage medium are executed by a program or a processor of a terminal, the terminal is enabled to perform the steps of the binary translation method of the aforementioned embodiment.

[0194] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0195] It will be appreciated by those skilled in the art that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0196] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0197] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0198] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0199] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0200] Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A binary translation method, characterized in that: The method comprises: If the current instruction translated is a memory access instruction, query whether there is a reusable target cache register in the allocated cache register; the allocated cache register stores the memory access address of the translated memory access instruction; the memory access address in the reusable target cache register is the same as the high bit of the memory access address of the current instruction; If there is a reusable target cache register, a target difference is obtained; the target difference is the difference between the memory access address of the current instruction and the memory access address in the target cache register; translating the current instruction into a target instruction according to the target difference and the target cache register; The querying whether there is a reusable target cache register in the allocated cache registers includes: Identify the memory access type of the current instruction; Querying the saved cache items based on the memory access type of the current instruction; each cache item has a corresponding relationship with each allocated cache register; the cache item includes memory access information of the translated memory access instruction, and the memory access information includes the memory access type; If a target cache entry with the same memory access type as the current instruction is found, it is determined whether the target cache entry meets the reuse condition. If so, it is determined that the allocated cache register corresponding to the target cache entry is a reusable target cache register.

2. The method according to claim 1, characterized in that The memory access information also includes static value and dynamic value fields in the memory access instruction, and the determining whether the target cache item meets the reuse condition includes: If the memory access type of the current instruction is identified as indirect, then determine whether the target cache item meets the first condition; if the first condition is met, then determine whether the target cache item meets the second condition; if the second condition is met, then determine that the target cache item meets the reuse condition; otherwise, determine that the target cache item does not meet the reuse condition; If the memory access type of the current instruction is identified as a direct type, determining whether the target cache item satisfies a second condition, and if so, determining that the target cache item satisfies a reuse condition, otherwise, determining that the target cache item does not satisfy the reuse condition; Among them, the first condition includes: the dynamic value field in the current instruction is consistent with the dynamic value field in the target cache item; the second condition includes: the difference between the static value in the current instruction and the static value in the target cache item is less than or equal to a preset value; the preset value is the maximum value of the immediate value supported by the memory access instruction of the host platform.

3. The method according to claim 1, characterized in that The querying of the saved cache item based on the memory access type of the current instruction includes: If the memory access type of the current instruction is identified as indirect, then the saved and marked valid cache items are queried based on the memory access type of the current instruction; the marked valid cache items mean that after the cache item is created and before the current instruction is translated, the register on which the memory access address of the memory access instruction corresponding to the cache item depends has not been modified by other instructions.

4. The method according to any one of claims 1 to 3, characterized in that: The method further comprises: After querying whether there is a reusable target cache register in the allocated cache registers, if there is no reusable target cache register, a new cache register is allocated to the current instruction for storing the memory access address of the current instruction; Creating a new cache entry, and recording the memory access information of the current instruction in the new cache entry; A corresponding relationship between the new cache entry and the new cache register is established.

5. The method according to claim 4, characterized in that The method further comprises: After creating the new cache item, marking the new cache item as valid; Creating a dependency array corresponding to the new cache item; the dependency array records the registers that the dynamic value field in the new cache item depends on; If it is detected that an instruction modifies the register recorded in the dependency array, the cache entry corresponding to the dependency array is marked as invalid.

6. The method according to claim 4, characterized in that The method further comprises: Before allocating a new cache register for the current instruction, query whether there is an allocatable cache register; If there is no allocatable cache register, the cache entry with the least number of uses is removed and the cache register corresponding to the cache entry is released.

7. The method according to claim 1, characterized in that According to the target difference and the target cache register, translating the current instruction into a target instruction includes: According to the target difference and the target cache register, the current instruction is translated into a load instruction of the host platform, or the current instruction is translated into a store instruction of the host platform; the load instruction is used to load data from the target memory address to the specified register; the store instruction is used to write the data in the specified register to the target memory address; the target memory address is the memory address in the target cache register plus the target difference.

8. A binary translation device, characterized in that: The device comprises: A cache query module, for querying whether there is a reusable target cache register in the allocated cache register if the current instruction translated is a memory access instruction; the allocated cache register stores the memory access address of the translated memory access instruction; the memory access address in the reusable target cache register is the same as the high bit of the memory access address of the current instruction; A difference acquisition module, used for acquiring a target difference if there is a reusable target cache register; the target difference is the difference between the memory access address of the current instruction and the memory access address in the target cache register; An optimization translation module, configured to translate the current instruction into a target instruction according to the target difference and the target cache register; The cache query module includes: A type identification submodule, used to identify the memory access type of the current instruction; A cache query submodule, used for querying the saved cache items based on the memory access type of the current instruction; each cache item has a corresponding relationship with each allocated cache register; the cache item includes the memory access information of the translated memory access instruction, and the memory access information includes the memory access type; The conditional judgment submodule is used to judge whether the target cache item meets the reuse condition if a target cache item with the same memory access type as the current instruction is queried; if so, determine that the allocated cache register corresponding to the target cache item is a reusable target cache register.

9. The device according to claim 8, characterized in that The memory access information also includes static value and dynamic value fields in the memory access instruction, and the condition judgment submodule includes: A first judgment unit is used to judge whether the target cache item satisfies a first condition if the memory access type of the current instruction is identified as an indirect type, and if the first condition is satisfied, judge whether the target cache item satisfies a second condition, and if the second condition is satisfied, determine that the target cache item satisfies a reuse condition, otherwise, determine that the target cache item does not satisfy the reuse condition; A second judgment unit is used to judge whether the target cache item satisfies a second condition if the memory access type of the current instruction is identified as a direct type, and if so, determine that the target cache item satisfies a reuse condition; otherwise, determine that the target cache item does not satisfy the reuse condition; Among them, the first condition includes: the dynamic value field in the current instruction is consistent with the dynamic value field in the target cache item; the second condition includes: the difference between the static value in the current instruction and the static value in the target cache item is less than or equal to a preset value; the preset value is the maximum value of the immediate value supported by the memory access instruction of the host platform.

10. The device according to claim 8, characterized in that The cache query submodule is specifically used for: If the memory access type of the current instruction is identified as indirect, then the saved and marked valid cache items are queried based on the memory access type of the current instruction; the marked valid cache items mean that after the cache item is created and before the current instruction is translated, the register on which the memory access address of the memory access instruction corresponding to the cache item depends has not been modified by other instructions.

11. The device according to any one of claims 8 to 10, characterized in that: The device also includes: A register allocation module, configured to allocate a new cache register for the current instruction to store the memory access address of the current instruction if there is no reusable target cache register after querying whether there is a reusable target cache register in the allocated cache registers; A cache entry creation module, used to create a new cache entry and record the memory access information of the current instruction in the new cache entry; The mapping establishment module is used to establish a corresponding relationship between the new cache item and the new cache register.

12. The device according to claim 11, characterized in that The device also includes: An initial marking module, used for marking the new cache item as valid after the new cache item is created; An array creation module, used to create a dependency array corresponding to the new cache item; the dependency array records the registers that the dynamic value field in the new cache item depends on; The marking modification module is used to mark the cache item corresponding to the dependency array as invalid if it is detected that an instruction modifies the register recorded in the dependency array.

13. The device according to claim 11, characterized in that The device also includes: An allocation query module, used for querying whether there is an allocatable cache register before allocating a new cache register for the current instruction; The cache replacement module is used to remove the cache item with the least number of uses and release the cache register corresponding to the cache item if there is no allocatable cache register.

14. The device according to claim 8, characterized in that The optimized translation module is specifically used for: According to the target difference and the target cache register, the current instruction is translated into a load instruction of the host platform, or the current instruction is translated into a store instruction of the host platform; the load instruction is used to load data from the target memory address to the specified register; the store instruction is used to write the data in the specified register to the target memory address; the target memory address is the memory address in the target cache register plus the target difference.

15. An electronic device, characterized in that: include: A processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other via the communication bus; The memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the steps of the binary translation method according to any one of claims 1 to 7.

16. A readable storage medium, characterized in that: The readable storage medium stores a program or instruction, and when the program or instruction is executed by a processor, the steps of the binary translation method according to any one of claims 1 to 7 are implemented.

17. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the binary translation method according to any one of claims 1 to 7 are implemented.

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