Substrate contact design method and device, electronic equipment and storage medium

Abstract

The invention provides a substrate contact design method and device, electronic equipment and a storage medium, and relates to the technical field of integrated circuits. The method comprises the steps of obtaining a layout design of a preset integrated circuit, wherein the layout design comprises a plurality of logic units placed according to preset positions; a substrate contact unit is inserted into a preset area of a first logic unit in the preset integrated circuit, and the first logic unit is a logic unit without the substrate contact unit in the preset area; updating the substrate existence states of the plurality of logic units according to the insertion positions of the substrate contact units and a first preset range; and traversing the plurality of logic units in sequence, continuing to insert a new substrate contact unit according to the updated substrate existence state until the substrate contact units exist in the preset areas of the plurality of logic units, and completing the substrate contact design of the preset integrated circuit. The anti-latch performance of the circuit can be improved, and the area utilization rate of the substrate contact unit can be improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a substrate contact design method, device, electronic device and storage medium. Background Art

[0002] In the design and manufacture of integrated circuits, there is usually a dedicated substrate basic unit module to connect the substrate and well of the integrated circuit to the potential required by the design. The quality of the substrate contact will affect the performance of the integrated circuit device. The design of the substrate contact is mainly to increase the number of substrate contacts as much as possible, thereby reducing the parasitic substrate resistance to reduce the occurrence of latch-up effect caused by the parasitic resistance of the substrate.

[0003] Figure 1 is a schematic diagram of the arrangement of the existing substrate contact unit, such as Figure 1 As shown in the figure, the semi-custom design will use a fixed spacing to place the substrate contact unit Tap Cell, and the placement of the substrate contact unit is planned in advance before the logic unit Logic Cell is placed. Figure 1 As shown in (a), the fixed spacing is used for alternating arrangement, such as Figure 1 As shown in (b), a vertical arrangement with a fixed spacing is adopted.

[0004] For general integrated circuit application scenarios, the above-mentioned arrangement of substrate contact units can basically avoid the influence of the latch-up effect introduced by the substrate parasitic resistance. However, for semi-custom integrated circuit design under irradiation environment, due to the randomness of high-energy particles, they can hit the substrate of the chip at any direction and any position. The latch-up effect caused by this may cause circuit malfunction.

[0005] Therefore, a substrate contact design method with better anti-latch performance is needed. Summary of the invention

[0006] The purpose of the present application is to provide a substrate contact design method, device, electronic device and storage medium to address the deficiencies in the above-mentioned prior art, so as to improve the circuit anti-latch performance and improve the area utilization of the substrate contact unit.

[0007] To achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:

[0008] In a first aspect, an embodiment of the present application provides a substrate contact design method, the method comprising:

[0009] Obtaining a layout design of a preset integrated circuit, wherein the layout design includes a plurality of logic units arranged at preset positions;

[0010] Inserting a substrate contact unit in a preset region of a first logic unit in the preset integrated circuit, wherein the first logic unit is a logic unit in which no substrate contact unit exists in the preset region;

[0011] updating the substrate existence status of the plurality of logic units according to the insertion position of the substrate contact unit and the first preset range, wherein the substrate existence status indicates whether the substrate contact unit exists in a preset area of ​​the logic unit;

[0012] The multiple logic units are traversed in sequence, and new substrate contact units are continuously inserted according to the updated substrate existence status, until the substrate contact units exist in the preset areas of the multiple logic units, thereby completing the substrate contact design for the preset integrated circuit.

[0013] Optionally, updating the substrate existence status of the plurality of logic units according to the insertion position of the substrate contact unit and the first preset range includes:

[0014] Determining a second logic unit located within the first preset range according to an insertion position of the substrate contact unit and the first preset range;

[0015] According to the preset area of ​​the second logic unit and the insertion position of the substrate contact unit, a target logic unit is selected from the second logic units, wherein the target logic unit is a second logic unit whose insertion position of the substrate contact unit is within the corresponding preset area;

[0016] The substrate existence status of the target logic unit is updated to the existence status, and the substrate existence status of other logic units is updated to the non-existence status.

[0017] Optionally, each substrate contact unit includes: a substrate contact, and determining a second logic unit located within the first preset range according to an insertion position of the substrate contact unit and the first preset range includes:

[0018] According to the insertion position of the substrate contact unit, a logic unit directly adjacent to the substrate contact unit on the substrate contact of the substrate contact unit is determined as the second logic unit, and the first preset range is the directly adjacent range.

[0019] Optionally, each substrate contact unit further includes a well contact, and the second logic unit located within the first preset range is determined according to the insertion position of the substrate contact unit and the first preset range, and further includes:

[0020] According to the insertion position of the substrate contact unit, a logic unit adjacent to the substrate contact unit on the well contact of the substrate contact unit is determined as the second logic unit.

[0021] Optionally, each logic unit has a substrate contact mark and a well contact mark, and after inserting the substrate contact unit into the preset region of the first logic unit in the preset integrated circuit, the method further includes:

[0022] Determining a substrate contact identifier and a well contact identifier of the first logic unit as a first identifier;

[0023] The updating of the substrate existence state of the target logic unit to the existence state and the substrate existence state of other logic units to the non-existence state includes:

[0024] Determine the substrate contact identifier and the well contact identifier of the target logic unit as the first identifier, and the substrate contact identifiers and the well contact identifiers of other logic units as the second identifier;

[0025] The first identifier indicates that the substrate existence state of the logic unit is the existence state, and the second identifier indicates that the substrate existence state of the logic unit is the non-existence state.

[0026] Optionally, the step of continuing to insert a new substrate contact unit according to the updated substrate existence status includes:

[0027] Determine whether the free space of the preset area of ​​the third logic unit whose substrate existence state is the non-existence state supports the insertion of the substrate contact unit;

[0028] If the free space in the preset area of ​​the third logic unit is insufficient to insert the substrate contact unit, it is determined not to insert the substrate contact unit in the preset area of ​​the third logic unit, and the substrate existence state of the third logic unit is the non-existence state.

[0029] Optionally, the method further comprises:

[0030] Increasing the first preset range to a second preset range;

[0031] The substrate existence status of the third logic unit is updated again according to the insertion position of each substrate contact unit and the second preset range.

[0032] Optionally, the method further comprises:

[0033] Adjusting the placement position of the third logic unit so that the free space of the preset area of ​​the third logic placement unit is sufficient to insert the substrate contact unit;

[0034] The substrate contact unit is inserted into a preset area of ​​the adjusted third logic unit.

[0035] In a second aspect, an embodiment of the present application further provides a substrate contact design device, the device comprising:

[0036] An acquisition module, used to acquire a layout design of a preset integrated circuit, wherein the layout design includes a plurality of logic units placed at preset positions;

[0037] An insertion module, used for inserting a substrate contact unit in a preset region of a first logic unit in the preset integrated circuit, wherein the first logic unit is a logic unit in the preset region where no substrate contact unit exists;

[0038] An updating module, configured to update the substrate existence status of the plurality of logic units according to the insertion position of the substrate contact unit and a first preset range, wherein the substrate existence status indicates whether the substrate contact unit exists in a preset area of ​​the logic unit;

[0039] The traversal module is used to traverse the multiple logic units in sequence, and continue to insert new substrate contact units according to the updated substrate existence status until the substrate contact units exist in the preset areas of the multiple logic units, thereby completing the substrate contact design for the preset integrated circuit.

[0040] Optionally, the update module is specifically used to determine a second logic unit located within the first preset range based on the insertion position of the substrate contact unit and the first preset range; filter a target logic unit from the second logic units based on the preset area of ​​the second logic unit and the insertion position of the substrate contact unit, the target logic unit being a second logic unit whose insertion position of the substrate contact unit is within the corresponding preset area; and update the substrate existence status of the target logic unit to an existence status and the substrate existence status of other logic units to a non-existence status.

[0041] Optionally, each substrate contact unit includes: a substrate contact, and the update module is further used to determine, based on the insertion position of the substrate contact unit, that a logic unit directly adjacent to the substrate contact unit on the substrate contact of the substrate contact unit is the second logic unit, and the first preset range is the directly adjacent range.

[0042] Optionally, each substrate contact unit further includes: a well contact, and the update module is further used to determine, based on the insertion position of the substrate contact unit, a logic unit adjacent to the substrate contact unit on the well contact of the substrate contact unit as the second logic unit.

[0043] Optionally, each logic unit has a substrate contact identifier and a well contact identifier, and the update module is further used to determine that the substrate contact identifier and the well contact identifier of the first logic unit are first identifiers; determine that the substrate contact identifier and the well contact identifier of the target logic unit are the first identifier, and the substrate contact identifier and the well contact identifier of other logic units are second identifiers; the first identifier indicates that the substrate existence state of the logic unit is an existence state, and the second identifier indicates that the substrate existence state of the logic unit is a non-existence state.

[0044] Optionally, the traversal module is specifically used to determine whether the free space in the preset area of ​​the third logic unit whose substrate existence state is the non-existent state supports the insertion of the substrate contact unit; if the free space in the preset area of ​​the third logic unit is insufficient to insert the substrate contact unit, it is determined not to insert the substrate contact unit in the preset area of ​​the third logic unit, and the substrate existence state of the third logic unit is the non-existent state.

[0045] Optionally, the updating module is further configured to increase the first preset range to a second preset range; and update the substrate existence status of the third logic unit again according to the insertion position of each substrate contact unit and the second preset range.

[0046] Optionally, the device further comprises:

[0047] An adjustment module, used for adjusting the placement position of the third logic unit so that the free space of the preset area of ​​the third logic placement unit is sufficient to insert the substrate contact unit;

[0048] The insertion module is further used to insert the substrate contact unit into a preset area of ​​the adjusted third logic unit.

[0049] In the third aspect, an embodiment of the present application also provides an electronic device, comprising: a processor, a storage medium and a bus, wherein the storage medium stores program instructions executable by the processor, and when the electronic device is running, the processor communicates with the storage medium through the bus, and the processor executes the program instructions to perform the steps of the substrate contact design method as described in any one of the first aspects.

[0050] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the substrate contact design method as described in any one of the first aspects are executed.

[0051] The beneficial effects of this application are:

[0052] The substrate contact design method, device, electronic device and storage medium provided in the present application update the substrate existence status of multiple logic units based on the insertion position and the first preset range of the substrate contact unit inserted in the preset area of ​​the logic unit, and traverse the multiple logic units in turn. After determining that the substrate contact units exist in the preset areas of the multiple logic units according to the substrate existence status of the multiple logic units, the substrate contact design of the preset integrated circuit is completed. The method optimizes the strategy of sharing the substrate contact unit between the multiple logic units to ensure that there is a substrate contact unit with a relatively close distance in the preset area of ​​each logic unit. In special cases, only a low-resistance substrate contact or well contact leakage path may be provided for the case of high-energy particle injection, thereby improving the anti-latch performance of the circuit. Moreover, by sharing the substrate contact unit between the logic units, the area utilization rate of the substrate contact unit can be improved, and the local unit density of the chip can be reduced, which is beneficial to improving the chip performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0054] Figure 1 is a schematic diagram of arrangement of existing substrate contact units;

[0055] Figure 2 It is a schematic diagram of arrangement of the existing optimized substrate contact unit;

[0056] Figure 3 Schematic diagram of the process of the substrate contact design method provided in the embodiment of the present application Figure 1 ;

[0057] Figure 4 Schematic diagram of the process of the substrate contact design method provided in the embodiment of the present application Figure 2 ;

[0058] Figure 5 Schematic diagram of inserting the substrate contact unit provided in the embodiment of the present application Figure 1 ;

[0059] Figure 6 A schematic diagram of the layout design of a preset integrated circuit provided in an embodiment of the present application;

[0060] Figure 7 A schematic diagram of a preset area of ​​a preset integrated circuit provided in an embodiment of the present application;

[0061] Figure 8Schematic diagram of inserting the substrate contact unit provided in the embodiment of the present application Figure 2 ;

[0062] Fig. 9 Schematic diagram of the process of the substrate contact design method provided in the embodiment of the present application Figure 3 ;

[0063] Fig.10 Schematic diagram of the process of the substrate contact design method provided in the embodiment of the present application Figure 4 ;

[0064] Fig.11 Schematic diagram of the process of the substrate contact design method provided in the embodiment of the present application Figure 5 ;

[0065] Fig.12 A schematic diagram of the structure of a substrate contact design device provided in an embodiment of the present application;

[0066] Fig.13 A schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0067] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments.

[0068] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0069] In the description of the present application, it should be noted that if the terms "upper", "lower", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the drawings, or is the orientation or position relationship in which the product of the application is usually placed when used. It is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0070] In addition, the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0071] It should be noted that, in the absence of conflict, the features in the embodiments of the present application may be combined with each other.

[0072] For general integrated circuit application scenarios, use Figure 1 The arrangement of the substrate contact units shown can basically avoid the influence of the latch effect introduced by the substrate parasitic resistance, but for the semi-custom integrated circuit design under the irradiation environment, due to the randomness of high-energy particles, they can hit the substrate of the chip at any direction and any position, and the latch effect caused by this may cause the circuit to malfunction. Therefore, a substrate contact design method with better anti-latch performance is needed.

[0073] Generally speaking, reducing the spacing of substrate contact cells can improve the chip's anti-latch performance. In the design of radiation-resistant integrated circuits, reducing the spacing of substrate contacts is also an effective method. However, the logic cells in the radiation-resistant semi-custom digital standard cell library are often larger than the cells in the general standard cell library. Reducing the spacing of substrate contact cells will occupy more chip area on the one hand, and on the other hand, because the spacing of substrate contact cells is reduced, the area where logic cells can be placed between substrate contact cells will also be limited, which increases the local cell density and the wiring length between logic cells, which is not conducive to the optimization of chip performance.

[0074] For example, Figure 2 is a schematic diagram of the arrangement of the existing optimized substrate contact unit, such as Figure 2 As shown in (a) and (b) in FIG. 5 , whether the pitch of the fixed-pitch alternating arrangement or the fixed-pitch vertical arrangement is reduced, the density of the same number of logic cells is significantly increased within the same chip area.

[0075] Based on the problems existing in the above-mentioned prior art, the present application intends to provide a substrate contact design method, device, electronic device and storage medium, by inserting a substrate contact unit in a preset area of ​​a first logic unit in a preset integrated circuit, updating the substrate existence status of multiple logic units according to the insertion position of the substrate contact unit and the first preset range, and traversing the multiple logic units in the preset integrated circuit in turn, and completing the substrate contact design of the preset integrated circuit after determining that substrate contact units exist in the preset areas of the multiple logic units according to the substrate existence status of the multiple logic units. This method can improve the area utilization of the substrate contact unit and reduce the local unit density of the chip by optimizing the strategy of sharing the substrate contact unit between multiple logic units, which is beneficial to improving chip performance.

[0076] The specific implementation of the substrate contact design method, device, electronic device and storage medium provided in the present application is described below in conjunction with the embodiments.

[0077] In one possible implementation, Figure 3 Schematic diagram of the process of the substrate contact design method provided in the embodiment of the present application Figure 1 ,like Figure 3 As shown, the method may include:

[0078] S101. Obtain a layout design of a preset integrated circuit, wherein the layout design includes a plurality of logic units placed at preset positions.

[0079] In the prior art substrate contact design method, a fixed spacing of substrate contact units is set before the logic units are placed, and the logic units are placed after the substrate contact units are placed according to the fixed spacing.

[0080] In this embodiment, the logic units in the preset integrated circuit are first arranged, and the arranged logic units are optimized using a layout and routing tool to ensure that the requirements of the design timing and the wiring resources are met.

[0081] S102 . Insert a substrate contact unit in a preset region of a first logic unit in a preset integrated circuit, wherein the first logic unit is a logic unit in which no substrate contact unit exists in the preset region.

[0082] In this embodiment, a preset area is set for a plurality of logic units in a preset integrated circuit, and the size of the preset area can be determined according to actual conditions and is not limited here.

[0083] Each logic unit has a substrate existence state to indicate whether there is a substrate contact unit in a preset area of ​​each logic unit. Before substrate contact design is performed on a preset integrated circuit, the substrate existence states of all logic units are in a non-existent state. One logic unit is selected from multiple logic units as a first logic unit, a substrate contact unit is inserted in the preset area of ​​the first logic unit, and the substrate existence state of the first logic unit is updated to a present state.

[0084] In some embodiments, the method of selecting the first logic unit from multiple logic units can be to select the first logic unit as the first logic unit according to the position arrangement order of the multiple logic units in the preset integrated circuit; or, according to the numbers of the multiple logic units in the preset integrated circuit, select the logic unit numbered 1 as the first logic unit, and the number indicates the order of placement of the logic units.

[0085] In some embodiments, before inserting the substrate contact unit in the predetermined region of the first logic unit in the predetermined integrated circuit, the method may further include:

[0086] Determine whether there is enough free space in the preset area of ​​the first logic unit to insert the substrate contact unit. If so, insert the substrate contact unit in the free space in the preset area of ​​the first logic unit. If not, do not insert the substrate contact unit and continue to traverse the next logic unit.

[0087] S103 . Update substrate existence status of a plurality of logic units according to the insertion position of the substrate contact unit and the first preset range, wherein the substrate existence status indicates whether there is a substrate contact unit in a preset area of ​​the logic unit.

[0088] In this embodiment, after inserting the substrate contact unit into the first logic unit, it is necessary to determine whether other logic units of the preset integrated circuit can share the substrate contact unit with the first logic unit. For the logic units that can share the substrate contact unit with the first logic unit, their substrate existence status is updated to the existence status; for the logic units that cannot share the substrate contact unit with the first logic unit, their substrate existence status is updated to the non-existence status.

[0089] In some embodiments, it can be determined whether other logic units can share the substrate contact unit with the first logic unit according to the insertion position of the substrate contact unit and the preset area of ​​other logic units of the preset integrated circuit. If the preset area of ​​the other logic unit can cover the insertion position of the substrate contact unit, it is determined that the other logic unit can share the substrate contact unit with the first logic unit; if the preset area of ​​the other logic unit cannot cover the insertion position of the substrate contact unit, it is determined that the other logic unit cannot share the substrate contact unit with the first logic unit.

[0090] In other embodiments, it can be determined whether the logic unit within the first preset range can share the substrate contact unit with the first logic unit according to the insertion position of the substrate contact unit and the first preset range. If the preset area of ​​the logic unit within the first preset range can cover the insertion position of the substrate contact unit, it is determined that the logic unit within the first preset range can share the substrate contact unit with the first logic unit; if the preset area of ​​the logic unit within the first preset range cannot cover the insertion position of the substrate contact unit, it is determined that the logic unit within the first preset range cannot share the substrate contact unit with the first logic unit.

[0091] S104, traversing the plurality of logic units in sequence, and continuing to insert new substrate contact units according to the updated substrate existence status, until substrate contact units exist in the preset areas of the plurality of logic units, thereby completing the substrate contact design for the preset integrated circuit.

[0092] In this implementation, continue to traverse the next logical unit to determine the substrate existence status of the next logical unit. If the substrate existence status of the next logical unit is already existing, it is determined that the next logical unit has shared a substrate contact unit with the first logical unit, and no substrate contact unit needs to be inserted into the next logical unit. If the substrate existence status of the next logical unit is not existing, it is determined that the next logical unit does not share a substrate contact unit with the first logical unit, and a substrate contact unit is inserted into a preset area of ​​the next logical unit.

[0093] Afterwards, according to the insertion position of the substrate contact unit inserted into the preset area of ​​the next logic unit and the first preset range, the substrate existence status of other logic units is updated again.

[0094] It should be noted that, for a logic unit that has already been inserted with a substrate contact unit, or that has shared a substrate contact unit with other logic units to update its substrate existence status to an existence status, when updating the substrate existence status based on the newly inserted substrate contact unit, its substrate existence status will not be modified to a non-existence status because it cannot share the newly inserted substrate contact unit with the next logic unit. That is, the substrate existence status of the logic unit whose substrate existence status is still a non-existence status is updated again according to the insertion position and the first preset range of the substrate contact unit inserted in the preset area of ​​the next logic unit.

[0095] Traverse each logic unit in turn to determine the substrate existence state of the logic unit. If the substrate existence state is a non-existent state, insert a substrate existence unit in its preset area, and then update the substrate existence state of the logic unit whose substrate existence state is a non-existent state according to the insertion position of the inserted substrate existence unit and the first preset range; if the substrate existence state is a present state, continue to traverse the next logic unit until all logic units are traversed, so that there are substrate contact units in the preset areas of all logic units, and the substrate contact design of the preset integrated circuit is completed.

[0096] The substrate contact design method provided in the above embodiment updates the substrate existence status of multiple logic units based on the insertion position and the first preset range of the substrate contact unit inserted in the preset area of ​​the logic unit, and traverses the multiple logic units in turn. After determining that the substrate contact units exist in the preset areas of the multiple logic units according to the substrate existence status of the multiple logic units, the substrate contact design of the preset integrated circuit is completed. The method optimizes the strategy of sharing the substrate contact unit between the multiple logic units to ensure that there is a substrate contact unit at a relatively close distance in the preset area of ​​each logic unit. In special cases, only a low-resistance substrate contact or well contact leakage path may be provided for the case of high-energy particle injection, thereby improving the anti-latch performance of the circuit. In addition, by sharing the substrate contact unit between the logic units, the area utilization rate of the substrate contact unit can be improved, and the local unit density of the chip can be reduced, which is beneficial to improving the chip performance.

[0097] In one possible implementation, Figure 4 Schematic diagram of the process of the substrate contact design method provided in the embodiment of the present application Figure 2 ,like Figure 4 As shown, the process of updating the substrate existence status of the plurality of logic units according to the insertion position of the substrate contact unit and the first preset range in S103 may include:

[0098] S201 . Determine a second logic unit located within the first preset range according to an insertion position of a substrate contact unit and a first preset range.

[0099] In this embodiment, taking the insertion position of the substrate contact unit as the center, a search is performed within a first preset range of the insertion position, and a logic unit located within the first preset range among the plurality of logic units is determined as the second logic unit.

[0100] In some embodiments, if there is no logic unit within the first preset range of the insertion position, it is determined that there is no logic unit that shares a substrate contact unit with the first logic unit, and the traversal continues to the next logic unit.

[0101] S202 , selecting a target logic unit from the second logic units according to the preset area of ​​the second logic unit and the insertion position of the substrate contact unit, the target logic unit being the second logic unit whose insertion position of the substrate contact unit is within the corresponding preset area.

[0102] In this embodiment, it is determined whether the preset area of ​​the second logic unit can cover the insertion position of the substrate contact unit, that is, whether the insertion position of the substrate contact unit is within the preset area of ​​the second logic unit. If the preset area of ​​the second logic unit can cover the insertion position of the substrate contact unit, it is determined that the second logic unit can share the substrate contact unit with the first logic unit, and the second logic unit is determined to be the target logic unit. If the preset area of ​​the second logic unit cannot cover the insertion position of the substrate contact unit, it is determined that the second logic unit cannot share the substrate contact unit with the first logic unit, and the second logic unit is determined not to be the target logic unit.

[0103] S203 , updating the substrate existence status of the target logical unit to the existence status, and updating the substrate existence status of other logical units to the non-existence status.

[0104] In this embodiment, it is determined that the substrate existence state of the target logical unit is the existence state, and the substrate existence states of other logical units except the target logical unit and the first logical unit are the non-existence state.

[0105] The substrate contact design method provided in the above embodiment searches for the second logic unit located within the first preset range of the insertion position of the substrate contact unit, and determines whether the second logic unit can share the substrate contact unit with the first logic unit based on the preset area of ​​the second logic unit and the insertion position of the substrate contact unit. By sharing the substrate contact unit, the area utilization of the substrate contact unit can be improved, the area of ​​the substrate contact unit is optimized, and it is beneficial to improve the chip performance.

[0106] In a possible implementation, each substrate contact unit includes: a substrate contact, and the process of determining the second logic unit located within the first preset range according to the insertion position of the substrate contact unit and the first preset range in S201 may include:

[0107] According to the insertion position of the substrate contact unit, a logic unit directly adjacent to the substrate contact unit on the substrate contact of the substrate contact unit is determined as the second logic unit, and the first preset range is the directly adjacent range.

[0108] In this embodiment, the substrate contact unit is composed of a substrate contact and a well contact, the substrate contact provides a connection between the metal and the substrate, the substrate contact is connected to the VDD potential or the VSS potential, and the logic unit shares the substrate contact with the substrate contact unit to be connected to the VDD potential or the VSS potential through the substrate contact of the substrate contact unit.

[0109] Determine the logic unit located in the substrate placement row of the substrate contact unit, and determine the logic unit directly adjacent to the substrate contact unit on the substrate contact as the second logic unit according to the insertion position of the substrate contact unit, and the directly adjacent range is the range located on the left and right sides of the substrate contact unit on the substrate contact.

[0110] In some embodiments, the power line divides the substrate contact of the substrate contact unit into two substrate placement rows, and a second logic unit directly adjacent to the substrate contact unit needs to be determined on the two substrate placement rows respectively.

[0111] For example, Figure 5 Schematic diagram of inserting the substrate contact unit provided in the embodiment of the present application Figure 1 ,like Figure 5 As shown, the substrate contact unit Tap Cell includes: a substrate contact, a power line is set in the middle of the substrate contact, and two substrate rows of logic units in contact with it are placed on the upper and lower sides of the power line, namely Substrate Row1 and Substrate Row2, and the substrates of Substrate Row1 and Substrate Row2 are connected to their corresponding potentials, namely VDD potential or VSS potential, through the substrate contact, so that two adjacent rows of logic units can share the power line.

[0112] like Figure 5 As shown, although the insertion position of the substrate contact unit Tap Cell shown in the figure is on the substrate placement row Substrate Row2, in fact, the substrate placement rows Substrate Row1 and Substrate Row2 together constitute the substrate contact of the substrate contact unit. Therefore, the insertion position of the substrate contact unit Tap Cell also includes the corresponding position of the substrate placement row Substrate Row1.

[0113] The second logic cells directly adjacent to the substrate contact unit Tap Cell on the substrate placement row Substrate Row2 are Logic Cell5 and Logic Cell6, and the second logic cells directly adjacent to the substrate contact unit Tap Cell on the substrate placement row Substrate Row1 are Logic Cell2 and Logic Cell7.

[0114] In a possible implementation, each substrate contact unit includes: a substrate contact, and the process of determining the second logic unit located within the first preset range according to the insertion position of the substrate contact unit and the first preset range in S201 may include:

[0115] In this embodiment, the well contact provides a connection between the metal and the well well, the well contact is connected to the VDD potential or the VSS potential, and the logic unit and the substrate contact unit share the well contact to be connected to the VDD potential or the VSS potential through the well contact of the substrate contact unit. If the substrate contact is connected to the VDD potential, the well contact is connected to the VSS potential, and if the substrate contact is connected to the VSS potential, the well contact is connected to the VDD potential, which needs to be determined according to the type of the logic unit.

[0116] Determine the logic unit located in the well placement row of the substrate contact unit, and according to the insertion position of the substrate contact unit, determine the logic unit directly adjacent to the substrate contact unit on the well contact as the second logic unit, and the directly adjacent range is the range on the left and right sides of the substrate contact unit on the well placement row.

[0117] In some embodiments, the substrate contact unit may be a substrate contact unit of an N-well P-substrate, or a substrate contact unit of a P-well N-substrate. In the drawings of this solution, an N-well P-substrate is used for representation.

[0118] In some embodiments, the power line divides the well contact of the substrate contact unit into two well placement rows, and a second logic unit directly adjacent to the substrate contact unit needs to be determined on the two well placement rows respectively.

[0119] For example, Figure 5 As shown, the substrate contact unit Tap Cell includes: a well contact, a power line is arranged in the middle of the well contact, and the upper and lower sides of the power line are well rows of logic units in contact with it, namely Well Row1 and Well Row2. The well contacts of WellRow1 and Well Row2 are connected to their corresponding potentials, namely VDD potential or VSS potential, through the well contacts, so that two adjacent rows of logic units can share the power line.

[0120] like Figure 5 As shown, although the insertion position of the substrate contact unit Tap Cell shown in the figure is on the well row Well Row1, in fact, the well row Well Row1 and Well Row2 together constitute the well contact of the substrate contact unit. Therefore, the insertion position of the substrate contact unit Tap Cell also includes the corresponding position of the well row Well Row2.

[0121] The second logic cells directly adjacent to the substrate contact cell Tap Cell on the well row Well Row1 are Logic Cell5 and Logic Cell6, and the second logic cell directly adjacent to the substrate contact cell Tap Cell on the well row Substrate 2 is Logic Cell4.

[0122] The contact substrate design method provided in the above embodiment determines the second logic unit adjacent to the substrate contact unit on the substrate contact and the well contact of the substrate contact unit respectively, thereby ensuring that the logic unit sharing the substrate contact unit with the first logic unit can be found on both the substrate contact and the well contact, thereby optimizing the sharing strategy of the substrate contact unit and improving the area utilization of the substrate contact unit.

[0123] In a possible implementation, each logic unit has a substrate contact mark and a well contact mark. After the above S102 inserts the substrate contact unit in a preset region of the first logic unit in the preset integrated circuit, the method may further include:

[0124] A substrate contact identifier and a well contact identifier of the first logic unit are determined as first identifiers.

[0125] The process of updating the substrate existence status of the target logic unit to the existence status and the substrate existence status of other logic units to the non-existence status in S203 may include:

[0126] The substrate contact identifier and the well contact identifier of the target logic unit are determined as the first identifier, and the substrate contact identifiers and the well contact identifiers of other logic units are determined as the second identifier.

[0127] In this embodiment, two identifiers are set for each logic unit, namely a substrate contact identifier and a well contact identifier. The substrate contact identifier and the well contact identifier can be set to a first identifier or a second identifier. The first identifier indicates that the substrate existence state of the logic unit is an existence state, and the second identifier indicates that the substrate existence state of the logic unit is a non-existence state. After the logic unit is inserted into a preset integrated circuit, the substrate contact identifier and the well contact identifier of the logic unit default to the second identifier.

[0128] After the substrate contact unit is inserted into the preset area of ​​the first logic unit, the substrate contact identifier and the well contact identifier of the first logic unit are modified to the first identifier, and according to the insertion position of the substrate contact unit and the first preset range, the target logic unit that can share the substrate insertion unit with the first logic unit within the first preset range is determined, and the substrate contact identifier and the well contact identifier of the target logic unit are modified to the first identifier.

[0129] Continue to traverse the next logic unit. If the substrate contact identifier and well contact identifier of the next logic unit are the second identifier, insert the substrate contact unit in the preset area of ​​the next logic unit, and continue to determine the target logic unit that can share the substrate contact unit with the next logic unit within the first preset range of the newly inserted substrate contact unit, and modify the substrate contact identifier and well contact identifier of the target logic unit to the first identifier. If the substrate contact identifier and well contact identifier of the next logic unit are the first identifier, continue to traverse other logic units.

[0130] The specific process of designing substrate contacts for a preset integrated circuit is described below with reference to the accompanying drawings.

[0131] Figure 6 A schematic diagram of the layout design of a preset integrated circuit provided in an embodiment of the present application is shown in FIG. Figure 6 As shown, after the layout design of the preset integrated circuit is performed, a preset integrated circuit including a plurality of arranged logic units is obtained.

[0132] Figure 7 A schematic diagram of a preset region of a preset integrated circuit provided in an embodiment of the present application, such as Figure 7 As shown, with each logic cell Logic Cell i as the center and a preset r value as the radius, a circular area is set for the Omni logic cell Logic Cell i, and is named Circle Logic Cell1, Circle Logic Cell2, and so on.

[0133] A substrate contact flag Flag Substrate Logic Cell i and a well contact flag Flag Well Logic Cell i are set for each logic cell Logic Cell i. If the substrate contact flag Flag Substrate Logic Cell i and the well contact flag Flag Well Logic Cell i are 0, it indicates that there is no substrate contact unit in the circular area CircleLogic Cell i of the logic cell Logic Cell i; if the substrate contact flag Flag Substrate Logic Cell i and the well contact flag Flag Well Logic Cell i are 1, it indicates that there is a substrate contact unit in the circular area CircleLogic Cell i of the logic cell Logic Cell i.

[0134] like Figure 7As shown, taking the logic cell Logic Cell5 as an example, if there is no substrate contact unit in the circular area Circle Logic Cell5 of the logic cell Logic Cell5, that is, the substrate contact flag Flag Substrate Logic Cell5 and the well contact flag Flag Well Logic Cell5 are 0.

[0135] Figure 8 Schematic diagram of inserting the substrate contact unit provided in the embodiment of the present application Figure 2 ,like Figure 8 As shown, a substrate contact cell Tap Cell is inserted into the empty space of the circular area Circle Logic Cell5 of the logic cell Logic Cell5, and the substrate contact flag Flag Substrate Logic Cell5 and the well contact flag Flag Well Logic Cell5 of the logic cell Logic Cell5 are modified to 1.

[0136] Taking the inserted substrate contact unit Tap Cell as the center, the substrate contact and the well contact of the substrate contact unit Tap Cell are respectively searched for the second logic unit adjacent to the substrate contact unit Tap Cell.

[0137] like Figure 8 As shown, the logic cell adjacent to the substrate contact unit Tap Cell searched to the left of substrate placement row Substrate Row1 is Logic Cell2, the logic cell adjacent to the substrate contact unit Tap Cell searched to the right of substrate placement row Substrate Row1 is Logic Cell7, the logic cell adjacent to the substrate contact unit Tap Cell searched to the left of substrate placement row Substrate Row2 is Logic Cell5, and the logic cell adjacent to the substrate contact unit Tap Cell searched to the right of substrate placement row Substrate Row2 is Logic Cell6.

[0138] Similarly, the logic cell adjacent to the substrate contact unit Tap Cell found to the left of the well row Well Row1 is Logic Cell5, the logic cell adjacent to the substrate contact unit Tap Cell found to the right of the well row Well Row1 is Logic Cell6, the logic cell adjacent to the substrate contact unit Tap Cell found to the left of the well row Well Row2 is Logic Cell4, and no logic cell adjacent to the substrate contact unit Tap Cell is found to the right of the well row Well Row2.

[0139] Therefore, it can be determined that the second logic cells within the first preset range include: Logic Cell 2, Logic Cell 4, Logic Cell 6, and Logic Cell 7.

[0140] Next, the searched second logic cell is screened to determine whether the circular area of ​​the searched second logic cell can cover the inserted substrate contact unit Tap Cell. If the circular area of ​​the searched second logic cell cannot cover the inserted substrate contact unit Tap Cell, the corresponding substrate contact identifier Flag Substrate LogicCell i and the well contact identifier Flag Well Logic Cell i are not modified. If the circular area of ​​the searched second logic cell can cover the inserted substrate contact unit Tap Cell, they are modified to 1.

[0141] like Figure 8 As shown, the circular area of ​​the logic cell Logic Cell2 cannot cover the substrate contact cell TapCell, so the substrate contact flag Flag Substrate Logic Cell2 and the well contact flag Flag Well Logic Cell2 of the logic cell Logic Cell2 remain at 0.

[0142] The circular area of ​​the logic cell Logic Cell4 cannot cover the substrate contact cell Tap Cell, so the substrate contact flag Flag Substrate Logic Cell4 and the well contact flag Flag WellLogic Cell4 of the logic cell Logic Cell24 remain at 0.

[0143] The circular area of ​​the logic cell Logic Cell6 can cover the substrate contact cell Tap Cell, so the substrate contact flag Flag Substrate Logic Cell6 and the well contact flag Flag WellLogic Cell6 of the logic cell Logic Cell6 are modified to 1.

[0144] The circular area of ​​the logic cell Logic Cell7 can cover the substrate contact cell Tap Cell, so the substrate contact flag Flag Substrate Logic Cell7 and the well contact flag Flag WellLogic Cell7 of the logic cell Logic Cell7 are modified to 1.

[0145] Next, continue to traverse other logic cells. When traversing to logic cell Logic Cell4 or logic cell Logic Cell6, it is necessary to insert a substrate contact unit in its circular area, and use this substrate contact unit to update the substrate contact identifiers and well contact identifiers of other logic cells. When traversing to logic cell Logic Cell6 and logic cell Logic Cell7, it is not necessary to insert new substrate contact units in logic cell Logic Cell6 and logic cell Logic Cell7. Logic cell Logic Cell6 and logic cell Logic Cell7 share substrate contact units with logic cell Logic Cell5.

[0146] Traverse each logic cell Logic Cell i in turn, and repeat the above steps until all logic cells Logic Cell are traversed. If the substrate contact flag Flag Substrate Logic Celli and the well contact flag Flag Well Logic Cell i of all logic cells are 1, the substrate contact design of the preset integrated circuit is completed.

[0147] In one possible implementation, Fig. 9 Schematic diagram of the process of the substrate contact design method provided in the embodiment of the present application Figure 3 ,like Fig. 9 As shown, the process of continuing to insert a new substrate contact unit according to the updated substrate existence status in S104 may include:

[0148] S301 , determining whether the free space in the preset area of ​​the third logic unit whose substrate presence state is the non-existent state supports the insertion of the substrate contact unit.

[0149] S302: If the free space in the preset area of ​​the third logic unit is insufficient to insert the substrate contact unit, determine not to insert the substrate contact unit in the preset area of ​​the third logic unit, and the substrate existence state of the third logic unit is the non-existence state.

[0150] In this embodiment, since this scheme adopts the logic of placing the logic unit first and then inserting the substrate contact unit, other logic units may exist in the preset area set for the logic unit, resulting in insufficient space in the preset area of ​​the logic unit to support the insertion of the substrate contact unit. Therefore, for each logic unit, in addition to determining the existence status of its substrate, it is also necessary to determine whether the free space in its preset area supports the substrate contact unit.

[0151] In the process of traversing each logic unit, if the substrate existence state of the traversed logic unit is the existence state, it is determined that there is no need to insert a substrate contact unit in the preset area of ​​the logic unit. Therefore, it is not necessary to consider whether the size of the free space in the preset area of ​​the logic unit supports the insertion of the substrate contact unit. If the third logic unit whose substrate existence state is the non-existence state is traversed, since the third logic unit and the logic unit into which the substrate contact unit has been inserted cannot share the substrate contact unit, it is necessary to insert a substrate contact unit for the third logic unit.

[0152] Before inserting the substrate contact unit into the third logic unit, it is necessary to first determine whether the free space in the preset area of ​​the third logic unit supports the insertion of the substrate contact unit. If the free space in the preset area of ​​the third logic unit supports the insertion of the substrate contact unit, directly insert the substrate contact unit into the free space in the preset area of ​​the third logic unit, and perform the same steps as the above S103 to update the substrate existence status of other logic units.

[0153] If the free space of the preset area of ​​the third logic unit does not support the insertion of the substrate contact unit, the substrate contact unit is not inserted in the preset area of ​​the third logic unit, and it is determined that the substrate existence state of the third logic unit is still not in the non-existence state.

[0154] After that, continue to traverse other logic cells, after traversing all logic cells, for the remaining logic cells whose substrate exists but not exists, that is, the substrate contact flag Flag Substrate Logic Cell i and the well contact flag Flag Well Logic Cell i are still not 0. Taking the third logic cell as an example, two different solutions are provided.

[0155] In one possible implementation, Fig.10 Schematic diagram of the process of the substrate contact design method provided in the embodiment of the present application Figure 4 ,like Fig.10 As shown, the method may also include:

[0156] S401: Increase the first preset range to a second preset range.

[0157] S402 , updating the substrate existence state of the third logic unit again according to the insertion position of each substrate contact unit and the second preset range.

[0158] In this embodiment, the first preset range is increased to a second preset range. For each inserted substrate contact unit, it is determined whether the preset area of ​​the logic unit whose substrate existence state is still in the non-existent state within the second preset range can cover the corresponding substrate contact unit according to the insertion position of each substrate contact unit and within the second preset range. If the preset area of ​​the logic unit whose substrate existence state is still in the non-existent state within the second preset range can cover the corresponding substrate contact unit, the substrate existence state of the logic unit is modified to the existing state.

[0159] If the third logic unit is located within the second preset range, determine whether the preset area of ​​the third logic unit can cover the corresponding substrate contact unit; if the preset area of ​​the third logic unit can cover the corresponding substrate contact unit, modify the substrate existence state of the third logic unit to the existence state.

[0160] In some embodiments, the second preset range may be an indirectly adjacent range, for example, may be an adjacent range separated by one logical unit.

[0161] Furthermore, the preset range of the substrate contact unit may be continuously increased, for example, by spacing the range between two adjacent logic units, so that the preset areas of all logic units may cover at least one substrate contact unit.

[0162] In another possible implementation, if the preset range of the substrate contact unit is expanded without limit, on the one hand, the logic unit within the expanded preset range is far away from the substrate contact unit, and its preset area is difficult to cover the substrate contact unit, and the logic unit still cannot share the substrate contact unit; on the other hand, even if the preset area of ​​the logic unit is large enough so that the preset area of ​​the logic unit can still cover the substrate contact unit under the expanded preset range, the logic unit is far away from the substrate contact unit, so it cannot use the substrate contact unit to achieve anti-latch. For this reason, another implementation method of inserting substrate contact units into these logic units is provided.

[0163] Specifically, if the preset area of ​​the third logic unit cannot cover the corresponding substrate contact unit, the substrate existence state of the third logic unit is still in the non-existence state. Fig.11 Schematic diagram of the process of the substrate contact design method provided in the embodiment of the present application Figure 5 ,like Fig.11 As shown, the method also includes:

[0164] S501, adjusting the placement position of the third logic unit so that the free space in the preset area of ​​the third logic placement unit is sufficient to insert the substrate contact unit.

[0165] S502 , inserting a substrate contact unit into a preset area of ​​the adjusted third logic unit.

[0166] In this embodiment, since the free space of the preset area of ​​the third logic unit is not enough to insert the substrate contact unit, the third logic unit can be controlled to move to the free area of ​​the preset integrated circuit by adjusting the placement position of the third logic unit, so that the free space on at least one side of the preset area of ​​the third logic unit is increased to be sufficient to insert the substrate contact unit, and then the substrate contact unit is inserted into the free space. For example, the third logic unit can be moved upward, downward, leftward or rightward so that the free space on the upper side, lower side, left side or right side of the preset area of ​​the third logic unit is sufficient to insert the substrate contact unit.

[0167] In some embodiments, if the substrate existence status of multiple logic units is a non-existent state, after each adjustment of the placement position of a logic unit and the insertion of a substrate contact unit, the step S103 described above is continued to update the substrate existence status of the logic unit in the non-existent state to ensure that the substrate contact unit can be shared between the logic units as much as possible.

[0168] It should be noted that the above steps S401-S402 and S501-S502 can be two steps implemented in parallel, that is, for the third logic unit, you can choose to execute S401-S402 or S501-S502. The above steps S401-S402 and S501-S502 can also be steps executed sequentially, that is, for the third logic unit, first execute S401-S402. If after executing S401-S402, the substrate existence state of the third logic unit is still the non-existence state, then execute S501-S502. This embodiment does not limit this.

[0169] The substrate contact design method provided in the above embodiment increases the preset range of the substrate contact unit or adjusts the placement of the logic unit so that there is a substrate contact unit in the preset area of ​​each logic unit, thereby ensuring that there is a substrate contact unit at a relatively close distance in the preset area of ​​each logic unit, thereby improving the anti-latch performance of the circuit and optimizing the strategy of sharing the substrate contact unit between logic units, which can improve the area utilization of the substrate contact unit, reduce the local unit density of the chip, and is beneficial to improving chip performance.

[0170] Based on the above method embodiment, the present application embodiment further provides a substrate contact design device. Fig.12 A schematic diagram of the structure of the substrate contact design device provided in the embodiment of the present application, such as Fig.12 As shown, the device may include:

[0171] An acquisition module 601 is used to acquire a layout design of a preset integrated circuit, wherein the layout design includes a plurality of logic units placed at preset positions;

[0172] Insertion module 602, used for inserting a substrate contact unit in a preset region of a first logic unit in a preset integrated circuit, wherein the first logic unit is a logic unit in which no substrate contact unit exists in the preset region;

[0173] An updating module 603 is used to update the substrate existence status of the plurality of logic units according to the insertion position of the substrate contact unit and the first preset range, wherein the substrate existence status indicates whether there is a substrate contact unit in a preset area of ​​the logic unit;

[0174] The traversal module 604 is used to traverse the multiple logic units in sequence, and continue to insert new substrate contact units according to the updated substrate existence status until there are substrate contact units in the preset areas of the multiple logic units, thereby completing the substrate contact design for the preset integrated circuit.

[0175] Optionally, the update module 603 is specifically used to determine the second logic unit located within the first preset range based on the insertion position of the substrate contact unit and the first preset range; filter the target logic unit from the second logic units based on the preset area of ​​the second logic unit and the insertion position of the substrate contact unit, the target logic unit being the second logic unit whose insertion position of the substrate contact unit is within the corresponding preset area; and update the substrate existence status of the target logic unit to the existence state and the substrate existence status of other logic units to the non-existence state.

[0176] Optionally, each substrate contact unit includes: a substrate contact, an update module 603, and is further used to determine, according to the insertion position of the substrate contact unit, a logic unit directly adjacent to the substrate contact unit on the substrate contact of the substrate contact unit as a second logic unit, and the first preset range is a directly adjacent range.

[0177] Optionally, each substrate contact unit further includes: a well contact, and an updating module 603 is further used to determine, according to the insertion position of the substrate contact unit, a logic unit adjacent to the substrate contact unit on the well contact of the substrate contact unit as the second logic unit.

[0178] Optionally, each logic unit has a substrate contact identifier and a well contact identifier, and the update module 603 is further used to determine the substrate contact identifier and the well contact identifier of the first logic unit as the first identifier; determine the substrate contact identifier and the well contact identifier of the target logic unit as the first identifier, and the substrate contact identifier and the well contact identifier of other logic units as the second identifier; the first identifier indicates that the substrate existence state of the logic unit is the existence state, and the second identifier indicates that the substrate existence state of the logic unit is the non-existence state.

[0179] Optionally, the traversal module 604 is specifically used to determine whether the free space in the preset area of ​​the third logic unit whose substrate existence state is the non-existent state supports the insertion of the substrate contact unit; if the free space in the preset area of ​​the third logic unit is insufficient to insert the substrate contact unit, it is determined not to insert the substrate contact unit in the preset area of ​​the third logic unit, and the substrate existence state of the third logic unit is the non-existent state.

[0180] Optionally, the updating module 603 is further configured to increase the first preset range to a second preset range; and update the substrate existence state of the third logic unit again according to the insertion position of each substrate contact unit and the second preset range.

[0181] Optionally, the device further comprises:

[0182] An adjustment module, used for adjusting the placement position of the third logic unit so that the free space of the preset area of ​​the third logic placement unit is sufficient to insert the substrate contact unit;

[0183] The inserting module 602 is further used to insert a substrate contact unit into a preset area of ​​the adjusted third logic unit.

[0184] The above-mentioned device is used to execute the method provided by the aforementioned embodiment, and its implementation principle and technical effect are similar, which will not be repeated here.

[0185] The above modules may be one or more integrated circuits configured to implement the above methods, such as one or more application specific integrated circuits (ASICs), or one or more microprocessors, or one or more field programmable gate arrays (FPGAs). For another example, when a module is implemented in the form of a processing element scheduling program code, the processing element may be a general-purpose processor, such as a central processing unit (CPU) or other processor that can call program code. For another example, these modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).

[0186] Fig.13 A schematic diagram of an electronic device provided in an embodiment of the present application, such as Fig.13As shown, the electronic device 700 may include: a processor 701, a storage medium 702 and a bus, the storage medium 702 stores program instructions executable by the processor 701, when the electronic device 700 is running, the processor 701 and the storage medium 702 communicate through the bus, and the processor 701 executes the program instructions to execute the above method embodiment. The specific implementation method and technical effect are similar and will not be repeated here.

[0187] Optionally, the present application further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the above method embodiment is executed.

[0188] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0189] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0190] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0191] The above-mentioned integrated unit implemented in the form of a software functional unit can be stored in a computer-readable storage medium. The above-mentioned software functional unit is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor (English: processor) to perform some steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (English: Read-Only Memory, abbreviated: ROM), random access memory (English: Random Access Memory, abbreviated: RAM), disk or optical disk and other media that can store program codes.

[0192] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A substrate contact design method, characterized in that: The method comprises: Obtaining a layout design of a preset integrated circuit, wherein the layout design includes a plurality of logic units arranged at preset positions; Inserting a substrate contact unit in a preset region of a first logic unit in the preset integrated circuit, wherein the first logic unit is a logic unit in which no substrate contact unit exists in the preset region; updating the substrate existence status of the plurality of logic units according to the insertion position of the substrate contact unit and the first preset range, wherein the substrate existence status indicates whether the substrate contact unit exists in a preset area of ​​the logic unit; The multiple logic units are traversed in sequence, and new substrate contact units are continuously inserted according to the updated substrate existence status, until the substrate contact units exist in the preset areas of the multiple logic units, thereby completing the substrate contact design for the preset integrated circuit.

2. The method according to claim 1, characterized in that The updating of the substrate existence status of the plurality of logic units according to the insertion position of the substrate contact unit and the first preset range includes: Determining a second logic unit located within the first preset range according to an insertion position of the substrate contact unit and the first preset range; According to the preset area of ​​the second logic unit and the insertion position of the substrate contact unit, a target logic unit is selected from the second logic units, wherein the target logic unit is a second logic unit whose insertion position of the substrate contact unit is within the corresponding preset area; The substrate existence status of the target logic unit is updated to the existence status, and the substrate existence status of other logic units is updated to the non-existence status.

3. The method according to claim 2, characterized in that Each substrate contact unit includes: a substrate contact, wherein the second logic unit located within the first preset range is determined according to the insertion position of the substrate contact unit and the first preset range, including: According to the insertion position of the substrate contact unit, a logic unit directly adjacent to the substrate contact unit on the substrate contact of the substrate contact unit is determined as the second logic unit, and the first preset range is the directly adjacent range.

4. The method according to claim 3, characterized in that Each substrate contact unit further includes a well contact, and the second logic unit located within the first preset range is determined according to the insertion position of the substrate contact unit and the first preset range, and further includes: According to the insertion position of the substrate contact unit, a logic unit adjacent to the substrate contact unit on the well contact of the substrate contact unit is determined as the second logic unit.

5. The method according to claim 2, characterized in that Each logic unit has a substrate contact mark and a well contact mark. After inserting the substrate contact unit in the preset area of ​​the first logic unit in the preset integrated circuit, the method further includes: Determining a substrate contact identifier and a well contact identifier of the first logic unit as a first identifier; The updating of the substrate existence state of the target logic unit to the existence state and the substrate existence state of other logic units to the non-existence state includes: Determine the substrate contact identifier and the well contact identifier of the target logic unit as the first identifier, and the substrate contact identifiers and the well contact identifiers of other logic units as the second identifier; The first identifier indicates that the substrate existence state of the logic unit is the existence state, and the second identifier indicates that the substrate existence state of the logic unit is the non-existence state.

6. The method according to claim 1, characterized in that The method of continuing to insert a new substrate contact unit according to the updated substrate existence state includes: Determine whether the free space of the preset area of ​​the third logic unit whose substrate existence state is the non-existence state supports the insertion of the substrate contact unit; If the free space in the preset area of ​​the third logic unit is insufficient to insert the substrate contact unit, it is determined not to insert the substrate contact unit in the preset area of ​​the third logic unit, and the substrate existence state of the third logic unit is the non-existence state.

7. The method according to claim 6, characterized in that The method further comprises: Increasing the first preset range to a second preset range; The substrate existence status of the third logic unit is updated again according to the insertion position of each substrate contact unit and the second preset range.

8. The method according to claim 6 or 7, characterized in that The method further comprises: Adjusting the placement position of the third logic unit so that the free space of the preset area of ​​the third logic placement unit is sufficient to insert the substrate contact unit; The substrate contact unit is inserted into a preset area of ​​the adjusted third logic unit.

9. A substrate contact design device, characterized in that: The device comprises: An acquisition module, used to acquire a layout design of a preset integrated circuit, wherein the layout design includes a plurality of logic units placed at preset positions; An insertion module, used for inserting a substrate contact unit in a preset region of a first logic unit in the preset integrated circuit, wherein the first logic unit is a logic unit in the preset region where no substrate contact unit exists; An updating module, configured to update the substrate existence status of the plurality of logic units according to the insertion position of the substrate contact unit and a first preset range, wherein the substrate existence status indicates whether the substrate contact unit exists in a preset area of ​​the logic unit; The traversal module is used to traverse the multiple logic units in sequence, and continue to insert new substrate contact units according to the updated substrate existence status until the substrate contact units exist in the preset areas of the multiple logic units, thereby completing the substrate contact design for the preset integrated circuit.

10. An electronic device, characterized in that: include: A processor, a storage medium and a bus, wherein the storage medium stores program instructions executable by the processor, and when the electronic device is running, the processor communicates with the storage medium via the bus, and the processor executes the program instructions to perform the steps of the substrate contact design method as described in any one of claims 1 to 8.

11. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the substrate contact design method according to any one of claims 1 to 8 are executed.

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