GCN-oriented bidirectional aggregation computing accelerator and system

Abstract

The invention discloses a GCN-oriented bidirectional aggregation calculation accelerator, which relates to the technical field of graph convolutional networks and comprises a preprocessing algorithm, a CPU, a DDR, a controller, a bidirectional connection aggregation calculation array, a connection edge data buffer area, a sliding data table, a node data buffer area, a feature matrix buffer area, a conflict data buffer area and an aggregation result buffer area. The CPU configures the size of a two-way aggregation calculation array and the line number of data sliding, and a preprocessing algorithm judges whether data sliding is carried out or not and records the data in a sliding data table; the preprocessing algorithm schedules a product result and writes the product result into an aggregation result buffer. The decoding complexity is reduced by simply sliding the data information, and the calculation result is slid to the corresponding calculation unit, so that the hardware resource consumption is reduced, the problem of unbalanced load of each calculation unit caused by unbalanced data distribution of the connection edge is effectively solved, the utilization rate of the calculation unit is remarkably improved, and better configurability and universality are achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of graph convolutional networks, and more specifically, to a bidirectional aggregation computing accelerator and system for GCN. Background Art

[0002] In recent years, with the rapid development of artificial intelligence and big data technology, Graph Convolutional Network (GCN), as an emerging deep learning method, has demonstrated excellent capabilities in modeling and learning graph structured data, and has made breakthrough progress in many application fields such as social network analysis, bioinformatics, and recommendation systems. With the continuous advancement of technology and the continuous expansion of application scenarios, the application prospects of GCN will be broader.

[0003] In real graph datasets, graphs usually present irregular structures, resulting in uneven node distribution and irregular arrangement of the adjacency matrix of the graph. The sparsity of the feature matrix varies with different datasets. For example, the feature matrix of the core dataset is highly sparse, while the feature matrix of the reddit dataset is dense. Therefore, GCN needs to perform sparse-sparse matrix multiplication or sparse-dense matrix multiplication when performing node aggregation. This large-scale and irregular computing mode poses a huge challenge to the hardware architecture.

[0004] At present, traditional hardware structures have poor adaptability to irregular computing requirements, which easily leads to waste of computing resources and low computing efficiency. Architectures with high computing efficiency often require complex software scheduling or hardware design, which is not conducive to subsequent system integration and layout and wiring. Summary of the invention

[0005] The purpose of the present invention is to overcome the defects of the traditional hardware structure in the prior art that has poor adaptability to irregular computing requirements, easily causes waste of computing resources and low computing efficiency, and the architecture with high computing efficiency often requires complex software scheduling or hardware design, which is not conducive to subsequent system integration and layout and wiring, and to provide a bidirectional aggregate computing accelerator for GCN.

[0006] To achieve the above object, the technical solution of the present invention is as follows:

[0007] A bidirectional aggregation computing accelerator for GCN, comprising: a CPU, a preprocessing algorithm, a DDR, a controller, a bidirectional connection aggregation computing array, a connection edge data buffer, a sliding data table, a node data buffer, a feature matrix buffer, a conflict data buffer, and an aggregation result buffer;

[0008] The CPU configures the size of the bidirectional aggregation calculation array and the number of rows of data sliding and determines whether each connection edge data needs to slide data through the preprocessing algorithm. The preprocessing algorithm schedules the product results in the bidirectional connection aggregation calculation array and obtains the sliding data table according to the result determined by the preprocessing algorithm.

[0009] The CPU configures the controller and initiates reading and writing of the DDR. The controller reads the node information of the connection edge data buffer and controls the data flow of the corresponding data of the node data buffer and the feature matrix buffer in each computing unit in the bidirectional connection aggregation computing array according to the information in the sliding data table. The conflict data buffer is used to store the redundant connection edge data in the node that cannot slide data;

[0010] After the calculation is completed, the calculation unit sends an end signal, and the calculation result is written into the aggregation result buffer.

[0011] As a preferred solution, the preprocessing algorithm comprises the following steps:

[0012] Initialize and create a list of fixed number of boxes, an empty sequence for storing numbers that cannot be put into the box, and the state parameters of all boxes;

[0013] Input a digital sequence and traverse it, count the number of times the number appears, and split the input digital sequence into the first-appearing and non-first-appearing digital sequences;

[0014] Traverse the first occurrence of the number sequence. If the box with the corresponding number is empty, put the corresponding number in it and set the state parameter of the box.

[0015] Traverse the non-first-appearing number sequence. For each number, first check the previous box of the corresponding number box with a sequence number greater than 1. If the previous box is empty, put the number in and update the state parameter of the corresponding box. If the previous box is not empty, check the next box of the corresponding number box with a sequence number less than the total number of boxes. If the next box is empty, put the number in and update the state parameter of the corresponding box. If the next box is not empty either, add the number to the empty sequence.

[0016] Traverse all boxes and update the status parameters of empty boxes;

[0017] The output results include the state parameters of each box and the sequence of numbers that cannot be put into the box.

[0018] As a preferred solution, the sliding data table includes connection edge data, sliding information configuration and a valid value flag, the sliding information configuration indicates that the product result does not need to slide or slide up or down, and the valid value flag indicates whether the value of the second multiplication number in the product result is valid.

[0019] As a preferred solution, the preprocessing algorithm schedules the product results in the bidirectional connection aggregation calculation array, and obtains the sliding data table according to the result determined by the preprocessing algorithm, specifically including:

[0020] When a node has only one connection edge data, writing the corresponding feature data in the feature matrix buffer into the computing unit of the node;

[0021] When a node has multiple connection edge data, the feature data corresponding to the connection edge that appears for the first time is written into the calculation unit of the node, and the adjacent nodes of the node are traversed to see whether there are connection edge data. If the adjacent nodes have no connection edge data, the feature data corresponding to the connection edges that do not appear for the first time are written into the calculation unit of the adjacent nodes, and the results are written into the sliding data table; if the adjacent nodes have connection edge data, the redundant connection edge data are stored in the conflict data buffer. The above operations are all recorded by the sliding data table as the result of the algorithm traversal.

[0022] As a preferred solution, after the calculation is completed, the calculation unit sends an end signal to write the calculation result into the aggregation result buffer, specifically:

[0023] After the calculation is completed, the calculation unit sends an end signal to write the calculation result into the aggregation result buffer. If a node has excess connection edge data and data sliding is not possible, the excess connection edge data is stored in the conflict data buffer.

[0024] As a preferred solution, the bidirectionally connected aggregate computing array is composed of a plurality of rows of computing units, and each row of computing units is connected to adjacent uplink computing units and downlink computing units via a network.

[0025] As a preferred solution, the calculation unit includes 5 input signals and 3 output signals, the input signals are m1, m2, mr1, mr2 and the sliding information configuration, and the output signals are ps1, ps2, outAggrData; m1 and m2 are two values ​​sent to the calculation unit for multiplication; mr1 and mr2 are product data from the adjacent previous row and the adjacent next row, which are used for accumulation in the calculation unit; ps1 and ps2 are the product result outputs of the calculation unit, which are sent to the calculation units of the adjacent previous row and the adjacent next row for accumulation;

[0026] Among the 5 input signals and the 3 output signals, except for the sliding information configuration, the remaining input signals and the output signals include payload and valid, wherein the payload represents the value itself, and the valid is used to mark whether the value is valid.

[0027] As a preferred solution, the aggregation calculation process in the calculation unit includes:

[0028] First, determine whether to perform multiplication based on the validity of m1 and m2. If both signals are valid, the value is sent to the multiplier, and the input sliding information is configured as a control signal for the product result, which is used to control whether the product result is output to ps1, ps2 or sent to the adder;

[0029] If the output is to an external adder, the valid value of the corresponding ps1 or ps2 is set to a high level, otherwise it is set to a low level;

[0030] Next, determine whether the valid of the input signals mr1 and mr2 is valid. If only one signal is valid, the product result is added to the signal. If both are valid, the product result is added to the two input signals.

[0031] Each of the computing units has a built-in register reg for temporarily storing the results of multiplication and addition calculations. When the calculation result data of the next slice arrives, the data in reg is added to the data; when the end signal is pulled high, the data in reg is output, indicating that the aggregation calculation of the node has been completed.

[0032] As a preferred solution, the number of rows of the size of the bidirectional connection aggregation calculation array is the number of configured target nodes, and the number of columns is the dimension of the feature matrix.

[0033] To achieve the purpose of the invention, the present invention further provides a bidirectional aggregation computing acceleration system for GCN, which uses a bidirectional aggregation computing accelerator for GCN described in the above technical solution, and the system includes:

[0034] An algorithm module, including a preprocessing algorithm, is used to determine whether each connection edge data of each slice needs to be slid;

[0035] Data storage module, including DDR, node data buffer, sliding data table, connection edge data buffer, feature matrix buffer, conflict data buffer and aggregation result buffer, used for storing various types of data;

[0036] An aggregation calculation module, comprising a bidirectionally connected aggregation calculation array, wherein the bidirectionally connected aggregation calculation array comprises a plurality of rows of calculation units for performing bidirectional aggregation calculation;

[0037] The controller module includes a controller, which first controls the reading and writing of DDR to move off-chip data to the on-chip buffer, and then controls the data of the sliding data table, the node data buffer, and the feature matrix buffer to be transferred to the computing array according to the information of the connection edge data buffer. The controller also controls the storage of conflicting data in the conflicting data buffer;

[0038] The configuration module includes a CPU, which is used to configure the size of the bidirectionally connected aggregation computing array and the number of rows of data sliding, run the preprocessing algorithm, configure the controller module, and initiate reading and writing of the DDR.

[0039] Compared with the prior art, the present invention has the following beneficial effects:

[0040] The present invention uses a preprocessing algorithm on the software side to determine whether each connection edge data needs to be slid, and records the determination result in a sliding data table; on the hardware side, the node data buffer data is loaded into the computing unit, and the corresponding feature matrix buffer data is written into the corresponding computing unit according to the sliding data table, and the sliding data flow of the product result is controlled, which effectively solves the problem of unbalanced load of each computing unit caused by uneven distribution of connection edge data and irregular calculation. Simple sliding data information reduces the complexity of decoding, so that the hardware can quickly determine the scheduling of data, and significantly improves the utilization rate and computing efficiency of the computing units in the computing array. The size of the computing array and the number of sliding rows can be configured, which has better configurability and versatility. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 This is an overall framework diagram of a bidirectional aggregation computing accelerator for GCN in this application;

[0042] Figure 2 is a schematic diagram of a sliding data table of Example 1 of the present application;

[0043] Figure 3 A flowchart of the preprocessing algorithm of this application;

[0044] Figure 4 This is an interface signal diagram of a single computing unit of Example 1 of the present application;

[0045] Figure 5 The internal circuit design diagram of a single computing unit of Embodiment 1 of the present application;

[0046] Figure 6 This is a structural diagram of a bidirectionally connected aggregation computing array according to Embodiment 1 of the present application;

[0047] Figure 7 This is a schematic diagram of a calculation example of a bidirectional aggregate calculation array of Example 2 of the present application. DETAILED DESCRIPTION

[0048] In order to more clearly understand the above-mentioned purpose, features and advantages of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the embodiments of the present application and the features in the embodiments can be combined with each other without conflict.

[0049] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the protection scope of the present invention is not limited to the specific embodiments disclosed below.

[0050] Example 1

[0051] Embodiment 1 of the present application provides a bidirectional aggregation computing accelerator for GCN, including:

[0052] CPU, preprocessing algorithm, DDR, controller, bidirectional connection aggregation calculation array, connection edge data buffer, sliding data table, node data buffer, feature matrix buffer, conflict data buffer and aggregation result buffer;

[0053] The CPU configures the size of the bidirectional aggregation calculation array and the number of rows of data sliding and determines whether each connection edge data needs to slide data through the preprocessing algorithm. The preprocessing algorithm schedules the product results in the bidirectional connection aggregation calculation array and obtains the sliding data table according to the results of the preprocessing algorithm.

[0054] The CPU configures the controller and initiates reading and writing of the DDR. The controller reads the node information of the connection edge data buffer and controls the data flow of the corresponding data of the node data buffer and the feature matrix buffer in each computing unit in the bidirectional connection aggregation computing array according to the information in the sliding data table. The conflict data buffer is used to store the redundant connection edge data in the node that cannot slide data;

[0055] After the calculation is completed, the calculation unit sends an end signal and writes the calculation result to the aggregation result buffer.

[0056] The above technical solution in Example 1 of the present invention will be fully described below in conjunction with the accompanying drawings. For the convenience of explanation, the PE (process element) in the accompanying drawings represents a network-connected computing unit in a bidirectional aggregate computing array.

[0057] See also Figure 1The entire accelerator includes a CPU, a double data rate synchronous dynamic random access memory (DDR), a sliding data table obtained by a preprocessing algorithm, a node data buffer, a connection edge data buffer, a feature matrix buffer, a controller, a bidirectional connection aggregation calculation array, a conflict data buffer, and an aggregation result buffer. The CPU first configures the calculation array size and the number of sliding rows, and then uses an intelligent preprocessing algorithm to determine whether each connection edge data of each slice needs to be slid. The sliding data table records the results of the algorithm traversal, configures the controller through the AXI bus, and initiates reading and writing to the DDR. Since graph data is usually large, DDR is used to store a large amount of data, including a node data buffer, a connection edge data buffer, a feature matrix buffer, a conflict data buffer, an aggregation result buffer, and a sliding data table obtained by preprocessing. The controller reads the node information of the connection edge data buffer, controls the corresponding data of the node number buffer and the feature matrix buffer to be written into the multiplication and addition unit array, and writes it into the corresponding computing unit according to the configuration information in the sliding data table, thereby controlling the data flow of each computing unit in the computing array. After the calculation is completed, the calculation unit sends an end signal and writes the calculation result into the aggregation result buffer. If a node has excess connection edge data and data sliding is not possible, the excess connection edge data is stored in the conflict data buffer.

[0058] See also Figure 2 , Figure 2 The sliding information table is obtained by the CPU through intelligent preprocessing algorithm. The hardware side controls the sliding data flow according to the information in the table. Among them, config is the connection edge data, for example, [1, r1, 3] means that node 1 and node 3 are connected by relationship r1; isOrNo is the sliding information configuration, indicating whether the product data needs to slide, 0 means that the data does not slide and is sent to the adder, 1 means that the data slides down, and 2 means that the data slides up; m2.valid is the valid value flag, indicating whether the value of the second multiplied number is valid. For example, if node 4 has no node connected to it, the value multiplied by node 4 is invalid.

[0059] See also Figure 3 , Figure 3 The preprocessing process for the intelligent preprocessing algorithm.

[0060] Step 1: Initialization: Create a fixed number of box lists and an empty sequence to store numbers that cannot be put into the boxes and the state parameters of all boxes; Step 2: Data preprocessing and classification: Traverse the input sequence, count the number of times the number appears, and split the input sequence into the first-appearing and non-first-appearing number sequences; Step 3: Process the first-appearing number sequence: Traverse the first-appearing number sequence, if the box with the corresponding sequence number is empty, put the number in, and set the state parameters of the box; Step 4: Process the non-first-appearing number sequence, traverse the non-first-appearing number sequence, for each number, first check the previous box of the corresponding sequence number box (if the sequence number is greater than 1), if the previous box is If the box is empty, put a number in it and update the box status, isorNO is 2, and m2Valid is 1; if the previous box is not empty, check the next box with the corresponding serial number (if the serial number is less than the total number of boxes); if the next box is empty, put a number in it and update the box status parameters, isorNO is 2, and m2Valid is 1; if the next box is not empty either, add the number to the empty sequence; Step 5: Process empty boxes and numbers that do not appear: traverse all boxes, and for empty boxes, set m2Valid to False; Step 6: Output results: Output the status of each box, the sequence of numbers that cannot be put into the box, and the status parameters of each box.

[0061] See also Figure 4 For a single computing unit PE, there are 5 input signals and 3 output signals. Except for the sliding information configuration, the remaining signals are composed of payload and valid, where payload represents the value itself and valid is used to mark whether the value is valid. m1 and m2 are two values ​​sent to PE for multiplication; mr1 and mr2 are the product data from the adjacent previous row and the adjacent next row, which are used for accumulation in the PE; ps1 and ps2 are the product results of the PE, which are sent to the PE of the adjacent previous row and the adjacent next row for accumulation.

[0062] See also Figure 5 , attached Figure 5The internal circuit design diagram of a single PE. The specific implementation process of the calculation in the calculation unit is as follows: First, determine whether to multiply based on the validity of m1 and m2. If both signals are valid, the value is sent to the multiplier. The input sliding information isOrNo is used as the control signal of the product result to control whether the product result is output to ps1, ps2 or sent to the adder. If it is output to the outside, the valid value of the corresponding ps is set to a high level, otherwise it is set to a low level. Next, determine whether the valid of the input signals mr1 and mr2 is valid. If only one signal is valid, the product result is added to it. If both are valid, the product result is added to the two input signals. Each PE has a built-in register (reg) for temporarily storing the results of multiplication and addition calculations. When the calculation result data of the next slice arrives, the data in reg is added to the data. When the end signal is pulled high, the data in reg is output, indicating that the aggregation calculation of the node has been completed.

[0063] See also Figure 6 The size of the bidirectional multiplication and addition calculation array depends on the CPU configuration, as shown in the attached Figure 6 , the number of rows is the number of configured target nodes, and the number of columns is the dimension of the feature matrix. When the end signal is pulled high, the reg data of each PE is output, and the values ​​of each row of PE are spliced ​​together and passed into the FIFO (First-In-First-Out, an important data structure used to store and transmit data in a data stream). In addition, the parameters of the bidirectional connection of each PE can also be configured, that is, the data slide of each PE can be configured to slide up or down N rows.

[0064] Example 2

[0065] See also Figure 7 This embodiment 2 further illustrates the calculation process of the bidirectional aggregation calculation array based on the accelerator of embodiment 1, including:

[0066] according to Figure 7 The adjacency matrix information in the middle left figure calculates the data flow of each PE in the array as follows Figure 7 As shown in the middle right figure, for the data set [2,r3,4], calculation is performed in the row PE of node 3, and the multiplication result is sent to the row PE of node 2 for accumulation; for the data set [6,r6,5], calculation is performed in the row PE of node 5, and the multiplication result is sent to the row PE of node 6 for accumulation; node 4 has no connected data, so there is no related calculation operation.

[0067] The other technical details and steps of this embodiment 2 are the same as those of embodiment 1 and will not be repeated here.

[0068] Example 3

[0069] This embodiment 3 also provides a bidirectional aggregation computing acceleration system for GCN, which applies a bidirectional aggregation computing accelerator for GCN provided in embodiment 1. The system includes the following modules:

[0070] An algorithm module, including a preprocessing algorithm, is used to determine whether each connection edge data of each slice needs to be slid;

[0071] Data storage module, including DDR, node data buffer, sliding data table, connection edge data buffer, feature matrix buffer, conflict data buffer and aggregation result buffer, used for storing various types of data;

[0072] An aggregation calculation module, comprising a bidirectionally connected aggregation calculation array, wherein the bidirectionally connected aggregation calculation array comprises a plurality of rows of calculation units for performing bidirectional aggregation calculation;

[0073] The controller module includes a controller, which first controls the reading and writing of DDR to move off-chip data to the on-chip buffer, and then controls the data of the sliding data table, the node data buffer, and the feature matrix buffer to be transferred to the computing array according to the information of the connection edge data buffer. The controller also controls the storage of conflicting data in the conflicting data buffer;

[0074] The configuration module includes a CPU, which is used to configure the size of the bidirectionally connected aggregation computing array and the number of rows of data sliding, run the preprocessing algorithm, configure the controller module, and initiate the reading and writing of the DDR.

[0075] The other technical details and implementation steps of this embodiment 3 are the same as those of embodiment 1 and will not be repeated here.

[0076] From the above embodiments, it can be seen that the present invention effectively solves the problem of unbalanced load of each computing unit caused by unbalanced distribution of connection edge data, and at the same time significantly improves the utilization rate of the computing units in the computing array. Simple sliding data information reduces the complexity of decoding, so that the hardware can quickly determine the scheduling of data and slide the calculation results to the corresponding computing unit, reducing the consumption of hardware resources; the size of the computing array and the number of sliding rows can be configured to meet the multiplication and addition operation requirements of one node corresponding to multiple connection edge data, and has better configurability and versatility.

[0077] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the embodiments here. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the claims of the present invention.

Claims

1. A bidirectional aggregation computing accelerator for GCN, characterized in that: include: CPU, preprocessing algorithm, DDR, controller, bidirectional connection aggregation calculation array, connection edge data buffer, sliding data table, node data buffer, feature matrix buffer, conflict data buffer and aggregation result buffer; The CPU configures the size of the bidirectional aggregation calculation array and the number of rows of data sliding and determines whether each connection edge data needs to slide data through the preprocessing algorithm. The preprocessing algorithm schedules the product results in the bidirectional connection aggregation calculation array and obtains the sliding data table according to the result determined by the preprocessing algorithm. The CPU configures the controller and initiates reading and writing of the DDR. The controller reads the node information of the connection edge data buffer and controls the data flow of the corresponding data of the node data buffer and the feature matrix buffer in each computing unit in the bidirectional connection aggregation computing array according to the information in the sliding data table. The conflict data buffer is used to store the redundant connection edge data in the node that cannot slide data; After the calculation is completed, the calculation unit sends an end signal, and the calculation result is written into the aggregation result buffer.

2. A bidirectional aggregation computing accelerator for GCN according to claim 1, characterized in that: The preprocessing algorithm comprises the following steps: Initialize and create a list of fixed number of boxes, an empty sequence for storing numbers that cannot be put into the box, and the state parameters of all boxes; Input a digital sequence and traverse it, count the number of times the number appears, and split the input digital sequence into the first-appearing and non-first-appearing digital sequences; Traverse the first occurrence of the number sequence. If the box with the corresponding number is empty, put the corresponding number in it and set the state parameter of the box. Traverse the non-first-appearing number sequence. For each number, first check the previous box of the corresponding number box with a sequence number greater than 1. If the previous box is empty, put the number in and update the state parameter of the corresponding box. If the previous box is not empty, check the next box of the corresponding number box with a sequence number less than the total number of boxes. If the next box is empty, put the number in and update the state parameter of the corresponding box. If the next box is not empty either, add the number to the empty sequence. Traverse all boxes and update the status parameters of empty boxes; The output results include the state parameters of each box and the sequence of numbers that cannot be put into the box.

3. A bidirectional aggregation computing accelerator for GCN according to claim 2, characterized in that: The sliding data table includes connection edge data, sliding information configuration and a valid value flag, the sliding information configuration indicates that the product result does not need to slide or slide up or down, and the valid value flag indicates whether the value of the second multiplication number in the product result is valid.

4. The bidirectional aggregation computing accelerator for GCN according to claim 1, characterized in that: The preprocessing algorithm schedules the product results in the bidirectional connection aggregation calculation array, and obtains the sliding data table according to the result determined by the preprocessing algorithm, specifically including: When a node has only one connection edge data, writing the corresponding feature data in the feature matrix buffer into the computing unit of the node; When a node has multiple connection edge data, the feature data corresponding to the connection edge that appears for the first time is written into the calculation unit of the node, and the adjacent nodes of the node are traversed to see whether there are connection edge data. If the adjacent nodes have no connection edge data, the feature data corresponding to the connection edges that do not appear for the first time are written into the calculation unit of the adjacent nodes, and the results are written into the sliding data table; if the adjacent nodes have connection edge data, the redundant connection edge data are stored in the conflict data buffer. The above operations are all recorded by the sliding data table as the result of the algorithm traversal.

5. The bidirectional aggregation computing accelerator for GCN according to claim 1, characterized in that: After the calculation is completed, the calculation unit sends an end signal, and the calculation result is written into the aggregation result buffer, specifically: After the calculation is completed, the calculation unit sends an end signal and the calculation result is written into the aggregation result buffer. If a node has excess connection edge data and its product result cannot slide data to other calculation units, the excess connection edge data is stored in the conflict data buffer.

6. The bidirectional aggregation computing accelerator for GCN according to claim 1, characterized in that: The bidirectionally connected aggregate computing array is composed of a plurality of rows of computing units, and each row of computing units is connected to adjacent upstream computing units and downstream computing units via a network.

7. The bidirectional aggregation computing accelerator for GCN according to claim 6, characterized in that: The calculation unit includes 5 input signals and 3 output signals, the input signals are m1, m2, mr1, mr2 and the sliding information configuration, and the output signals are ps1, ps2, outAggrData; m1 and m2 are two values ​​sent to the calculation unit for multiplication; mr1 and mr2 are product data from the adjacent previous row and the adjacent next row, which are used for accumulation in the calculation unit; ps1 and ps2 are the product result outputs of the calculation unit, which are sent to the calculation units of the adjacent previous row and the adjacent next row for accumulation; Among the 5 input signals and the 3 output signals, except for the sliding information configuration, the remaining input signals and the output signals include payload and valid, wherein the payload represents the value itself, and the valid is used to mark whether the value is valid.

8. The bidirectional aggregation computing accelerator for GCN according to claim 7, characterized in that: The aggregation calculation process in the calculation unit includes: First, determine whether to perform multiplication based on the validity of m1 and m2. If both signals are valid, the value is sent to the multiplier, and the input sliding information is configured as a control signal for the product result, which is used to control whether the product result is output to ps1, ps2 or sent to the adder; If the output is to an external adder, the valid value of the corresponding ps1 or ps2 is set to a high level, otherwise it is set to a low level; Next, determine whether the valid of the input signals mr1 and mr2 are valid. If only one signal is valid, the product result is added to the signal. If both are valid, the product result is added to the two input signals. Each of the computing units has a built-in register reg for temporarily storing the results of multiplication and addition calculations. When the calculation result data of the next slice arrives, the data in reg is added to the data; when the end signal is pulled high, the data in reg is output, indicating that the aggregation calculation of the node has been completed.

9. The bidirectional aggregation computing accelerator for GCN according to claim 1, characterized in that: The size of the bidirectional connection aggregation calculation array has a row number that is the number of configured target nodes, and a column number that is the dimension of the feature matrix.

10. A bidirectional aggregation computing acceleration system for GCN, using a bidirectional aggregation computing accelerator for GCN as described in any one of claims 1 to 9, characterized in that: The system comprises: An algorithm module, including a preprocessing algorithm, is used to determine whether each connection edge data of each slice needs to be slid; Data storage module, including DDR, node data buffer, sliding data table, connection edge data buffer, feature matrix buffer, conflict data buffer and aggregation result buffer, used for storing various types of data; An aggregation calculation module, comprising a bidirectionally connected aggregation calculation array, wherein the bidirectionally connected aggregation calculation array comprises a plurality of rows of calculation units for performing bidirectional aggregation calculation; The controller module includes a controller, which first controls the reading and writing of DDR to move off-chip data to the on-chip buffer, and then controls the data of the sliding data table, the node data buffer, and the feature matrix buffer to be transferred to the computing array according to the information of the connection edge data buffer. The controller also controls the storage of conflicting data in the conflicting data buffer; The configuration module includes a CPU, which is used to configure the size of the bidirectionally connected aggregation computing array and the number of rows of data sliding, run the preprocessing algorithm, configure the controller module, and initiate reading and writing of the DDR.

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