Wafer bonding chuck with discrete actuators

Abstract

The invention relates to a wafer bonding chuck with discrete actuators. A semiconductor wafer bonding tool is provided. The semiconductor wafer bonding tool may be used to perform wafer-to-wafer bonding between a first semiconductor wafer and a second semiconductor wafer. The semiconductor wafer bonding tool includes a wafer bonding chuck configured to support a first semiconductor wafer at a first side. A plurality of discrete actuators are disposed at the first side of the wafer bonding chuck. Respective actuators of the plurality of discrete actuators are displaceable independently of each other. The respective actuators may be displaced based on one or more characteristics of the first semiconductor wafer or the second semiconductor wafer. As such, an improved wafer-to-wafer bonding process may be implemented.

Description

Technical Field

[0001] The present disclosure relates generally to wafer bonding tools, and more particularly, to a wafer bonding chuck having discrete actuators. Background Art

[0002] Wafer bonding is a wafer-level packaging technology that can be used to form semiconductor device assemblies. Wafer bonding is typically performed using a bonding chuck that is capable of contacting two semiconductor wafers in a controlled manner. During wafer bonding, the two semiconductor wafers may be brought into contact with each other at their respective bonding surfaces. The bonding surfaces may include conductive pads coupled to circuitry at each of the respective wafers and dielectric material surrounding the conductive pads. Once in contact, the conductive pads on each of the two semiconductor wafers may be bonded to form an interconnect between the wafers. Similarly, the dielectric material at each respective wafer may be bonded to mechanically couple the two semiconductor wafers. Summary of the invention

[0003] In one aspect, the present disclosure relates to a semiconductor wafer bonding tool comprising: a chuck configured to support a first semiconductor wafer at a first side, the chuck comprising: the first side; and a plurality of discrete actuators at the first side, the plurality of discrete actuators being displaceable independently of one another.

[0004] In another aspect, the present disclosure relates to a method for performing wafer-to-wafer bonding, comprising: providing a first semiconductor wafer, a second semiconductor wafer, and a wafer bonding tool comprising a chuck having a plurality of discrete actuators at a first side; attaching the first semiconductor wafer to the chuck at the first side; aligning the second semiconductor wafer with the first semiconductor wafer; bringing the first semiconductor wafer into contact with the second semiconductor wafer; determining an estimate of one or more characteristics of the first semiconductor wafer or the second semiconductor wafer during wafer-to-wafer bonding of the first semiconductor wafer with the second semiconductor wafer; and in response to bringing the first semiconductor wafer into contact with the second semiconductor wafer, shifting a corresponding actuator of the plurality of discrete actuators based on the estimate of the one or more characteristics of the first semiconductor wafer or the second semiconductor wafer.

[0005] In another aspect, the present disclosure relates to a semiconductor wafer bonding tool, comprising: a chuck configured to support a first semiconductor wafer at a first side, the chuck comprising: the first side; and a plurality of discrete actuators at the first side; and a controller configured to: receive an estimate of one or more characteristics of the first semiconductor wafer or the second semiconductor wafer during wafer-to-wafer bonding of the first semiconductor wafer and a second semiconductor wafer; and independently shift the plurality of discrete actuators during the wafer-to-wafer bonding based on the estimate of the one or more characteristics of the first semiconductor wafer or the second semiconductor wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 A simplified perspective view illustrating a wafer bonding chuck.

[0007] Figure 2 A simplified schematic cross-sectional view illustrating a wafer bonding tool during a wafer-to-wafer bonding process in accordance with an embodiment of the present technology.

[0008] Figure 3 A simplified schematic cross-sectional view illustrating a wafer bonding tool during a wafer-to-wafer bonding process in accordance with an embodiment of the present technology.

[0009] Figure 4 A schematic diagram illustrating a wafer bonding tool in accordance with an embodiment of the present technology.

[0010] Figure 5 A method for performing a wafer-to-wafer bonding process according to an embodiment of the present technology is described. DETAILED DESCRIPTION

[0011] Semiconductor devices are integrated into many devices to implement memory cells, processor circuits, imager devices, and other functional features. As more applications for semiconductor devices are discovered, designers are tasked with creating improved devices that can perform a greater number of operations per second, store greater amounts of data, or operate with a higher level of security. To accomplish this task, designers continue to develop new techniques to increase the number of circuit elements on a semiconductor device without simultaneously increasing the size of the device.

[0012] One such technique is to implement a stacked semiconductor device in which multiple semiconductor dies are assembled in a vertical stack. Interconnects may be created between the semiconductor dies to enable signals to be passed between the dies. In some cases, a stacked semiconductor device may be created by wafer-to-wafer bonding. For example, a semiconductor wafer may include multiple semiconductor dies. Multiple semiconductor wafers may be bonded to create a vertical stack of wafers such that corresponding dies on the wafers are bonded to form multiple die stacks. Various die stacks may be singulated from a wafer stack to create a semiconductor die stack.

[0013] Some wafer-wafer bonding processes bring challenges. For example, wafer-wafer bonding can be performed by placing two semiconductor wafers in close proximity and contacting the wafers at the center of the wafers (for example, in a high temperature environment). Once the wafers are in contact, the wafers can be bonded to each other. The wafers can be bonded to each other according to a bonding wave, which causes the wafers to shift. When the bonding wave propagates from the center of the wafer to the edge, the bonding surfaces of the wafers may become misaligned. This misalignment may cause a portion of the bonding surface of the first wafer to bond to a non-similar portion of the bonding surface of the second wafer, which may create a gap along the bonding interface between the first wafer and the second wafer. When a portion of the bonding surface of the wafer is not bonded, a gap may appear. These gaps may reduce the strength of the bond between the wafers or increase the stress in the wafer, which may reduce the mechanical strength of the semiconductor device. In addition, the misalignment of the wafers may cause the interconnects between the wafers to become misaligned, which may cause the semiconductor device manufactured by the wafer to become inoperable or unreliable in performance.

[0014] To address these and other issues, the present technology relates to a wafer bonding tool that includes a wafer bonding chuck having a plurality of discrete actuators. The semiconductor wafer bonding tool can be used to perform wafer-wafer bonding between a first semiconductor wafer and a second semiconductor wafer. The plurality of discrete actuators are disposed at a first side of the wafer bonding chuck. Respective actuators in the plurality of discrete actuators can be displaced independently of each other. The first semiconductor wafer can be attached to the wafer bonding chuck at the first side (e.g., by suction) so that when the actuator is displaced, the first semiconductor wafer is displaced together with the corresponding actuator.

[0015] The respective actuators may be displaced based on one or more characteristics of the first semiconductor wafer or the second semiconductor wafer. For example, the respective actuators may be displaced based on the propagation of the bonding wave across the first semiconductor wafer or the second semiconductor wafer. One or more characteristics of the first semiconductor wafer may be determined by measurement or simulation. For example, the behavior of the first and second wafers during the wafer-wafer bonding process may be predicted based on the properties of the wafer (e.g., size, thickness, material, shape, impurities) and the properties of the bonding process (e.g., bonding temperature, applied force, separation between wafers). In this way, the displacement of the wafer during the bonding process (e.g., due to the bonding wave) may be determined. In other cases, one or more characteristics of the wafer may be determined based on actual measurements of the bonding process. For example, an optical sensor (e.g., a lidar sensor, a radar sensor, an image sensor) may be used to determine the displacement of the wafer during the bonding process. In some embodiments, a stress sensor may be used to determine the displacement of the wafer. In some aspects, the measurement may be performed in real time. That is, the measurement may be determined during the bonding process, and the actuator may be displaced based on the measurement during the same bonding process. In other cases, the actuator may be displaced based on measurements taken during a previous bonding process.

[0016] In general, the respective actuators may be displaced to maintain alignment between the first semiconductor wafer and the second semiconductor wafer. For example, the displacement of the actuators may cause corresponding portions of the bonding surfaces on the first wafer and the second wafer to be parallel to each other to ensure uniform bonding between the wafers. In some cases, the displacement of the actuators may compensate for displacement of the first wafer during the bonding process (e.g., due to propagation of bonding waves). In yet other aspects, the actuators may be used to bring portions of the bonding surfaces of the wafers into contact with each other to provide greater control over the bonding process.

[0017] Compared to other techniques, the present technique enables localized control of the wafer-wafer bonding process. For example, discrete actuators can be displaced relative to each other to enable individual portions of the first semiconductor wafer to be adjusted with minimal impact on other portions of the first semiconductor wafer. Thus, wafer-wafer bonding can be controlled at a finer granularity, which can improve the quality of the bond between the two wafers.

[0018] Figure 1A wafer bonding chuck 102 including a plurality of discrete actuators 104 is illustrated. As illustrated, the wafer bonding chuck 102 may have a support surface (e.g., the illustrated surface) at which a semiconductor wafer may be attached. The wafer bonding chuck 102 may have any number of shapes. For example, as illustrated, the wafer bonding chuck 102 is circular; however, in other embodiments, the wafer bonding chuck 102 is rectangular, triangular, polygonal, or any other shape. The discrete actuators 104 may be disposed around the wafer bonding chuck 102. For example, the discrete actuators 104 may be arranged in a grid spanning at least a portion of the support surface of the wafer bonding chuck 102. The density of the discrete actuators 104 may vary across embodiments. For example, in some cases, the discrete actuators 104 are arranged such that the discrete actuators 104 cover more than 90%, 95%, or 99% of the support surface of the wafer bonding chuck 102. In other cases, the discrete actuators 104 cover a smaller portion (e.g., less than 25%, 50%, 75%, or 80%) of the support surface of the wafer bonding chuck. In this manner, the discrete actuators 104 may be arranged closely to one another or sparsely spread across the wafer bonding chuck 102. For example, the discrete actuators 104 may be placed at locations on the support surface corresponding to portions of the semiconductor wafer that experience large displacements during bonding.

[0019] The discrete actuators 104 may be arranged such that there are gaps 106 between the various actuators. The size of the gaps 106 may vary based on the density and arrangement of the discrete actuators 104. In aspects, the wafer bonding chuck 102 may include a vacuum (not shown) capable of providing suction through the gaps 106. In this way, portions of the semiconductor wafer may remain attached to the wafer bonding chuck 102 even when one or more of the discrete actuators 104 are displaced. In some embodiments, the gaps 106 may be placed within the discrete actuators 104 (e.g., at the center of the discrete actuators 104) to enable suction through the gaps 106. In other embodiments, the semiconductor wafer may be attached to the wafer bonding chuck 102 by an adhesive or a clamp.

[0020] The discrete actuator 104 may have a variety of shapes. As illustrated, the discrete actuator 104 is polygonal (e.g., triangular, rectangular, pentagonal, hexagonal, heptagonal, octagonal), which may enable the discrete actuator 104 to be densely arranged. In other cases, the discrete actuator 104 is elliptical or any other shape. The discrete actuator 104 may include a protrusion on the exposed surface. The protrusion may be configured to support the semiconductor wafer, for example, so that the semiconductor wafer only contacts the protrusion when attached to the wafer bonding chuck 102. As illustrated, the protrusion is positioned at the center of the discrete actuator 104; however, in other cases, the protrusion may be positioned at other locations (e.g., edges) of the discrete actuator 104. In yet other aspects, the discrete actuator 104 need not include a protrusion. Instead, the discrete actuator 104 may have a flat exposed surface at which the semiconductor wafer is attached.

[0021] Although illustrated as separate structures, the discrete actuators 104 may be disposed under a continuous surface. For example, although the discrete actuators 104 may be displaced independently of one another, each discrete actuator need not be disposed under a discrete structure. Instead, the discrete actuators 104 may be placed under a continuous surface such that the discrete actuators 104 are displaced to cause displacement at different portions of the continuous surface. In this way, the exposed surfaces of the discrete actuators need not have gaps 106.

[0022] Each of the discrete actuators 104 may be displaced independently. For example, different discrete actuators 104 may be displaced in different directions or by different amounts. Each of the discrete actuators 104 may include a motor or another actuator capable of converting potential energy (e.g., electrical energy) into mechanical energy. In some cases, the discrete actuators 104 may include a piezoelectric motor. Considering that the displacement of the wafer caused by the bonding process may be relatively small, the discrete actuators 104 may be displaced by a relatively small amount (e.g., less than 10 microns, less than 1 micron, less than 0.1 microns). In this way, the discrete actuators 104 may include a motor capable of causing a small displacement.

[0023] Figure 2 A simplified schematic cross-sectional view of a wafer bonding tool 200 during a wafer-wafer bonding process according to an embodiment of the present technology is illustrated. The wafer bonding tool 200 includes a wafer bonding chuck 102 that includes a plurality of discrete actuators 104. A first semiconductor wafer 202 can be attached to the wafer bonding chuck 102 such that the first semiconductor wafer 202 contacts the discrete actuators 104. The first semiconductor wafer 202 can be attached to the wafer bonding chuck 102 by suction, adhesive, clamping, or any other technique. In some embodiments, the first semiconductor wafer 202 is attached to the wafer bonding chuck by suction through the gap 106.

[0024] The second semiconductor wafer 204 is similarly disposed adjacent to and spaced from the semiconductor wafer 202. In some embodiments, a spacer (not shown) is disposed between the first semiconductor wafer 202 and the second semiconductor wafer 204 to maintain separation between the wafers. The second semiconductor wafer 204 can be attached to the wafer bonding tool 200 by any number of techniques. For example, the second semiconductor wafer 204 can be clamped to a lower portion of the bonding tool (e.g., at the wafer bonding chuck 102). In other cases, the wafer bonding tool may include an upper wafer bonding chuck (not shown) to which the second semiconductor wafer 204 is attached (e.g., by suction, bonding, clamping, or any other technique). In some embodiments, the upper wafer bonding chuck may include discrete actuators to support and adjust the configuration of the second semiconductor wafer 204. In this case, the discrete actuators at the upper bonding chuck may perform functions similar to the discrete actuators 104 at the wafer bonding chuck 102.

[0025] Back reference Figure 2 , illustrates a wafer bonding tool 200 at the beginning of a wafer-wafer bonding process before bonding has begun. Before bonding has begun, the discrete actuators 104 may be configured in a stationary position, wherein the discrete actuators 104 form a horizontal upper surface at which a first semiconductor wafer 202 may be disposed. Considering that the first semiconductor wafer 202 may be attached to the wafer bonding chuck 102, the first semiconductor wafer 202 may be flat (e.g., without deformation caused by wafer stress) at the beginning of the wafer bonding process. The second semiconductor wafer 204 may be similarly flattened against an upper wafer bonding chuck (not shown). In some embodiments, the discrete actuators 104 or discrete actuators on the upper wafer bonding chuck may be displaced to flatten the first semiconductor wafer 202 or the second semiconductor wafer 204 on the wafer bonding chuck 102 or the upper wafer bonding chuck, respectively. The second semiconductor wafer 204 is aligned with the first semiconductor wafer 202 (e.g., such that the edges of the wafers or corresponding semiconductor dies on the wafers are located at the same lateral position). In several aspects, the wafers may be aligned using optical sensors. When the wafers are aligned, the bonding surface 208 of the first semiconductor wafer 202 may face the bonding surface 210 of the second semiconductor wafer 204 .

[0026] Once aligned, bonding may be initiated by applying a force 206 to the first semiconductor wafer 202 or the second semiconductor wafer 204 to bring a portion of the first semiconductor wafer 202 and a portion of the second semiconductor wafer 204 into contact with each other (e.g., at the bonding surface 208 and the bonding surface 210). As illustrated, the force 206 may be applied at the center of the first semiconductor wafer 202 or the second semiconductor wafer 204 to start the bonding process at the center of the wafer. The force 206 may be applied by a probe or chuck that may press down on the first semiconductor wafer 202 or the second semiconductor wafer 204. In other cases, the force 206 may be applied by releasing a suction force that attaches a portion of the first semiconductor wafer 202 or a portion of the second semiconductor wafer 204 (e.g., enabling the wafer to return to a warped shape in which the semiconductor wafers are in contact). In yet other aspects, the force 206 may be applied using discrete actuators. For example, one or more of the discrete actuators 104 (e.g., at the center of the wafer) may be displaced to bring a portion of the first semiconductor wafer 202 into contact with a portion of the second semiconductor wafer 204. When the first semiconductor wafer 202 and the second semiconductor wafer 204 are in contact, the bonding surface 208 and the bonding surface 210 may be bonded to each other.

[0027] Applying force 206 to the first semiconductor wafer or the second semiconductor wafer may be caused by applying a force directly or indirectly to at least one wafer. For example, force 206 may be applied by a physical object contacting at least one wafer or by air pushing or pulling at least one wafer. In some embodiments, force 206 may be a magnetic force that attracts or repels the wafers. In yet another aspect, force 206 may be caused by stress in the wafer. For example, force 206 may be caused by releasing a portion of the wafer from a chuck to which it is attached (e.g., stopping suction at a portion of the wafer) while leaving another portion of the wafer attached to the chuck (e.g., maintaining suction at this portion). In this way, stress in the wafer may cause the wafers to deform and contact. In some embodiments, the bonding process is controlled by releasing suction from portions of the wafer at different times during the bonding process (e.g., starting at the center of the wafer and moving toward the edge of the wafer).

[0028] The bonding process may be performed in a heated environment, for example, in an oven. In some cases, the bonding process may be used to form an initial bond between the first semiconductor wafer 202 and the second semiconductor wafer 204, which is then cured at a higher temperature. In other cases, only a single bond is performed. In general, the force 206 applied to the first semiconductor wafer 202 or the second semiconductor wafer 204 may cause the bond to be formed between the wafers, such as Figure 3 As described in .

[0029] Figure 3A simplified schematic cross-sectional view illustrating a wafer bonding tool 200 during a wafer-to-wafer bonding process according to an embodiment of the present technology. Figure 2 In contrast, the first semiconductor wafer 202 and the second semiconductor wafer 204 are bonded at their centers (eg, due to Figure 2 206). The bonding wave generated by the bonding process can propagate through the first semiconductor wafer 202 or the second semiconductor wafer 204 to displace the wafers. As described, the bonding wave displaces the first semiconductor wafer 202 upward or downward at different locations.

[0030] The discrete actuator 104 of the wafer bonding tool 200 may be displaced to maintain alignment between the first semiconductor wafer 202 and the second semiconductor wafer 204 during the wafer bonding process. Considering that the second semiconductor wafer 204 is supported by the discrete actuator 104, the second semiconductor wafer 204 may be displaced in response to the displacement of the discrete actuator 104. For example, the discrete actuator 104 may be displaced to keep a portion of the bonding surface 210 of the second semiconductor wafer 204 parallel to a corresponding portion of the bonding surface 208 of the first semiconductor wafer 202 (e.g., tangents at the portions of the bonding surface are parallel). The discrete actuator 104 may be displaced based on one or more characteristics of the first semiconductor wafer 202 or the second semiconductor wafer 204. For example, the discrete actuator 104 may be displaced based on displacement or stress experienced by the first semiconductor wafer 202 or the second semiconductor wafer 204 (e.g., due to a bonding wave).

[0031] In some cases, the discrete actuators 104 may compensate for the propagation of the bonding wave through the first semiconductor wafer 202 or the second semiconductor wafer 204. For example, when the bonding wave displaces the first semiconductor wafer 202 upward, one or more of the discrete actuators 104 supporting the corresponding portion of the second semiconductor wafer 202 may be displaced to displace the second semiconductor wafer 204 upward (e.g., by the same amount as the portion of the first semiconductor wafer 202). Alternatively or in addition, when the bonding wave would otherwise displace a portion of the second semiconductor wafer 204 (e.g., upward), one or more of the discrete actuators 104 supporting the portion of the second semiconductor wafer 204 may be displaced in the opposite direction (e.g., downward) to keep the portion of the second semiconductor wafer 204 flat. In other cases, the discrete actuators 104 may be displaced according to other characteristics of the first semiconductor wafer 202 or the second semiconductor wafer 204 that are unrelated to the propagation of the bonding wave.

[0032] The one or more characteristics of the first semiconductor wafer 202 or the second semiconductor wafer 204 may be measured in any number of ways. For example, the displacement of the first semiconductor wafer 202 or the second semiconductor wafer 204 may be measured using an optical sensor or by converting stress measurements from a stress sensor. The one or more characteristics of the first semiconductor wafer 202 or the second semiconductor wafer 204 may be actual measurements taken during the same bonding process that it is used to displace the discrete actuator 104, a previous bonding process between different wafers (e.g., having similar properties), or measurements from a simulation of bonding between two wafers (e.g., having similar properties).

[0033] The discrete actuators 104 can be displaced independently of each other. For example, the first discrete actuator and the second discrete actuator can be displaced by different amounts simultaneously (e.g., without tilting or changing the plane of the discrete actuators 104 within the wafer chuck 102). For example, the first discrete actuator can be displaced by a first amount (e.g., corresponding to the displacement of the first semiconductor wafer 202 or the second semiconductor wafer 204 at a portion having the same lateral position as the first discrete actuator), and the second discrete actuator can be displaced by a second amount (e.g., corresponding to the displacement of the first semiconductor wafer 202 or the second semiconductor wafer 204 at a portion having the same lateral position as the second discrete actuator). Compared to other devices, the wafer bonding tool 200 is capable of local displacement by the discrete actuators 104, which can improve the alignment between the first semiconductor wafer 202 and the second semiconductor wafer 204 during bonding.

[0034] The discrete actuators 104 may be displaced individually. In some cases, the discrete actuators 104 may be displaced as the bonding wave propagates. The bonding wave may propagate from the center of the wafer to the edge. As the bonding wave propagates, additional portions of the first semiconductor wafer 202 and the second semiconductor wafer 204 may contact at the bonding surface 208 and the bonding surface 210. In doing so, a bond between the wafers may be formed. In some cases, only the discrete actuators 104 at the front of the bonding wave are actuated. For example, when bonding is first initiated, the discrete actuators 104 supporting the center of the second semiconductor wafer 204 may be actuated. As the bonding wave propagates outward toward the edge, the discrete actuators 104 at the edge of the wafer are displaced (e.g., the discrete actuators 104 corresponding to the portion of the wafer that has been bonded or the portion that has not yet been bonded are maintained in a neutral position). In this way, only some of the discrete actuators 104 need to be displaced at the same time. Alternatively or additionally, the discrete actuator 104 may be displaced away from the bonding wave to keep the first semiconductor wafer 202 and the second semiconductor wafer 204 aligned.

[0035] Although in the foregoing example embodiments, the wafer bonding tool has been illustrated and described in a particular configuration, in other embodiments, the wafer bonding tool may have a different configuration. For example, the wafer bonding tool described in any of the foregoing examples may be implemented using, for example, more or less discrete actuators, a top chuck including discrete actuators, a bottom chuck including discrete actuators, or both top and bottom chucks including discrete actuators, mutatis mutandis.

[0036] Figure 4 A wafer bonding tool 402 (eg, an example of which is Figure 2 4. The wafer bonding tool 402 includes a controller 404 including at least one processor 406, at least one computer readable medium 408, and a bonding simulation / measurement module 410. The wafer bonding tool 402 includes a discrete actuator 414 (e.g., an example of which is Figure 1 The discrete actuator 104 described in FIG. 4 is a wafer engagement chuck 412 (eg, an example of which is Figure 1 4. The controller 404 may control one or more operations during the wafer bonding process. For example, the controller 404 may shift one or more of the discrete actuators 414 during the wafer bonding process based on one or more characteristics of the wafer. The computer readable medium 408 may include computer readable instructions that, when executed by the processor 406, perform one or more aspects described herein.

[0037] One or more characteristics of the wafer may be determined using the bonding simulation / measurement module 410. The bonding simulation / measurement module 410 may include a computer-readable medium storing instructions that, when executed by at least one processor (e.g., processor 406), cause the controller 404 to receive one or more characteristics of the wafer. The bonding simulation / measurement module 410 may perform or analyze a simulation of a wafer bonding process to determine one or more characteristics of the wafer (e.g., displacement or stress). In some cases, the bonding simulation / measurement module 410 may measure a current or previous bonding process to determine one or more characteristics of the wafer. In some cases, the measurement or simulation is performed by a component external to the wafer bonding tool 402 and provided to the bonding simulation / measurement module 410 (e.g., the measurement or simulation is analyzed there).

[0038] The controller 404 may control operations performed using a wafer bonding chuck 412. The wafer bonding chuck 412 may be an upper chuck or a lower chuck. The wafer bonding tool 402 may include discrete actuators 414 on the upper chuck or the lower chuck. The discrete actuators 414 may be independently displaced to achieve local control of the wafer bonding process.

[0039] The wafer bonding tool 402 may further include a vacuum 416 that may be used to attach a semiconductor wafer to the wafer bonding chuck 412 by suction at the wafer bonding chuck 412. In several aspects, the controller 404 may control the operation of the vacuum 416. For example, the controller 404 may cause the vacuum 416 to provide suction at one or more portions of the wafer bonding chuck 412. In some cases, the controller 404 may cause the vacuum 416 to provide suction at certain portions of the wafer bonding chuck 412 to help facilitate the wafer bonding process. For example, the controller 404 may cause the vacuum 416 to release suction at the center of the wafer bonding chuck 412 without releasing suction at the edge of the wafer bonding chuck 412 to initiate the wafer bonding process.

[0040] Generally speaking, the wafer bonding tool 402 may be used to perform an improved wafer bonding process that provides various advantages over other processes, including achieving better alignment between bonded wafers. Figure 5 An example method 500 for performing a wafer-to-wafer bonding process according to an embodiment of the present technology is described. Although described with a specific configuration, one or more operations of the method 500 may be omitted, repeated, or reorganized. In addition, the method 500 may include Figure 5 Other operations not described in the method 500, for example, operations detailed in one or more other methods described herein. In some aspects, one or more operations of the method 500 can be performed by a wafer bonding tool (e.g., Figure 4 In some cases, the wafer bonding tool 402 can be used to perform the wafer bonding process. Figure 4 One or more operations of method 500 are performed under the control of controller 404).

[0041] At 502, a first semiconductor wafer, a second semiconductor wafer, and a wafer bonding tool are provided. The wafer bonding tool has a chuck with a plurality of discrete actuators at a first side. At 504, the first semiconductor wafer is attached to the chuck at the first side. The first semiconductor wafer may be attached to the chuck such that the discrete actuators support the first semiconductor wafer. The semiconductor wafer may be attached to the chuck by suction, by a clamp, by an adhesive, or by any other technique.

[0042] At 506, the second semiconductor wafer is aligned with the first semiconductor wafer while maintaining a distance between the wafers. For example, the first semiconductor wafer and the second semiconductor wafer may be separated by a spacer. The second semiconductor wafer may be attached (e.g., clamped) to a portion of a wafer bonding tool (e.g., at a wafer bonding chuck). In some embodiments, the second semiconductor wafer may be attached to an additional wafer bonding chuck. The first semiconductor wafer and the second semiconductor wafer may be optically aligned. Once aligned, the wafers may be bonded.

[0043] At 508, the first semiconductor wafer is brought into contact with the second semiconductor wafer. The wafers may be brought into contact by applying a force to the first semiconductor wafer or the second semiconductor wafer. The force may be applied by bringing one or more of the wafers into physical contact with an object. Alternatively or in addition, the force may be applied by applying or releasing suction from a portion of one or more of the wafers, by a magnet, or by any other technique. In aspects, the wafers are brought into contact at their centers, and the bonding process is initiated from the center.

[0044] At 510, estimates of one or more characteristics of the first semiconductor wafer or the second semiconductor wafer during a wafer-to-wafer bonding process are determined. In some cases, the estimates of the one or more characteristics may be determined based on simulations or previous records of wafers having characteristics similar to the first and second semiconductor wafers. In other cases, the estimates of the one or more characteristics may be determined during the wafer-to-wafer bonding process between the first semiconductor wafer and the second semiconductor wafer. In aspects, the one or more characteristics may relate to displacement, stress, or other characteristics of one or more of the wafers.

[0045] At 512, a respective actuator of a plurality of discrete actuators is displaced during a wafer-wafer bonding process between a first semiconductor wafer and a second semiconductor wafer. The respective actuator may be displaced based on an estimate of one or more characteristics of the first or second semiconductor wafer during the wafer-wafer bonding process. The respective actuator may be displaced to maintain alignment between the first semiconductor wafer and the second semiconductor during the wafer-wafer bonding process. In general, method 500 may be performed to assemble semiconductor devices having better alignment and higher yield, among other advantages.

[0046] A semiconductor device assembly constructed by practicing one or more aspects of the present disclosure may include a memory die, such as a dynamic random access memory (DRAM) die, a NAND memory die, a NOR memory die, a magnetic random access memory (MRAM) die, a phase change memory (PCM) die, a ferroelectric random access memory (FeRAM) die, a static random access memory (SRAM) die, or the like. In an embodiment in which multiple dies are disposed in a single assembly, the semiconductor device may include the same kind of memory die (e.g., both are NAND, both are DRAM, etc.) or different kinds of memory die (e.g., one is DRAM and one is NAND, etc.). According to another aspect of the present disclosure, the semiconductor die of the assembly described above may be a logic die (e.g., a controller die, a processor die, etc.), or a mixture of logic die and memory die (e.g., a memory controller die and a memory die controlled by it).

[0047] Any of the semiconductor devices and semiconductor device assemblies constructed according to one or more aspects of the present disclosure may be incorporated into any of a myriad of larger and / or more complex systems. The system may perform any of a wide variety of functions, such as memory storage, data processing, and / or other suitable functions. Thus, representative systems may include, but are not limited to, handheld devices (e.g., mobile phones, tablet computers, digital readers, and digital audio players), computers, vehicles, appliances, and other products.

[0048] Unless the context indicates otherwise, conventional semiconductor fabrication techniques may be used to form the structures disclosed herein. Materials may be deposited, for example, using chemical vapor deposition, physical vapor deposition, atomic layer deposition, plating, electroless plating, spin coating, and / or other suitable techniques. Similarly, materials may be removed, for example, using plasma etching, wet etching, chemical mechanical planarization (CMP), or other suitable techniques.

[0049] The technology disclosed herein relates to semiconductor devices, systems having semiconductor devices, and related methods for manufacturing semiconductor devices. The term "semiconductor device" generally refers to a solid-state device including one or more semiconductor materials. Examples of semiconductor devices include logic devices, memory devices, and diodes, among others. In addition, the term "semiconductor device" may refer to a finished device or to an assembly or other structure at various processing stages before becoming a finished device. Depending on the context in which the term "substrate" is used, the term "substrate" may refer to a structure (e.g., a die) that supports an electronic component, such as a printed circuit board (PCB) or a wafer-level substrate, a die-level substrate, or another die for die stacking or 3DI applications.

[0050] The devices discussed herein, including memory devices, may be formed on a semiconductor substrate or die, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In some cases, the substrate is a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate may be controlled by doping using various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping may be performed by ion implantation during the initial formation or growth of the substrate or by any other doping means.

[0051] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. Other examples and implementations are within the scope of the present disclosure and the appended claims. Features that implement the functions may also be physically located at various locations, including portions that are distributed so that the functions are implemented at different physical locations.

[0052] As used herein, "or" as used in a list of items (for example, a list of items preceded by a phrase such as "at least one of" or "one or more of") in the claims includes indicating an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on" should not be interpreted as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" can be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on".

[0053] As used herein, the terms "vertical," "lateral," "up," "down," "above," and "below" may refer to the relative direction or position of features in a semiconductor device in view of the orientation shown in the figure. For example, "upper" or "uppermost" may refer to a feature that is positioned closer to the top of the page than another feature. However, these terms should be broadly interpreted to include semiconductor devices with other orientations, such as inverted or tilted orientations, where top / bottom, over / under, above / under, up / down, and left / right may be interchanged depending on the orientation.

[0054] It will be appreciated from the foregoing that specific embodiments of the present invention have been described herein for illustrative purposes, but various modifications may be made without departing from the scope of the present invention. Rather, in the foregoing description, numerous specific details are discussed to provide a thorough and illustrative description of embodiments of the present technology. However, those skilled in the relevant art will recognize that the present disclosure may be practiced without one or more of the specific details. In other examples, well-known structures or operations typically associated with memory systems and devices are not shown or described in detail to avoid obscuring other aspects of the present technology. In general, it should be understood that various other devices, systems, and methods other than those specific embodiments disclosed herein may also be within the scope of the present technology.

Claims

1. A semiconductor wafer bonding tool, comprising: A chuck configured to support a first semiconductor wafer at a first side, the chuck comprising: the first side; and A plurality of discrete actuators at the first side, the plurality of discrete actuators being displaceable independently of one another. 2 . The semiconductor wafer bonding tool of claim 1 , further comprising a vacuum configured to provide suction at the first side. 3 . The semiconductor wafer bonding tool of claim 2 , wherein the plurality of discrete actuators are separated by gaps through which the suction force is provided. 4 . The semiconductor wafer bonding tool of claim 1 , wherein the plurality of discrete actuators are displaceable along an axis normal to a plane defined by the first side. 5 . The semiconductor wafer bonding tool of claim 1 , wherein the plurality of discrete actuators are arranged in an array across the first side.

6. The semiconductor wafer bonding tool of claim 1, wherein one or more of the plurality of discrete actuators are polygonal.

7. The semiconductor wafer bonding tool of claim 6, wherein the one or more of the plurality of discrete actuators are hexagonal.

8. The semiconductor wafer bonding tool of claim 1, wherein each respective actuator of the plurality of discrete actuators comprises a respective piezoelectric motor configured to displace the respective actuator.

9. The semiconductor wafer bonding tool of claim 1, wherein the plurality of discrete actuators are configured to shift to maintain at least a portion of a first bonding surface of the first semiconductor wafer parallel to a corresponding portion of a second bonding surface of a second semiconductor wafer, the first semiconductor wafer being bonded to the second semiconductor wafer. 10 . The semiconductor wafer bonding tool of claim 9 , wherein respective ones of the plurality of discrete actuators are configured to be displaced to different positions at different times during a bonding process between the first semiconductor wafer and the second semiconductor wafer.

11. A method for performing wafer-to-wafer bonding, comprising: providing a first semiconductor wafer, a second semiconductor wafer, and a wafer bonding tool including a chuck having a plurality of discrete actuators at a first side; attaching the first semiconductor wafer to the chuck at the first side; aligning the second semiconductor wafer with the first semiconductor wafer; bringing the first semiconductor wafer into contact with the second semiconductor wafer; determining an estimate of one or more characteristics of the first semiconductor wafer or the second semiconductor wafer during wafer-to-wafer bonding of the first semiconductor wafer and the second semiconductor wafer; and In response to contacting the first semiconductor wafer with the second semiconductor wafer, a corresponding actuator of the plurality of discrete actuators is displaced based on the estimate of the one or more characteristics of the first semiconductor wafer or the second semiconductor wafer. 12 . The method of claim 11 , wherein determining the estimate of the one or more characteristics of the first semiconductor wafer or the second semiconductor wafer is based on simulated wafer-to-wafer bonding.

13. The method of claim 11, wherein determining the estimate of the one or more characteristics of the first semiconductor wafer or the second semiconductor wafer comprises measuring the one or more characteristics of the first semiconductor wafer or the second semiconductor wafer during the wafer-to-wafer bonding.

14. The method of claim 11, wherein attaching the first semiconductor wafer to the chuck comprises providing suction at the first side.

15. The method according to claim 11, further comprising: displacing a first actuator of the plurality of discrete actuators to a first position at a first time during the wafer-to-wafer bonding; and The first actuator is displaced to a second position different from the first position at a second time during the wafer-to-wafer bonding.

16. The method of claim 11, wherein displacing the respective actuator comprises displacing the respective actuator along an axis normal to a plane defined by the first side.

17. A semiconductor wafer bonding tool comprising: A chuck configured to support a first semiconductor wafer at a first side, the chuck comprising: the first side; and a plurality of discrete actuators at the first side; and A controller configured to: receiving an estimate of one or more characteristics of the first semiconductor wafer or the second semiconductor wafer during wafer-to-wafer bonding of the first semiconductor wafer and the second semiconductor wafer; and The plurality of discrete actuators are independently displaced during the wafer-to-wafer bonding based on the estimation of the one or more characteristics of the first semiconductor wafer or the second semiconductor wafer.

18. The semiconductor wafer bonding tool of claim 17, wherein: A respective actuator of the plurality of discrete actuators comprises a respective piezoelectric motor; and The controller is configured to actuate the piezoelectric motor based on the estimate of the one or more characteristics of the first semiconductor wafer or the second semiconductor wafer.

19. The semiconductor wafer bonding tool of claim 17, wherein the controller is configured to independently displace the plurality of discrete actuators along an axis normal to a plane defined by the first side.

20. The semiconductor wafer bonding tool of claim 17, wherein the plurality of discrete actuators are arranged in an array across the first side.

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