Double-track pre-charging power-attack-resistant CMOS gate circuit unit based on random delay

Abstract

The invention discloses a double-track pre-charging power-attack-resistant CMOS gate circuit unit based on random delay, which comprises a single-track-to-double-track circuit with random delay and a double-track masking gate circuit, and is characterized in that the single-track-to-double-track circuit generates a signal with random delay as an input value of the double-track masking gate circuit; the double-track masking gate circuit comprises a first single-track masking gate circuit and a second single-track masking gate circuit. According to the invention, random delay in operation time is provided for the input signal of a subsequent circuit through the output signal of the single-track-to-double-track circuit with random delay, so that the power consumption of the power supply end of the gate circuit unit can be well kept constant under different input signals; and due to the function design of random delay, the time when the circuit processes key data is not a fixed moment, and power consumption attacks can be resisted to a certain extent.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a dual-rail pre-charging CMOS gate circuit unit resistant to power consumption attacks based on random delay. Background Art

[0002] As a carrier for storing important data, cryptographic chips are subject to a variety of attacks, among which power consumption attacks are more common. Attackers generally obtain key information by analyzing the power consumption fluctuation characteristics of the power supply end of the cryptographic chip when it is working. That is, there is a mathematical statistical correlation between power consumption and key information, which requires attackers to align power consumption information with data. Therefore, designing a circuit structure to reduce this correlation is an idea to resist power consumption attacks. On the one hand, using random delay technology to randomly delay the time for the circuit to process key data within a certain range, thereby disrupting the alignment relationship between power consumption information and data, is an effective method. On the other hand, circuits with constant power consumption are also an effective way to defend against this type of attack. The power consumption constant technology mainly utilizes the dual-rail pre-charge logic structure, which can make the power consumption of the logic circuit not change with the change of the calculation result, thereby making the power consumption relatively constant during operation. Therefore, combining random delay technology with dual-rail pre-charge technology can disrupt the time relationship between power consumption information and data, and eliminate the correlation between circuit calculation results and power consumption, increasing the difficulty for attackers to analyze circuit logic, thereby improving the circuit's ability to resist power consumption attacks. Summary of the invention

[0003] In order to make up for the deficiencies of the prior art, the present invention aims to provide a dual-rail pre-charging CMOS gate circuit unit resistant to power consumption attacks based on random delay.

[0004] The technical problem solved by the present invention can be achieved by the following technical solutions:

[0005] The dual-rail pre-charging CMOS gate circuit unit with power consumption attack resistance based on random delay comprises a single-rail to dual-rail circuit with random delay and a dual-rail masking gate circuit. The single-rail to dual-rail circuit generates a randomly delayed signal as an input value of the dual-rail masking gate circuit. The dual-rail masking gate circuit comprises a first single-rail masking gate circuit and a second single-rail masking gate circuit.

[0006] Furthermore, the single-rail to dual-rail circuit includes an inverter NOT1, an inverter NOT2, a NOR gate NOR1, a NOR gate NOR2, a multiplexer MUX1, a multiplexer MUX2 and an Arbiter PUF, input signal A is connected to input terminal x1 of NOR gate NOR1, and connected to input terminal x2 of inverter NOT1; output terminal of inverter NOT1 is connected to input terminal x2 of NOR gate NOR2; input signal en is connected to input terminal of inverter NOT2, and output terminal of inverter NOT2 is simultaneously connected to input terminal y1 of NOR gate NOR1 and input terminal y2 of NOR gate NOR2; output terminal of NOR gate NOR1 has two connection paths, which are respectively connected to input terminal 0 and input terminal 1 of multiplexer MUX1, where input terminal 1 is a delay path; output terminal of NOR gate NOR2 has two connection paths, which are respectively connected to input terminal 0 and input terminal 1 of multiplexer MUX2, where input terminal 1 is a delay path; A1 port of multiplexer MUX1 and A2 port of multiplexer MUX2 are both connected to output terminal F of Arbiter PUF, and output terminal F1 of multiplexer MUX1 is connected to output signal The output terminal F2 of the multiplexer MUX2 is connected to the output signal ɑ.

[0007] Furthermore, the first single-rail masked gate circuit includes 25 PMOS tubes and 13 NMOS tubes, the PMOS tubes are respectively recorded as P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P1', P2', P3', P4', P5', P6', P7', P8', P9', P10', P11', P12', P13', and the NMOS tubes are respectively recorded as N1, N2, N3, N4, N5, N6, N7, N1', N2', N3', N4', N5', N6'.

[0008] Furthermore, the drain of P1 is connected to the source of N1 and N2 and to the drain of P3 and N5, the gate of P1 is connected to the input signal ɑ, the source of P1 is connected to the drain of P2; the gate of P2 is connected to the input signal The source is connected to the source of P4 and connected to the power supply Vdd; the gate of P3 is connected to the input signal The source is connected to the drain of P4; the gate of P4 is connected to the input signal ɑ; the drain of P5 is connected to the source of N3 and N4 and to the drain of P7 and N6, the gate of P5 is connected to the input signal ɑ, the source of P5 is connected to the drain of P6; the gate of P6 is connected to the input signal The source is connected to the source of P8 and connected to the power supply Vdd; the gate of P7 is connected to the input signal The source is connected to the drain of P8; the gate of P8 is connected to the input signal ɑ; the drain of P9 is connected to the sources of N5 and N6 and to the drain of P11 and the input of the inverter, the gate of P9 is connected to the input signal b, the source of P9 is connected to the drain of P10; the gate of P10 is connected to the input signal The source is connected to the source of P12 and connected to the power supply Vdd, and the gate of P11 is connected to the input signal The source is connected to the drain of P12; the gate of P12 is connected to the input signal b; the gate of N1 is connected to the input signal connected, the drain is connected to the drain of N2, and the input signal is connected The gate of N2 is connected to the input signal ɑ; the gate of N3 is connected to the input signal connected, the drain is connected to the drain of N4, and the input signal is connected The gate of N4 is connected to the input signal ɑ; the gate of N5 is connected to the input signal b, and the gate of N6 is connected to the input signal The drain of N7 is connected to the output signal of the inverter, the gate is connected to the input signal R, the source is connected to the source of P13 ', and the output signal q is connected.

[0009] Furthermore, the input signal R is derived from the output terminal F of the Arbiter PUF, and the output result of the first single-track masking gate circuit is encrypted.

[0010] Furthermore, the drain of P1' is connected to the source of N1' and N2' and to the drain of P3' and N5', the gate of P1' is connected to the input signal ɑ, the source of P1' is connected to the drain of P2'; the gate of P2' is connected to the input signal The source is connected to the source of P4' and connected to the power supply Vdd; the gate of P3' is connected to the input signal The source is connected to the drain of P4'; the gate of P4' is connected to the input signal ɑ; the drain of P5' is connected to the source of N3' and N4' and to the drain of P7' and N6', the gate of P5' is connected to the input signal ɑ, the source of P5' is connected to the drain of P6'; the gate of P6' is connected to the input signal The source is connected to the source of P8' and connected to the power supply Vdd; the gate of P7' is connected to the input signal The source is connected to the drain of P8'; the gate of P8' is connected to the input signal ɑ. The drain of P9' is connected to the sources of N5' and N6' and is connected to the drain of P11' and the input of the inverter. The gate of P9' is connected to the input signal b; the source of P9' is connected to the drain of P10'; the gate of P10' is connected to the input signal The source is connected to the source of P12' and connected to the power supply Vdd; the gate of P11' is connected to the input signal The source is connected to the drain of P12'; the gate of P12' is connected to the input signal b; the gate of N1' is connected to the input signal The drain is connected to the drain of N2' and connected to the input signal b; the gate of N2' is connected to the input signal ɑ; the gate of N3' is connected to the input signal The drain is connected to the drain of N4' and is connected to the input signal ɑ; the gate of N4' is connected to the input signal ɑ; the gate of N5' is connected to the input signal b; the gate of N6' is connected to the input signal The drain of P13' is connected to the output signal of the inverter, and the gate is connected to the input signal R.

[0011] Furthermore, the difference between the second single-track masking gate circuit and the first single-track masking gate circuit is that the NMOS transistor N7 of the first single-track masking gate circuit is replaced by a PMOS transistor and the PMOS transistor P13' is replaced by an NMOS transistor, and then the same circuit connections are performed.

[0012] Compared with the prior art, the present invention has the following advantages: the present invention can better keep the power consumption of the power supply end of the gate circuit unit constant under different input signals, and the random delay function design makes the time when the circuit processes key data not a fixed moment, which can resist power consumption attacks to a certain extent. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 A single-track to dual-track circuit diagram with random delay according to the present invention;

[0014] Figure 2 A circuit diagram of a single-track masked gate circuit of the present invention;

[0015] Figure 3 It is a circuit diagram of the double-track masked gate circuit of the present invention. DETAILED DESCRIPTION

[0016] In order to enable those skilled in the art to more clearly understand the technical solution of the present application, a dual-rail pre-charging power consumption attack-resistant CMOS gate circuit unit based on random delay of the present invention is further described below in conjunction with the accompanying drawings.

[0017] The present invention seeks to protect a random-delay-based dual-rail pre-charged CMOS gate circuit unit that is resistant to power consumption attacks, comprising a randomly delayed single-rail to dual-rail circuit and a dual-rail masking gate circuit, wherein the output signal of the randomly delayed single-rail to dual-rail circuit provides a random delay in the operation time for the input signal of the dual-rail masking gate circuit.

[0018] like Figure 1As shown, the single-rail to dual-rail circuit with random delay includes inverter NOT1, inverter NOT2, NOR gate NOR1, NOR gate NOR2, multiplexer MUX1, multiplexer MUX2 and Arbiter PUF. The single-rail to dual-rail circuit generates a randomly delayed signal as an input value of a subsequent dual-rail masking gate circuit.

[0019] Specifically, the input signal A is connected to the input terminal x1 of the NOR gate NOR1, and is also connected to the input terminal of the inverter NOT1; the output terminal of the inverter NOT1 is connected to the input terminal x2 of the NOR gate NOR2; the input signal en is connected to the input terminal of the inverter NOT2, and the output terminal of the inverter NOT2 is simultaneously connected to the input terminal y1 of the NOR gate NOR1 and the input terminal y2 of the NOR gate NOR2; the output terminal of the NOR gate NOR1 has two connection paths, which are respectively connected to the input terminals 0 and 1 of the multiplexer MUX1, wherein the input terminal 1 is a delay path; the output terminal of the NOR gate NOR2 has two connection paths, which are respectively connected to the input terminals 0 and 1 of the multiplexer MUX2, wherein the input terminal 1 is a delay path; the A1 port of the multiplexer MUX1 and the A2 port of the multiplexer MUX2 are both connected to the output terminal F of the Arbiter PUF, and the output terminal F1 of the multiplexer MUX1 is connected to the output signal The output terminal F2 of the multiplexer MUX2 is connected to the output signal ɑ.

[0020] When en=0, it is the pre-charge stage, and the two output signals ɑ and The values ​​of are all 0; when en=1, it is the evaluation stage, and the two output signals ɑ and The values ​​of are complementary. Take the input signal A=0, en=0 and F=0 as an example to explain the principle: at this time, en outputs 1 after passing through the inverter NOT2, and the high-level signal will be transmitted to the NOR gate NOR1 and the NOR gate NOR2. According to the logic of the NOR gate, the outputs of the two NOR gates are both 0. At this time, since F=0, the output signals of the two NOR gates will enter through the 0 terminals of the multiplexers MUX1 and MUX2 without delay, and finally output ɑ=0 and

[0021] like Figure 2 As shown, the first single-rail masked gate circuit includes 25 PMOS tubes and 13 NMOS tubes. The PMOS tubes are respectively recorded as P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P1', P2', P3', P4', P5', P6', P7', P8', P9', P10', P11', P12', and P13', and the NMOS tubes are respectively recorded as N1, N2, N3, N4, N5, N6, N7, N1', N2', N3', N4', N5', and N6'.

[0022] Specifically, the drain of P1 is connected to the source of N1 and N2 and to the drain of P3 and N5, the gate of P1 is connected to the input signal ɑ, the source of P1 is connected to the drain of P2; the gate of P2 is connected to the input signal The source is connected to the source of P4 and connected to the power supply Vdd; the gate of P3 is connected to the input signal The source is connected to the drain of P4; the gate of P4 is connected to the input signal ɑ; the drain of P5 is connected to the source of N3 and N4 and to the drain of P7 and N6, the gate of P5 is connected to the input signal ɑ, the source of P5 is connected to the drain of P6; the gate of P6 is connected to the input signal The source is connected to the source of P8 and connected to the power supply Vdd; the gate of P7 is connected to the input signal The source is connected to the drain of P8; the gate of P8 is connected to the input signal ɑ; the drain of P9 is connected to the sources of N5 and N6 and to the drain of P11 and the input of the inverter, the gate of P9 is connected to the input signal b, the source of P9 is connected to the drain of P10; the gate of P10 is connected to the input signal The source is connected to the source of P12 and connected to the power supply Vdd, and the gate of P11 is connected to the input signal The source is connected to the drain of P12; the gate of P12 is connected to the input signal b; the gate of N1 is connected to the input signal connected, the drain is connected to the drain of N2, and the input signal is connected The gate of N2 is connected to the input signal ɑ; the gate of N3 is connected to the input signal connected, the drain is connected to the drain of N4, and the input signal is connected The gate of N4 is connected to the input signal ɑ; the gate of N5 is connected to the input signal b, and the gate of N6 is connected to the input signal The drain of N7 is connected to the output signal of the inverter, the gate is connected to the input signal R, the source is connected to the source of P13 ', and the output signal q is connected.

[0023] The drain of P1' is connected to the source of N1' and N2' and to the drain of P3' and N5'. The gate of P1' is connected to the input signal ɑ. The source of P1' is connected to the drain of P2'. The gate of P2' is connected to the input signal The source is connected to the source of P4' and connected to the power supply Vdd; the gate of P3' is connected to the input signal The source is connected to the drain of P4'; the gate of P4' is connected to the input signal ɑ; the drain of P5' is connected to the source of N3' and N4' and to the drain of P7' and N6', the gate of P5' is connected to the input signal ɑ, the source of P5' is connected to the drain of P6'; the gate of P6' is connected to the input signal The source is connected to the source of P8' and connected to the power supply Vdd; the gate of P7' is connected to the input signal The source is connected to the drain of P8'; the gate of P8' is connected to the input signal ɑ. The drain of P9' is connected to the sources of N5' and N6' and is connected to the drain of P11' and the input of the inverter. The gate of P9' is connected to the input signal b; the source of P9' is connected to the drain of P10'; the gate of P10' is connected to the input signal The source is connected to the source of P12' and connected to the power supply Vdd; the gate of P11' is connected to the input signal The source is connected to the drain of P12'; the gate of P12' is connected to the input signal b; the gate of N1' is connected to the input signal The drain is connected to the drain of N2' and connected to the input signal b; the gate of N2' is connected to the input signal ɑ; the gate of N3' is connected to the input signal The drain is connected to the drain of N4' and is connected to the input signal ɑ; the gate of N4' is connected to the input signal ɑ; the gate of N5' is connected to the input signal b; the gate of N6' is connected to the input signal The drain of P13' is connected to the output signal of the inverter, and the gate is connected to the input signal R. The input signal R comes from the output terminal F of the Arbiter PUF, and the output result of the first single-rail masking gate circuit is encrypted.

[0024] like Figure 3 As shown, the dual-track masking gate circuit of the present invention is composed of two single-track masking gate circuits (SRSGC) combined in an upper and lower manner, wherein the first single-track masking gate circuit is as described above, and the second single-track masking gate circuit only needs to replace the NMOS tube N7 in the first single-track masking gate circuit with a PMOS tube, and replace the PMOS tube P13' with an NMOS tube, and then perform the same line connection. (That is, the difference between the second single-track masking gate circuit and the first single-track masking gate circuit is that the NMOS tube N7 in the first single-track masking gate circuit is replaced with a PMOS tube, and the PMOS tube P13' is replaced with an NMOS tube.)

[0025] The PMOS tube conducts when the input signal is low, and the NMOS tube conducts when the input signal is high. b=0, Take R=0 as an example to illustrate the principle: When the above input signal is satisfied, it indicates that the entire circuit is in the pre-charging stage. The main operation circuit of the first single-rail masking gate is V dd After passing through P10' and P9' to the inverter, it outputs a low level, and then passes through P13' to reach the output terminal q. At this time, the main operation circuit of the second single-track masking gate is V ddAfter passing through P10 and P9 to the inverter, it outputs a low level, and then passes through the PMOS tube to reach the output end The output signal q and The values ​​of are all low level, meeting the pre-charge requirements.

[0026] The present invention combines random delay with dual-rail pre-charging, which can effectively reduce the threat brought by power consumption attacks, so that the power consumption of the circuit does not change with the change of the input signal, that is, the power consumption is kept constant, and it has a good ability to resist power consumption attacks; the functional design of random delay makes the time when the circuit processes key data not a fixed moment, which can resist power consumption attacks to a certain extent.

[0027] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A dual-rail pre-charging CMOS gate circuit unit with power consumption attack resistance based on random delay, characterized in that: The invention comprises a single-track to dual-track circuit with random delay and a dual-track masking gate circuit. The single-track to dual-track circuit generates a randomly delayed signal as an input value of the dual-track masking gate circuit. The dual-track masking gate circuit comprises a first single-track masking gate circuit and a second single-track masking gate circuit.

2. A dual-rail pre-charging CMOS gate circuit unit with power consumption attack resistance based on random delay according to claim 1, characterized in that: The single-rail to dual-rail circuit includes an inverter NOT1, an inverter NOT2, a NOR gate NOR1, a NOR gate NOR2, a multiplexer MUX1, a multiplexer MUX2 and an arbiter PUF, input signal A is connected to input terminal x1 of NOR gate NOR1, and connected to input terminal x2 of inverter NOT1; output terminal of inverter NOT1 is connected to input terminal x2 of NOR gate NOR2; input signal en is connected to input terminal of inverter NOT2, and output terminal of inverter NOT2 is simultaneously connected to input terminal y1 of NOR gate NOR1 and input terminal y2 of NOR gate NOR2; output terminal of NOR gate NOR1 has two connection paths, which are respectively connected to input terminal 0 and input terminal 1 of multiplexer MUX1, where input terminal 1 is a delay path; output terminal of NOR gate NOR2 has two connection paths, which are respectively connected to input terminal 0 and input terminal 1 of multiplexer MUX2, where input terminal 1 is a delay path; A1 port of multiplexer MUX1 and A2 port of multiplexer MUX2 are both connected to output terminal F of Arbiter PUF, and output terminal F1 of multiplexer MUX1 is connected to output signal The output terminal F2 of the multiplexer MUX2 is connected to the output signal ɑ.

3. A dual-rail pre-charged CMOS gate circuit unit based on random delay and anti-power consumption attack according to claim 2, characterized in that: The first single-rail masked gate circuit includes 25 PMOS tubes and 13 NMOS tubes. The PMOS tubes are respectively recorded as P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P1', P2', P3', P4', P5', P6', P7', P8', P9', P10', P11', P12', and P13', and the NMOS tubes are respectively recorded as N1, N2, N3, N4, N5, N6, N7, N1', N2', N3', N4', N5', and N6'.

4. A dual-rail pre-charging CMOS gate circuit unit based on random delay and anti-power consumption attack according to claim 3, characterized in that: The drain of P1 is connected to the source of N1 and N2 and to the drain of P3 and N5. The gate of P1 is connected to the input signal ɑ. The source of P1 is connected to the drain of P2. The gate of P2 is connected to the input signal The source is connected to the source of P4 and connected to the power supply Vdd; the gate of P3 is connected to the input signal The source is connected to the drain of P4; the gate of P4 is connected to the input signal ɑ; the drain of P5 is connected to the source of N3 and N4 and to the drain of P7 and N6, the gate of P5 is connected to the input signal ɑ, the source of P5 is connected to the drain of P6; the gate of P6 is connected to the input signal The source is connected to the source of P8 and connected to the power supply Vdd; the gate of P7 is connected to the input signal The source is connected to the drain of P8; the gate of P8 is connected to the input signal ɑ; the drain of P9 is connected to the sources of N5 and N6 and to the drain of P11 and the input of the inverter, the gate of P9 is connected to the input signal b, the source of P9 is connected to the drain of P10; the gate of P10 is connected to the input signal The source is connected to the source of P12 and connected to the power supply Vdd, and the gate of P11 is connected to the input signal The source is connected to the drain of P12; the gate of P12 is connected to the input signal b; the gate of N1 is connected to the input signal connected, the drain is connected to the drain of N2, and the input signal is connected The gate of N2 is connected to the input signal ɑ; the gate of N3 is connected to the input signal connected, the drain is connected to the drain of N4, and the input signal is connected The gate of N4 is connected to the input signal ɑ; the gate of N5 is connected to the input signal b, and the gate of N6 is connected to the input signal The drain of N7 is connected to the output signal of the inverter, the gate is connected to the input signal R, the source is connected to the source of P13 ', and the output signal q is connected.

5. A dual-rail pre-charging CMOS gate circuit unit based on random delay and anti-power consumption attack according to claim 4, characterized in that: The input signal R comes from the output terminal F of the Arbiter PUF, and encrypts the output result of the first single-track masking gate circuit.

6. A random delay-based dual-rail pre-charging power consumption attack-resistant CMOS gate circuit unit according to claim 5, characterized in that: The drain of P1' is connected to the source of N1' and N2' and to the drain of P3' and N5'. The gate of P1' is connected to the input signal ɑ. The source of P1' is connected to the drain of P2'. The gate of P2' is connected to the input signal The source is connected to the source of P4' and connected to the power supply Vdd; the gate of P3' is connected to the input signal The source is connected to the drain of P4'; the gate of P4' is connected to the input signal ɑ; the drain of P5' is connected to the source of N3' and N4' and to the drain of P7' and N6', the gate of P5' is connected to the input signal ɑ, the source of P5' is connected to the drain of P6'; the gate of P6' is connected to the input signal The source is connected to the source of P8' and connected to the power supply Vdd; the gate of P7' is connected to the input signal The source is connected to the drain of P8'; the gate of P8' is connected to the input signal ɑ. The drain of P9' is connected to the sources of N5' and N6' and is connected to the drain of P11' and the input of the inverter. The gate of P9' is connected to the input signal b; the source of P9' is connected to the drain of P10'; the gate of P10' is connected to the input signal The source is connected to the source of P12' and connected to the power supply Vdd; the gate of P11' is connected to the input signal The source is connected to the drain of P12'; the gate of P12' is connected to the input signal b; the gate of N1' is connected to the input signal The drain is connected to the drain of N2' and connected to the input signal b; the gate of N2' is connected to the input signal ɑ; the gate of N3' is connected to the input signal The drain is connected to the drain of N4' and is connected to the input signal ɑ; the gate of N4' is connected to the input signal ɑ; the gate of N5' is connected to the input signal b; the gate of N6' is connected to the input signal The drain of P13' is connected to the output signal of the inverter, and the gate is connected to the input signal R.

7. A dual-rail pre-charging CMOS gate circuit unit based on random delay and resistant to power consumption attack according to claim 6, characterized in that: The difference between the second single-track masking gate circuit and the first single-track masking gate circuit is that the NMOS transistor N7 of the first single-track masking gate circuit is replaced by a PMOS transistor and the PMOS transistor P13' is replaced by an NMOS transistor, and then the same circuit connections are performed.

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