Analog-to-digital converter and method for stabilizing reference voltage in analog-to-digital converter

Abstract

Apparatuses, methods, and systems related to analog-to-digital converters (ADCs) are disclosed herein, and in particular, to stabilize reference voltages in ADCs and to stabilize reference voltages in time-interleaved arrangements of ADCs. A method of stabilizing a reference voltage in an ADC may include generating an analog reference voltage on a reference voltage line, and connecting a pre-charge capacitor of the ADC to the reference voltage line while generating the analog reference voltage to reduce a voltage error during generation of the analog reference voltage.

Description

Technical Field

[0001] Aspects of the present disclosure relate generally to analog-to-digital converters (ADCs), and more particularly to stabilizing reference voltages in an ADC and stabilizing reference voltages in a time-interleaved arrangement of an ADC. Background Art

[0002] Analog-to-digital converters are often used as basic building blocks in high-speed broadband (mixed-signal) systems such as serializer / deserializer receivers, cellular base stations, 5G and 6G high-speed communication systems, imaging radar systems, and other high-speed IO technologies such as wireless I / O, mmWave I / O, etc.

[0003] The ADC may include at least one digital-to-analog converter (DAC) to convert the digital code to an analog signal representing a reference voltage. Typically, each time the ADC converts a bit from the digital code, the reference voltage (VREF) drops briefly. In high-speed systems, this voltage difference or error may distort the conversion of the next bit, i.e., the reference voltage may take too long to stabilize, thereby reducing the overall performance of the ADC.

[0004] In high speed systems using a time-interleaved ADC arrangement / array, including multiple time-interleaved ADCs, where a common reference voltage is shared between all ADC slices, crosstalk may further degrade the performance of both individual slices and the combined time-interleaved ADC arrangement. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] In the drawings, like reference characters generally refer to like parts throughout the different views. The drawings are not necessarily drawn to scale, instead emphasis is generally placed on illustrating the principles of the invention. It is understood that the drawings are diagrammatic and schematic representations of exemplary aspects of the invention and are neither limiting of the invention nor necessarily drawn to scale. In the following description, various embodiments of the invention will be described with reference to the following drawings, in which:

[0006] Figure 1 An exemplary ADC is shown;

[0007] Figure 2 An exemplary ADC including a capacitor bank according to some aspects is shown;

[0008] Figure 3 A schematic overview of the different signals and current pulses is shown;

[0009] Figure 4 An exemplary fast charging circuit including a charge pump according to some aspects is shown;

[0010] Figure 5 An exemplary ADC including a cycle-by-cycle error correction circuit according to some aspects is shown;

[0011] Figure 6 An exemplary ADC including a multi-cycle error correction circuit according to some aspects is shown;

[0012] Figure 7 shows a schematic overview of reference voltage degradation in a TI ADC;

[0013] Figure 8 shows an exemplary arrangement of a TI ADC according to some aspects;

[0014] Fig. 9 A flow chart illustrating a method of stabilizing a reference voltage in an ADC according to some aspects is shown;

[0015] Fig.10 A flow chart illustrating a method of stabilizing a reference voltage in multiple time-interleaved ADCs sharing a common reference voltage source is shown; and

[0016] Fig.11 An exemplary ADC according to some aspects is shown. DETAILED DESCRIPTION

[0017] The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the invention may be practiced.

[0018] The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

[0019] The terms "at least one" and "one or more" may be understood to include a number greater than or equal to one (e.g., one, two, three, four, [...], etc.). The term "plurality" may be understood to include a number greater than or equal to two (e.g., two, three, four, five, [...], etc.).

[0020] The words "plurality" and "multiple" in the description and claims clearly refer to quantities greater than one. Thus, any phrase that explicitly references the above words referring to a quantity of elements (e.g., "plurality [elements]," "multiple [elements]") clearly refers to more than one of the elements. The phrases "group," "set," "collection," "series," "sequence," "grouping," and the like in the description and claims, if any, refer to a quantity equal to or greater than one, i.e., one or more.

[0021] The phrase "at least one" with respect to a group of elements may be used herein to refer to at least one element from the group that includes the elements. For example, the phrase "at least one" with respect to a group of elements may be used herein to refer to selecting one of the listed elements, a plurality of one of the listed elements, a plurality of a single listed element, or a plurality of a plurality of a single listed element.

[0022] The term "data" as used herein may be understood to include information in any suitable analog or digital form, for example, information provided in the form of a file, a portion of a file, a group of files, a signal or data stream, a portion of a signal or data stream, a group of signals or data streams, etc. In addition, the term "data" may also be used to refer to a reference to information, such as in the form of a pointer. However, the term "data" is not limited to the above examples and may take various forms and represent any information understood in the art.

[0023] For example, the term "processor" or "controller" used in this article can be understood as any technical entity that allows data to be processed. Data can be processed according to one or more specific functions performed by the processor or controller. In addition, the processor or controller used in this article can be understood as any type of circuit, for example, any type of analog or digital circuit, and can also be referred to as "processing circuit", "processing circuit system", etc. Therefore, the processor or controller can be or include an analog circuit, a digital circuit, a mixed signal circuit, a logic circuit, a processor, a microprocessor, a central processing unit (CPU), a graphics processor (GPU), a digital signal processor (DSP), a field programmable gate array (FPGA), an integrated circuit, an application-specific integrated circuit (ASIC), etc., or any combination thereof. Any other type of specific implementation of the corresponding function, which will be further described in detail below, can also be understood as a processor, a controller or a logic circuit. It is understood that any two (or more) of the processors, controllers or logic circuits described in detail herein can be implemented as a single entity with equivalent functions, etc., and conversely, any single processor, controller or logic circuit described in detail herein can be implemented as two (or more) independent entities with equivalent functions.

[0024] As used herein, "memory" is understood to be a computer-readable medium that can store data or information for retrieval. Therefore, the "memory" mentioned herein can be understood to refer to volatile or non-volatile memory, including random access memory (RAM), read-only memory (ROM), flash memory, solid-state storage, magnetic tape, hard drive, optical drive, etc., or any combination thereof. Registers, shift registers, processor registers, data buffers, etc. are also included in the term memory. The term "software" refers to any type of executable instructions, including firmware.

[0025] The term "computing" includes both "direct" computations via mathematical expressions / formulas / relationships and "indirect" computations via lookup or hash tables and other array indexing or searching operations. The term "determining" includes both "direct" determinations via mathematical expressions / formulas / relationships and "indirect" determinations via lookup or hash tables and other array indexing or searching operations.

[0026] Hereinafter, examples and embodiments of an ADC and a method for stabilizing a reference voltage of the ADC will be described in detail.

[0027] In the following exemplary embodiments, the present invention is shown and described with particular reference to a successive approximation register ADC. However, it will be appreciated by those skilled in the art that various changes may be made in form and detail, and that the present invention may be applied to other types of ADCs, such as, for example, flash ADCs that perform digital approximation of input voltages in parallel, pipeline ADCs, delta-sigma ADCs, hybrid ADCs, and the like.

[0028] Figure 1 An exemplary successive approximation register (SAR) analog-to-digital converter (ADC) 100 is shown. A SAR ADC is a device that converts an analog voltage signal V IN ADC that converts to the corresponding digital representation.

[0029] The exemplary SAR ADC 100 includes a clock generator 110 , a sampling switch 120 , a digital-to-analog converter DAC 130 , a comparator 140 , and a SAR controller 150 .

[0030] The clock generator 110 is configured to receive an (external) input clock signal 112 , generate a sampling clock signal 114 , and send the sampling clock signal 114 to a sampling switch 120 .

[0031] The sampling switch 120 is configured to receive the sampling clock signal 114 from the clock generator 110 and also receive the (analog) input voltage signal 116 (V IN ). The sampling switch 120 can remain on until the input signal V IN The sampling switch 120 is configured to convert the input voltage 116 (V IN ) is sent to the comparator 140.

[0032] The DAC 130 is configured to receive an n-bit digital code / signal from the SAR controller 150. The initial digital code is typically selected by the controller to be the midpoint of the total possible bit range.

[0033] For example, if the DAC has a 12-bit resolution, the initial digital code may be set to 0111 1111 1111, which is the midpoint of the range 0000 0000 0000 to 1111 1111 1111.

[0034] The digital code is converted by DAC 130 into an analog reference signal / voltage 132 and transmitted to comparator 140 .

[0035] The comparator 140 is configured to receive the input voltage 116 (V IN ) and the generated reference voltage VREF on line 132 from the DAC 130 to compare the two to determine whether the generated reference voltage 132 is higher or lower than the input voltage 116. The comparator 140 is also configured to transmit the result of the comparison to the SAR controller 150.

[0036] The SAR controller 150 is configured to determine an initial digital code and send it to the DAC 130. The SAR controller 150 is also configured to determine a digital code representative of the input voltage 116 (V IN ) of a series of digital codes (after the initial code) that are successive digital approximations of the digital code. The determination is based on the result of the comparison received from the comparator 140.

[0037] The SAR controller 150 typically approximates the digital code bit by bit, starting with the most significant bit (MSB) (or MSB-1), and sets each bit to 1 or 0 depending on the result of the comparison.

[0038] For example, when the comparison result output by the comparator 140 indicates that the input voltage 116 (V IN ) is higher than the generated reference voltage VREF on line 132, the SAR controller 150 may set the MSB to 1, otherwise it is set to 0. The new digital code is then transferred to the DAC 130, and the resulting output reference voltage 132 is again compared to the analog input voltage 116. The SAR controller 150 repeats this process until it reaches the least significant bit (LSB) of the digital code.

[0039] The SAR controller 150 may also be configured to complete one iteration and output the final digital code as the input voltage 116 (V IN ) is an approximate numerical representation of .

[0040] In an ADC, and in particular in a SAR ADC, the conversion of the previous bit typically requires a large current to be drawn from the (common) reference rail 132, causing the reference voltage VREF on the reference rail to drop. To avoid distortion during the conversion of the following bit, it is critical for the ADC included in a high-speed system that VREF settles quickly.

[0041] For example, if VREF does not settle quickly enough, it may degrade the ADC's signal-to-noise ratio (SNR), signal-to-noise and distortion ratio (SINAD), and / or error vector magnitude (EVM) in a high-speed system.

[0042] In high-speed systems using a time-interleaved (TI) ADC arrangement / array (comprising multiple time-interleaved ADCs with all ADC slices sharing a common reference voltage), crosstalk may further degrade the performance of both the individual slices and the combined TI ADC arrangement.

[0043] In particular, in a time-interleaved arrangement of ADCs, a slice array with reference voltages supplied from both sides of adjacent slice groups may experience a gradient that further degrades the received reference voltage at the internal slices due to the accumulation of parasitic resistance and inductance voltage drops from all slices on the shared reference rail.

[0044] To minimize the reference voltage drop and / or ensure fast settling of the reference voltage, large current buffers and / or large capacitors may be added to the reference rail.

[0045] Typically, a combination of an active buffer amplifier is used along with a decoupling capacitor (at the output). For example, the decoupling capacitor can be increased to meet the specification of supplying the required instantaneous charge. An active buffer (e.g., operating in class AB) may further be used, where the active buffer has a quiescent current sufficient to meet the peak instantaneous current consumption, and a speed / bandwidth to deliver current during the stable period of the reference voltage.

[0046] To improve the stability of a shared VREF in a TI arrangement / array of ADCs, a combination of the above techniques can be used between TI slices. However, the above techniques have several disadvantages. Adding decoupling capacitors increases the required (silicon) area, thereby increasing the circuit cost.

[0047] In the TI arrangement, larger capacitors also require larger inter-chip spacing and / or spacing of the ADC array. Active buffers require high power to meet stability requirements, increasing power / current consumption.

[0048] Therefore, there is a need to improve the stabilization of reference voltages in ADCs and TI ADC arrays.

[0049] Figure 2 An exemplary ADC 200 is shown including a capacitor bank 260 according to some aspects. The ADC 200 may be a SAR ADC including the capacitor bank (array) 260. Alternatively, the ADC 200 may include a single capacitor instead of the capacitor bank 260.

[0050] ADC 200 includes a clock generator 210, a sampling switch 220, a digital-to-analog converter DAC 230, a comparator 240, a controller 250, a capacitor bank 260, and a charging voltage source 270. Charging voltage source 270 may alternatively be located outside ADC 200.

[0051] The clock generator 210 may be similar to the clock generator 110 and is configured to receive an (external) input clock signal 212 to generate a sampling clock signal 214 and send the sampling clock signal 214 to the sampling switch 220. The clock generator 210 is also configured to send a delayed reset signal (φ) to the sampling switch 220 and the capacitor bank 260. r ).

[0052] The sampling switch 220 may be similar to the sampling switch 120 and is configured to receive the sampling clock signal 214 from the clock generator 210 and also receive the (analog) input voltage signal 216 (V IN ). The sampling switch 220 can remain on until the input signal V IN and / or until a (first) reset signal 217 is received from the clock generator 210. For example, the sampling switch 220 may be implemented as a sample and hold circuit. The sampling switch 220 is also configured to convert the input voltage 216 (V IN ) is sent to comparator 240.

[0053] DAC 230 may be identical to DAC 130, and is configured to receive an n-bit digital code / signal 252 from controller 250. DAC 230 may be implemented, for example, as a capacitive DAC.

[0054] The received digital code is converted by DAC 230 to an analog reference signal / voltage VREF, which is output on line or rail 232 and transmitted to comparator 240 .

[0055] The comparator 240 may be the same as the comparator 140 and is configured to receive the input voltage 216 (V IN) and a reference voltage VREF generated on line 232 from DAC 230, and compare the two to determine whether the generated reference voltage on line 232 is higher or lower than input voltage 216. Comparator 240 is also configured to transmit the result of the comparison to controller 250.

[0056] The controller 250 may be similar and / or identical to the SAR controller 150 and is configured to determine an initial digital code and send it to the DAC 230. The controller 250 is also configured to determine a digital code representative of the input voltage 216 (V IN ) in a series of digital codes that are successive digital approximations of ). The determination is based on the result of the comparison received from comparator 240.

[0057] The controller 250 may also be configured to complete one iteration and output the final digital code as the input voltage 216 (V IN ) is an approximate numerical representation of .

[0058] The controller 250 may include circuitry configured to detect and track the bit currently being processed by the DAC 230. The controller 250 may also be configured to track the precise time at which each bit is processed. For example, the controller 250 may include latches and / or memory ( Figure 2 ), to keep track of the bits that have been processed (from MSB to LSB).

[0059] Capacitor bank 260 includes a plurality of pre-charged capacitors. For example, capacitor bank 260 may include n+1 pre-charged capacitors, where n is the resolution of the ADC. The capacitors of capacitor bank 260 are pre-charged to a voltage equal to the reference voltage to be generated, or alternatively to a voltage supply (V DD1 ). The capacitor bank 260 further includes a plurality of switches 262. The capacitor bank 260 may have a long stabilization period and loose requirements compared to other parts of the ADC 200. The capacitor bank 260 is also configured to be controlled and synchronized by the controller 250.

[0060] The controller 250 is configured to control the switch 262 to pre-charge one or more capacitors of the capacitor bank 260 from a charging voltage source 270 via a voltage line 272 , which is also connected to the reference voltage line 232 .

[0061] The charging voltage source 270 may be configured to provide a voltage that is equal (at least substantially equal) to the reference voltage to be generated. In particular, the charging voltage source 270 may be implemented by a programmable voltage source that is configured to provide a voltage that is equal to the analog reference voltage generated by the ADC 200. The charging voltage source 270 may alternatively be configured to provide a voltage that is higher than the analog reference voltage to be generated, which may speed up the stabilization of the analog reference voltage on the line 232. The charging voltage source 270 may be an external power source rather than a part of the ADC 200 ( Figure 2 In addition, a buffer may be provided between the charging voltage source 270 and the ADC 200 ( Figure 2 not shown).

[0062] The capacitors included in the capacitor bank 260 may have different capacitances and / or may be precharged to different charge levels. The capacitors may be precharged to a voltage higher than the charging voltage by using a voltage booster as a charging voltage source ( Figure 2 Furthermore, the capacitance value of the capacitor may be (pre) calibrated during production and / or in a laboratory.

[0063] Hereinafter, the capacitor bank 260 may also be referred to as a “fast charging circuit” 260 .

[0064] The controller 250 is configured to select one (or more) pre-charge capacitors from the capacitor bank 260 and connect the selected capacitors to the common reference voltage line 232 by means of the switch 262 .

[0065] The controller 250 is configured to send (delay) signals 254 (signals Φ0, Φ1, ...; Φ n ) to the capacitor bank 260 in order to connect the pre-charge capacitors to the reference voltage line 232 at a precise time. The controller 250 is configured to monitor and track each bit (and / or the position of the bit in the digital code) processed by the DAC 230 to synchronously (and accurately) connect one (or more) selected pre-charge capacitors in the capacitor bank 260 to the reference voltage line 232. For example, the controller 250 may connect the selected one (or more) pre-charge capacitors before the next bit is converted by the DAC 230, thereby precisely providing the desired charge level at the precise / accurate time required.

[0066] The capacitor bank 260 may also be configured to receive a signal from the clock generator 210 or alternatively from the controller 250 ( Figure 2 The delayed reset signal 218 (Φ r) to turn off and / or discharge the specified capacitor. Alternatively, the controller 250 may be configured to turn on or off the specified capacitor. r )218 allows a reset before the next sampling phase and / or before each individual bit.

[0067] Compared to ADC 100, ADC 200 allows synchronous and accurate current boosting of the reference voltage before converting subsequent bits, thereby minimizing VREF voltage drops and / or improving VREF stability. The selected pre-charge capacitor from fast charge circuit 260 provides a current pulse that matches the current consumed by the ADC for conversion.

[0068] ADCs such as exemplary ADC 200 allow power and area savings by reducing the active buffer requirements to just the DC average current replenishment at the active buffer output and smaller decoupling capacitors. This in turn can allow faster conversion rates at higher resolutions, where otherwise the ADC's reference settling speed and accuracy would limit the overall system.

[0069] Figure 3 The event (bit) decision drive timing and matching current pulses that switch the pre-charge capacitor to the reference voltage line 232 are shown.

[0070] Figure 3 A schematic overview 300 of different signals and current pulses of an exemplary ADC 200 over time is shown.

[0071] As in Figure 3 As can be seen in , ADC 200 receives a reset signal 302 (eg, generated by clock generator 210 ) indicating a reset of sampling switch 220 .

[0072] Then, the sampling switch 220 receives the sampling clock signal 304, indicating the start of the (next) sampling phase. At 306, the fast charging circuit 260 receives the delayed reset signal (Φ r )(corresponding to the delayed reset signal 218).

[0073] In 308, comparator 240 is enabled, and after a short delay, is ready for operation in 310. DAC 230 begins processing the digital code bit by bit, starting with the MSB in 312 (then MSB-1 in 316, etc.).

[0074] The controller 250 is configured to send (delay) signals 254 (Φ0, Φ1, ..., Φ n ) to the fast charging circuit 260, whereby Φ0 and Φ1 correspond to Figure 3210, and the DAC 230 may further include signals 314 and 318 in the DAC 230, thereby selecting a corresponding pre-charge capacitor (or capacitors) from the fast charge circuit 260 and connecting them to the reference voltage line 232 at the precise time (or just before) that the DAC 230 processes a bit. The controller 250 (and / or the clock generator 210) is also configured to send a delayed reset signal (Φ) to the fast charge circuit 260. r )306.

[0075] The current consumed by ADC 200 over time is shown at 322. Figure 3 As can be seen in FIG. 2 , the current consumed by the ADC spikes up when the comparator 240 is enabled and ready, and when the DAC 230 begins processing a bit of the digital code (eg, MSB or MSB-1). The current consumed by the ADC also spikes at the beginning of the reset phase.

[0076] The output current of the fast charge circuit is shown at 320. Figure 3 As can be seen in the figure, by selecting and connecting a corresponding one (or more) pre-charge capacitors from the fast charge circuit 260 on the reference voltage line 232 when the DAC starts processing a bit of the digital code and when the reset phase begins (via the delayed reset signal 306), the current pulses of the output current from the fast charge circuit 260 are synchronously matched with the pulses of the ADC current consumption.

[0077] The reference voltage varying with time is shown at 324. Due to matching with the current pulse, V REF The voltage drop is minimized and VREF remains (almost) constant over time and especially does not drop significantly every time the current consumed by the ADC spikes.

[0078] Figure 4 A fast charging circuit 400 is shown, which can operate as a charge pump. Figure 2 This provides a method of using a charging voltage source (power supply) that is only slightly above or slightly below a reference voltage.

[0079] Fast charge circuit 400 includes an additional switch 410 to allow the charge pump to operate. Switch 410 helps keep the circuit time-aligned with other parts of the ADC, such as the comparator and DAC. Voltage 420 represents a lower charging voltage (power source) for boosting to provide a supplemental source of charge.

[0080] In fast charge circuit 400, different weighted (pre-charge) capacitor values ​​are used than in fast charge circuit 260 in order to balance the added charge with the consumed charge.

[0081] Figure 5An exemplary ADC 500 including an on-cycle error correction circuit 580 is shown.

[0082] ADC 500 includes a clock generator 510, a sampling switch 520, a digital-to-analog converter DAC 530, a comparator 540, a controller 550, a capacitor bank 560, a charging voltage source 570, and a same-cycle error correction circuit 580. The configuration of ADC 500 may be similar to ADC 200. ADC 500 may be a SAR ADC. Alternatively, charging voltage source 570 may be an external voltage source rather than a part of ADC 500.

[0083] The clock generator 510 may be the same as the clock generator 210 and is configured to receive an (external) input clock signal 512 to generate a sampling clock signal 514 and send the sampling clock signal 514 to the sampling switch 520. The clock generator 510 is also configured to send a reset signal 518 to the sampling switch 520 and the capacitor bank 560.

[0084] The sampling switch 520 may be the same as the sampling switch 220 and is configured to receive the sampling clock signal 514 from the clock generator 510 and also receive the (analog) input voltage signal 216 (V IN ). The sampling switch 520 can remain on until the input signal V IN The final digital approximation of and / or until a reset signal 518 is received from the clock generator 510. For example, the sampling switch 520 can be implemented as a sample and hold circuit. The sampling switch 520 is also configured to send the input voltage 516 to the comparator 540.

[0085] DAC 530 may be identical to DAC 130 or 230, and is configured to receive an n-bit digital code / signal 552 from controller 550. DAC 530 may be implemented, for example, as a capacitive DAC.

[0086] The received digital code is converted by DAC 530 into an analog reference signal / voltage 532 and transmitted to comparator 540 .

[0087] The comparator 540 may be the same as the comparator 140 or 240, and is configured to receive both the input voltage 516 from the sampling switch 520 and the generated reference voltage 532 from the DAC 530, compare the two, and thereby determine whether the generated reference voltage 532 is higher or lower than the input voltage 516. The comparator 540 is also configured to transmit the result of the comparison to the controller 550.

[0088] The controller 550 may be similar to the SAR controller 150 or the controller 250 and is configured to determine an initial digital code and send it to the DAC 530. The controller 550 is also configured to determine each additional digital code in a series of digital codes (after the initial code) that represent successive digital approximations of the input voltage 516. This determination is based on the result of the comparison received from the comparator 540.

[0089] The controller 550 may also be configured to complete one iteration and output a final digital code as an approximate digital representation of the input voltage 516 once all bits have been processed / determined.

[0090] The controller 550 may include circuitry configured to detect and track the bit that the DAC 530 is currently processing. The controller 550 may also be configured to track the precise time at which each bit is processed. For example, the controller 550 may include latches and / or memory ( Figure 5 ), to keep track of the bits that have been processed (from MSB to LSB).

[0091] The controller 550 is configured to send a signal 554 (signal Φ0, Φ1, ...; Φ n ) to capacitor group 560 so as to connect the pre-charge capacitors to the reference voltage line 532 and to the same cycle error correction circuit 580.

[0092] The controller 550 is configured to send a signal 554 (signal Φ0, Φ1, ...; Φ n ) to the same cycle error correction circuit 580. The controller 550 is configured to detect and track each bit processed by the DAC 530 and synchronously connect one (or more) selected pre-charge capacitors of the capacitor bank 560 to the reference voltage line 532 based on the timing and bit value (and / or the position of the bit in the digital code).

[0093] Capacitor bank 560 may be the same as capacitor bank 260 and include a plurality of pre-charged capacitors. The capacitors of capacitor bank 560 are pre-charged to a voltage equal to VREF. Alternatively, the capacitors of the capacitor bank may be pre-charged to a voltage higher than VREF.

[0094] The capacitor bank 560 also includes a plurality of switches 562. The capacitor bank 560 may have a long settling period, and loose requirements compared to other parts of the ADC 500. The capacitor bank 560 is also configured to be controlled and synchronized by the controller 550.

[0095] The controller 550 is configured to control the switch 562 to pre-charge one or more capacitors of the capacitor bank 560 from a charging voltage source 570 on a voltage line 572 , which is also connected to the reference voltage line 532 .

[0096] The charging voltage source 570 may be configured to provide a voltage equal to the reference voltage to be generated. In particular, the charging voltage source 570 may be implemented by a programmable voltage source configured to provide a voltage equal to the analog reference voltage generated by the ADC 500. The active buffer 574 is located between the charging voltage source 570 and the ADC 500. Alternatively, the charging voltage source 570 may be located outside the ADC 500 ( Figure 5 not shown).

[0097] The same cycle error correction circuit 580 is configured to correct errors within one sampling cycle, ie, errors occurring during the conversion of a single analog input voltage 516. The controller 550 may be configured to control and synchronize the error correction circuit 580.

[0098] The same cycle error correction circuit 580 includes a plurality of comparators 582 and a (unique) correction capacitor 584. The same cycle error correction circuit 580 may include a comparator 582 and a (unique) correction capacitor 584 for a single event / bit, for multiple events / bits, and / or for all events / bits occurring during a sampling period.

[0099] The error correction circuit 580 receives a signal 554 from the controller 550 corresponding to a delayed version (Φ0, Φ1, ...; Φ n ). The reference voltage VREF generated on line 532 is then compared with a clean reference on line 590 obtained from voltage source 570 via a plurality of comparators 582. Clean reference 590 may be generated by another (external) voltage source ( Figure 5 Depending on the result of the comparison, the correction capacitor 584 may be switched on the reference voltage line 532.

[0100] Error correction circuit 580 allows for a more accurate voltage reference level to be achieved. For example, it can correct / adjust for errors caused by mismatches in added and consumed charge, errors caused by variations in voltage levels, errors due to variations in capacitors, and errors due to other losses.

[0101] Figure 6 An example ADC 600 including a multi-cycle error correction circuit is shown in accordance with some aspects.

[0102] The ADC 600 includes a clock generator 510 , a sampling switch 520 , a digital-to-analog converter DAC 530 , a comparator 540 , a controller 650 , a capacitor bank 660 , a charging voltage source 570 , and a multi-cycle error correction circuit 680 .

[0103] ADC 600 is similar to ADC 500 and includes a different error correction circuit 680 (rather than circuit 580) and a different capacitor bank 660 including variable / programmable (array) capacitors.

[0104] Capacitor bank 660 of ADC 600 includes variable / programmable (array) capacitors with switches 662. Controller 650 may be similar to controller 550 and is configured to control and synchronize multi-cycle error correction circuit 680. Other components of ADC 600 are configured similarly to corresponding components of ADC 500.

[0105] The multi-cycle error correction circuit 680 is configured to detect and correct deviations of multiple sampling cycles, ie, conversion deviations of multiple analog input voltages 516 .

[0106] The multi-cycle error correction circuit 680 includes a plurality of comparators 682 and a loop filter 684. The multi-cycle error correction circuit 680 may include comparators 682 and loop filters 684 for a single event / bit, multiple events / bits, and / or all events / bits occurring within multiple sampling periods.

[0107] The multi-cycle error correction circuit 680 receives a signal 654 from the controller 650 corresponding to a delayed version (Φ0, Φ1, ...; Φ n ). Each of the received signals is then compared to the voltage value of the clean reference 590 via a plurality of comparators 682. Based on the results of the comparison, the loop filter 684 is configured to adjust the corresponding variable (programmable) capacitor 664 of the capacitor bank 660 so as to minimize the reference voltage error within a plurality of sampling clock cycles.

[0108] The multi-cycle error correction circuit 680 allows the values ​​of the capacitors included in the capacitor bank 660 to be adjusted to account for mismatches in capacitor values, voltage reference values, supply voltage values, temperature variations, or other effects.

[0109] In the case of multiple ADCs arranged in a time interleaved (TI) manner and sharing a common reference voltage source between all ADC slices (such as charging voltage source 270, 570 or 670), the reference voltage received by the ADC slices may be degraded (dropped) due to crosstalk and / or voltage drops.

[0110] In other words, the internal slices of the TI ADC arrangement / array may receive an incorrect (lower) reference voltage. The voltage error will generally be greater the further the ADC slice is from the common reference voltage source.

[0111] Figure 7A schematic overview of typical reference voltage errors in TI ADCs is shown.

[0112] exist Figure 7 In the schematic diagram of FIG. 702, 704 represents the voltage level of the common reference voltage source of the TI ADC arrangement, and 704 represents the voltage actually received by the ADC (chip). Figure 7 As can be seen in , the further the ADC is from the common reference voltage source, the greater the error 706.

[0113] In the following, the above techniques, examples, and embodiments for improving the stability of reference voltages in ADCs are modified to arrangements of TI ADCs including multiple ADCs. These modifications apply to a single ADC slice, across multiple slices or groups of slices of a TI ADC, or across multiple unique ADCs in a larger system (multi-channel) that share one or more common references.

[0114] Figure 8 An example arrangement 800 including a plurality of TI ADCs 802 is shown in accordance with some aspects.

[0115] Arrangement 800 includes a plurality of ADCs 802, wherein each ADC 802 may be a Figure 2 ADC 200, Figure 5 ADC500 or Figure 6 ADC 600 of ADC. Each ADC 802 is configured to include a fast charging circuit 810, such as capacitor bank 260, 560 or 660. Each fast charging circuit 810 includes at least one pre-charge capacitor ( Figure 8 ADC 802 also includes an error correction circuit 820, such as, for example, error correction circuit 580 or 680.

[0116] A first reference voltage 840 is provided to each ADC in ADC 802, and in particular to fast charging circuit 810. Similar to Figure 5 and Figure 6 In an exemplary embodiment of the present invention, a second (clean) reference voltage 850 is provided to each ADC in the ADC 802, and in particular to the error correction circuit 820, so that the error correction circuit 820 can compare the two reference voltages.

[0117] The controller 830 is configured to control and synchronize the operation of multiple ADCs. The controller 830 may include (dynamic) multi-input, multi-output control logic and a loop filter. The controller 830 is configured to receive a signal 822 from each of the error correction circuits 820 of the multiple TI ADCs. The controller 830 is also configured to determine the (optimal) value of one or more pre-charged capacitors included in the fast charging circuit 810 based on the received signal 822. The controller 830 is also configured to send a control signal 824 to one or more ADCs 802, which indicates that one or more pre-charged capacitors included in the fast charging circuit 810 are selected and connected to the reference line. The controller 830 may be configured to directly connect the determined pre-charged capacitor, for example, by controlling a switch ( Figure 8 not shown).

[0118] The controller 830 is also configured to weight the correction capacitors included in the fast charge circuit 810 differently based on the location of the ADCs in the ADC arrangement 800 in order to compensate for the crosstalk / voltage drop on the shared reference voltage 840 (eg, Figure 7 shown).

[0119] The controller 830 is also configured to take into account errors of adjacent ADC slices and dynamically adjust the errors along the arrangement / array over multiple sampling periods.

[0120] In other words, Figure 8 In the arrangement 800, based on a synchronous (or asynchronous) data-driven decision event occurring in the ADC 802, a time-aligned, data-dependent feed-forward capacitor pre-charged to a higher voltage (or charge pump voltage) is switched to a reference, thereby speeding up the stabilization of the reference voltage with a matching pulse current and reducing crosstalk among multiple ADC chips sharing a reference.

[0121] As an example, in a 5nm technology implementation of the above TI ADC arrangement 800, the reference (active) buffer of the ADC slice may occupy 20μm of the 200μm total slice width. With the above arrangement 800, the area required for the active buffer is greatly reduced, for example, by 50% or more, and the current required for the active buffer may also be greatly reduced, for example, by 50% or more.

[0122] Fig. 9 FIG. 4 shows a flow chart showing a method for stabilizing a reference voltage in an analog-to-digital converter ADC. Fig. 9As shown, a method 900 of stabilizing a reference voltage includes generating 902 an analog reference voltage on a reference voltage line, and connecting a pre-charge capacitor 904 of an ADC to the reference voltage line when generating the analog reference voltage to reduce voltage errors during the generation of the reference voltage.

[0123] Fig.10 FIG. 1 shows a flow chart illustrating a method 1000 for stabilizing a reference voltage in multiple time-interleaved analog-to-digital converters ADCs that share a common reference voltage source. Fig.10 As shown, method 1000 includes generating 1002 an analog reference voltage for a corresponding ADC among a plurality of ADCs along a common reference voltage line to which the plurality of ADCs are connected; determining 1004 a capacitance value and / or a charge level of a pre-charge capacitor in a corresponding ADC based on a position of the corresponding ADC on the common reference voltage line; and when generating the analog reference voltage, connecting 1006 the pre-charge capacitor of the corresponding ADC to the reference voltage line based on the value of the analog reference voltage to be generated, so as to reduce a voltage error during generation of the reference voltage by the corresponding ADC.

[0124] Fig.11 An exemplary analog-to-digital converter ADC 1100 configured to convert an input analog voltage into a digital representation according to some aspects is shown. Fig.11 As shown, ADC 1100 includes a digital-to-analog converter DAC 1110 configured to generate an analog reference voltage, wherein the analog reference voltage is generated on a reference voltage line 1112, a pre-charge capacitor 1120, and a controller 1130, the controller being configured to connect the pre-charge capacitor to the reference voltage line when the DAC 1110 generates the analog reference voltage, so as to reduce a voltage error during the period when the DAC 1110 generates the analog reference voltage.

[0125] Although the above description and connection diagrams may describe electronic device elements as separate elements, the skilled person will appreciate the various possibilities of combining or integrating discrete elements into a single element. This may include combining two or more circuits to form a single circuit, mounting two or more circuits onto a common semiconductor chip or chassis to form an integrated element, executing discrete software components on a common processor core, etc. Conversely, the skilled person will recognize the possibility of separating a single element into two or more discrete elements, such as splitting a single circuit into two or more separate circuits, separating a semiconductor chip or chassis into discrete elements originally provided thereon, separating a software component into two or more parts and executing each part on a separate processor core, etc.

[0126] It should be understood that the specific implementation of the method detailed herein is exemplary in nature and is therefore understood to be implemented in the corresponding device. Similarly, it should be understood that the specific implementation of the device detailed herein is understood to be implemented as a corresponding method. It is therefore understood that the device corresponding to the method detailed herein may include one or more components configured to perform each aspect of the related method.

[0127] All abbreviations defined in the above description are also valid in all claims included herein.

[0128] The following examples disclose various aspects of the present disclosure:

[0129] Example 1 is a method of stabilizing a reference voltage in an analog-to-digital converter (ADC). The method may include generating an analog reference voltage on a reference voltage line, and connecting a precharge capacitor of the ADC to the reference voltage line when generating the analog reference voltage to reduce a voltage error during the generation of the reference voltage.

[0130] In Example 2, the subject matter of Example 1 can optionally include the capacitor being precharged to a voltage higher than the generated reference voltage, or a voltage equal to the generated reference voltage.

[0131] In Example 3, the subject matter of Example 1 or 2 can optionally include selecting the pre-charge capacitor from a plurality of pre-charge capacitors of the ADC based on a value of the analog reference voltage to be generated.

[0132] In Example 4, the subject matter of Example 3 can optionally include multiple capacitors having different capacitances and / or being pre-charged to different charge levels.

[0133] In Example 5, the subject matter of any one of Examples 1 to 4 may optionally include: the ADC includes a digital-to-analog converter DAC configured to receive a digital code indicating an analog reference voltage to be generated and generate the analog reference voltage, and when the DAC generates the analog reference voltage, the pre-charge capacitor is connected to the reference voltage line.

[0134] In Example 6, the subject matter of any one of Examples 1 to 5 may optionally include that the digital code corresponds to a digital approximation of an analog input voltage to be converted by the ADC.

[0135] In Example 7, the subject matter of any one of Examples 1 to 6 may optionally include: the ADC includes a successive approximation register SAR configured to successively store a plurality of digital codes, and each digital code stored in the SAR indicates an analog reference voltage to be generated and corresponds to a successive approximation of an input analog voltage to be converted by the ADC.

[0136] In Example 8, the subject matter of any one of Examples 1 to 7 may optionally include receiving an additional reference voltage, comparing the value of the generated reference voltage with the value of the additional reference voltage, and adjusting the generated reference voltage according to the value of the additional reference voltage if the generated reference voltage value does not correspond to an expected value based on the value of the additional reference voltage.

[0137] In Example 9, the subject matter of Example 8 can optionally include receiving a sampling clock signal instructing the ADC to begin converting the analog input voltage to a digital representation, and adjusting the generated reference voltage during the sampling clock period.

[0138] In Example 10, the subject matter of Example 8 can optionally include receiving a sampling clock signal instructing the ADC to begin converting the analog input voltage to a digital representation, and adjusting the generated reference voltage over a plurality of sampling clock cycles across a plurality of conversions of the analog input voltage by the ADC.

[0139] In Example 11, the subject matter of Example 9 or 10 may optionally include receiving a reset signal before the sampling clock signal, wherein the reset signal indicates a reset phase of the ADC before a next conversion of the analog input voltage.

[0140] Example 12 is a method for stabilizing a reference voltage in a plurality of time-interleaved analog-to-digital converters ADCs that share a common reference voltage source. The method may include generating an analog reference voltage for a corresponding ADC in a plurality of ADCs along a common reference voltage line to which the plurality of ADCs are connected, and when generating the analog reference voltage, connecting a pre-charge capacitor of the corresponding ADC on the reference voltage line based on the value of the analog reference voltage to be generated to reduce a voltage error during the generation of the reference voltage by the corresponding ADC, wherein the capacitance value and / or charge level of the pre-charge capacitor in the corresponding ADC is determined based on the position of the corresponding ADC on the common reference voltage line.

[0141] In Example 13, the subject matter of Example 12 can optionally include selecting the pre-charge capacitor from a plurality of pre-charge capacitors of the corresponding ADC based on a value of the analog reference voltage to be generated.

[0142] In Example 14, the subject matter of Example 12 or 13 may optionally include adjusting the generated analog reference voltage in the corresponding ADC based on a result of the comparison of the generated reference voltage value with the further reference voltage value.

[0143] Example 15 is an analog-to-digital converter ADC configured to convert an input analog voltage into a digital representation. The ADC may include: a digital-to-analog converter DAC configured to generate an analog reference voltage, wherein the analog reference voltage is generated on a reference voltage line; a precharge capacitor; and a controller configured to connect the precharge capacitor to the reference voltage line when the DAC generates the analog reference voltage to reduce a voltage error during the DAC generating the analog reference voltage.

[0144] In Example 16, the subject matter of Example 15 can optionally include the DAC being further configured to receive a digital code indicative of an analog reference voltage to be generated, wherein the digital code corresponds to a digital approximation of an analog input voltage to be converted by the ADC.

[0145] In Example 17, the subject matter of Example 15 or 16 may optionally include: a comparator configured to compare an input analog voltage with a generated reference voltage; and a controller configured to receive a result of the comparison and determine a digital code indicating an analog reference voltage to be generated based on the result of the comparison.

[0146] In Example 18, the subject matter of any one of Examples 15 to 17 may optionally include: a successive approximation register SAR, which is configured to store a plurality of digital codes in succession, wherein each digital code stored in the SAR indicates an analog reference voltage to be generated and corresponds to a successive approximation of an input analog voltage to be converted by the ADC.

[0147] In Example 19, the subject matter of any one of Examples 15 to 18 can optionally include pre-charging the capacitor via a voltage booster.

[0148] In Example 20, the subject matter of any one of Examples 15 to 19 may optionally include the capacitor being precharged to a voltage higher than the generated reference voltage, or a voltage equal to the generated reference voltage.

[0149] In Example 21, the subject matter of any one of Examples 15 to 20 may optionally include a plurality of pre-charge capacitors, wherein the pre-charge capacitor connected to the reference voltage line is selected from the plurality of pre-charge capacitors based on a value of an analog reference voltage to be generated.

[0150] In Example 22, the subject matter of any one of Examples 15 to 21 can optionally include a plurality of pre-charge capacitors having different capacitances and / or being pre-charged to different charge levels.

[0151] In Example 23, the subject matter of any one of Examples 15 to 22 may optionally include the DAC being an algorithmically weighted capacitive DAC, or the DAC being a binary weighted capacitive DAC.

[0152] In Example 24, the subject matter of any one of Examples 15 to 23 can optionally include connecting the pre-charge capacitor to the reference voltage line by actuating a switch between the pre-charge capacitor and the reference voltage line.

[0153] In Example 25, the subject matter of any one of Examples 15 to 24 may optionally include: the ADC is configured to receive a sampling clock signal instructing the ADC to start converting an analog input voltage, and the ADC also includes a comparator and an error correction circuit, the comparator being configured to compare the value of the generated reference voltage with the value of another reference voltage after the pre-charge capacitor is connected to the reference voltage line, the error correction circuit being configured to receive a signal indicating a result of the comparison from the comparator, and adjusting the generated reference voltage based on the result of the comparison.

[0154] In Example 26, the subject matter of Example 25 can optionally include: the error correction circuit includes a plurality of capacitors, and based on a result of the comparison, the error correction circuit is configured to connect one or more of the plurality of capacitors to a reference voltage line during a sampling clock period.

[0155] In Example 27, the subject matter of Example 25 may optionally include: the pre-charge capacitor is a variable capacitor, and the error correction circuit includes multiple loop filters and is configured to adjust the generated reference voltage by adjusting the capacitance value and / or charge level of the pre-charge capacitor over multiple sampling clock cycles spanning multiple conversions of the analog input voltage performed by the ADC.

[0156] In Example 28, the subject matter of any one of Examples 25 to 27 may optionally include a sampling switch configured to receive a reset signal before the sampling clock signal, and to reset the sampling switch by closing the sampling switch.

[0157] Example 29 is an arrangement including a plurality of ADCs according to the subject matter of any one of Examples 15 to 28. The subject matter of Example 29 includes: the plurality of ADCs are time-interleaved and share a common reference voltage source and a common reference voltage line, and the capacitance value and / or the charge level of the pre-charge capacitor included in each ADC is determined based on the position of the ADC along the common reference voltage line.

[0158] In Example 30, the subject matter of Example 29 may optionally include: each corresponding ADC further includes a plurality of pre-charge capacitors, and the pre-charge capacitor of the corresponding ADC connected to the reference voltage line is selected from the plurality of pre-charge capacitors based on the value of the analog reference voltage to be generated.

[0159] In Example 31, the subject matter of Example 29 or 30 may optionally include a controller configured to adjust a value of the generated analog reference voltage in the corresponding ADC based on a result of a comparison of the generated reference voltage with a further reference voltage.

[0160] In Example 32, the subject matter of Example 31 may optionally include: the arrangement is also configured to receive a sampling clock signal instructing the corresponding ADC to start converting an analog input voltage; the pre-charge capacitor included in the corresponding ADC is variable, and the controller is also configured to: based on the result of the comparison, adjust the reference voltage generated by the corresponding ADC within multiple sampling clock cycles by adjusting the capacitance value and / or charge value of the pre-charge capacitor of the corresponding ADC.

[0161] Example 33 is a non-transitory computer-readable medium. The non-transitory computer-readable medium may include instructions that, when executed by one or more processors, are configured to cause the one or more processors to implement a method for stabilizing a reference voltage in an analog-to-digital converter ADC, wherein the method includes generating an analog reference voltage on a reference voltage line, and connecting a pre-charge capacitor of the ADC to the reference voltage line when generating the analog reference voltage to reduce a voltage error during the generation of the reference voltage.

[0162] In Example 34, the subject matter of Example 33 can optionally include the capacitor being precharged to a voltage higher than the generated reference voltage, or the capacitor being precharged to a voltage equal to the generated reference voltage.

[0163] In Example 35, the subject matter of Example 33 or 34 may optionally include: the instructions are further configured to cause the one or more processors to: select a pre-charge capacitor from a plurality of pre-charge capacitors of the ADC based on a value of the analog reference voltage to be generated.

[0164] In Example 36, the subject matter of Example 35 can optionally include multiple capacitors having different capacitances and / or being pre-charged to different charge levels.

[0165] In Example 37, the subject matter of any one of Examples 33 to 36 may optionally include: the ADC includes a digital-to-analog converter DAC, which is configured to receive a digital code indicating an analog reference voltage to be generated and generate the analog reference voltage; and when the DAC generates the analog reference voltage, the pre-charge capacitor is connected to the reference voltage line.

[0166] In Example 38, the subject matter of Example 37 can optionally include that the digital code corresponds to a digital approximation of an analog input voltage to be converted by the ADC.

[0167] In Example 39, the subject matter of any one of Examples 33 to 38 may optionally include: the ADC includes a successive approximation register SAR, which is configured to store multiple digital codes in succession, and each digital code stored in the SAR indicates an analog reference voltage to be generated and corresponds to a successive approximation of an input analog voltage to be converted by the ADC.

[0168] In Example 40, the subject matter of any one of Examples 33 to 39 may optionally include: the instructions are also configured to cause one or more processors to receive an additional reference voltage, compare the generated reference voltage value with the additional reference voltage value, and adjust the generated reference voltage according to the additional reference voltage value if the generated reference voltage value does not correspond to an expected value based on the additional reference voltage value.

[0169] In Example 41, the subject matter of Example 40 can optionally include: the instructions are further configured to cause the one or more processors to receive a sampling clock signal indicating the start of the ADC converting the analog input voltage to a digital representation, and adjust the generated reference voltage during the sampling clock period.

[0170] In Example 42, the subject matter of Example 40 may optionally include: the instructions are also configured to cause one or more processors to receive a sampling clock signal indicating the start of the ADC converting the analog input voltage to a digital representation, and to adjust the generated reference voltage over multiple sampling clock cycles spanning multiple conversions of the analog input voltage performed by the ADC.

[0171] In Example 43, the subject matter of Example 41 or 42 may optionally include: the instructions are further configured to cause the one or more processors to receive a reset signal before the sampling clock signal, wherein the reset signal indicates a reset phase of the ADC before conversion of a next analog input voltage.

[0172] Example 44 is a non-transitory computer-readable medium. The non-transitory computer-readable medium may include instructions that, when executed by one or more processors, are configured to cause the one or more processors to implement a method for stabilizing a reference voltage in a plurality of time-interleaved analog-to-digital converters (ADCs) that share a common reference voltage source, wherein the method includes generating an analog reference voltage for a corresponding ADC in a plurality of ADCs along a common reference voltage line to which the plurality of ADCs are connected, and when generating the analog reference voltage, connecting a pre-charge capacitor of the corresponding ADC to the reference voltage line to reduce a voltage error during generation of the reference voltage by the corresponding ADC, wherein a capacitance value and / or charge level of the pre-charge capacitor in the corresponding ADC is determined based on a position of the corresponding ADC on the common reference voltage line.

[0173] In Example 45, the subject matter of Example 44 can optionally include that the instructions are further configured to cause the one or more processors to: select a pre-charge capacitor from a plurality of pre-charge capacitors of the corresponding ADC based on a value of the analog reference voltage to be generated.

[0174] In Example 46, the subject matter of Example 44 or 45 may optionally include that the instructions are further configured to: cause the one or more processors to adjust the generated analog reference voltage in the corresponding ADC based on the result of the comparison of the generated reference voltage value with the other reference voltage value.

[0175] Example 47 is an analog-to-digital converter (ADC) configured to convert an input analog voltage into a digital representation. The ADC may include: means for generating an analog reference voltage, wherein the analog reference voltage is generated on a reference voltage line; and means for connecting a pre-charge capacitor of the ADC to the reference voltage line when generating the analog reference voltage to reduce voltage errors during the generation of the analog reference voltage.

[0176] In Example 48, the subject matter of Example 47 can optionally include means for receiving a digital code indicative of an analog reference voltage to be generated, wherein the digital code corresponds to a digital approximation of an analog input voltage to be converted by the ADC.

[0177] In Example 49, the subject matter of Example 47 or 48 may optionally include: a device for comparing an input analog voltage with a generated reference voltage; a device for receiving a result of the comparison, and a device for determining a digital code indicating an analog reference voltage to be generated based on the result of the comparison.

[0178] In Example 50, the subject matter of any one of Examples 47 to 49 may optionally include means for storing a plurality of digital codes, wherein each stored digital code is indicative of an analog reference voltage to be generated and corresponds to a successive approximation of an input analog voltage to be converted by the ADC.

[0179] In Example 51, the subject matter of any one of Examples 47 to 50 may optionally include pre-charging the capacitor via a voltage booster.

[0180] In Example 52, the subject matter of any one of Examples 47 to 51 may optionally include the capacitor being precharged to a voltage higher than the generated reference voltage, or a voltage equal to the generated reference voltage.

[0181] In Example 53, the subject matter of any one of Examples 47 to 52 may optionally include a plurality of pre-charged capacitors, and means for selecting a pre-charged capacitor connected to a reference voltage line from the plurality of pre-charged capacitors based on a value of an analog reference voltage to be generated.

[0182] In Example 54, the subject matter of any one of Examples 47 to 53 may optionally include multiple pre-charge capacitors having different capacitances and / or being pre-charged to different charge levels.

[0183] In Example 55, the subject matter of any one of Examples 47 to 54 may optionally include a device for receiving a sampling clock signal instructing the ADC to start converting an analog input voltage, a device for comparing the value of a reference voltage generated after the pre-charge capacitor is connected to a reference voltage line with the value of another reference voltage, a device for receiving a signal indicating a result of the comparison, and a device for adjusting the generated reference voltage based on the result of the comparison.

[0184] In Example 56, the subject matter of Example 55 can optionally include means for connecting one or more capacitors of the plurality of capacitors to a reference voltage line, wherein the one or more capacitors are connected during a sampling clock cycle and based on a result of the comparison.

[0185] In Example 57, the subject matter of Example 55 may optionally include means for adjusting the generated reference voltage by adjusting the capacitance value and / or charge level of the pre-charge capacitor over multiple sampling clock cycles spanning multiple conversions of the analog input voltage performed by the ADC.

[0186] In Example 58, the subject matter of any one of Examples 47 to 57 may optionally include that the multiple ADCs are time-interleaved and share a common reference voltage source and a common reference voltage line, and the capacitance value and / or charge level of the pre-charge capacitor included in each ADC is determined based on the position of the ADC along the common reference voltage line.

[0187] In Example 59, the subject matter of Example 58 may optionally include each corresponding ADC further comprising a plurality of pre-charge capacitors, and including a device for selecting a pre-charge capacitor of the corresponding ADC connected to the reference voltage line from the plurality of pre-charge capacitors based on the value of the analog reference voltage to be generated.

[0188] In Example 60, the subject matter of Example 58 or 59 may optionally include means for adjusting the value of the generated analog reference voltage in the corresponding ADC based on a result of the comparison of the generated reference voltage with the further reference voltage.

[0189] In Example 61, the subject matter of Example 60 may optionally include a device for receiving a sampling clock signal instructing the corresponding ADC to start converting an analog input voltage, and a device for adjusting the reference voltage generated by the corresponding ADC within multiple sampling clock cycles by adjusting the capacitance value and / or charge level of the pre-charge capacitor of the corresponding ADC based on the result of the comparison.

[0190] Although the present invention has been specifically shown and described with reference to specific embodiments, it will be appreciated by those skilled in the art that various changes may be made to the form and details of the present invention without departing from the spirit and scope of the present invention as defined in the appended claims. Therefore, the scope of the present invention is indicated by the appended claims, and therefore, all changes within the meaning and equivalent range of the claims are intended to be included therein.

Claims

1. A non-transitory computer-readable medium comprising instructions which, when executed by one or more processors, are configured to cause the one or more processors to: generating an analog reference voltage on a reference voltage line; and When generating the analog reference voltage, a precharge capacitor of an analog-to-digital converter (ADC) is connected to the reference voltage line to reduce a voltage error during generation of the analog reference voltage in the ADC.

2. The non-transitory computer-readable medium of claim 1, wherein the instructions further cause the one or more processors to: select the pre-charge capacitor from a plurality of pre-charge capacitors of the ADC based on a value of the analog reference voltage to be generated.

3. The non-transitory computer readable medium of claim 1, in, The ADC includes a digital-to-analog converter DAC configured to receive a digital code indicating the analog reference voltage to be generated and to generate the analog reference voltage, and The pre-charge capacitor is connected to the reference voltage line when the DAC generates the analog reference voltage.

4. The non-transitory computer readable medium of any one of claims 1 to 3, wherein the instructions further cause the one or more processors to: receiving another reference voltage; comparing the value of the analog reference voltage with the value of the further reference voltage; and In case the analog reference voltage value does not correspond to an expected value based on the reference voltage value, the analog reference voltage is adjusted according to the further reference voltage value.

5. A method for stabilizing a reference voltage in a plurality of time-interleaved analog-to-digital converters (ADCs) sharing a common reference voltage source, the method comprising: generating an analog reference voltage for a corresponding ADC of the plurality of ADCs along a common reference voltage line to which the plurality of ADCs are connected; as well as When generating the analog reference voltage and based on the value of the analog reference voltage to be generated, connecting a precharge capacitor of the corresponding ADC to the reference voltage line to reduce a voltage error during generation of the analog reference voltage by the corresponding ADC, Wherein, the capacitance value and / or charge level of the pre-charge capacitor in the corresponding ADC is determined based on the position of the corresponding ADC on the common reference voltage line.

6. The method according to claim 5, further comprising: The pre-charge capacitor is selected from a plurality of pre-charge capacitors of a corresponding ADC based on a value of the analog reference voltage to be generated.

7. The method according to claim 5 or 6, further comprising: Based on the result of the comparison of the generated analog reference voltage value with the further reference voltage value, the generated analog reference voltage in the corresponding ADC is adjusted.

8. An analog-to-digital converter (ADC) configured to convert an input analog voltage into a digital representation, the ADC comprising: a digital-to-analog converter (DAC) configured to generate an analog reference voltage on a reference voltage line; Pre-charge capacitors; as well as A controller, the controller being configured to: During the period when the DAC generates the analog reference voltage, the precharge capacitor is connected to the reference voltage line to reduce a voltage error during the period when the analog reference voltage is generated by the DAC.

9. The ADC according to claim 8, further comprising: a comparator configured to compare the input analog voltage with the analog reference voltage; as well as A controller is configured to receive a result of the comparison and determine a digital code indicative of the analog reference voltage to be generated based on the result of the comparison.

10. The ADC according to claim 8, further comprising: a successive approximation register (SAR) configured to successively store a plurality of digital codes, Wherein, each digital code stored in the SAR indicates the analog reference voltage to be generated and corresponds to a successive approximation of an input analog voltage to be converted by the ADC.

11. The ADC of claim 8, wherein the capacitor is pre-charged via a voltage booster.

12. The ADC according to any one of claims 8 to 11, further comprising: Multiple pre-charge capacitors, wherein a pre-charge capacitor connected to the reference voltage line is selected from the plurality of pre-charge capacitors based on a value of the analog reference voltage to be generated.

13. The ADC of claim 12, wherein the plurality of pre-charge capacitors have different capacitances and / or are pre-charged to different charge levels.

14. The ADC according to any one of claims 8 to 11, further configured to receive a sampling clock signal instructing the ADC to start converting the analog input voltage, and further comprising: a comparator configured to compare the value of the analog reference voltage with a value of another reference voltage after the pre-charge capacitor is connected to the reference voltage line; as well as An error correction circuit, the error correction circuit being configured to: receiving a signal from the comparator indicative of a result of the comparison; and The analog reference voltage is adjusted based on a result of the comparison.

15. The ADC according to claim 14, wherein the error correction circuit comprises a plurality of capacitors, and in, Based on the result of the comparison, the error correction circuit is configured to connect one or more of the plurality of capacitors to the reference voltage line during a sampling clock period.

16. The ADC according to claim 14, wherein the pre-charge capacitor is a variable capacitor, and The error correction circuit includes a plurality of loop filters and is configured to adjust the analog reference voltage by adjusting the capacitance value and / or charge level of the pre-charge capacitor over a plurality of sampling clock cycles spanning a plurality of conversions of the analog input voltage performed by the ADC.

17. A system comprising: a plurality of ADCs, wherein each ADC of the plurality of ADCs comprises the ADC according to claim 8, wherein the plurality of ADCs are time-interleaved and share a common reference voltage source and a common reference voltage line, and The capacitance value and / or charge level of the pre-charge capacitor included in each ADC is determined based on the position of the ADC along the common reference voltage line.

18. The system of claim 17, wherein each respective ADC of the plurality of ADCs further comprises: a plurality of pre-charge capacitors associated with the respective ADCs, and Wherein a pre-charge capacitor of a corresponding ADC connected to the reference voltage line is selected from the plurality of pre-charge capacitors based on the value of the analog reference voltage to be generated.

19. The system of claim 18, further comprising: A controller is configured to adjust a value of an analog reference voltage in the corresponding ADC based on a result of the comparison of the analog reference voltage with another reference voltage.

20. The system of claim 19, further configured to: receive a sampling clock signal instructing the corresponding ADC to start converting an analog input voltage, wherein the pre-charge capacitor included in the corresponding ADC is variable, and in, The controller is further configured to adjust an analog reference voltage of the corresponding ADC within a plurality of sampling clock cycles by adjusting a capacitance value and / or a charge level of a pre-charge capacitor of the corresponding ADC based on a result of the comparison.

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