Analog-to-digital converter with instability recovery circuit

Abstract

In described examples, an integrated circuit (IC) includes first and second integrators (202 and 210), first and second weighted adders (208 and 212), first and second digital-to-analog converters (DACs) (218 and 220), and a quantizer (214). The first and second inputs of the first weighted adder (208) are connected to the output of the first integrator (202) and the output of the second DAC (220), respectively. The input of the second integrator (210) is connected to the output of the first weighted adder (208). An input of the second weighted adder (212) is connected to an output of the second integrator (210). An input of the quantizer (214) is connected to an output of the second weighted adder (212). The inputs of the first and second DACs (218 and 220) are connected to respective outputs of the quantizer (214). An output of the first DAC (218) is connected to a first input of the first integrator (202). The second input of the first integrator (202) and the third input of the first weighted adder (208) are analog signal inputs.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit and priority of Indian Provisional Application No. 202341049171 filed on July 21, 2023, which is incorporated herein by reference. Technical Field

[0003] The present application relates generally to analog-to-digital converters (ADCs), and more particularly to continuous time delta-sigma modulator (CTDSM) ADCs. Background Art

[0004] ADCs are used in a variety of applications to convert analog input signals into digital signals to enable digital signal processing. In some examples, increasing the ADC resolution increases the power or area cost of the ADC. Some applications, such as audio processing, have use cases that support high-resolution signal processing where power consumption is lower and the device occupies a smaller area. Battery-driven audio devices such as mobile phones provide an example use case for ADCs where power and area budgets are lower. Summary of the invention

[0005] In the example, the integrated circuit (IC) includes first and second integrators, first and second weighted adders, first and second digital-to-analog converters (DACs), and a quantizer. The first and second inputs of the first weighted adder are connected to the output of the first integrator and the output of the second DAC, respectively. The input of the second integrator is connected to the output of the first weighted adder. The input of the second weighted adder is connected to the output of the second integrator. The input of the quantizer is connected to the output of the second weighted adder. The inputs of the first and second DACs are connected to the corresponding outputs of the quantizers. The output of the first DAC is connected to the first input of the first integrator. The second input of the first integrator and the third input of the first weighted adder are analog signal inputs.

[0006] In the example, the IC includes a delta-sigma modulator (DSM) and a control circuit that operates the DSM in first and second modes. The DSM includes N>1 integrators, a first DAC, a second DAC, and a quantizer. In the first mode, the control circuit operates the DSM as an N-order modulator so that the integrator output is responsive to a first feedback signal provided by the first DAC in response to the quantizer output. In the second mode, the control circuit operates the DSM as a first-order modulator so that the quantizer output is responsive to the output of a single one of the integrators, a second feedback signal provided by the second DAC in response to the quantizer output, and not responsive to the first feedback signal. The control circuit switches from the first mode to the second mode in response to the output of the integrator and a threshold.

[0007] In the example, the IC includes a low-pass analog filter, a sampling circuit, first and second integrators, first and second weighted adders, first and second DACs, a quantizer, and a low-pass digital filter. The input of the sampling circuit is connected to the output of the low-pass analog filter. The first input of the first integrator is connected to the output of the sampling circuit. The first, second, and third inputs of the first weighted adder are respectively connected to the output of the first integrator, the output of the second DAC, and the output of the sampling circuit. The input of the second integrator is connected to the output of the first weighted adder. The input of the second weighted adder is connected to the output of the second integrator. The input of the quantizer is connected to the output of the second weighted adder. The inputs of the first and second DACs are connected to the corresponding outputs of the quantizer. The output of the first DAC is connected to the second input of the first integrator. The second input of the first integrator and the third input of the first weighted adder are analog signal inputs. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A is a functional block diagram of an example system including an ADC having a CTDSM controlled by an instability recovery circuit.

[0009] Figure 1B yes Figure 1A An example functional block diagram of an ADC.

[0010] Figure 2A yes Figure 1A and 1B Functional block and circuit diagram of an example of a first operating state of the CTDSM and instability recovery circuit.

[0011] Figure 2B is from the recovery circuit to Figure 2A Functional block and circuit diagram of an example of the control connections of the various components of the CTDSM.

[0012] Figure 2C yes Figure 1A and 1B A functional block diagram of another example of a CTDSM and instability recovery circuit.

[0013] Figure 3 yes Figure 1A and 1B Functional block and circuit diagram of an example of a second operating state of the CTDSM and instability recovery circuit.

[0014] Figure 4 yes Figure 1A and 1B Functional block and circuit diagram of an example of a third operating state of the CTDSM and instability recovery circuit.

[0015] Figure 5is an example flow chart representing a method or process of recovering a CTDSM from an unstable state. DETAILED DESCRIPTION

[0016] Some ADCs use CTDSM to convert analog signals into digital signals. The CTDSM includes a delta block, a sigma block, a quantizer, and a feedback path from the quantizer to the delta block via a main (first) digital-to-analog converter (DAC) that provides a feedback signal. The delta block provides a signal to the sigma block in response to the difference between the analog signal and the feedback signal. The sigma block integrates (sums in time) the signal it receives from the delta block. The resulting integrated signal is weighted to balance the signal contribution, and the weighted result is provided to the quantizer to generate the output signal of the CTDSM.

[0017] The complexity of the sigma block is related to the order of the modulator. In some examples, a higher order (more complex) modulator enables a higher resolution (or precision) output signal at the expense of a certain amount of reliability in the stability of the modulator. In some examples, a finite impulse response (FIR) filter feeding the main DAC as part of the feedback loop further enhances the resolution of the CTDSM during nominal operation at the additional expense of reliability in the stability of the modulator.

[0018] Certain changes in the input signal amplitude can cause the CTDSM to saturate. In the saturated state, certain internal signals of the CTDSM oscillate between the maximum level and the minimum level, hindering the accurate operation of the CTDSM. In some examples, high-frequency, low-amplitude changes in the input signal cause the CTDSM to saturate or enter another unstable state. In some examples, changes that cause the CTDSM to receive a signal whose amplitude is equal to or greater than the maximum signal amplitude (MSA) that the CTDSM is designed to handle, regardless of the frequency of the change, cause saturation or another unstable state. Unstable states of the CTDSM, including saturation, are also referred to herein as unstable states or instability conditions.

[0019] Unstable conditions can be detected by comparing the signal levels at different points within the CTDSM to different corresponding thresholds. These different internal signals can be selected so that different causes of saturation or other instabilities are detected, such as high frequency, relatively low amplitude changes in the input signal, or large amplitude (or large amplitude changes) of the input signal.

[0020] When saturation or other unstable conditions are detected, the CTDSM down-adjusts its modulator order, allowing the CTDSM to use a simpler sigma block. In a simplified configuration, the CTDSM uses a second DAC that enables a smaller feedback loop (fewer components in the loop) that feeds a simpler sigma block, avoiding the output signal from the FIR filter (which may reduce stability). Reducing the modulator order and not including the FIR filter output signal in the CTDSM output signal path facilitates stabilizing the CTDSM. At the same time, the inputs of the FIR filter and the main DAC continue to receive the output signal from the quantizer, allowing the FIR filter and the main DAC to continue to be updated. Once the CTDSM has stabilized, the FIR filter and the main DAC that were updated during the down-adjustment operation can smoothly return to nominal operation.

[0021] In some examples, the CTDSM returns to nominal operation via an additional mode between the down-regulated sigma block mode and the nominal more complex sigma block mode. In the intermediate state, the CTDSM uses the medium complexity sigma block and uses the original feedback path via the FIR filter and the main DAC. In some examples, the use of the intermediate mode during recovery enables a shallower recovery path so that when returning to the nominal operation of the CTDSM in the original full complexity configuration, transients corresponding to deviations from the accurate CTDSM output signal are minimized.

[0022] Herein, some different but related structures or signals have reference numbers using the format of [number][letter], such as switches 228a, 228b, and 228c. In some examples, these structures or signals are generally referred to as a singular or a group using [number] without [letter], such as switch 228. In addition, the same reference numerals or other reference designators are used in the drawings to designate structurally and / or functionally related features.

[0023] Figure 1A 1 is a functional block diagram of an example system 100 including an ADC 104 having a CTDSM 112 controlled by an instability recovery circuit 114. The system 100 also includes an analog input 102, a digital signal processing circuit 106, a DAC 108, and an analog output 110. In some examples, the analog input 102 is or includes an audio device, such as a microphone or a memory circuit, or a temperature, pressure, force, voltage, current, or other sensor, having an analog output that provides an input signal to the ADC 104. The ADC 104 includes a clock 115 that provides a clock signal. In some examples, the digital signal processing block 106 includes a processor circuit, such as a central processing unit (CPU), a digital signal processor (DSP), or a microcontroller unit (MCU). In some examples, the analog input 102 or the analog output 110 includes an amplifier, such as a Class D amplifier.

[0024] In some examples, CTDSM 112 and instability recovery circuit 114 are fabricated on an integrated circuit (IC). In some examples, ADC 104 is fabricated on an IC. In some examples, the IC also includes digital signal processing circuit 106 and / or DAC 108.

[0025] The CTDSM 112 enables an analog signal to be sampled at a first frequency and converted to a relatively high resolution digital signal at a second frequency lower than the first frequency. This process uses a relatively low precision ADC that enables operation as a relatively high precision ADC, using a combination of oversampling and noise shaping to move quantization noise out of the signal frequency band, such as the bandwidth of the CTDSM 112, into higher frequencies. The higher frequency noise can be filtered, leaving a signal with an improved signal-to-noise ratio (SNR), and therefore with improved resolution.

[0026] In some examples, the design gain of the CTDSM 112, determined by the signal transfer function (STF) of the CTDSM 112, is a constant, such as one. In some examples, the ADC converts an analog signal into a digital signal representing the same information (such as frequency and amplitude). In some examples, certain types of input signals, such as step inputs, can cause instability in the output signal of the CTDSM 112. A step input is a relatively large change in input amplitude in a relatively short period of time, or can be expressed as a large change in input amplitude at a high frequency. In some examples, the meaning of a relatively large change is in response to the duration of the change in input signal amplitude. At a high enough frequency, or equivalently, at a short enough time, the step input that can cause instability in the output signal of the CTDSM 112 can be very small compared to the MSA of the CTDSM 112.

[0027] In some examples, the instability of the output signal of the CTDSM 112 corresponds to saturation of the CTDSM 112. Saturation corresponds to a relatively large transient overshoot in the output signal of the CTDSM 112. Therefore, the instability of the output signal of the CTDSM 112 can correspond to the output signal of the CTDSM 112 deviating from the designed gain of the CTDSM 112. In some examples, the transfer function of the CTDSM 112 results in a higher gain at a higher frequency. The instability recovery circuit 114 controls the CTDSM 112 to reliably recover from an unstable state such as saturation to return to accurate, stable function. Figure 1B The CTDSM 112 is further described in and subsequent figures.

[0028] Figure 1B yes Figure 1A1 is a functional block diagram of an example of an ADC 104. The ADC 104 includes a low-pass analog filter 116, an oversampling circuit 118, a CTDSM 112, an instability recovery circuit 114, and a low-pass digital filter 120. The CTDSM 112 includes a delta (△) block 122, a sigma (Σ) block 124, a sampling quantizer 126, and a feedback DAC 128. In some examples, the sampling quantizer 126 is implemented using a relatively low-resolution ADC, such as a 1-bit DAC, a 5-bit DAC, or a 6-bit DAC.

[0029] The output of the low-pass analog filter 116 is connected to the input of the oversampling circuit 118. The output of the oversampling circuit 118 is connected to the non-inverting input of the delta block 122. The output of the delta block 122 is connected to the input of the sigma block 124. The output of the sigma block 124 is connected to the input of the sampling quantizer 126. The output of the sampling quantizer 126 is connected to the input of the low-pass digital filter 120 and the input of the feedback DAC 128. The output of the feedback DAC 128 is connected to the inverting input of the delta block 122. The CTDSM 112 is communicatively connected to the instability recovery circuit 114. The output of the low-pass digital filter 120 provides the digital output signal (OUT) of the ADC 104. Thus, the CTDSM 112 performs analog-to-digital delta-sigma modulation on the filtered, oversampled analog signal provided by the oversampling circuit 118.

[0030] Feedback DAC 128 provides negative feedback. Delta block 122 provides a differential output signal in response to the negative feedback to continuously correct the quantization error and move the quantization noise to a frequency significantly higher than the bandwidth of the signal received from oversampling circuit 118. Thus, the quantization noise is moved to a sufficiently high frequency for low-pass digital filter 120 to filter out the corresponding high frequency noise. In some examples, delta block 122 encodes information about changes in the input signal.

[0031] In some examples, sigma block 124 accumulates the output signal of delta block 122 such that the difference between the in-phase and inverting inputs of delta block 122 is integrated. Thus, the accumulation is responsive to the difference between the input signal based on analog input 102 and the output signal of sampling quantizer 126. In some examples, sigma block 124 encodes information about the amplitude of the input signal into the signal provided to sampling quantizer 126.

[0032] The low pass digital filter 120 demodulates the output signal of the sampling quantizer 126 to provide a relatively high bit resolution digital output signal at a sampling frequency lower than the sampling frequency of the oversampling circuit 118. An example sampling frequency of the oversampling circuit 118 is 64 times the sampling frequency of the sampling quantizer 126. An example sampling frequency of the sampling quantizer 126 is 3 megahertz (MHz). The increase in the bit resolution of the output signal of the low pass digital filter 120 relative to the output signal of the sampling quantizer 126 is related in magnitude to the decrease in the sampling frequency from the output signal of the oversampling circuit 118 to the output signal of the sampling quantizer 126. In some examples, the effect of the low pass digital filter 120 includes time averaging, which enables high precision of the output amplitude.

[0033] Thus, oversampling by oversampling circuit 118, followed by decimation by low-pass digital filter 120, enables benefits that may include one or more of the following: higher temporal accuracy, use of a higher linearity ADC as sampling quantizer 126, noise shaping by moving noise to higher frequencies that can be filtered by low-pass digital filter 120, and / or reduced steepness requirements for the analog low-pass anti-aliasing filter. Note that in some examples, a relatively lower bit resolution ADC is more linear than a relatively higher bit resolution ADC.

[0034] In some examples, the bandwidth of the input signal to ADC 104 corresponds to an audio bandwidth, such as 20 Hz to 20 kHz. Thus, an example cutoff frequency of low-pass analog filter 116 is 20 kHz, and an example cutoff frequency of low-pass digital filter 120 is also 20 kHz.

[0035] In some examples, an oversampling ADC, such as ADC 104, uses a relatively high sampling rate compared to the Nyquist rate (or Nyquist frequency). The Nyquist rate of a signal is twice the bandwidth of the signal. The CTDSM 112 can be used to spread the quantization noise over the bandwidth in response to the sampling rate of the ADC while retaining the signal content within the selected bandwidth. This enables the CTDSM 112 to use a relatively low-bit ADC in the sampling quantizer 126 to provide a relatively high output signal resolution. The CTDSM 112 enables such high output signal resolution by sampling the input signal at a high sampling rate compared to the Nyquist rate and spreading the quantization noise of the sampling quantizer 126 over a relatively wide frequency range compared to the bandwidth of the input signal. The quantization noise outside the selected bandwidth can be filtered, thereby reducing the noise and thus improving the signal-to-quantization noise ratio (SQNR). In some examples, multiplying the sampling rate of the oversampling circuit 118 by four increases the SQNR by six decibels (dB), which corresponds to an increase in the resolution of the ADC 104 by one bit. Noise shaping performed by the CTDSM 112 provides additional resolution improvements, as described further below.

[0036] Figure 2A yes Figure 1A and 1B 1 and 14. In some examples, in the first operating state 200, all functional blocks of the CTDSM 112 are active. In some other operating states, such as reference Figures 3 to 5 Further described, certain functional blocks of CTDSM 112 are rendered inactive or at least partially inactive by instability recovery circuit 114 to increase stability of CTDSM 112 and / or provide a recovery path to facilitate stable initial operation when returning to full nominal functionality.

[0037] The CTDSM 112 includes a first integrator (integrator 1) 202, a second integrator (integrator 2) 204, a third integrator (integrator 3) 206, a first weighted adder (weighted sum 1) 208, a fourth integrator (integrator 4) 210, a second weighted adder (weighted sum 2) 212, a quantizer 214, a main finite impulse response (FIR) filter 216, a main DAC 218, a synchronization / recovery DAC 220, a compensation FIR filter 222, a compensation DAC 224, a first resistor 226a and a second resistor 226b, a recovery switch 227, and a first switch 228a, a second switch 228b, and a third switch 228c. The instability recovery circuit 114 includes a first instability detector (instability detector 1) 230, a second instability detector (instability detector 2) 232, and a recovery circuit 233. In some examples, the first and second instability detectors 230 and 232 are comparators. In some examples, quantizer 214 corresponds to Figure 1B In some examples, the instability recovery circuit 114 or the recovery circuit 233 may be described as a control circuit of the CTDSM 112.

[0038] The sync / recovery DAC 220 is so named because it is used to compensate for loop delays, thereby performing synchronization, and as part of the process of recovering from instabilities of the CTDSM 112. These functions of the sync / recovery DAC 220 are further described below.

[0039] The recovery circuit 233 includes a memory 234. In some examples, the memory 234 stores one or more instructions executed by the recovery circuit 233, the instability detector 230 and 232 threshold levels, timing values, weight coefficients of the weighted adders 208 and 212, or other parameters used by the recovery circuit 233 to control the operation of the CTDSM 112. In some examples, the timing values ​​correspond to the timing of transitions between operating states, such as the first, second, and third operating states 200, 300, and 400 (see Figures 2 to 5). In some examples, the timing values ​​correspond to the timing for changing other functions of the CTDSM 112, such as by releasing a reset signal of the latch 242 (see Figure 2C ).

[0040] The first input terminal 236a receives a positive input signal INP, and the second input terminal 236b receives a negative input signal INM. For example, INP and INM are positive and negative components of a differential input signal. In some examples, INP and INM are provided by a signal sampling circuit of the ADC 104, such as an oversampling circuit 118. The signal sampling circuit is used to oversample analog input signals, such as an input signal received from the analog input 102, in some examples, via a filter such as a low-pass analog filter 116.

[0041] The first input terminal 236a is connected to a first terminal of the first resistor 226a and a first input of the first weighted adder 208. The second input terminal 236b is connected to a first terminal of the second resistor 226b and a second input of the first weighted adder 208. The second terminal of the first resistor 226a is connected to a first terminal of the restore switching device 227, a first input of the first integrator 202, and a first output of the main DAC 218. The second terminal of the second resistor 226b is connected to a second terminal of the restore switching device 227, a second input of the first integrator 202, and a second output of the main DAC 218.

[0042] The output of the first integrator 202 is connected to the input of the second integrator 204, the third input of the first weighted adder 208, and the first input of the first instability detector 230. The output of the second integrator 204 is connected to the input of the third integrator 206 and the fourth input of the first weighted adder 208. The output of the third integrator 206 is connected to the fifth input of the first weighted adder 208.

[0043] The virtual grounds of the first, second and third integrators 202, 204 and 206 can be connected via the outputs of the corresponding integrators 202, 204 and 206 according to the switching state of the corresponding switching device 228. The virtual ground of the first integrator 202 is connected to the first terminal of the first switching device 228a, the virtual ground of the second integrator 204 is connected to the first terminal of the second switching device 228b, and the virtual ground of the third integrator 206 is connected to the first terminal of the third switching device 228c. The second terminal of each switching device 228 is connected to a node that receives a RESET signal. Therefore, closing any one of the switching devices 228 places the corresponding integrator 202, 204 or 206 corresponding to the closed switching device 228a, 228b or 228c in a reset state. In the reset state, a zero signal, such as a zero voltage and / or a zero current signal, is provided at the output of the corresponding integrator 202, 204 or 206. A zero signal corresponds to a signal that does not affect the accumulated sum of integrators 202, 204, or 206 or the output signal of weighted adders 208 or 212. In some examples, switching device 228 is a transistor, and the connection from recovery circuit 233 to switching device 228 corresponds to a connection to a corresponding gate or other control terminal of switching device 228.

[0044] Alternatively, the outputs and corresponding inputs of the first, second, and third integrators 202, 204, and 206 are differential outputs and inputs, and the input of the first weighted adder 208 is a differential input. A first terminal of the first switching device 228a is connected to the first differential output of the first integrator 202 and the first differential input of the second integrator 202, and a second terminal of the first switching device 228a is connected to the second differential output of the first integrator 202 and the second differential input of the second integrator 204. A first terminal of the second switching device 228b is connected to the first differential output of the second integrator 204 and the first differential input of the third integrator 206, and a second terminal of the second switching device 228b is connected to the second differential output of the second integrator 204 and the second differential input of the third integrator 206. And the first terminal of the third switching device 228c is connected to the first differential output of the third integrator 206 and the first differential input of the first weighted adder 208, and the second terminal of the third switching device 228c is connected to the third differential output of the first integrator 206 and the second differential input of the first weighted adder 208. Therefore (as described above), closing any one of the switching devices 228 will place the corresponding integrator 202, 204 or 206 corresponding to the closed switching device 228a, 228b or 228c into a reset state, wherein a zero signal is provided at the output of the corresponding integrator 202, 204 or 206.

[0045] The output of the first weighted adder 208 is connected to the input of the fourth integrator 210. The output of the fourth integrator 210 is connected to the first input of the second weighted adder 212 and the first input of the second instability detector 232. The output of the second weighted adder 212 is connected to the input of the quantizer 214. The output of the quantizer 214 is connected to the input of the main FIR filter 216, the input of the synchronization / recovery DAC 220, the input of the compensation FIR filter 222 and the first input of the recovery circuit 233.

[0046] The output of the main FIR filter 216 is connected to the input of the main DAC 218. The output of the compensation FIR filter 222 is connected to the input of the compensation DAC 224. The output of the compensation DAC 224 is connected to the second input of the second weighted adder 212. The output of the sync / recovery DAC 220 is connected to the sixth input of the first weighted adder 208.

[0047] The output of the first instability detector 230 is connected to the second input of the recovery circuit 233, and the output of the second instability detector 232 is connected to the third input of the recovery circuit 233. The first output of the recovery circuit 233 is connected to the second input of the first instability detector 230, and the second output of the recovery circuit 233 is connected to the second input of the second instability detector 232.

[0048] The third output of the restoration circuit 233 corresponds to the output of the instability restoration circuit 114. The third output of the restoration circuit 233 is connected to the control input of the CTDSM 112. In some examples, the third output of the restoration circuit 233 is a bus of multiple line widths, and the control input of the CTDSM 112 thus corresponds to the multiple input lines. In some examples, the control input of the CTDSM 112 is connected to the control terminals or control inputs of the restoration switching device 227, the first switching device 228a, the second switching device 228b, the third switching device 228c, the first weighted adder 208, the second weighted adder 212, the synchronization / recovery DAC 220, the compensation FIR filter 222, and the compensation DAC 224. For clarity, these connections from the control input of the CTDSM 112 to the control terminals or control inputs of the components of the CTDSM 112 are shown in FIG. Figure 2B In Figure 2A During operation in the first operating state 200, the restoration circuit 233 controls the restoration switching device 227 and each switching device 228 to be open (non-conductive).

[0049] The connection of the input of the first integrator to the resistor 226 and the output of the main DAC 218 acts as the delta block 122 for the CTDSM 112, as shown in FIG. Figure 2AAs shown. The first and second resistors 226 convert the signal received by the input terminal 236 into a corresponding current. In some examples, the output of the main DAC 218 is a differential output, which sinks a corresponding current according to the output signal of the main FIR filter 216, which depends on the output signal of the quantizer 214. Therefore, the current received by the corresponding input of the first integrator 202 is responsive to the difference between the current provided by the resistor 226 and the current provided (sunk) by the main DAC 218. This enables the first integrator 202 to handle quantization errors, which are the difference between the input signal and the feedback signal (and therefore, the input signal of the first integrator 202) (or are related to the difference).

[0050] Reference Figure 2A Some components described in the first operating state 200 are functionally and / or structurally similar to those described in reference Figure 1B 1. In some examples, in the first operating state 200 of the CTDSM 112 and the instability recovery circuit 114 of FIG. 1, the connections between the first and second outputs of the main DAC 218 and the first and second inputs of the first integrator 202, respectively, correspond to the delta block 122. The first, second, and third integrators 202, 204, and 206, the first weighted adder 208, the fourth integrator 210, and the second weighted adder 212 correspond to the sigma block 124. The quantizer 214 corresponds to the sampling quantizer 126. And, the feedback DAC 128 corresponds to the main FIR filter 216 with the main DAC 218.

[0051] During operation in the first operating state 200, the sync / recovery DAC 220 is used to compensate for loop delays introduced by the first, second, and third integrators 202, 204, and 206, such as loop delays associated with resistor-capacitor (RC) circuitry within the first, second, and third integrators 202, 204, and 206. Similarly, during operation in the first operating state 200, the compensation FIR filter 222 and the compensation DAC 224 are used to compensate for loop delays introduced by the fourth integrator 210, such as loop delays associated with resistor-capacitor (RC) circuitry within the fourth integrator 210. Thus, the sync / recovery DAC 220, the compensation FIR filter 222, and the compensation DAC 224 are used to achieve a designed noise transfer function (NTF) of the CTDSM 112.

[0052] In some examples, the accuracy or bit resolution of the ADC is proportional to the error or noise in the ADC output signal. In some examples, the bit resolution of the ADC is proportional to the SNR expressed in dB. In one example, a six-bit ADC has a 36dB SNR, and a 16-bit ADC has a 96dB SNR.

[0053] As described above, the quantizer 214 is or includes an ADC. The noise in the output signal of the quantizer 214 is quantization noise. In some examples, the quantization noise is a type of white noise. White noise, also known as flat noise, is a type of noise that has no preferred frequency. Such noise includes low-frequency components and can be described as not changing over time. Constant noise can be described as an offset applied to the output signal of the quantizer 214. The feedback DAC 128, the delta block 122, and the sigma block 124 together determine the input signal of the control sampling quantizer 126 to produce an output signal component (reverse offset) equal to the reverse (negative) of the offset. For example, if the offset is equal to one, then ideally, the reverse offset is equal to negative 1. Therefore, the reverse offset can be determined to adjust the input signal of the quantizer 214 so as to reduce or eliminate the low-frequency noise in the output signal of the quantizer 214.

[0054] Therefore, the noise is reduced by the loop filter (the feedback loop of the CTDSM 112) and the low-pass digital filter 120 that removes the high-frequency signal components. This improves the SNR, which enables the low-pass digital filter 120 to further increase the resolution of the ADC 104 by (or at the same time) reducing the sampling rate of the final output signal of the ADC 104. The quantization noise can be described as an additional noise source added to the output signal of the CTDSM 112. The additional noise source of the output transfer function that is inversely related to the NTF of the CTDSM 112 can be used to describe the noise within the signal band of the CTDSM 112 as being reduced by the total gain of the integrator (202, 204, 206 and 210, corresponding to the sigma block 124). The reduced noise amplitude is transferred to higher frequencies (frequencies outside the signal band). This can be called noise shaping. In one example, the sampling rate of the oversampling circuit 118 is 64 samples per second, the sigma block 124 includes four integrators, and the resolution of the ADC of the quantizer 214 is six bits, and the output signal sampling rate of the ADC 104 is one sample per second, and the resolution of the ADC 104 is sixteen bits.

[0055] Integrators 202, 204, 206, 210 are referred to as integrators because they maintain the current sum of the input signal. Integrators 202, 204, 206, 210 can be described as gain blocks, providing high limited gain at low frequencies. In one example, integrators 202, 204, 206, 210 can be implemented as analog components, such as capacitors. In another example, integrators 202, 204, 206, 210 can be implemented as digital components, such as adders with a memory for storing the current sum. The contribution of the output signals of integrators 202, 204, 206 and 210, synchronization / recovery DAC 220, compensation FIR filter 222 and compensation DAC 224 to the input signal of quantizer 214 is balanced by the corresponding weighted adders, so the first and second weighted adders 208 and 212.

[0056] Closing the restore switch 227 causes a zero signal or a null signal to be provided to the first integrator 202. In some examples, providing the null signal to the first integrator 202 (in response to the restore switch 227 being closed), the second integrator 204 (in response to the first switch 228a being closed), or the third integrator 206 (in response to the second switch 228b being closed) controls the corresponding integrator 202, 204, or 206 receiving the null signal to reset the current and current maintained by the corresponding integrator 202, 204, or 206.

[0057] The number of integrators in the modulator corresponds to the order of the modulator. Therefore, in the first operating state 200, the CTDSM112 operates as a fourth-order modulator. The more integrators there are in the modulator, the greater the gain available to the modulator. In some examples, the integrator has a high gain at low frequencies and a low gain at high frequencies, so that the signal receives more gain than the quantization noise. Therefore, by moving the quantization noise outside the selected bandwidth (signal frequency band), a more number of integrators can be used to enable more effective noise shaping, so that the low-pass digital filter 120 can filter a larger proportion of the quantization noise. In some examples, this can improve the resolution, exceeding the resolution that can be achieved by oversampling without using an integrator for noise shaping. Therefore, noise shaping using both integrators and oversampling enables improved SNR, and therefore enables a higher resolution ADC 104 output signal for the same sampling rate of the oversampling circuit 118. In some examples, the increase in the number of integrators corresponds to an increase in the delay from the signal received at the input terminal 236 to the output signal of the quantizer 214, which may reduce the stability of the CTDSM112.

[0058] The main FIR filter 216 reduces the clock jitter sensitivity, improves the linearity of the signal response of the main DAC 218, reduces the error in the feedback path, and filters out high-frequency signal components. The clock 115 is used, for example, to sample the input signal in the oversampling circuit 118, provide the output signal of the sigma block 124 at a first clock signal edge (e.g., rising edge) within the clock signal cycle, and use the sampling quantizer 126 to sample the output signal of the sigma block 124 at a second clock edge (e.g., falling edge) within the clock signal cycle. In some examples, the class D amplifier as a switching amplifier generates high-frequency noise at a specific modulator frequency. In some examples, the class D amplifier is used for audio-related applications.

[0059] FIR filters, such as main FIR filter 216 or compensating FIR filter 222, can be described by multiple taps, corresponding to multiple samples to which the FIR filter output signal responds. Taps can also be described as zeros in the FIR filter STR. In some examples, increasing the number of taps of the FIR filter improves the linearity and noise filtering effect of the FIR filter, but may also increase the delay and amplitude of the FIR filter output signal, reducing the overall stability of the modulator. In some examples, the main FIR filter 216 and the compensating FIR filter 222 are low-pass digital filters.

[0060] In some examples, such as at high input signal frequencies, the delay and amplitude increase of the main FIR filter output signal may cause the STR of the main FIR filter 216 to peak. In response, the CTDSM 112 may become unstable and / or have a non-unity gain. As the number of taps in the FIR filters of the CTDSM 112 (such as the main FIR filter 216 and the compensation FIR filter 222) increases, the CTDSM 112 may be more susceptible to these effects. In some examples, in response to a step input or an input signal that exceeds the design MSA of the CTDSM 112, the CTDSM 112 becomes unstable.

[0061] In some examples, the instability of CTDSM 112 corresponds to saturation of CTDSM 112. In the saturated state, main DAC 218 oscillates between providing a voltage signal at a maximum level (such as a level corresponding to a power supply voltage or other high reference voltage) and providing a voltage signal at a minimum level (such as a level corresponding to a ground voltage or other low reference voltage).

[0062] The first and second instability detectors 230 and 232 are used to detect instability in the CTDSM 112. The recovery circuit 233 provides threshold voltages to respective second inputs of the first and second instability detectors 230 and 232. In the first operating state 200, the first threshold voltage is provided to the first instability detector 230 and the second threshold voltage is provided to the second instability detector 232.

[0063] The first instability detector 230 compares the output signal of the first integrator 202 with a first threshold voltage, and the second instability detector 232 compares the output signal of the fourth integrator 210 with a second threshold voltage. Thus, the first instability detector 230 responds to high frequency changes in the input voltage, such as a step input, which may have a lower amplitude than the MSA of the CTDSM 112. The second instability detector 232 responds to high amplitude changes in the input signal, such as a lower frequency change of the input voltage to a voltage close to or greater than the MSA of the CTDSM 112. As described above, in some examples, at a sufficiently high frequency of changes in the input signal level, a step input that is much smaller than the MSA of the CTDSM 112 may control the signal level of the output signal of the first integrator 202 to exceed the first threshold.

[0064] If the output signal of the first integrator 202 is greater than the first threshold voltage, or the output signal of the fourth integrator 210 is greater than the second threshold voltage, the recovery circuit 233 controls the CTDSM 112 to transition to the second operating state 300. Figure 3 The second operating state 300 is depicted. Thus, as detected by the first or second instability detector 230 or 232 (respectively), exceeding the first threshold or second threshold voltage indicates a saturation state or other unstable state of the CTDSM 112. Operation in the second operating state 300 enables the CTDSM 112 to recover from the unstable state. Once the CTDSM 112 has recovered from the unstable state, the recovery circuit 233 controls the CTDSM 112 to return to the first operating state 200 directly or via the third operating state 400. Referring to Figure 4 A third operating state 400 is depicted.

[0065] In some examples, the first threshold voltage and the second threshold voltage each correspond to two voltages, and thus, a differential voltage. In one example, the first threshold voltage is V DD Minus 200 mV and V SS plus 200 mV, and the second threshold voltage is V DD Minus 200 mV and V SS Add 200 mV.

[0066] Figure 2B is from the recovery circuit 233 to Figure 2A 1. Functional block and circuit diagram of examples of control connections for various components of the CTDSM 112 of the present invention. The control output of the recovery circuit 233 is connected via bus 235 to a control terminal of the recovery switching device 227, a control terminal of the first switching device 228a, a control terminal of the second switching device 228b, a control terminal of the third switching device 228c, a control input of the first weighted adder 208, a control input of the second weighted adder 212, a control input of the sync / recovery DAC 220, a control input of the compensation FIR filter 222, and a control input of the compensation DAC 224. In some examples, the recovery circuit 233 controls additional, or different components than those described herein. In some examples, the recovery circuit 233 controls additional, or different component functions than those described herein.

[0067] The restore circuit 233 controls whether the restore switching device 227 is open or closed, and whether each switching device 228 is open or closed. In some examples, one of the closed switching devices 228 controls the RESET signal to be provided to the corresponding control input of the first, second or third integrator 202, 204 or 206. The corresponding virtual ground of the first, second or third integrator 202, 204 or 206 thus receives a signal that controls the output of the first, second or third integrator 202, 204 or 206 to provide a zero voltage signal or other null signal. As described above, in some examples, the restore circuit 233 controls different mechanisms to control the selected integrators of the first, second and third integrators 202, 204 and 206 to selectively provide null signals or normal operation signals.

[0068] The restoration circuit 233 also controls the compensation FIR filter 222 and the compensation DAC 224 to selectively disconnect them from the CTDSM 112 loop, or in some examples, to provide a null signal. In subsequent figures, the functional blocks controlled by the restoration circuit 233 to provide the null signal are indicated by dashed boxes. The corresponding communication lines carrying the null signal are indicated by dashed lines.

[0069] The restoration circuit 233 controls the weights used by the first weighted adder 208 to determine an output signal responsive to the signals provided by the input terminal 236, the first, second and third integrators 202, 204 and 206, and the synchronization / recovery DAC 220. The restoration circuit 233 controls the weights used by the second weighted adder 212 to determine an output signal responsive to the signals provided by the fourth integrator 214 and the compensation DAC 224. Note that the output signal of the fourth integrator 214 is responsive to the output signal of the first weighted adder 208.

[0070] Figure 2C yes Figure 1A and 1B1 and 14. Figure 2C In the example of , the instability recovery circuit includes a latch 242. The output of the first instability detector 230 is connected to the first data input of the latch 242, and the output of the second instability detector 232 is connected to the second data input of the latch 242. The data output of the latch 242 is connected to the input of the recovery circuit 233. The reset output of the recovery circuit 233 is connected to the reset input of the latch 242.

[0071] In response to the first or second instability detector 230 or 232 detecting an unstable state, the latch 242 stores a logic one. The latch 242 communicates this logic one to the recovery circuit 233. In response, the recovery circuit 233 controls the CTDSM 112 to transition to the second operating state 300. The recovery circuit 233 controls the CTDSM 112 to remain in the second operating state 300 until the recovery circuit 233 determines in response to the quantizer 214 output signal that the CTDSM 112 has returned from saturation to a normal operating range.

[0072] In response to detecting the normal operating range, the recovery circuit 233 applies and maintains (continues to apply) a reset signal at the reset output to the latch 242. This controls the latch 242 to reset to store a logic zero, and forces the latch 242 to continue to store a logic zero. Therefore, the instability detectors 230 and 232 cannot communicate the detected unstable state to the recovery circuit 233 until the recovery circuit 233 releases (stops sending) the reset signal.

[0073] The restore circuit 233 continues to maintain the reset signal to the reset output of the latch 242 until the CTDSM 112 returns to normal operation in the first operating state 200 and a predetermined amount of time has passed. In some examples, conditions other than the passage of time are used to determine the release of the reset signal. The restore circuit 233 then releases the reset signal at the reset output of the latch 242, which enables the first and second instability detectors 230 and 232 to return to detecting saturation or other unstable states.

[0074] Figure 3 yes Figure 1A and 1B1 and 14. The functional blocks and circuit diagram of an example of a second operating state 300 of the CTDSM 112 and the instability recovery circuit 114 of FIG. 1 is a block diagram of an example of a second operating state 300 of the CTDSM 112 and the instability recovery circuit 114. In the second operating state 300, the recovery circuit 233 controls the first, second and third switching devices 228 to close, thereby controlling the first, second and third integrators 202, 204 and 206 to provide corresponding null signals. This allows the output signal of the fourth integrator 210 to determine the input signal of the quantizer 214. Therefore, in the second operating state 300, the CTDSM 112 operates as a first-order modulator. In some examples, in a first-order system, the output signal closely follows the input signal, making the first-order system inherently stable.

[0075] In response to the first integrator 202 providing a null signal, the main FIR filter 216 and the main DAC 218 have no effect on the output signal of the quantizer 214. This is because the signal path of the output of the main DAC 218 goes to the first integrator 202, which, as described above, is limited to providing a null output signal when the CTDSM 112 is in the second operating state 300.

[0076] In the second operating state 300, the sync / recovery DAC 220 performs functions similar in some respects to the feedback DAC 128 (in some examples, performs the functions of the feedback DAC 128), and the first weighted adder 208 acts as the delta block 122. The recovery circuit 233 adjusts the weights in the first weighted adder 208 and / or activates a return-to-zero mode (described below) of the sync / recovery DAC 220 to enable this functionality. Thus, in the second operating state 300, the output signal of the first weighted adder 208 is responsive to the (non-null) signal provided by the input terminal 236 and the sync / recovery DAC 220. In some examples, the sync / recovery DAC 220 provides a negative feedback loop for the CTDSM 112 at a high sampling rate. Thus, during operation in the second operating state 300, the sampling rate of the oversampling circuit 118 is not reduced.

[0077] In the second operating state 300, the fourth integrator 210 and the second weighted adder 212 act as the sigma block 124. The restoration circuit 233 adjusts the weights in the second weighted adder 212 to enable this functionality.

[0078] In some examples, the sync / recovery DAC 220 operates in a non-return-to-zero (NRZ) mode in the first operating state 200 and in a return-to-zero (RZ) mode in the second operating state 300. In the NRZ mode, the sync / recovery DAC 220 transitions from an output signal corresponding to an old input signal received by the sync / recovery DAC 220 to an output signal corresponding to a new input signal received by the sync / recovery DAC 220 on a corresponding clock edge, such as a rising or falling clock edge, without returning to a zero signal between the old and new output signals.

[0079] In the RZ mode, the sync / recovery DAC 220 provides an output signal corresponding to the input signal of the sync / recovery DAC 220 within half of each clock cycle, such as after a rising clock edge, and returns to providing a zero signal within half of each clock cycle, such as after a falling clock edge. The RZ mode increases the predictability of the output signal of the sync / recovery DAC 220 as viewed through the input of the quantizer 214 and reduces the weight of the output signal of the sync / recovery DAC 220 by half. The RZ mode increases predictability because the sync / recovery DAC 220 has a known output signal within half of each clock cycle. In addition, switching to the RZ mode provides a convenient method for re-tuning the loop coefficients corresponding to the sync / recovery DAC 220 so that during operation in the second operating state 300, the designed NTF can be achieved with the designed resolution and accuracy.

[0080] As described above, in order to increase the stability of the CTDSM 112 when operating in the second operating state 300, the restoration circuit 233 controls the compensation FIR filter 222 and the compensation DAC 224 to provide a null signal. Therefore, in the second operating state 300, the compensation FIR filter 222 does not affect the input signal of the quantizer 214. In addition, as described above, because the first integrator 202 provides a null output signal, the main FIR filter 216 does not affect the input of the quantizer 214. This also increases the stability of the CTDSM 112.

[0081] In the second operating state 300, the input signal to the main FIR filter 216 continues to be updated by the output signal of the quantizer 214. Updating the input signal to the main FIR filter 216 updates the internal multi-sample filter components of the main FIR filter 216. Thus, using the sync / recovery DAC 220 and the first weighted adder 208 to provide a shortened loop filter for the CTDSM 112 avoids instabilities associated with the output signal of the main FIR filter 216 without bypassing or suppressing the input to the main FIR filter 216.

[0082] Because the first integrator 202 receives a null signal corresponding to the closure of the restore switch 227 and provides a null signal corresponding to the closure of the first switch 228a, the effect of the update on stability is avoided. The closure of the restore switch 227 also enables the signal path ending with the main FIR filter 216 and the main DAC 218 to act as a closed loop, so that the main FIR filter 216 and the main DAC 218 can be updated without interference from the differential input signal shorted by the restore switch 227. This enables the main FIR filter 216 to continue to be updated when the CTDSM 112 is in the second operating state 300.

[0083] The closed short-circuited switching devices, switching devices 227 and 228a, also enable the main FIR filter 216 and the main DAC 218 to accurately determine the output signal. The accurate determination of the output signal enables initialization of the main FIR filter 216 and the main DAC 218 to provide accurate feedback when returning to nominal operation (the first operating state 200). Accurate feedback promotes stable operation. In addition, the closure of the switching devices 227 and 228a keeps the main FIR filter 216 and the main DAC 218 outside the CTDSM 112 feedback loop so that they do not erroneously affect the operation in the second operating state 300. In some examples, in response to the accurate continued updating of the main FIR filter 216 and the main DAC 218, the second operating state 300 is referred to as a signal estimation mode.

[0084] The main FIR filter 216 and main DAC 218 may remain outside the CTDSM 112 feedback loop because the sync / recovery DAC 220 provides a negative feedback loop to enable the CTDSM 112 to continue operating during the second operating state 300. The negative feedback loop via the sync / recovery DAC 220 enables shaping of the quantization noise by moving the quantization noise out of the signal band to higher frequencies, such as frequencies outside the range allowed by the low-pass digital filter 120. As described above, oversampling enables further improvement in accuracy.

[0085] As described above, during operation in the second operating state 300, continued updating of the main FIR filter 216 enables the CTDSM 112 to continue to operate stably while the modulator recovers from operating as a first-order modulator in the second operating state 300 to operating as a fourth-order modulator in the first operating state 200. This avoids a period of instability that could result if the inputs to the main FIR filter 216 and / or the main DAC 218 were bypassed during recovery and the bypassing ended after the CTDSM 112 returned to normal operation.

[0086] Recall that the first instability detector 230 receives a null input signal because the first integrator 202 provides a null output signal during operation in the second operating state 300. In some examples, the CTDSM 112 exits the second operating state 300 after the voltage of the output signal of the fourth integrator 210 is less than the second threshold voltage, indicating that the CTDSM 112 has recovered from a saturation or other unstable state. In some examples, such as with reference to Figure 2C Instability recovery circuit 114, when latch 242 is set and when latch 242 reset signal is applied, recovery circuit 233 ignores second instability detector 232. In some examples, this corresponds to Figure 2C In some examples, the recovery circuit 233 ignores the detection of the saturation condition by the first instability detector 230 and / or the second instability detector 232 until a predetermined time after returning to the first operating state 200. In examples where the recovery circuit 233 ignores the second instability detector 232, the recovery circuit 233 determines when the output signal of the quantizer 214 returns to a normal operating range, indicating that the saturation or other unstable condition has ended. The recovery circuit 233 controls the CTDSM 112 to exit the second operating state 300 in response to the detected end of the saturation or other unstable condition.

[0087] In some examples, the recovery circuit 233 does not perform comparisons to determine the end of a saturation or other unstable condition until a selected amount of time has passed after entering the second operating state 300. In some examples, the comparisons of the second instability detector 232 are also or alternatively suspended until a condition is met. In some examples, the amount of time that the comparisons of the recovery circuit 233 and / or the second instability detector 232 are suspended corresponds to a number of clock cycles. In some examples, other or additional criteria are used to determine when to exit the second operating state 300. After transitioning to the second operating state 300, an example amount of time before the recovery circuit 233 begins performing comparisons to determine a return to normal quantizer 214 output signal behavior is 25 microseconds.

[0088] In some examples, the comparison by the recovery circuit 233 to determine whether the CTDSM 112 has returned to stable operation includes comparing the output signal of the quantizer 214 to the maximum and minimum codes of the quantizer 214. In one example, the maximum code is equal to 32 and the minimum code is equal to -32. If the output signal of the quantizer 214 is less than the maximum code and greater than the minimum code, then the recovery circuit 233 checks subsequent clock cycles, such as two or three subsequent clock cycles, to determine whether the absolute value of the output signal decreases, and therefore, recovers. If so, then the recovery circuit 233 controls the CTDSM 112 to transition to the third operating state 400.

[0089] Figure 4 yes Figure 1A and 1B 1 and 14. A functional block diagram and circuit diagram of an example of a third operating state 400 of the CTDSM 112 and the instability recovery circuit 114 of the embodiment of the present invention are shown. The third operating state 400 is an intermediate recovery state between the second operating state 300 and the first operating state 200. The CTDSM 112 transitions from the second operating state 300 to the third operating state 400 to reduce the amount of change in the transition between operating states in the recovery path toward the first operating state 200. Changes between operating states can cause instabilities. Therefore, operation in the third operating state 400 controls and enables the CTDSM 112 to return to high performance normal operation in the first operating state 200, reducing the risk, such as transient overshoot in the OUT signal, and in some examples, very small or no transient overshoot.

[0090] In the third operating state 400, the restoration circuit 233 controls the restoration switching device 227, the first switching device 228a and the second switching device 228b to be opened, thereby controlling the main FIR filter 216, the main DAC 218, the first integrator 202 and the second integrator 204 to operate normally. The restoration circuit 233 also controls the third switching device 228c to be closed, thereby controlling the third integrator 206 to continue to provide a null signal. The output signals of the first, second and fourth integrators 202, 204 and 210 are the input signals of the quantizer 214. Therefore, in the third operating state 400, the CTDSM 112 operates as a third-order modulator. When the CTDSM 112 is in the third operating state 400, the restoration circuit 233 also controls the compensation FIR filter 222 and the compensation DAC 224 to operate normally. In some examples, the normal operation of the compensation FIR filter 222 and the compensation DAC 224 means that they provide or are enabled to provide non-null feedback signals to the second weighted adder 212.

[0091] The third operating state 400 is comparable to the first operating state 200, except that the third integrator 206 continues to be controlled to provide a null signal and the latch 242 remains in a reset state. Therefore, the recovery circuit 233 adjusts the coefficients of the sync / recovery DAC 220, such as by returning the sync / recovery DAC 220 to operation in the NRZ mode. In addition, the recovery circuit 233 adjusts the weights of the first and second weighted adders 208 and 212 to enable stable function with a designed NTF. After a selected (e.g., predetermined) amount of time has passed after the CTDSM 112 has begun operating in the third operating state 400, the CTDSM 112 transitions to operation in the first operating state 200. An example of a selected time between transitioning to the third operating state 400 and transitioning to the first operating state 200 is 75 microseconds.

[0092] In some examples, the ADC 104 suspends providing output signals in response to the CTDSM 112 while the CTDSM 112 is in one or more of the second operating state 300 or the third operating state 400. In some examples, the recovery circuit 233 suspends detecting instabilities in one or more of the second operating state 300 or the third operating state 400, such as discussed above with reference to the latch 242. In some examples, the ADC 104 resumes providing output signals in response to the CTDSM 112 and / or the recovery circuit 233 resumes detecting instabilities after a selected (e.g., predetermined) amount of time has passed after the CTDSM 112 has resumed operation in the first operating state 200. An example amount of time before the ADC 104 resumes providing output signals and / or the recovery circuit 233 resumes detecting instabilities after the CTDSM 112 resumes operating in the first operating state 200 is 50 microseconds.

[0093] Figure 5 is an example flow chart representing a method or process 500 of recovering the CTDSM 112 from an unstable state. In block 502, the recovery circuit 233 controls the CTDSM 112 to operate in the first operating state 200. In block 504, the first instability detector 230 compares the voltage of the output signal of the first integrator 202 to a first threshold voltage, and the second instability detector 232 compares the voltage of the output signal of the fourth integrator 210 to a second threshold voltage. These checks determine whether the CTDSM 112 is in an unstable state, such as saturation.

[0094] If either threshold is exceeded, then in block 506, the recovery engine 233 controls the CTDSM 112 to operate in the second operating state 300 for a first predetermined amount of time and then proceeds to block 508. Otherwise, if neither threshold is exceeded, then return to block 502. In some examples, during operation of the CTDSM 112 in block 504 in the first operating state 200, block 504 is executed on every clock cycle (such as every rising edge of a clock cycle), or is executed at a different frequency.

[0095] In block 508, after the first predetermined amount of time has elapsed, the recovery engine 233 checks whether the voltage of the quantizer 214 output signal has returned to the normal operating range of the CTDSM 112, while continuing to control the CTDSM 112 to operate in the second operating state 300. This check corresponds to determining whether the unstable state has ended. If the voltage of the quantizer 214 output signal indicates that the CTDSM 112 has returned to normal, stable operation, then proceed to block 510. Otherwise, repeat block 508. This repetition can be performed on each clock cycle (such as each rising edge of the clock cycle), or at a different frequency.

[0096] In block 510, the recovery engine 233 controls the CTDSM 112 to operate in the third operating state 400 for a second predetermined amount of time. After the second predetermined time has elapsed, in block 512, the recovery engine 233 controls the CTDSM 112 to operate in the first operating state 200 for a third predetermined amount of time. After the third predetermined amount of time has elapsed, a return is made to block 502 so that the CTDSM 112 can continue to check for saturation conditions in iterations of block 504.

[0097] In some examples, the circuits described herein, such as CTDSM 112 or instability recovery circuit 114 , may be implemented using a processor, such as a CPU, DSP, or MCU.

[0098] In some examples, the processes described herein are implemented using software, hardware, or a combination of software and hardware.

[0099] In some examples, the sigma block includes a number of integrators other than four.

[0100] In some examples, design tools and / or MATLAB or other analysis are used to determine the weights used by weighted adders 208 and 212. In some examples, analysis and simulations are used to iteratively improve modulator design and / or weight assignments.

[0101] In some examples that do not include the main FIR filter 216 (or other FIR filters), the CTDSM 112 becomes unstable in response to a step input or a signal exceeding the MSA of the CTDSM 112. Some example CTDSM designs include other variations of the CTDSM 112 described herein. The systems and processes described herein may also be applied to such variant CTDSM designs.

[0102] In some examples, the differential analog input corresponding to INP and INM provided by input terminal 236 can be described as a first input to first integrator 202. In some examples, the differential output of main DAC 218 can be described as providing a second input to first integrator 202.

[0103] In some examples, instability detectors 230 and 232 remain active during second and / or third operating states 300 and / or 400. In some such examples, the threshold voltage is determined in response to whether CTDSM 112 is in first operating state 200 or a different operating state.

[0104] In some examples, restore circuit 233 may change or select a threshold voltage or other parameter stored in memory 234 , such as in response to an instruction from a user.

[0105] In some examples, recovery circuit 233 controls a clock signal to which the timing of signal processing by sigma block 124 and sampling by sampling quantizer 126 is responsive.

[0106] In some examples, the operating state is referred to as a mode of the CTDSM.

[0107] In some examples, the oversampling ratio is equal to the sampling frequency (f S ) divided by twice the Nyquist frequency. In some examples, the CTDSM 112 provides an SQNR improvement of (6N+3) dB with each doubling of the oversampling rate, where N is the order of the modulator. In some examples, the oversampling rate is about 64 times the Nyquist frequency corresponding to the audio bandwidth, or about 64 times another sampling rate responsive to the audio bandwidth.

[0108] The term "coupled" is used throughout this specification. The term may encompass connections, communications, or signal paths that achieve a functional relationship consistent with the present description. For example, if device A provides a signal to control device B to perform an action, then in the first example, device A is coupled to device B, or in the second example, if the intermediate component C does not substantially change the functional relationship between device A and device B, then device A is coupled to device B through the intermediate component C, such that device B is controlled by device A via the control signal provided by device A.

[0109] In this specification, the term "and / or" (when used in a form such as A, B and / or C) refers to any combination or subset of A, B, C, such as: (a) A alone; (B) B alone; (C) C alone; (d) A and B; (e) A and C; (f) B and C; and (g) A and B and C. Similarly, as used herein, the phrase "at least one of A or B" (or "at least one of A and B") refers to embodiments including any of the following: (a) at least one A; (b) at least one B; and (c) at least one A and at least one B.

[0110] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) by a manufacturer at the time of manufacture to perform the function, and / or may be configurable (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. The configuration may be programmable through the device's firmware and / or software, through the construction and / or layout of the device's hardware components and interconnections, or a combination thereof.

[0111] As used herein, the terms "terminal", "node", "interconnect", "pin", "ball" and "lead" are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to refer to an interconnection or its endpoint between device elements, circuit system elements, integrated circuits, devices or other electronic devices or semiconductor components.

[0112] Circuits or devices described herein that include certain components may instead be adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current sources) may instead include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources at the time of manufacture or after manufacture, such as by an end user and / or a third party, to form the described structure.

[0113] The circuits described herein can be reconfigured to include replaced components, thereby providing functionality that is at least partially similar to the functionality available before the component is replaced. Unless otherwise specified, components shown as resistors generally represent any one or more elements connected in series and / or in parallel to provide the impedance amount represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component can be changed to multiple resistors or capacitors connected in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component can be changed to multiple resistors or capacitors connected in series between the same two nodes as a single resistor or capacitor.

[0114] Although some elements of the described examples may be included in the integrated circuit and other elements are external to the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. Furthermore, some or all features described as external to the integrated circuit may be included in the integrated circuit, and / or some features described as internal to the integrated circuit may be incorporated outside the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that are: (i) incorporated in / on a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated in the same module; and / or (iv) incorporated in / on the same printed circuit board.

[0115] Modifications may be made to the examples described, as well as to other examples, within the scope of the claims.

Claims

1. An integrated circuit (IC), comprising: a first integrator having an analog signal input, a second input, and an output; a first weighted adder having an analog signal input, a second input, a third input, and an output, the analog signal input of the first weighted adder being coupled to the analog signal input of the first integrator and the second input of the first weighted adder being coupled to the output of the first integrator; a second integrator having an input and an output, the input of the second integrator being coupled to the output of the first weighted adder; a second weighted adder having an input and an output, the input of the second weighted adder being coupled to the output of the second integrator; a quantizer having an input and an output, the input of the quantizer being coupled to the output of the second weighted adder; a first digital-to-analog converter (DAC) having an input and an output, the input of the first DAC being coupled to the output of the quantizer and the output of the first DAC being coupled to the second input of the first integrator; as well as A second DAC has an input and an output, the input of the second DAC being coupled to the output of the quantizer and the output of the second DAC being coupled to the third input of the first weighted adder.

2. The IC of claim 1 , further comprising: a first comparator having a first input, a second input and an output, the first input being coupled to the output of the first integrator; a second comparator having a first input, a second input and an output, the first input being coupled to the output of the second integrator; as well as A recovery circuit having a first input, a second input, a first output, and a second output, wherein the first input of the recovery circuit is connected to the output of the first comparator, the second input of the recovery circuit is connected to the output of the second comparator, the first output of the recovery circuit is connected to the second input of the first comparator, and the second output of the recovery circuit is connected to the second input of the second comparator.

3. The IC according to claim 1, wherein the output of the first integrator is a first output, the first integrator has first and second outputs as differential outputs, and the input of the first weighted adder is a first input, the first weighted adder has first and second inputs as differential inputs; The IC also includes a switching device having a first terminal, a second terminal, and a control terminal, the first terminal of the switching device being coupled to the first output of the first integrator, and the second terminal of the switching device being coupled to the second output of the first integrator.

4. The IC of claim 1 , further comprising: a latch having a first input, a second input, a third input, and an output; a first comparator having a first input, a second input, and an output, the first input being coupled to the output of the first integrator, the output being coupled to the first input of the latch; a second comparator having a first input coupled to the output of the second integrator, a second input coupled to the second input of the latch, and an output; as well as A recovery circuit having first and second inputs and first, second and third outputs, the first input of the recovery circuit being coupled to the output of the latch, the second input of the recovery circuit being coupled to the output of the quantizer, the first output of the recovery circuit being coupled to the second input of the first comparator, the second output of the recovery circuit being coupled to the second input of the second comparator, and the third output of the recovery circuit being coupled to the third input of the latch.

5. The IC of claim 4, wherein the restoration circuit is coupled to respective control inputs of the first integrator, the first weighted adder, the second weighted adder, and the second DAC.

6. The IC according to claim 1, wherein the output of the first DAC is a second output, the first DAC has first and second outputs that are differential outputs, the first and second inputs of the first integrator are respective first and second analog signal inputs that are differential inputs, and the first analog signal input of the first DAC is coupled to the first output of the first DAC; The IC also includes a switching device having a first terminal, a second terminal, and a control terminal, the first terminal of the switching device being coupled to the first input of the first integrator and the first output of the first DAC, and the second terminal of the switching device being coupled to the second input of the first integrator and the second output of the first DAC.

7. The IC of claim 1 , further comprising: a third integrator having an input and an output, the input of the third integrator being coupled to the output of the first integrator; as well as A fourth integrator has an input and an output, the input of the fourth integrator being coupled to the output of the third integrator, and the output of the fourth integrator being coupled to the input of the first weighted adder.

8. The IC of claim 1 further comprising a finite impulse response (FIR) filter having an input and an output, the input of the FIR filter being coupled to the output of the quantizer, and the output of the FIR filter being coupled to the input of the first DAC.

9. The IC of claim 1, wherein the second weighted adder has a second input, the IC further comprising: a third DAC having an input and an output, said third DAC being said output coupled to said second input of said second weighted adder; as well as A finite impulse response (FIR) filter has an input and an output, the input of the FIR filter being coupled to the output of the quantizer and the output of the FIR filter being coupled to the input of the third DAC.

10. An integrated circuit (IC), comprising: a delta-sigma modulator (DSM) comprising a digital N integrator, a first digital-to-analog converter (DAC), a second DAC, and a quantizer, wherein N is greater than one; and A control circuit configured to: in a first mode, operating the DSM as an Nth order modulator such that the first DAC is responsive to a first feedback signal provided by an output of the quantizer, and such that the outputs of the N integrators are responsive to the first feedback signal; in a second mode, operating the DSM as a first order modulator such that the second DAC provides a second feedback signal in response to the output of the quantizer, and such that the output of the quantizer is responsive to the output of a single one of the integrators and to the second feedback signal and not to the first feedback signal; as well as The mode is switched from the first mode to the second mode in response to the output of the integrator and a threshold value.

11. The IC according to claim 10, wherein the N integrators are coupled in series from a first integrator having an input coupled to an output of the first DAC to a last integrator having an output coupled to an input of the quantizer; and Wherein the control circuit is configured to switch from the first mode to the second mode in response to at least one of: the output of the first integrator and a first threshold, or the output of the last integrator and a second threshold.

12. The IC according to claim 11, wherein the first threshold corresponds to a high frequency variation of the input voltage; and The second threshold corresponds to a high amplitude level of the input voltage.

13. The IC according to claim 10, It also includes a finite impulse response (FIR) filter; wherein the first DAC provides a feedback signal in response to a filtered signal provided by the FIR filter in response to the output of the quantizer; and Wherein the FIR filter continues to be updated in response to the output of the quantizer, and the output of the quantizer is responsive to the control circuit operating the DSM in the second mode.

14. The IC of claim 13, wherein the control circuit is configured to short together differential outputs of the first DAC in the second mode.

15. The IC according to claim 10, in, In the first mode, the control circuit controls the second DAC to operate in a non-return-to-zero mode; and Wherein, in the second mode, the control circuit controls the second DAC to operate in a return-to-zero mode.

16. The IC according to claim 10, wherein the N integrators are coupled in series from a first integrator having an input coupled to an output of the first DAC to a last integrator having an output coupled to an input of the quantizer; wherein the N integrators include a second integrator and a third integrator, the second integrator having an input coupled to an output of the first integrator, and the third integrator having an input coupled to an output of the second integrator; and Therein, in a third mode, the control circuit is configured to operate the DSM as a modulator with an order less than N and greater than two, so that the first, second and last integrators provide valid outputs and the third integrator provides a null signal output.

17. The IC of claim 10, wherein the control circuit is configured to exit the second mode and switch to the first mode in response to the output of the quantizer, wherein the output of the quantizer corresponds to a signal level within a normal operating range of the DSM.

18. The IC of claim 10, wherein the control circuit is configured to adjust a weight of an integrator and a weight of the second DAC as part of switching to the second mode.

19. A system comprising: a low pass analog filter having an analog signal input and an output; a sampling circuit having an input and an output, the input of the sampling circuit being coupled to the output of the low pass analog filter; a first integrator having a first input, a second input, and an output, the first input of the first integrator being coupled to the output of the sampling circuit; a first weighted adder having a first input, a second input, a third input and an output, the first input of the first weighted adder being coupled to the output of the sampling circuit and the second input of the first weighted adder being coupled to the output of the first integrator; a second integrator having an input and an output, the input of the second integrator being coupled to the output of the first weighted adder; a second weighted adder having an input and an output, the input of the second weighted adder being coupled to the output of the second integrator; a quantizer having an input and an output, the input of the quantizer being coupled to the output of the second weighted adder; a first digital-to-analog converter (DAC) having an input and an output, the input of the first DAC being coupled to the output of the quantizer and the output of the first DAC being coupled to the second input of the first integrator; a second DAC having an input and an output, the input of the second DAC being coupled to the output of the quantizer and the output of the second DAC being coupled to the third input of the first weighted adder; A low pass digital filter has an input and an output, the input of the low pass digital filter being coupled to the output of the quantizer.

20. The system of claim 19, further comprising: a digital signal processing circuit (DSP) having an input and an output, the input of the DSP being coupled to the output of the low pass digital filter; as well as A third DAC has an input and an output, the input of the third DAC being coupled to the output of the DSP.

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