Semiconductor common unit structure, block structure, memory device structure, and method of fabrication

Abstract

The present disclosure relates to the technical field of semiconductor, and provides a semiconductor shared unit structure, a block structure, a memory device structure and a preparation method. The semiconductor shared unit structure comprises a first storage unit and a second storage unit. The first storage unit and the second storage unit are distributed in parallel in mirror image along a first direction. The first storage unit and the second storage unit share a same source-drain unit layer. The first direction is parallel to the surface of a substrate. The first storage unit and the second storage unit each comprise a first transistor and a second transistor. The fourth source-drain region of the second transistor in the first storage unit and the fourth source-drain region of the second transistor in the second storage unit are respectively connected to opposite surfaces of the source-drain unit layer. The memory device structure of the present disclosure has a higher storage density, a shorter process flow and a lower manufacturing cost.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor, and in particular, to a semiconductor shared cell structure, a block structure, a memory device structure and a preparation method. BACKGROUND

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor device in electronic devices such as computers. A conventional DRAM memory cell usually includes a transistor and a capacitor. The gate of the transistor is electrically connected to a word line, the source is electrically connected to a bit line, and the drain is electrically connected to the capacitor. The word line voltage on the word line can control the opening and closing of the transistor, so that the data information stored in the capacitor can be read through the bit line, or the data information can be written into the capacitor. This structure needs to constantly refresh the charge in the capacitor to ensure that the data is not lost, and the charge in the capacitor needs to be discharged when reading, and then re-written after reading is completed, which has high power consumption. At the same time, due to the large area occupied by the manufacturing process of the capacitor, size scaling becomes a problem.

[0003] A 2Transistor 0Capacitor (2T0C) uses two vertical structure transistors as a unit structure, in which the drain of one transistor is connected to the gate of the other transistor, and the gate capacitance is used to store charge and change the transistor transconductance to store information. This structure can increase the storage density by continuously increasing the number of stacked layers in the vertical direction without reducing the critical size, but it is necessary to make each layer of device and then make the next layer of device, which has a long process flow and high cost.

[0004] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0005] The present disclosure provides a semiconductor shared cell structure, a block structure, a memory device structure and a preparation method, which can simplify the process flow, reduce the manufacturing cost and improve the storage density.

[0006] According to one aspect of the present disclosure, a semiconductor shared cell structure is prepared on a substrate,

[0007] comprising:

[0008] a first memory cell and a second memory cell, the first memory cell and the second memory cell are distributed in mirror image side by side along a first direction, the first memory cell and the second memory cell share the same source-drain cell layer, and the first direction is parallel to the surface of the substrate.

[0009] The first storage unit and the second storage unit each comprise:

[0010] A first transistor is located above the top surface of the substrate, and comprises a first gate, a first gate dielectric layer and a first semiconductor layer, the first gate extends along the first direction, the first gate dielectric layer conformally covers the sidewall and one end of the first gate, the first semiconductor layer covers the surface of the first gate dielectric layer, and the first semiconductor layer comprises a first source-drain region, a first channel region and a second source-drain region distributed along the first direction in sequence;

[0011] A second transistor is distributed along the first direction side by side with the first transistor, and comprises a second gate, a second gate dielectric layer and a second semiconductor layer, the second gate extends along the first direction, the second gate dielectric layer conformally covers the sidewall and the end of the second gate away from the first transistor, the second semiconductor layer covers the surface of the second gate dielectric layer, and the second semiconductor layer comprises a third source-drain region, a second channel region and a fourth source-drain region distributed along the first direction in sequence; the second source-drain region is electrically connected with the second gate;

[0012] The fourth source-drain region in the first storage unit and the fourth source-drain region in the second storage unit are respectively connected to opposite surfaces of the source-drain unit layer.

[0013] In an exemplary embodiment of the present disclosure, the plane in which the source-drain unit layer is located is perpendicular to the first direction, and the source-drain unit layer comprises a first conductive barrier layer, a conductive metal layer and a second conductive barrier layer stacked along the first direction in sequence; the fourth source-drain region in the first storage unit is connected with the first conductive barrier layer, and the fourth source-drain region in the second storage unit is connected with the second conductive barrier layer.

[0014] In an exemplary embodiment of the present disclosure, the materials of the first conductive barrier layer and the second conductive barrier layer are both titanium nitride, and the material of the conductive metal layer is tungsten.

[0015] In an exemplary embodiment of the present disclosure, the materials of the first gate and the second gate are both indium zinc oxide, and the materials of the first semiconductor layer and the second semiconductor layer are both indium gallium zinc oxide.

[0016] According to an aspect of the present disclosure, a semiconductor common block structure prepared on a substrate comprises:

[0017] a plurality of semiconductor common unit structures as any one of the above described semiconductor common unit structures on the substrate, the plurality of semiconductor common unit structures arranged along a second direction and a third direction, the second direction parallel to the substrate and intersecting the first direction, the third direction perpendicular to the first direction and the second direction;

[0018] a plurality of word lines extending along the second direction and arranged along the first direction and the third direction, each of the word lines connected to an end portion of a row of the first gates in the same plane arranged along the second direction and not covered by the first gate dielectric layer;

[0019] a plurality of first bit lines extending along the third direction and arranged along the first direction and the second direction, each of the first bit lines covering an outer periphery of a row of the first source-drain regions in the same plane arranged along the third direction;

[0020] a plurality of second bit lines extending along the third direction and arranged along the first direction and the second direction, each of the second bit lines covering an outer periphery of a row of the third source-drain regions in the same plane arranged along the third direction;

[0021] a source-drain layer formed by sequentially connecting all the source-drain unit layers in the same plane end to end.

[0022] In an exemplary embodiment of the present disclosure, the materials of the word lines, the first bit lines, and the second bit lines are all electrically conductive materials, and the electrically conductive materials are independently selected from at least one of tungsten, copper, aluminum, tungsten nitride, titanium, and titanium nitride.

[0023] In an exemplary embodiment of the present disclosure, the word lines, the first bit lines, and the second bit lines each include a layer of electrically conductive barrier material and a layer of metal material, the material of the layer of electrically conductive barrier material is titanium nitride, and the material of the layer of metal material is tungsten.

[0024] According to an aspect of the present disclosure, there is provided a semiconductor memory device structure, comprising:

[0025] a substrate and a plurality of semiconductor common block structures as any one of the above described semiconductor common block structures on the substrate, the plurality of semiconductor common block structures arranged along the first direction;

[0026] two adjacent semiconductor common block structures are independently arranged.

[0027] According to an aspect of the present disclosure, there is provided a method for manufacturing a semiconductor memory device structure, comprising the following steps:

[0028] providing a substrate;

[0029] sequentially and alternately depositing layers of insulating material and layers of semiconductor material on the substrate to form a layer stack structure;

[0030] performing a patterning process on the stacked structure to form a patterned stacked structure, a pattern of the patterned stacked structure comprising a plurality of first patterns extending along a first direction and spaced apart along a second direction, and a plurality of second patterns extending along the second direction and spaced apart along the first direction; the first direction being parallel to a surface of the substrate, the second direction being parallel to the substrate and intersecting the first direction; the first patterns and the second patterns being overlapped;

[0031] forming a plurality of first openings extending through the patterned stacked structure along a third direction, the first openings being arranged one-to-one corresponding to the second patterns, the first openings dividing a corresponding second pattern into two sub-patterns which are mirror-symmetrically arranged side by side along the first direction; the third direction being perpendicular to the first direction and the second direction, the first openings being parallel to a plane in which the second direction and the third direction lie;

[0032] lateral etching away part of the semiconductor material layer through the first openings to form a plurality of first transistors and word line accommodation grooves, the first transistors and word line accommodation grooves comprising a row of first transistor accommodation grooves extending along the first direction and arranged along the second direction, and a word line accommodation groove extending along the second direction and communicating the row of first transistor accommodation grooves;

[0033] sequentially depositing a first semiconductor layer, a first gate dielectric layer and a first gate material layer in the first transistor and word line accommodation grooves; the first semiconductor layer covering side walls and a bottom surface of the first transistor and word line accommodation grooves, the first gate dielectric layer conformally covering a surface of the first semiconductor layer, and the first gate material layer filling a remaining space of the first transistor and word line accommodation grooves;

[0034] etching away the first gate material layer deposited in the word line accommodation groove to form a first gate of a first transistor, and further filling a word line material into the word line accommodation groove to form a word line and the first transistor located in the first transistor accommodation groove, the word line being in contact with the first gate; the first transistor comprising the first gate, the first gate dielectric layer conformally covering side walls and an end portion of the first gate, and the first semiconductor layer conformally covering the first gate dielectric layer, the first semiconductor layer on the first gate comprising a first source / drain region, a first channel region and a second source / drain region which are sequentially arranged along the first direction;

[0035] forming a plurality of second openings extending through the patterned stacked structure along the third direction, the second openings being located at a middle position between two adjacent first openings, the second openings being parallel to a plane in which the second direction and the third direction lie;

[0036] etching away part of the insulating material layer through the second opening laterally to both sides to form a second gate of a second transistor, and then sequentially depositing a second gate dielectric layer and a second semiconductor layer, the second gate dielectric layer conformally covering sidewalls of the second gate and an end of the second gate away from the first transistor, the second semiconductor layer covering a surface of the second gate dielectric layer, and the second semiconductor layer comprising a third source-drain region, a second channel region and a fourth source-drain region sequentially distributed along the first direction;

[0037] filling the space between adjacent second transistors with insulating material to seal the second opening; forming a plurality of third openings extending through the insulating material along the third direction, the third openings being located within the second opening and exposing the fourth source-drain region in the second transistor, the third openings being parallel to the plane in which the second direction and the third direction lie;

[0038] forming a source-drain layer in the third opening;

[0039] forming a plurality of first bit line accommodating holes and second bit line accommodating holes extending along the third direction, forming a first bit line in the first bit line accommodating hole and a second bit line in the second bit line accommodating hole; each of the first bit lines covering the outer periphery of a row of the first source-drain regions arranged in the same plane along the third direction, and each of the second bit lines covering the outer periphery of a row of the third source-drain regions arranged in the same plane along the third direction.

[0040] In an exemplary embodiment of the present disclosure, before the step of forming a plurality of first openings extending through the patterned layer stack along the third direction, the method further comprises:

[0041] filling the space in the patterned layer stack with insulating material.

[0042] In an exemplary embodiment of the present disclosure, after forming the word lines and before forming the second opening, the method further comprises:

[0043] filling the first opening with insulating material.

[0044] In an exemplary embodiment of the present disclosure, forming a source-drain layer in the third opening comprises:

[0045] forming a conductive barrier layer conformally covering the inner walls and the bottom of the third opening;

[0046] depositing a conductive metal layer in the third opening, the conductive metal layer filling the remaining space of the third opening.

[0047] The semiconductor shared block structure in the present disclosure, the first storage unit and the second storage unit can be distributed on the substrate surface in a direction parallel to the substrate, and the first storage unit and the second storage unit can be formed simultaneously in the process, without waiting for the first storage unit to be completed before forming the second storage unit, so that the process flow is shorter and the manufacturing cost is lower. Since the first storage unit and the second storage unit share the same source-drain unit layer, the signal paths and conditions received by the two are consistent, which helps to reduce reading errors and data inconsistency caused by signal transmission differences; the area of the region where the first storage unit and the second storage unit are located can be reduced, the device integration is improved, and the storage density of the memory is further improved.

[0048] In the semiconductor shared block structure in the present disclosure, in each layer, the word line corresponding to the first storage unit and the word line corresponding to the second storage unit extend in the second direction and are arranged in the first direction, so that the semiconductor shared block structure is stacked in the first direction, the substrate area is maximized, and the storage density is increased.

[0049] The memory device structure in the present disclosure is a double-transistor capacitorless dynamic random access memory, and the two transistors in the storage unit are located above the substrate and are arranged transversely, with the channel parallel to the substrate direction. The storage density is increased by vertical stacking, and compared with the existing double-transistor capacitorless dynamic random access memory which increases the storage density by vertical stacking, the height of each layer in the memory device structure in the present disclosure is greatly reduced, and the storage density is higher.

[0050] The preparation method of the semiconductor memory device structure in the present disclosure, compared with the preparation method of the existing double-transistor capacitorless dynamic random access memory which needs to prepare the storage functional layer layer by layer to realize vertical stacking to increase the storage density, all the vertically stacked layers are prepared simultaneously in the preparation method of the semiconductor memory device structure in the present disclosure; compared with the preparation method of the existing double-transistor capacitorless dynamic random access memory in which the write bit line layer and the read bit line layer are formed respectively, all the first bit lines and the second bit lines are prepared simultaneously in the preparation method of the semiconductor memory device structure in the present disclosure; compared with the word line layer of the existing double-transistor capacitorless dynamic random access memory which prepares the storage functional layer layer by layer, all the word lines are also prepared simultaneously in the preparation method of the semiconductor memory device structure in the present disclosure. Therefore, the preparation method of the semiconductor memory device structure in the present disclosure has a shorter process flow and lower manufacturing cost.

[0051] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0052] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments consistent with the present disclosure and, together with the description, further serve to explain the principles of the disclosure. It is to be understood that the drawings are designed solely for purposes of illustration to be used in conjunction with the description insofar as specifically placed herein below.

[0053] Figure 1 A schematic diagram of a semiconductor common unit structure in an embodiment of the present disclosure.

[0054] Figure 2 A schematic diagram of a semiconductor common block structure in an embodiment of the present disclosure.

[0055] Figure 3 An equivalent circuit diagram of a semiconductor common block structure in an embodiment of the present disclosure.

[0056] Figure 4 A schematic diagram of a semiconductor memory device structure in an embodiment of the present disclosure.

[0057] Figure 5 A schematic diagram of a substrate, a laminated structure, a protective layer, a first mask layer and a developed pattern in an embodiment of the present disclosure.

[0058] Figure 6 A schematic diagram of a patterned laminated structure in an embodiment of the present disclosure.

[0059] Figure 7 A schematic diagram of a structure after step S4 is completed in an embodiment of the present disclosure.

[0060] Figure 8 A schematic diagram of a structure after step S210 is completed in an embodiment of the present disclosure.

[0061] Figure 9 A schematic diagram of a second mask layer and a second photoresist layer in an embodiment of the present disclosure.

[0062] Figure 10 A schematic diagram of a structure after step S5 is completed in an embodiment of the present disclosure.

[0063] Figure 11 A cross-sectional view of a structure along direction AA in an embodiment of the present disclosure. Figure 10

[0064] A schematic diagram of a structure in which a first semiconductor layer, a first gate dielectric layer and a first gate material layer are completed in an embodiment of the present disclosure. Figure 12 Figure 11 A schematic diagram of a structure after step S6 is completed in an embodiment of the present disclosure.

[0065] Figure 13 Figure 12 A schematic diagram of a structure after step S6 is completed in an embodiment of the present disclosure. ​​

[0066] Figure 14 The structure after step S7 is completed in the structure of Figure 13 The structure after step S7 is completed in the structure of

[0067] Figure 15 The structure after step S220 is completed in the structure of the embodiment of the present disclosure.

[0068] Figure 16 The structure after step S8 is completed in the structure of the embodiment of the present disclosure.

[0069] Figure 17 The structure after step S8 is completed in the structure of the embodiment of the present disclosure.

[0070] Figure 18 The structure after step S8 is completed in the structure of the embodiment of the present disclosure. Figure 17 The structure after step S8 is completed in the structure of the embodiment of the present disclosure.

[0071] Figure 19 The structure after step S8 is completed in the structure of the embodiment of the present disclosure. Figure 18 The structure after step S8 is completed in the structure of the embodiment of the present disclosure.

[0072] Figure 20 The structure after step S8 is completed in the structure of the embodiment of the present disclosure. Figure 19 The structure after step S10 is completed in the structure of

[0073] Figure 21 The structure after step S11 is completed in the structure of Figure 20 The structure after step S11 is completed in the structure of

[0074] Figure 22 The structure after step S11 is completed in the structure of

[0075] Figure 23 The structure after step S11 is completed in the structure of Figure 22 The structure after step S11 is completed in the structure of

[0076] Figure 24 The structure after step S12 is completed in the structure of the embodiment of the present disclosure.

[0077] Explanation of reference signs:

[0078] 1, substrate; 2, first memory cell; 3, second memory cell; 4, source-drain layer; 410, source-drain cell layer; 41, first conductive barrier layer; 42, conductive metal layer; 43, second conductive barrier layer; 10, first transistor; 101, first gate; 1011, first gate material layer; 102, first gate dielectric layer; 103, first semiconductor layer; 20, second transistor; 201, second gate; 202, second gate dielectric layer; 203, second semiconductor layer; 5, word line; 51, conductive barrier material layer; 52, metal material layer; 6, first bit line; 601, first bit line accommodating hole; 7, second bit line; 701, second bit line accommodating hole; 8, insulating material; 81, third opening; 9, protective layer; 30, stacked structure; 301, insulating material layer; 302, semiconductor material layer; 40, patterned stacked structure; 401, first pattern; 402, second pattern; 4021, sub-pattern; 403, first opening; 404, first transistor accommodating groove; 405, word line accommodating groove; 406, second opening; 50, developed pattern; 60, second photoresist layer; 6001, first developed area; 100, first mask layer; 200, second mask layer; x, first direction; y, second direction; z, third direction. DETAILED DESCRIPTION

[0079] Example implementations are now described with reference to the drawings; however, these implementations are merely examples of implementations and are not intended to be limiting. Rather, these implementations are presented as understood by one of ordinary skill in the art to fully and completely convey the scope of the example implementations to those skilled in the art. Like reference numbers in the figures indicate like components, and thus a detailed description thereof will not be repeated. Additionally, the figures are not necessarily drawn to scale.

[0080] Although relative terms such as "upper," "lower," are used herein to describe one component's relationship to another component of a device, such terminology is used herein for convenience only and is not intended to limit the scope of the disclosure to only such orientations. It is to be understood that the devices described herein can be inverted, such that what is described as "upper" can become "lower." When a structure is "on" another structure, it can mean that the structure is formed integrally with the other structure, or that the structure is "directly on" the other structure, or that the structure is "indirectly on" the other structure via another structure.

[0081] The terms "one", "a", "an", "the", and "at least one" are used to indicate the existence of one or more elements / components / etc.; the term "comprising" and "having" are used to indicate an open-ended inclusion of one or more elements / components / etc. in the description of a process, a method, an article, a preparation, a composition, a device, a system, etc., and that the addition of one or more elements / components / etc. is not precluded; the terms "first", "second", "third", and "fourth" are used to indicate a relative order, and are not used to limit the number of elements / components / etc.

[0082] With the rapid development of the semiconductor industry, the storage density of memory is increasingly required. However, the traditional 1T1C (i.e., one transistor and one capacitor) structure faces severe challenges in improving the storage density. The key size reduction is limited by the lithography capability limit of the lithography machine, and it is difficult to continue to shrink. At the same time, the 1T1C structure is difficult to realize three-dimensional stacking, and the improvement of the storage density is severely restricted by the key size. In order to break this bottleneck, the research focus of those skilled in the art is turned to the 2T0C (i.e., two transistors, no capacitor) structure. The existing vertical structure of 2T0C DRAM memory, the transistor channel in the storage unit is perpendicular to the substrate, and the storage density is significantly improved by sequentially stacking the storage functional layer. However, the structure process flow of the sequentially stacked storage functional layer is long and the manufacturing cost is high.

[0083] Based on this, the semiconductor shared cell structure provided by the embodiments of the present disclosure is prepared on a substrate. Figure 1 A schematic diagram of the semiconductor shared cell structure of the present disclosure is shown as Figure 1 As shown, the semiconductor shared cell structure includes a first storage unit 2 and a second storage unit 3, the first storage unit 2 and the second storage unit 3 are distributed in mirror image side by side along a first direction x, the first storage unit 2 and the second storage unit 3 share the same source-drain cell layer 410, and the first direction x is parallel to the surface of the substrate;

[0084] The first storage unit 2 and the second storage unit 3 each include a first transistor 10 and a second transistor 20,

[0085] Wherein:

[0086] The first transistor 10 is located above the top surface of the substrate, and the first transistor 10 includes a first gate 101, a first gate dielectric layer 102, and a first semiconductor layer 103, the first gate 101 extends along the first direction x, the first gate dielectric layer 102 covers the sidewall and one end of the first gate 101, the first semiconductor layer 103 covers the surface of the first gate dielectric layer 102, and the first semiconductor layer 103 includes a first source-drain region, a first channel region, and a second source-drain region distributed in sequence along the first direction x;

[0087] The second transistor 20 is distributed along the first direction x side by side with the first transistor 10, and the second transistor 20 comprises a second gate 201, a second gate dielectric layer 202, and a second semiconductor layer 203. The second gate 201 extends along the first direction x. The second gate dielectric layer 202 covers the sidewalls of the second gate 201 and the end of the second gate 201 away from the first transistor 10. The second semiconductor layer 203 covers the surface of the second gate dielectric layer 202, and the second semiconductor layer 203 comprises a third source-drain region, a second channel region, and a fourth source-drain region distributed along the first direction x in sequence. The second source-drain region is electrically connected with the second gate 201.

[0088] The fourth source-drain region in the first storage unit 2 and the fourth source-drain region in the second storage unit 3 are respectively connected to opposite sides of the source-drain unit layer 410.

[0089] The semiconductor shared unit structure of the present disclosure, the first storage unit 2 and the second storage unit 3 can be distributed laterally on the surface of the substrate 1 along the direction parallel to the substrate 1. In the process, the first storage unit 2 and the second storage unit 3 can be formed simultaneously. In this process, there is no need to wait for the first storage unit 2 to be completed before forming the second storage unit 3. The process flow is shorter, and the manufacturing cost is lower. At the same time, since the first storage unit 2 and the second storage unit 3 share the same source-drain unit layer 410, the signal path and condition received by the two are consistent, which helps to reduce the reading error and data inconsistency caused by the difference in signal transmission. It can also reduce the area of the region where the first storage unit 2 and the second storage unit 3 are located, improve the device integration, and further improve the storage density of the memory.

[0090] The following will describe the parts of the semiconductor shared unit structure of the present disclosure and their specific details in detail:

[0091] The substrate (not shown in the figure) can be in a flat plate structure, for example, it can be a flat plate structure. The substrate can be rectangular, circular, elliptical, polygonal, or irregular, and its material can be a semiconductor material, for example, its material can be silicon, but it is not limited to silicon or other semiconductor materials, and the shape and material of the substrate are not specially limited here.

[0092] The first storage unit 2 and the second storage unit 3 can be formed on the substrate. The first storage unit 2 and the second storage unit 3 can both be 2T0C (i.e., including two transistors, no capacitor) structure. The first storage unit 2 can be distributed along the first direction x side by side with the second storage unit 3 in a mirror image, and the first storage unit 2 can share the same source-drain unit layer 410 with the second storage unit 3. This can reduce the area of the region where the first storage unit 2 and the second storage unit 3 are located, improve the device integration, and further improve the storage density of the memory. In an exemplary embodiment of the present disclosure, the first direction x can be parallel to the surface of the substrate.

[0093] In an example embodiment of the present disclosure, the first storage unit 2 and the second storage unit 3 each include a first transistor 10 and a second transistor 20, wherein:

[0094] The first transistor 10 is located above the top surface of the substrate, the first transistor 10 can be a CAA (Channel-All-Around) structure transistor and the channel is parallel to the plane of the substrate and can extend along the first direction x. Please continue to see Figure 1 As shown, the first transistor 10 can include a first gate 101, a first gate dielectric layer 102, and a first semiconductor layer 103, the first gate 101 can be in the form of a strip and can extend along the first direction x; the material of the first gate 101 can be a conductive material, for example, the material of the first gate 101 can be IZO (Indium Zinc Oxide) or polysilicon. The first gate dielectric layer 102 can conformally cover the sidewall and one end of the first gate 101, the material of the first gate dielectric layer 102 can be a material with high dielectric constant, for example, it can be aluminum oxide, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide or a mixture thereof, of course, it can also be other materials, which are not listed one by one here. The first semiconductor layer 103 can conformally cover the surface of the first gate dielectric layer 102, and the first semiconductor layer 103 can include a first source-drain region, a first channel region and a second source-drain region distributed along the first direction x in turn, wherein the first source-drain region is located on the side of the first channel region away from the source-drain unit layer 410, and the second source-drain region is located on the side of the first channel region close to the source-drain unit layer 410. The material of the first semiconductor layer 103 can cooperate with the material of the first gate 101; for example, when the material of the first gate 101 is IZO (Indium Zinc Oxide), the material of the first semiconductor layer 103 can be IGZO (Indium Gallium Zinc Oxide); when the material of the first gate 101 is polysilicon, the material of the first semiconductor layer 103 can be single crystal silicon.

[0095] Optionally, the material of the first semiconductor layer 103 of the present disclosure is IGZO (Indium Gallium Zinc Oxide), compared with the traditional single crystal silicon as the material of the first semiconductor layer 103, in the present disclosure, IGZO is used as the material of the first semiconductor layer 103, because the off-state current of the IGZO thin film transistor (TFT) is extremely small, which can significantly reduce the leakage speed of the 2T0C DRAM storage unit, help to reduce the power consumption of the device, and improve the reliability of the device.

[0096] The second transistor 20 can also be located above the top surface of the substrate, the second transistor 20 can be a CAA structure transistor and the channel is parallel to the plane where the substrate is located, and can extend along the first direction x. The second transistor 20 can be distributed along the first direction x with the first transistor 10, that is, the second transistor 20 and the first transistor 10 are distributed laterally on the surface of the substrate. The second transistor 20 can include a second gate 201, a second gate dielectric layer 202, and a second semiconductor layer 203. The second gate 201 can be in the form of a strip and can extend along the first direction x. For example, the second gate 201 and the first gate 101 can be sequentially distributed along the first direction x. The material of the second gate 201 can be a conductive material, for example, it can be indium zinc oxide (IZO) or polysilicon. In some embodiments of the present disclosure, the material of the second gate 201 is the same as the material of the first gate 101, for example, the material of the second gate 201 and the first gate 101 can both be indium zinc oxide (IZO). The second gate dielectric layer 202 can conformally cover the sidewalls of the second gate 201 and the end of the second gate 201 away from the first transistor 10. The material of the second gate dielectric layer 202 can be a material with high dielectric constant, for example, it can be aluminum oxide, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide or a mixture thereof, of course, other materials are also possible, which are not listed one by one here. It should be noted that the material of the second gate dielectric layer 202 can be the same as the material of the first gate dielectric layer 102. The second semiconductor layer 203 can conformally cover the surface of the second gate dielectric layer 202, and the second semiconductor layer 203 includes a third source-drain region, a second channel region and a fourth source-drain region sequentially distributed along the first direction x, wherein the third source-drain region is located on one side of the second channel region away from the source-drain unit layer 410, and the fourth source-drain region is located on one side of the second channel region close to the source-drain unit layer 410; The material of the second semiconductor layer 203 can be matched with the material of the second gate 201; for example, when the material of the second gate 201 is indium zinc oxide (IZO), the material of the second semiconductor layer 203 can be indium gallium zinc oxide (IGZO); when the material of the second gate 201 is polysilicon, the material of the second semiconductor layer 203 can be single crystal silicon. In some embodiments of the present disclosure, the material of the second semiconductor layer 203 can be the same as the material of the first semiconductor layer 103, for example, the material of the second semiconductor layer 203 and the material of the first semiconductor layer 103 can both be indium gallium zinc oxide.

[0097] In an exemplary embodiment of the present disclosure, the first transistor 10 can be a write transistor, and the second transistor 20 can be a read transistor. The second source-drain region of the first transistor 10 is electrically connected with the second gate 201 of the second transistor 20. By changing the charge in the gate capacitance of the second transistor 20 (i.e. the read transistor) through the first transistor 10 (i.e. the write transistor), the resistance state between the source and drain of the second transistor 20 (i.e. the read transistor) is affected, thereby realizing the distinction between "0" and "1". The specific principle is as follows:

[0098] The writing "1" process, a positive voltage (greater than the threshold voltage Vth) is applied to the write word line WWL to turn on the first transistor 10 (i.e., the writing transistor), and a positive voltage is applied to the write bit line WBL to inject charges into the gate capacitor (i.e., the storage node) of the second transistor 20 (i.e., the reading transistor); after the charge injection, the positive voltage applied to the write word line WWL and the positive voltage applied to the write bit line WBL are removed, and the "1" state is saved. The reading "1" process, a reading voltage is applied to the drain of the second transistor 20 (i.e., the reading transistor), and a certain amount of charges are stored in the gate capacitor, so that the second transistor 20 (i.e., the reading transistor) is in a low resistance state, a large current is obtained, and the reading "1" process is completed after amplification and identification by the peripheral circuit. The writing "0" process, a positive voltage (greater than the threshold voltage Vth) is applied to the write word line WWL to turn on the first transistor 10 (i.e., the writing transistor), and a negative voltage is applied to the write bit line WBL to extract charges from the gate capacitor (i.e., the storage node) of the second transistor 20 (i.e., the reading transistor); after the charge extraction, the positive voltage applied to the write word line WWL and the negative voltage applied to the write bit line WBL are removed, and the "0" state is saved. The reading "0" process, a reading voltage is applied to the drain of the second transistor 20 (i.e., the reading transistor), and no charges are stored in the gate capacitor, so that the second transistor 20 (i.e., the reading transistor) is in a high resistance state, a small current is obtained, and the reading "0" process is completed after amplification and identification by the peripheral circuit.

[0099] In an exemplary embodiment of the present disclosure, the source-drain unit layer 410 can extend in a direction perpendicular to the substrate, i.e., the plane in which the source-drain unit layer 410 is located is perpendicular to the first direction x, and the fourth source-drain region in the first storage unit 2 and the fourth source-drain region in the second storage unit 3 are respectively connected to opposite surfaces of the source-drain unit layer 410 distributed along the first direction x. Such a design can ensure that the signal paths and conditions received by the first storage unit 2 and the second storage unit 3 are consistent, which helps to reduce reading errors and data inconsistency caused by signal transmission differences.

[0100] In some embodiments of the present disclosure, please continue to refer to Figure 1 As shown in the figure, the source-drain unit layer 410 can include a first conductive barrier layer 41, a conductive metal layer 42, and a second conductive barrier layer 43 stacked in the first direction x in sequence, i.e., the first conductive barrier layer 41, the conductive metal layer 42, and the second conductive barrier layer 43 form a sandwich structure. The fourth source-drain region in the first storage unit 2 can be in contact with the surface of the first conductive barrier layer 41 away from the conductive metal layer 42, and the fourth source-drain region in the second storage unit 3 can be in contact with the surface of the second conductive barrier layer 43 away from the conductive metal layer 42.

[0101] The material of the conductive metal layer 42 can be a metal material with good conductive performance, for example, tungsten. The material of the first conductive barrier layer 41 can be a conductive material with ion blocking function, and the material of the second conductive barrier layer 43 can also be a conductive material with ion blocking function, for example, the material of the first conductive barrier layer 41 and the second conductive barrier layer 43 can both be titanium nitride. The first conductive barrier layer 41 and the second conductive barrier layer 43 can prevent the metal ions in the conductive metal layer 42 from diffusing to other surrounding structures, which can help to reduce the probability of coupling or short circuit between the source-drain unit layer 410 and other structures, and improve the reliability of the device.

[0102] The present disclosure also provides a semiconductor common block structure, Figure 2 A schematic diagram of the semiconductor common block structure of the present disclosure is shown, as Figure 2 The semiconductor common block structure can be prepared on a substrate 1, and the semiconductor common block structure can include a plurality of semiconductor common unit structures in any of the above embodiments, a plurality of word lines 5, a plurality of first bit lines 6, a plurality of second bit lines 7, and a source-drain layer 4 on the substrate 1, wherein:

[0103] The plurality of semiconductor common unit structures are arranged along a second direction y and a third direction z, the second direction y is parallel to the substrate 1 and intersects the first direction x, and the third direction z is perpendicular to the first direction x and the second direction y;

[0104] The plurality of word lines 5 extend along the second direction y and are arranged along the first direction x and the third direction z, and each word line 5 is connected to the end portion of a row of first gates 101 in the same plane arranged along the second direction y and not covered by the first gate dielectric layer 102;

[0105] The plurality of first bit lines 6 extend along the third direction z and are arranged along the first direction x and the second direction y, and each first bit line 6 covers the outer periphery of a row of first source-drain regions arranged along the third direction z in the same plane;

[0106] The plurality of second bit lines 7 extend along the third direction z and are arranged along the first direction x and the second direction y, and each second bit line 7 covers the outer periphery of a row of third source-drain regions arranged along the third direction z in the same plane;

[0107] The source-drain layer 4 is formed by sequentially connecting all the source-drain unit layers 410 in the same plane.

[0108] In the semiconductor shared block structure disclosed herein, multiple memory cells (e.g., first memory cell 2 or second memory cell 3) arranged along the second direction y can share the same word line 5, multiple first memory cells 2 arranged along the third direction z can share the same first bit line 6, and multiple second memory cells 3 arranged along the third direction z can share the same second bit line 7. Selecting one word line 5 and one first bit line 6 selects one first transistor 10 (i.e., write transistor). By sharing the same word line 5, first bit line 6, and second bit line 7, the number of metal interconnects is reduced, allowing more memory cells to be accommodated in the same area. This not only increases the physical storage density of the memory but also reduces parasitic capacitance and resistance between interconnects, helping to reduce power consumption. Furthermore, due to the reduction in the number of metal interconnects, steps such as photolithography and etching in the manufacturing process are simplified, helping to reduce production complexity and cost.

[0109] The following provides a detailed description of the various parts and specific details of the semiconductor common block structure disclosed herein:

[0110] like Figure 2 As shown, multiple semiconductor shared cell structures can be arranged along the second direction y and the third direction z. For example, multiple semiconductor shared cell structures can form multiple shared cell structure groups arranged along the third direction z. Each shared cell structure group can include multiple semiconductor shared cell structures arranged along the second direction y.

[0111] The second direction y is parallel to the substrate 1 and intersects the first direction x. For example, the second direction y can be perpendicular to the first direction x, and the third direction z is perpendicular to both the first direction x and the second direction y. It should be noted that parallelism can be absolute or approximately parallel; similarly, perpendicularity can be absolute or approximately perpendicular. Deviations are inevitable during the manufacturing process. In this disclosure, angular deviations may occur due to limitations in the manufacturing process, resulting in a certain deviation in the angle between the first direction x (or the second direction y) and the surface of the substrate 1, or a certain deviation in the angle between the third direction z and the first direction x (or the second direction y). As long as the angular deviation is within a preset range, the first direction x (or the second direction y) can be considered parallel to the substrate 1; or, the third direction z can be considered perpendicular to the first direction x (or the second direction y). For example, the preset range can be 10°, that is: when the angle between the first direction x (or the second direction y) and the surface of the substrate 1 is less than or equal to 10°, the first direction x (or the second direction y) can be considered parallel to the surface of the substrate 1; when the angle between the third direction z and the first direction x (or the second direction y) is greater than or equal to 80° and less than or equal to 100°, the third direction z can be considered perpendicular to the first direction x (or the second direction y).

[0112] The word line 5 can be in the form of a strip and can extend along the second direction y. Each common cell structure group can include two word lines 5, which can be spaced apart along the first direction x, one of which can be in contact with the end of each of the first gates 101 in a row arranged along the second direction y in all the first storage units 2 in the same common cell structure group and not covered by the first gate dielectric layer 102; the other of which can be in contact with the end of each of the first gates 101 in a row arranged along the second direction y in all the second storage units 3 in the same common cell structure group and not covered by the first gate dielectric layer 102. The word lines 5 connected to the first storage units 2 in the common cell structure groups arranged along the third direction z can be spaced apart along the third direction z.

[0113] Please continue to see Figure 2 As shown, the first bit line 6 can be in the form of a strip and can extend along the third direction z. The semiconductor common block structure of the present disclosure can include a plurality of bit line groups spaced apart along the second direction y, each of which can include two first bit lines 6, which can be spaced apart along the first direction x, one of which can cover the outer periphery of a row of first source-drain regions arranged along the third direction z in each of the first storage units 2 in the common cell structure groups arranged along the third direction z; the other of which can cover the outer periphery of a row of first source-drain regions arranged along the third direction z in each of the second storage units 3 in the common cell structure groups arranged along the third direction z. It should be noted that different semiconductor common cell structures arranged along the second direction y are respectively provided with a bit line group, and each of the first bit lines 6 in different bit line groups can be spaced apart and parallelly arranged along the second direction y.

[0114] Please continue to see Figure 2 As shown, the second bit line 7 can be in the form of a strip and can extend along the third direction z. Each bit line group can include two second bit lines 7, which can be spaced apart along the first direction x, one of which can cover the outer periphery of a row of third source-drain regions arranged along the third direction z in each of the first storage units 2 in the common cell structure groups arranged along the third direction z; the other of which can cover the outer periphery of a row of third source-drain regions arranged along the third direction z in each of the second storage units 3 in the common cell structure groups arranged along the third direction z. It should be noted that each of the second bit lines 7 in different bit line groups can be spaced apart and parallelly arranged along the second direction y.

[0115] In an example embodiment of the present disclosure, the materials of the word line 5, the first bit line 6 and the second bit line 7 are all conductive materials, which can be independently selected from at least one of tungsten, copper, aluminum, tungsten nitride, titanium, and titanium nitride. For example, the word line 5, the first bit line 6 and the second bit line 7 can each include a conductive barrier material layer and a metal material layer. Taking the word line 5 as an example, the metal material layer can be in a strip shape and extend along the second direction y, and the conductive barrier material layer can at least wrap the upper surface, the lower surface and the surface of the metal material layer close to the first gate 101 along the third direction z, that is, the first gate 101 is in contact with the conductive barrier material layer in the word line 5. The diffusion of metal ions in the metal material layer to other surrounding structures can be prevented through the conductive barrier material layer, which helps to reduce the risk of short circuit or coupling and improve the reliability of the device. In some embodiments of the present disclosure, the material of the conductive barrier material layer can be titanium nitride, and the material of the metal material layer can be tungsten. The diffusion of tungsten ions into the first gate 101 can be prevented by titanium nitride.

[0116] In an example embodiment of the present disclosure, as shown in Figure 2 and Figure 3 all the source-drain unit layers 410 in the same plane in the plurality of semiconductor shared unit structures are sequentially connected end to end to form a source-drain layer 4. The specific details and benefits of the source-drain layer 4 have been described in detail in the embodiments of the corresponding semiconductor shared unit structure, and therefore will not be repeated here. It should be noted that the two first bit lines 6 in the same bit line group are distributed in mirror symmetry along the source-drain layer 4, and the two second bit lines 7 in the same bit line group are distributed in mirror symmetry along the source-drain layer 4. At the same time, the two word lines 5 in the same shared unit structure group are distributed in mirror symmetry along the source-drain layer 4.

[0117] The present disclosure also provides a semiconductor storage device structure, as shown in Figure 4 which includes a substrate 1 and a plurality of semiconductor shared block structures as in any of the above embodiments on the substrate 1, the plurality of semiconductor shared block structures are arranged along the first direction x; and the adjacent two semiconductor shared block structures are independently arranged. For example, the adjacent semiconductor shared block structures in the semiconductor storage device structure are distributed with a spacing. The other details and benefits of the semiconductor storage device structure of the present disclosure have been described in detail in the embodiments of the corresponding semiconductor shared block structure and semiconductor shared unit structure, and therefore will not be repeated here.

[0118] Defining a semiconductor shared block structure includes two semiconductor storage block structures which are distributed in mirror symmetry along the source-drain layer 4: a first semiconductor storage block structure and a second semiconductor storage block structure, and the first semiconductor storage block structure and the second semiconductor storage block structure share one source-drain layer.

[0119] The read-write principle of the semiconductor memory device structure provided by the present disclosure is as follows:

[0120] When writing, a storage unit (including a first transistor 10 (i.e., a write transistor) and a second transistor 10 (i.e., a read transistor)) can be selected by selecting one word line 5 and one first bit line 6, and the first transistor 10 (i.e., the write transistor) can be turned on by applying voltages to the selected word line 5 and the selected first bit line 6, so that the gate capacitor of the second transistor 10 (i.e., the read transistor) can be injected or extracted with electric charges, thereby realizing the writing operation.

[0121] When reading, the first transistor 10 (i.e., the write transistor) in the semiconductor memory block structure where the selected storage unit is located can be turned on except for the first transistor 10 corresponding to the selected storage unit, the gate capacitor of the second transistor 10 (i.e., the read transistor) except for the selected storage unit can be extracted with electric charges, and then all the first transistors 10 (i.e., the write transistors) can be turned off; a read voltage can be applied to the second bit line 7 corresponding to the selected storage unit and the source-drain layer 4, thereby realizing the reading operation of the selected storage unit.

[0122] It should be understood that after each reading operation, a refresh operation needs to be performed on the semiconductor memory block structure where the selected storage unit is located, so as to restore the storage data of the semiconductor memory block structure before the reading operation.

[0123] The memory device structure of the present disclosure is a two-transistor capacitorless dynamic random access memory, and the two transistors in the storage unit are arranged transversely above the substrate and have channels parallel to the substrate direction. The storage density is increased by vertical stacking, and compared with the existing two-transistor capacitorless dynamic random access memory which increases the storage density by vertical stacking, the height of each layer in the memory device structure of the present disclosure is greatly reduced, and the storage density is higher.

[0124] The present disclosure also provides a preparation method of a semiconductor memory device structure, which is used to form the semiconductor memory device structure in any of the above embodiments. The preparation method can include steps S1-S12, wherein:

[0125] Step S1, providing a substrate 1;

[0126] Step S2, sequentially and alternately depositing an insulating material layer 301 and a semiconductor material layer 302 on the substrate 1 to form a layer structure 30;

[0127] Step S3, the laminated structure 30 is subjected to a patterning process to form a patterned laminated structure 40, the pattern of the patterned laminated structure 40 includes a plurality of first patterns 401 extending along the first direction x and spaced along the second direction y, and a plurality of second patterns 402 extending along the second direction y and spaced along the first direction x; the first direction x is parallel to the surface of the substrate 1, the second direction y is parallel to the substrate 1 and intersects with the first direction x; the first pattern 401 and the second pattern 402 overlap;

[0128] Step S4, a plurality of first openings 403 extending through the patterned laminated structure 40 along the third direction z are formed, the first openings 403 are arranged one-to-one corresponding to the second patterns 402, and the first openings 403 divide the corresponding second patterns 402 into two sub-patterns 4021 arranged side by side in mirror image along the first direction x; the third direction z is perpendicular to the first direction x and the second direction y, and the first openings 403 are parallel to the plane of the second direction y and the third direction z;

[0129] Step S5, a portion of the semiconductor material layer 302 is etched away laterally to both sides through the first openings 403 to form a plurality of first transistors 10 and word line containing grooves 405, the first transistors 10 and the word line containing grooves 405 include a row of first transistor containing grooves 404 extending along the first direction x and arranged along the second direction y, and a word line containing groove 405 extending along the second direction y and communicating with the row of first transistor containing grooves 404;

[0130] Step S6, a first semiconductor layer 103, a first gate dielectric layer 102 and a first gate material layer 1011 are sequentially deposited in the first transistor 10 and the word line containing groove 405; the first semiconductor layer 103 covers the sidewalls and the bottom surface of the first transistor 10 and the word line containing groove 405, the first gate dielectric layer 102 is conformally deposited on the surface of the first semiconductor layer 103, and the first gate material layer 1011 fills the remaining space of the first transistor 10 and the word line containing groove 405;

[0131] Step S7, the first gate material layer 1011 deposited in the word line containing groove 405 is etched away to form a first gate 101 of the first transistor 10, and the word line 5 material is filled into the word line containing groove 405 to form a word line 5 and a first transistor 10 located in the first transistor containing groove 404, and the word line 5 is in contact with the first gate 101; the first transistor 10 includes the first gate 101, the first gate dielectric layer 102 conformally covering the sidewalls and one end of the first gate 101, and the first semiconductor layer 103 conformally covering the first gate dielectric layer 102, and the first semiconductor layer 103 includes a first source-drain region, a first channel region and a second source-drain region arranged along the first direction x in sequence;

[0132] Step S8, a plurality of second openings 406 are formed through the patterned layered structure 40 along the third direction z, the second openings 406 are located at the middle position between two adjacent first openings 403, and the second openings 406 are parallel to the plane where the second direction y and the third direction z are located;

[0133] Step S9, a part of the insulating material layer 301 is etched away laterally to both sides through the second openings 406 to form the second gate 201 of the second transistor 20, and then a second gate dielectric layer 202 and a second semiconductor layer 203 are sequentially deposited, the second gate dielectric layer 202 covers the sidewall of the second gate 201 and the end of the second gate 201 away from the first transistor 10, the second semiconductor layer 203 covers the surface of the second gate dielectric layer 202, and the second semiconductor layer 203 includes a third source-drain region, a second channel region and a fourth source-drain region which are sequentially distributed along the first direction x;

[0134] Step S10, the insulating material 8 is filled between the adjacent second transistors 20 to seal the second openings 406, a plurality of third openings 81 are formed through the insulating material 8 along the third direction z, the third openings 81 are located in the second openings 406, and the third openings 81 expose the fourth source-drain region in the second transistor 20, and the third openings 81 are parallel to the plane where the second direction y and the third direction z are located;

[0135] Step S11, a source-drain layer 4 is formed in the third openings 81;

[0136] Step S12, a plurality of first bit line accommodating holes 601 and second bit line accommodating holes 701 are formed along the third direction z, a first bit line 6 is formed in the first bit line accommodating hole, and a second bit line 7 is formed in the second bit line accommodating hole 701; each first bit line 6 covers the outer periphery of a row of first source-drain regions arranged in the same plane along the third direction z, and each second bit line 7 covers the outer periphery of a row of third source-drain regions arranged in the same plane along the third direction z.

[0137] Compared with the preparation method of the existing vertical structure double transistor capacitorless dynamic random memory which needs to prepare the storage functional layer layer by layer to realize vertical stacking to increase the storage density, all the vertical stacked layers in the preparation method of the semiconductor memory device structure of the present disclosure are prepared at the same time; compared with the preparation method of the existing vertical structure double transistor capacitorless dynamic random memory in which the write bit line layer and the read bit line layer are formed respectively, all the first bit lines and the second bit lines in the preparation method of the semiconductor memory device structure of the present disclosure are prepared at the same time; compared with the word line layer of the existing vertical structure double transistor capacitorless dynamic random memory which is prepared layer by layer, all the word lines in the preparation method of the semiconductor memory device structure of the present disclosure are also prepared at the same time. Therefore, the preparation method of the semiconductor memory device structure of the present disclosure has a shorter process flow and lower manufacturing cost.

[0138] The following provides a detailed description of each step and specific details of the fabrication method for the semiconductor memory device structure disclosed herein:

[0139] In step S1, substrate 1 is provided.

[0140] like Figure 5 As shown, substrate 1 may have a planar structure, for example, it may be a planar structure. Substrate 1 may be rectangular, circular, elliptical, polygonal or irregular in shape, and its material may be a semiconductor material, for example, it may be silicon, but is not limited to silicon or other semiconductor materials. No special limitation is made on the shape and material of substrate 1 here.

[0141] In step S2, an insulating material layer 301 and a semiconductor material layer 302 are sequentially and alternately deposited on the substrate 1 to form a stacked structure 30.

[0142] Referring again to Figure 2, the stacked structure 30 may include multiple insulating material layers 301 and multiple semiconductor material layers 302, which may be alternately distributed along a direction perpendicular to the substrate 1 (i.e., the third direction z). In an exemplary embodiment of this disclosure, the insulating material layer 301 may be made of silicon oxide, and the semiconductor material layer 302 may be made of indium zinc oxide (IZO). The insulating material layer 301 and the semiconductor material layer 302 may be alternately deposited on the substrate 1 by means of chemical vapor deposition, physical vapor deposition, or atomic layer deposition. It should be noted that the film layer in the stacked structure 30 that is in contact with the substrate 1 is the insulating material layer 301, and the film layer in the stacked structure 30 that is farthest from the substrate 1 is also the insulating material layer 301.

[0143] In one exemplary embodiment of this disclosure, after forming the stacked structure 30, a protective layer 9 may be formed on the surface of the stacked structure 30. The protective layer 9 can prevent damage to the topmost insulating material layer 301 in the stacked structure 30 during subsequent etching. The material of the protective layer 9 is different from the material of the insulating material layer 301; for example, it may be silicon nitride.

[0144] In step S3, the stacked structure 30 is patterned to form a patterned stacked structure 40. The pattern of the patterned stacked structure 40 includes multiple first patterns 401 extending along the first direction x and spaced apart along the second direction y, and multiple second patterns 402 extending along the second direction y and spaced apart along the first direction x. The first direction x is parallel to the surface of the substrate 1, and the second direction y is parallel to the substrate 1 and intersects with the first direction x. The first patterns 401 and the second patterns 402 overlap.

[0145] The layered structure 30 can be patterned by etching. Please continue reading.Figure 4 As shown, the first mask layer 100 can be formed on the side of the laminated structure 30 away from the substrate 1. For example, when the protective layer 9 is formed on the surface of the laminated structure 30, the first mask layer 100 can be formed on the surface of the protective layer 9. Then, the first photoresist layer can be formed on the surface of the first mask layer 100. The first photoresist layer can be exposed and developed to form a developed pattern 50 corresponding to the first pattern 401 and the second pattern 402. Figure 6 As shown, the protective layer 9 and the laminated structure 30 can be anisotropically etched using the developed pattern 50 as a mask to form a patterned laminated structure 40. It should be noted that the developed pattern 50 and the first mask layer 100 can be removed after the patterned laminated structure 40 is formed, so that the surface of the protective layer 9 is exposed.

[0146] In some embodiments of the present disclosure, the first pattern 401 and the second pattern 402 are both strip-shaped, and the second direction y is perpendicular to the first direction x. In this case, the second pattern 402 is distributed perpendicularly to the first pattern 401.

[0147] In step S4, a plurality of first openings 403 extending through the patterned laminated structure 40 along a third direction z are formed. The first openings 403 are arranged one-to-one corresponding to the second patterns 402, and each first opening 403 divides the corresponding second pattern 402 into two sub-patterns 4021 distributed side by side along the first direction x in a mirror image manner. The third direction z is perpendicular to the first direction x and the second direction y, and the first openings 403 are parallel to the plane in which the second direction y and the third direction z lie.

[0148] The patterned laminated structure 40 can be etched to form the first openings 403 extending along the second direction y and penetrating the second patterns 402 along the third direction z. The number of the first openings 403 can be plural, and the plural first openings 403 are arranged one-to-one corresponding to the plural second patterns 402. Different first openings 403 are distributed apart along the first direction x and parallel to each other. In an embodiment of the present disclosure, the structure after step S4 is as shown in Figure 7 .

[0149] In an exemplary embodiment of the present disclosure, before forming the plural first openings 403 extending through the patterned laminated structure 40 along the third direction z, the method for manufacturing the structure of the semiconductor memory device of the present disclosure can further include:

[0150] In step S210, the voids of the patterned laminated structure 40 are filled with the insulating material 8.

[0151] The insulating material 8 can be the same material as the insulating material layer 301; for example, the insulating material 8 can be silicon oxide. The insulating material 8 can be filled within the patterned stacked structure 40 by methods such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition, filling the voids within the patterned stacked structure 40. Subsequently, the surface of the insulating material 8 away from the substrate 1 can be planarized to provide a flat process reference for subsequent processes. For example, the surface of the insulating material 8 away from the substrate 1 can be ground using a chemical mechanical polishing process to make the top surface of the filled insulating material 8 flush with the surface of the patterned stacked structure 40. When the top of the patterned stacked structure 40 is a protective layer 9, the surface of the insulating material 8 away from the substrate 1 can be made flush with the surface of the protective layer 9 away from the substrate 1. In this embodiment, the structure after step S210 is as follows: Figure 8 As shown.

[0152] In some embodiments of this disclosure, such as Figure 9 As shown, before forming the first opening 403, a protective material can be deposited on the surface of the structure jointly formed by the insulating material 8 and the protective layer 9 to form a new protective layer 9 (the new protective layer 9 consists of the original protective layer 9 on top of the patterned stacked structure 40 and the newly deposited protective material). The protective material is the same as the original protective layer 9 on top of the patterned stacked structure 40; for example, the protective material can be silicon nitride. A second mask layer 200 can be formed on the surface of the new protective layer 9, and a second photoresist layer 60 can be formed on the surface of the second mask layer 200. The second photoresist layer 60 is exposed and developed to form a plurality of first developing areas 6001 extending along the second direction y and spaced apart along the first direction x. In the first direction x, each first developing area 6001 is located in the middle region of each second pattern 402. The second mask layer 200 and the second pattern 402 can be etched in the first developing area 6001 to form a first opening 403 in the patterned stacked structure 40; the first opening 403 divides the second pattern 402 into two sub-patterns 4021 that are mirror-distributed along the first direction x.

[0153] It should be noted that after the first opening 403 is formed, the second photoresist layer 60 and the second mask layer 200 can be removed, thereby exposing the surface of the protective layer 9. The structure after removing the second photoresist layer 60 and the second mask layer 200 is as follows: Figure 7 As shown.

[0154] In step S5, a portion of the semiconductor material layer 302 is etched laterally to both sides through the first opening 403 to form a plurality of first transistor and word line receiving grooves. The first transistor and word line receiving grooves include a row of first transistor receiving grooves 404 extending along the first direction x and arranged along the second direction y, and word line receiving grooves 405 extending along the second direction y and communicating with the row of first transistor receiving grooves 404.

[0155] The semiconductor material layer 302 on both sides of the first opening 403 can be etched by an isotropic etching process to form a plurality of first transistors and word line accommodation grooves arranged along the third direction z. The word line accommodation groove 405 in the first transistor and the word line accommodation groove is located in the region where the sub-pattern 4021 of the second pattern 402 is located. The semiconductor material layer 302 in the region corresponding to the sub-pattern 4021 of the second pattern 402 can be completely etched to form the word line accommodation groove 405. The first transistor accommodation groove 404 is located in the region where the first pattern 401 is located. When the semiconductor material layer 302 is etched, the semiconductor material layer 302 corresponding to the first pattern 401 is not completely etched. The depth of the first transistor accommodation groove 404 is less than one half of the length of the first pattern 401 between two adjacent first openings 403. The etching depth of the first transistor accommodation groove 404 can be controlled by controlling the etching time during the etching process. In the embodiment of the present disclosure, the structure after step S5 is as shown in Figure 10 Figure 10 Figure 11

[0156] In step S6, a first semiconductor layer 103, a first gate dielectric layer 102 and a first gate material layer 1011 are sequentially deposited in the first transistor and the word line accommodation groove. The first semiconductor layer 103 covers the sidewall and bottom surface of the first transistor and the word line accommodation groove. The first gate dielectric layer 102 is formed on the surface of the first semiconductor layer 103. The first gate material layer 1011 fills the remaining space of the first transistor and the word line accommodation groove.

[0157] The material of the first semiconductor layer 103 can be indium gallium zinc oxide (IGZO) or single crystal silicon. The material of the first gate dielectric layer 102 can be a material with high dielectric constant, for example, the material can be aluminum oxide, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide or a mixture thereof. The material of the first gate material layer 1011 can be indium zinc oxide (IZO) or polysilicon. It should be noted that the material of the first gate material layer 1011 is matched with the material of the first semiconductor layer 103. For example, when the material of the first semiconductor layer 103 is indium gallium zinc oxide (IGZO), the material of the first gate material layer 1011 is indium zinc oxide (IZO). When the material of the first semiconductor layer 103 is single crystal silicon, the material of the first gate material layer 1011 is polysilicon.

[0158] In some embodiments of the present disclosure, as Figure 12 ​​​As shown, the first semiconductor layer 103, the first gate dielectric layer 102 and the first gate material layer 1011 can be sequentially deposited on the side of the protection layer 9 away from the substrate 1 by chemical vapor deposition, physical vapor deposition or atomic layer deposition, etc. In this process, the first semiconductor layer 103 can conformally cover the first transistor and the inner wall of the word line accommodation groove. In order to facilitate the process, the first semiconductor layer 103 can also cover the surface of the protection layer 9 and the sidewall of each insulating material layer 301 exposed in the first opening 403; the first gate dielectric layer 102 can conformally cover the surface of the first semiconductor layer 103, and the first gate material layer 1011 is located on the surface of the first gate dielectric layer 102 and can fill the remaining space of the first transistor and the word line accommodation groove. In this process, in order to ensure that the first gate material layer 1011 can fill the remaining space of the first transistor and the word line accommodation groove, the first gate material layer 1011 can also fill the first opening 403. Subsequently, the first gate material layer 1011 located in the first opening 403 and the first gate material layer 1011 located on the top of the protection layer 9 can be removed, and the structure after step S6 in the embodiment of the present disclosure is as shown in Figure 13

[0159] In step S7, the first gate material layer 1011 deposited in the word line accommodation groove 405 is etched to form the first gate 101 of the first transistor 10, and the word line material is filled into the word line accommodation groove 405 to form the word line 5 and the first transistor 10 located in the first transistor accommodation groove 404, and the word line 5 is in contact with the first gate 101; the first transistor 10 includes the first gate 101, the first gate dielectric layer 102 conformally covering the sidewall and one end of the first gate 101, and the first semiconductor layer 103 conformally covering the first gate dielectric layer 102, and the first semiconductor layer 103 includes the first source-drain region, the first channel region and the second source-drain region which are sequentially distributed along the first direction x.

[0160] The first gate material layer 1011 can be etched back by isotropic etching to remove the first gate material layer 1011 in the word line accommodation groove 405, and the first gate material layer 1011 in the first transistor accommodation groove 404 is taken as the first gate 101 of the first transistor 10, the first gate dielectric layer 102 covering the surface of the first gate 101 is taken as the first gate dielectric layer 102 of the first transistor 10, and the first semiconductor layer 103 covering the surface of the first gate dielectric layer 102 is taken as the active region of the first transistor 10, which can be divided into the first source-drain region, the first channel region and the second source-drain region which are sequentially distributed along the first direction x, wherein the region of the active region close to the word line accommodation groove 405 can be taken as the first source-drain region. The first gate 101, the first gate dielectric layer 102 and the first semiconductor layer 103 can jointly constitute the first transistor 10.

[0161] ​After the first gate 101 is formed, the word line material can be filled into the word line accommodating recess 405 to form the word line 5. The word line material can be a conductive material, which can be independently selected from at least one of tungsten, copper, aluminum, tungsten nitride, titanium, and titanium nitride. In an embodiment of the present disclosure, the structure after step S7 is shown in Figure 14 .

[0162] In an exemplary embodiment of the present disclosure, please continue to refer to Figure 13 , the word line 5 can include a conductive barrier material layer 51 and a metal material layer 52, wherein the conductive barrier material layer 51 can be located on the sidewall and bottom of the word line accommodating recess 405, i.e., the conductive barrier material layer 51 can be in contact with the first gate 101 at the bottom of the word line accommodating recess 405. The metal material layer 52 can fill the remaining space in the word line accommodating recess 405. It should be noted that, in the process of forming the conductive barrier material layer 51, the conductive barrier material layer can be simultaneously deposited on the top of the protection layer 9 and the sidewall of the first opening 403 for process convenience, and at the same time, the metal material layer 52 can also fill the first opening 403; then the metal material layer 52, the conductive barrier material layer 51, the first gate dielectric layer 102, and the first semiconductor layer 103 located on the top of the protection layer 9 and in the first opening 403 can be removed; and the remaining conductive barrier material layer 51 and the metal material layer 52 in the word line accommodating recess 405 can be used as the word line 5.

[0163] In an exemplary embodiment of the present disclosure, after the word line 5 is formed, the method for manufacturing the semiconductor memory device structure of the present disclosure can further include:

[0164] Step S220, filling the first opening 403 with the insulating material 8.

[0165] The insulating material 8 filled in the first opening 403 can be the same material as the insulating material layer 301, for example, the insulating material 8 can be silicon oxide. The insulating material 8 can be filled in the first opening 403 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition, etc., and in this process, for process convenience, the insulating material 8 can also cover the surface of the protection layer 9. Then the insulating material 8 can be subjected to chemical mechanical polishing, so that the insulating material 8 filled this time is flush with the surface of the protection layer 9 away from the substrate 1. In an embodiment of the present disclosure, the structure after step S220 is shown in Figure 15 .

[0166] In an exemplary embodiment of the present disclosure, after the first opening 403 is filled with the insulating material 8, a protection material can be deposited on the surface of the insulating material 8 and the protection layer 9, thereby forming a new protection layer 9, which is composed of the original protection layer 9 and the newly deposited protection material.

[0167] In step S8, a plurality of second openings 406 are formed through the patterned stack 40 along the third direction z, the second openings 406 are located at the middle position between two adjacent first openings 403, and the second openings 406 are parallel to the plane where the second direction y and the third direction z are located.

[0168] After the first openings 403 are filled with the insulating material 8, step S8 can be performed. The patterned stack 40 can be anisotropically etched to form a plurality of second openings 406 extending along the second direction y and through the patterned stack 40 along the third direction z, one second opening 406 can be formed between every two first openings 403; and in the first direction x, the second openings 406 are located at the middle position between two adjacent first openings 403. In the embodiment of the present disclosure, the structure after step S8 is shown in FIG. 4B. Figure 16

[0169] For example, a third mask layer can be formed on the surface of the new protective layer 9, a third photoresist layer can be formed on the surface of the third mask layer, the third photoresist layer can be etched to form a plurality of second developing areas, the second developing areas can be strips and can extend along the second direction y, one second developing area can be formed between every two first openings 403 on the patterned stack 40, and the orthographic projection of the second developing area on the patterned stack 40 is located at the middle position between two adjacent first openings 403. The third mask layer and the patterned stack 40 can be anisotropically etched in the second developing areas to form the second openings 406 through the patterned stack 40 along the third direction z. After the second openings 406 are formed, the third photoresist layer and the third mask layer can be removed.

[0170] In step S9, part of the insulating material layer 301 is etched away laterally to both sides through the second openings 406 to form a second gate 201 of a second transistor 20, and then a second gate dielectric layer 202 and a second semiconductor layer 203 are sequentially deposited, the second gate dielectric layer 202 conformally covers the sidewall of the second gate 201 and the end of the second gate 201 away from the first transistor 10, the second semiconductor layer 203 covers the surface of the second gate dielectric layer 202, and the second semiconductor layer 203 includes a third source-drain region, a second channel region and a fourth source-drain region distributed along the first direction x in sequence.

[0171] As shown in FIG. 4C. Figure 17 ​As shown, the insulating material layer 301 on both sides of the second opening 406 can be etched by an isotropic etching process to expose the sidewall of the semiconductor material layer 302 on both sides of the second opening 406. It should be noted that when the insulating material layer 301 is etched, the insulating material layer 301 corresponding to the first pattern 401 is not completely etched, and the exposed length of the semiconductor material layer 302 is less than half of the length of the insulating material layer 301 between two adjacent first openings 403. The exposed part of the semiconductor layer after etching the insulating material layer 301 can be used as the second gate 201 of the second transistor 20. It should be noted that in order to clearly show the structure of the second gate 201, only one row of second gates 201 distributed along the second direction y is shown. It can be understood that there are multiple rows of second gates 201 spaced apart along the second direction y. Figure 16

[0172] As shown, the insulating material layer 301 on both sides of the second opening 406 can be etched by an isotropic etching process to expose the sidewall of the semiconductor material layer 302 on both sides of the second opening 406. It should be noted that when the insulating material layer 301 is etched, the insulating material layer 301 corresponding to the first pattern 401 is not completely etched, and the exposed length of the semiconductor material layer 302 is less than half of the length of the insulating material layer 301 between two adjacent first openings 403. The exposed part of the semiconductor layer after etching the insulating material layer 301 can be used as the second gate 201 of the second transistor 20. It should be noted that in order to clearly show the structure of the second gate 201, only one row of second gates 201 distributed along the second direction y is shown. It can be understood that there are multiple rows of second gates 201 spaced apart along the second direction y. Figure 18 As shown, the insulating material layer 301 on both sides of the second opening 406 can be etched by an isotropic etching process to expose the sidewall of the semiconductor material layer 302 on both sides of the second opening 406. It should be noted that when the insulating material layer 301 is etched, the insulating material layer 301 corresponding to the first pattern 401 is not completely etched, and the exposed length of the semiconductor material layer 302 is less than half of the length of the insulating material layer 301 between two adjacent first openings 403. The exposed part of the semiconductor layer after etching the insulating material layer 301 can be used as the second gate 201 of the second transistor 20. It should be noted that in order to clearly show the structure of the second gate 201, only one row of second gates 201 distributed along the second direction y is shown. It can be understood that there are multiple rows of second gates 201 spaced apart along the second direction y.

[0173] In step S10, the insulating material 8 is filled between the adjacent second transistors 20 to seal the second opening 406; a plurality of third openings 81 penetrating the insulating material 8 along the third direction z are formed, the third openings 81 are located in the second opening 406, and the third openings 81 expose the fourth source / drain region in the second transistor 20, and the third openings 81 are parallel to the plane where the second direction y and the third direction z are located.

[0174] As shown, the insulating material layer 301 on both sides of the second opening 406 can be etched by an isotropic etching process to expose the sidewall of the semiconductor material layer 302 on both sides of the second opening 406. It should be noted that when the insulating material layer 301 is etched, the insulating material layer 301 corresponding to the first pattern 401 is not completely etched, and the exposed length of the semiconductor material layer 302 is less than half of the length of the insulating material layer 301 between two adjacent first openings 403. The exposed part of the semiconductor layer after etching the insulating material layer 301 can be used as the second gate 201 of the second transistor 20. It should be noted that in order to clearly show the structure of the second gate 201, only one row of second gates 201 distributed along the second direction y is shown. It can be understood that there are multiple rows of second gates 201 spaced apart along the second direction y. Figure 19 ​As shown, after the second transistors 20 are formed, the insulating material 8 can be filled between the adjacent second transistors 20 by chemical vapor deposition, physical vapor deposition, atomic layer deposition or the like, at this time, the insulating material 8 fills the second openings 406. In this process, for the convenience of process, the insulating material 8 can be deposited on the top of the protective layer 9 at the same time. After the insulating material 8 is filled in the second openings 406, the insulating material 8 on the top of the protective layer 9 can be removed, and the insulating material 8 can also be anisotropically etched along the third direction z to form a third opening 81 extending along the second direction y and penetrating through the insulating material 8 along the third direction z in the region corresponding to each second opening 406, and the third opening 81 can expose the fourth source / drain regions at the end of the second gate 201 in each second transistor 20. In the embodiment of the present disclosure, the structure after step S10 is as shown in Figure 20

[0175] In step S11, a source / drain layer 4 is formed in the third opening 81.

[0176] The material of the source / drain layer 4 can be a conductive material, for example, it can be at least one of tungsten, copper, aluminum, tungsten nitride, titanium, titanium nitride. The source / drain layer 4 can fill the third opening 81 and can be in contact with the fourth source / drain region of the second transistor 20. In the embodiment of the present disclosure, the structure after step S11 is as shown in Figure 21

[0177] In an exemplary embodiment of the present disclosure, forming the source / drain layer 4 in the third opening 81 (i.e. step S11) includes steps S310 and S320, wherein:

[0178] Step S310, forming a conductive barrier layer conformally covering the inner wall and bottom of the third opening 81.

[0179] The material of the conductive barrier layer can be a conductive material with ion blocking function, for example, it can be titanium nitride or tantalum nitride, etc. The conductive barrier layer can be formed on the sidewall and bottom of the third opening 81 by chemical vapor deposition, physical vapor deposition or atomic layer deposition, etc. The part of the conductive barrier layer on one sidewall of the third opening 81 can be taken as the first conductive barrier layer 41, and the part of the conductive barrier layer on the other sidewall of the third opening 81 can be taken as the second conductive barrier layer 43, and the first conductive barrier layer 41 and the second conductive barrier layer 43 can be connected through the conductive barrier layer at the bottom of the third opening 81. Of course, the conductive barrier layer can also be formed by other ways, which are not specially limited herein.

[0180] Step S320, depositing a conductive metal layer 42 in the third opening 81, and the conductive metal layer 42 fills the remaining space of the third opening 81.

[0181] ​​The conductive metal layer 42 can be made of a metal with good conductivity, such as tungsten. The metal material can be deposited within the third opening 81 with the conductive barrier layer using methods such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition to form the conductive metal layer 42. The conductive metal layer 42 and the conductive barrier layer together constitute the source / drain layer 4. The conductive barrier layer prevents metal ions in the conductive metal layer 42 from diffusing into other surrounding structures, thus helping to improve device reliability.

[0182] In step S12, a plurality of first bit line receiving holes 601 and second bit line receiving holes 701 extending along the third direction z are formed. A first bit line 6 is formed in the first bit line receiving hole 601 and a second bit line 7 is formed in the second bit line receiving hole 701. Each first bit line 6 covers the outer periphery of a row of first source / drain regions arranged along the third direction z in the same plane, and each second bit line 7 covers the outer periphery of a row of third source / drain regions arranged along the third direction z in the same plane.

[0183] In one exemplary embodiment of this disclosure, after the source / drain layer 4 is formed, a protective material may be deposited on the structure formed by the source / drain layer 4 and the protective layer 9 to form a new protective layer 9 (the new protective layer 9 consists of the original protective layer 9 and the newly deposited protective material), the protective material being the same as the original protective layer 9.

[0184] A fourth mask layer and a fourth photoresist layer can be formed on the surface of the new protective layer 9. The fourth photoresist layer can be etched to form multiple arrayed third developing areas, which can be rectangular, square, circular, or elliptical. Anisotropic etching can be performed on the fourth mask layer, protective layer 9, patterned stacked structure 40, and insulating material 8 filled in the patterned stacked structure 40 in the third developing areas to form multiple first bit-line accommodating holes 601 spaced apart along the second direction y and extending along the third direction z, and multiple second bit-line accommodating holes 701 spaced apart along the second direction y and extending along the third direction z. The first bit-line accommodating holes 601 can expose the surfaces of the first active regions arranged along the third direction z, and the second bit-line accommodating holes 701 can expose the surfaces of the third active regions arranged along the third direction z. After forming each first bit-line accommodating hole 601 and each second bit-line accommodating hole 701, the fourth photoresist layer and the fourth mask layer can be removed. In this embodiment of the present disclosure, the first line receiving hole 601 and the second line receiving hole 701 are as follows: Figure 22 and Figure 23 As shown.

[0185] The first bit line 6 can be formed in each first bit line accommodating hole 601, and the second bit line 7 can be formed in each second bit line accommodating hole 701. The material of the first bit line 6 and the second bit line 7 can be independently selected from at least one of tungsten, copper, aluminum, tungsten nitride, titanium, and titanium nitride. The first bit line 6 can be wrapped around the outer periphery of a row of first source-drain regions arranged in the same plane along the third direction z. Each second bit line 7 can be wrapped around the outer periphery of a row of third source-drain regions arranged in the same plane along the third direction z.

[0186] In an exemplary embodiment of the present disclosure, forming the first bit line 6 and the second bit line 7 can include forming a layer of conductive barrier material conformally covering the first bit line accommodating hole 601 and the second bit line accommodating hole 701, and filling the first bit line accommodating hole 601 and the second bit line accommodating hole 701 with a metal material to form a layer of metal material, where the material of the layer of conductive barrier material is titanium nitride, and the material of the layer of metal material is tungsten. The titanium nitride can prevent tungsten ions from diffusing into surrounding structures, which can help improve the reliability of the device. Figure 24

[0187] It should be noted that although the steps of the method of manufacturing the semiconductor memory device structure in the present disclosure are described in a particular order in the accompanying drawings, this does not require or imply that the steps must be performed in this particular order, or that all of the steps shown must be performed to achieve the desired result. Additionally or alternatively, some steps can be omitted, multiple steps can be combined into one step, and / or one step can be divided into multiple steps, etc.

[0188] Other embodiments of the present disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the features disclosed herein. The present disclosure is intended to cover any variations, uses, or adaptations of the present disclosure following, in general, the principles of the present disclosure and including such features to the extent that they are not disclosed in the prior art. The specification and examples are to be regarded as illustrative only, and the true scope and spirit of the present disclosure are indicated by the appended claims.​

Claims

1. A semiconductor common unit structure prepared on a substrate, characterized by, The semiconductor shared cell structure comprises: a first storage unit and a second storage unit, the first storage unit and the second storage unit are distributed in mirror image along a first direction, the first storage unit and the second storage unit share a same source-drain unit layer, and the first direction is parallel to a surface of the substrate; the first storage unit and the second storage unit each comprise: a first transistor located above a top surface of the substrate, the first transistor comprises a first gate, a first gate dielectric layer, and a first semiconductor layer, the first gate extends along the first direction, the first gate dielectric layer conformally covers side walls and an end of the first gate, the first semiconductor layer covers a surface of the first gate dielectric layer, and the first semiconductor layer comprises a first source-drain region, a first channel region, and a second source-drain region distributed along the first direction in sequence; a second transistor distributed along the first direction with the first transistor, the second transistor comprises a second gate, a second gate dielectric layer, and a second semiconductor layer, the second gate extends along the first direction, the second gate dielectric layer conformally covers side walls and an end of the second gate away from the first transistor, the second semiconductor layer covers a surface of the second gate dielectric layer, and the second semiconductor layer comprises a third source-drain region, a second channel region, and a fourth source-drain region distributed along the first direction in sequence; and the second source-drain region is electrically connected with the second gate; the fourth source-drain region in the first storage unit and the fourth source-drain region in the second storage unit are respectively connected to opposite surfaces of the source-drain unit layer.

2. The semiconductor common unit structure of claim 1, wherein, A plane in which the source-drain unit layer is located is perpendicular to the first direction, the source-drain unit layer comprises a first conductive barrier layer, a conductive metal layer, and a second conductive barrier layer stacked along the first direction in sequence; the fourth source-drain region in the first storage unit is connected with the first conductive barrier layer, and the fourth source-drain region in the second storage unit is connected with the second conductive barrier layer.

3. The semiconductor die structure of claim 2, wherein, Materials of the first conductive barrier layer and the second conductive barrier layer are both titanium nitride, and a material of the conductive metal layer is tungsten.

4. The semiconductor common unit structure of claim 1, wherein, Materials of the first gate and the second gate are both indium-zinc oxide, and materials of the first semiconductor layer and the second semiconductor layer are both indium-gallium-zinc oxide.

5. A semiconductor common block structure fabricated on a substrate, characterized by, The semiconductor shared cell structure comprises: a plurality of semiconductor shared cell structures as claimed in any one of claims 1-4 located on the substrate, the plurality of semiconductor shared cell structures are arranged along a second direction and a third direction, the second direction is parallel to the substrate and intersects the first direction, and the third direction is perpendicular to the first direction and the second direction; a plurality of word lines extending along the second direction and arranged along the first direction and the third direction, each of the word lines is connected with an end of a row of the first gates not covered by the first gate dielectric layer arranged along the second direction in a same plane; a plurality of first bit lines extending along the third direction and arranged along the first direction and the second direction, each of the first bit lines covers an outer periphery of a row of the first source-drain regions arranged along the third direction in a same plane; and a plurality of second bit lines extending along the third direction and arranged along the first direction and the second direction, each of the second bit lines being wrapped around an outer periphery of a row of the third source-drain regions arranged in the same plane along the third direction; a source-drain layer formed by sequentially connecting all the source-drain unit layers in the same plane.

6. The semiconductor copack structure of claim 5, wherein, The materials of the word lines, the first bit lines, and the second bit lines are independently selected from at least one of tungsten, copper, aluminum, tungsten nitride, titanium, and titanium nitride.

7. The semiconductor copack structure of claim 5, wherein, The word lines, the first bit lines, and the second bit lines each include a conductive barrier material layer and a metal material layer, the material of the conductive barrier material layer is titanium nitride, and the material of the metal material layer is tungsten.

8. A semiconductor memory device structure, characterized by, The semiconductor common block structure comprises: a substrate and a plurality of semiconductor common block structures as claimed in any one of claims 5-7 disposed on the substrate, the plurality of semiconductor common block structures being arranged along the first direction; adjacent two of the semiconductor common block structures are independently disposed.

9. A method of fabricating a semiconductor memory device structure, characterized by, The method comprises the following steps: providing a substrate; sequentially and alternately depositing an insulating material layer and a semiconductor material layer on the substrate to form a layer stack; performing a patterning process on the layer stack to form a patterned layer stack, the pattern of the patterned layer stack includes a plurality of first patterns extending along a first direction and spaced apart along a second direction, and a plurality of second patterns extending along the second direction and spaced apart along the first direction; the first direction is parallel to the surface of the substrate, the second direction is parallel to the substrate and intersects the first direction; the first patterns and the second patterns overlap each other; forming a plurality of first openings extending through the patterned layer stack along a third direction, the first openings are arranged one-to-one corresponding to the second patterns, and the first openings divide the corresponding second patterns into two sub-patterns which are mirror-symmetrically and side-by-side arranged along the first direction; the third direction is perpendicular to the first direction and the second direction, and the first openings are parallel to the plane in which the second direction and the third direction lie; laterally etching away part of the semiconductor material layer through the first openings to form a plurality of first transistors and word line containing grooves, the first transistors and word line containing grooves include a row of first transistor containing grooves extending along the first direction and arranged along the second direction, and word line containing grooves extending along the second direction and communicating with the row of first transistor containing grooves; sequentially depositing a first semiconductor layer, a first gate dielectric layer, and a first gate material layer in the first transistor and word line containing grooves; the first semiconductor layer covers the sidewalls and the bottom surface of the first transistor and word line containing grooves, the first gate dielectric layer is conformally deposited on the surface of the first semiconductor layer, and the first gate material layer fills the remaining space of the first transistor and word line containing grooves; etching away the first gate material layer deposited in the word line accommodation groove to form a first gate of a first transistor, and then filling the word line accommodation groove with word line material to form a word line and the first transistor in the first transistor accommodation groove, the word line being in contact with the first gate; the first transistor comprising the first gate, the first gate dielectric layer conformally covering the sidewall and one end of the first gate, and the first semiconductor layer conformally covering the first gate dielectric layer, the first semiconductor layer on the first gate comprising a first source-drain region, a first channel region and a second source-drain region arranged in sequence along the first direction; forming a plurality of second openings penetrating through the patterned layer stack along the third direction, the second openings being located at intermediate positions between adjacent two first openings, the second openings being parallel to the plane in which the second direction and the third direction lie; etching away part of the insulating material layer through the second openings to form a second gate of a second transistor, and then sequentially depositing a second gate dielectric layer and a second semiconductor layer, the second gate dielectric layer conformally covering the sidewall of the second gate and the end of the second gate away from the first transistor, the second semiconductor layer covering the surface of the second gate dielectric layer, and the second semiconductor layer comprising a third source-drain region, a second channel region and a fourth source-drain region arranged in sequence along the first direction; filling the insulating material between adjacent second transistors to seal the second openings; forming a plurality of third openings penetrating through the insulating material along the third direction, the third openings being located in the second openings, and the third openings exposing the fourth source-drain region in the second transistor, the third openings being parallel to the plane in which the second direction and the third direction lie; forming a source-drain layer in the third openings; forming a plurality of first bit line accommodation holes and second bit line accommodation holes extending along the third direction, forming a first bit line in the first bit line accommodation hole, and forming a second bit line in the second bit line accommodation hole; each first bit line covering the outer periphery of a row of first source-drain regions arranged in the same plane along the third direction, and each second bit line covering the outer periphery of a row of third source-drain regions arranged in the same plane along the third direction.

10. The method of producing a semiconductor memory device structure according to Claim 9, wherein Before the step of forming a plurality of first openings penetrating through the patterned layer stack along the third direction, the method further comprises: filling the voids of the patterned layer stack with insulating material.

11. The method of fabricating a semiconductor memory device structure of claim 9, wherein, After forming the word line and before forming the second openings, the method further comprises: filling the first openings with insulating material.

12. The method of fabricating a semiconductor memory device structure of claim 9, wherein, Forming a source-drain layer in the third openings comprises: forming a conductive barrier layer conformally covering the inner wall and bottom of the third opening; depositing a conductive metal layer in the third openings, the conductive metal layer filling the remaining space of the third openings.

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