Semiconductor element with programmable insulating layer and preparation method thereof

Abstract

The invention discloses a semiconductor element and a preparation method thereof. The semiconductor element comprises a substrate; the valley is concavely arranged on a top surface of the substrate; the programmable insulating layer is conformally arranged on the concave valley and comprises a V-shaped cross section profile; and the top electrode is arranged on the programmable insulating layer. The programmable insulating layer is configured to be burnt out at a programming voltage.

Description

[0001] This application claims priority to U.S. patent application No. 18 / 224,185 (i.e., the priority date is "July 20, 2023"), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates to a semiconductor element and a method for preparing the same, and in particular to a semiconductor element with a programmable insulating layer and a method for preparing the same. Background Art

[0003] Semiconductor components are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. The size of semiconductor components continues to shrink to meet the growing demand for computing power. However, in the process of shrinking, various problems have also emerged, and these problems are still increasing. Therefore, challenges still exist in improving quality, yield, performance and reliability, and reducing complexity.

[0004] The above “prior art” description only provides background technology, does not admit that the above “prior art” description discloses the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and any description of the above “prior art” should not be regarded as any part of this case. Summary of the invention

[0005] One aspect of the present disclosure provides a semiconductor device, comprising a substrate; a valley, which is concavely disposed on a top surface of the substrate; a programmable insulating layer, which is conformally disposed on the valley and comprises a V-shaped cross-sectional profile; and a top electrode, which is disposed on the programmable insulating layer. The programmable insulating layer is configured to be blown under a programming voltage.

[0006] Another aspect of the present disclosure provides a semiconductor device, comprising a substrate including an array region and a peripheral region adjacent to the array region; a valley disposed concavely on a top surface of the peripheral region of the substrate; a programmable insulating layer disposed conformally on the valley and comprising a V-shaped cross-sectional profile; a top electrode disposed on the programmable insulating layer; and a peripheral gate structure disposed on the top surface of the peripheral region of the substrate. The programmable insulating layer is configured to be blown at a programming voltage.

[0007] Another aspect of the present disclosure provides a method for preparing a semiconductor device, including providing a substrate; forming a bottom layer on the substrate; forming a mask layer on the bottom layer; forming a first protective layer on the bottom layer and covering the mask layer; removing a portion of the first protective layer to expose the mask layer; removing the mask layer to expose a portion of the bottom layer; using the first protective layer as a mask, removing a portion of the bottom layer to form an opening exposing a portion of the substrate; performing a valley etching process to remove a portion of the substrate and form a valley on a top surface of the substrate; conformally forming a programmable insulating layer on the valley; and forming a top electrode on the programmable insulating layer. The programmable insulating layer includes a V-shaped cross-sectional profile and is configured to be burned at a programming voltage.

[0008] Due to the design of the semiconductor element of the present disclosure, the programming voltage can be reduced by adopting a programmable insulating layer including a V-shaped cross-sectional profile. The reduction in programming voltage helps prevent potential damage to other elements of the semiconductor element that may be caused by a high programming voltage.

[0009] The above has been a fairly broad overview of the technical features and advantages of the present disclosure so that the detailed description of the present disclosure below can be better understood. Other technical features and advantages that constitute the subject matter of the patent application scope of the present disclosure will be described below. Those with ordinary knowledge in the technical field to which the present disclosure belongs should understand that the concepts and specific embodiments disclosed below can be used to modify or design other structures or processes to achieve the same purpose as the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that such equivalent constructions cannot depart from the spirit and scope of the present disclosure as defined by the attached patent application scope. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] When referring to the embodiments and the scope of the claims in combination with the drawings, a more comprehensive understanding of the disclosure of the present application can be obtained, in which the same element symbols in the drawings refer to the same elements.

[0011] Figure 1 is a flow chart illustrating a method for preparing a semiconductor element according to an embodiment of the present disclosure;

[0012] Figures 2 to 24 is a cross-sectional view illustrating a process of manufacturing a semiconductor device in one embodiment of the present disclosure; and

[0013] Figures 25 to 29 The cross-sectional views illustrate semiconductor devices in other embodiments of the present disclosure.

[0014]

Explanation of symbols

[0015] 1A: Semiconductor components

[0016] 1B: Semiconductor components

[0017] 1C: Semiconductor components

[0018] 1D: Semiconductor components

[0019] 1E: Semiconductor components

[0020] 1F: Semiconductor components

[0021] 10: Preparation method

[0022] 101: Base

[0023] 101TS: Top

[0024] 103-1: Character line groove

[0025] 103-3: Character line groove

[0026] 105: concave valley

[0027] 107: Isolation layer

[0028] 109: Well

[0029] 200: Character line structure

[0030] 201: word line dielectric layer

[0031] 201TS: Top

[0032] 203: word line bottom conductive layer

[0033] 205: word line top conductive layer

[0034] 207: Character line covering layer

[0035] 207TS: Top

[0036] 300: Peripheral gate structure

[0037] 301: Gate dielectric layer

[0038] 303: Gate bottom conductive layer

[0039] 303TS: Top surface

[0040] 305: Gate top conductive layer

[0041] 305TS: Top

[0042] 400: Programmable Structure

[0043] 401: Programmable insulation layer

[0044] 403: Top electrode

[0045] 403-1: Bottom

[0046] 403-1TS: Top

[0047] 403-3: Top

[0048] 403-3TS: Top

[0049] 403R: concave part

[0050] 511: first hard mask layer

[0051] 511TS: Top

[0052] 521: First protective layer

[0053] 523: Opening

[0054] 531: Bottom

[0055] 611: bottom conductive layer

[0056] 613: Encapsulation insulation layer

[0057] 615: bias conductive layer

[0058] 711: first insulating material

[0059] 713: Second insulating material

[0060] 713TS: Top

[0061] 715: first conductive material

[0062] 717: second conductive material

[0063] 717TS: Top

[0064] 721: first hard mask layer

[0065] 723: Second hard mask layer

[0066] 725: third hard mask layer

[0067] AR: Array Area

[0068] H1: Height

[0069] PR: Peripheral Area

[0070] S11: Steps

[0071] S13: Steps

[0072] S15: Steps

[0073] S17: Steps

[0074] T1: Thickness

[0075] T2: Thickness

[0076] T3:Thickness

[0077] VL1: Vertical Level

[0078] VL2: Vertical Level

[0079] VL3: Vertical Level

[0080] W1: Width

[0081] W2: Width

[0082] W3: Width

[0083] Z: Direction DETAILED DESCRIPTION

[0084] The following description of the present disclosure is accompanied by the accompanying drawings which are incorporated into and constitute a part of the specification, and illustrates an embodiment of the present disclosure, but the present disclosure is not limited to the embodiment. In addition, the following embodiments can be appropriately integrated to complete another embodiment.

[0085] "One embodiment", "embodiment", "illustrative embodiment", "other embodiments", "another embodiment", etc. refer to embodiments described in the present disclosure that may include specific features, structures or characteristics, but not every embodiment must include the specific features, structures or characteristics. Furthermore, repeated use of the phrase "in an embodiment" does not necessarily refer to the same embodiment, but may refer to the same embodiment.

[0086] In order to make the present disclosure fully understandable, the following description provides detailed steps and structures. Obviously, the implementation of the present disclosure will not be limited to the specific details known to those skilled in the art. In addition, the known structures and steps are no longer described in detail to avoid unnecessarily limiting the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to the detailed description, the present disclosure can also be widely implemented in other embodiments. The scope of the present disclosure is not limited to the content of the detailed description, but is defined by the scope of the patent application.

[0087] In the present disclosure, a semiconductor element generally refers to an element that can function by utilizing semiconductor characteristics, and electro-optical elements, light-emitting display elements, semiconductor circuits, and electronic elements all fall into the category of semiconductor elements.

[0088] It should be noted that, in the description of the present disclosure, the upper side (or up) corresponds to the direction of the arrow in the Z direction, and the lower side (or down) corresponds to the opposite direction of the arrow in the Z direction.

[0089] It should be noted that in the description of the present disclosure, the terms "form", "formed" and "form" may represent and include any method of creating, constructing, patterning, implanting or depositing elements, dopants or materials. Examples include atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering, co-sputtering, spin coating, diffusion, deposition, crystal growth, implantation, lithography, dry etching and wet etching, but are not limited thereto.

[0090] It should be noted that in the description of the present disclosure, the functions or steps mentioned herein may appear in a different order than the order marked in the drawings. For example, depending on the functions or steps involved, two figures shown in succession may actually be performed substantially simultaneously or may sometimes be performed in the reverse order.

[0091] Figure 1 1 is a flow chart illustrating a method 10 for manufacturing a semiconductor device 1A according to an embodiment of the present disclosure. Figures 2 to 24 2 is a cross-sectional view illustrating a manufacturing process of a semiconductor device 1A in one embodiment of the present disclosure.

[0092] Reference Figures 1 to 10 In step S11 , a substrate 101 including an array region AR and a peripheral region PR is provided, and a plurality of word line structures 200 are formed in the array region AR of the substrate 101 .

[0093] Reference Figure 2 The substrate 101 may be a bulk semiconductor substrate. The bulk semiconductor substrate may be formed of, for example, a single semiconductor such as silicon or germanium, or a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other III-V compound semiconductors or II-VI compound semiconductors. In some embodiments, the crystal orientation of the substrate 101 is <100> , <110> or <111> In some embodiments, the crystal orientation of the substrate 101 is <100> or <110> In some embodiments, the bottom of the substrate 101 may be amorphous, and only the top of the substrate 101 is single crystalline. The crystal orientation of the top of the substrate 101 is <100> , <110> or <111> .

[0094] Reference Figure 2, an isolation layer 107 is formed in the substrate 101. For example, the isolation layer 107 can be formed in the array region AR of the substrate 101. A series of deposition processes are performed to deposit a pad oxide layer (not shown) and a pad nitride layer (not shown) on the substrate 101. A lithography process and a subsequent etching process, such as an anisotropic dry etching process, are performed to form a plurality of trenches penetrating the pad oxide layer, the pad nitride layer and extending to the substrate 101. An insulating material can be deposited into the trenches, and then a planarization process, such as chemical mechanical polishing, is performed until the top surface 101TS of the substrate 101 is exposed to remove excess filling material, provide a substantially flat surface for subsequent processing steps, and form the isolation layer 107. The insulating material can be, for example, silicon oxide or other suitable insulating materials.

[0095] Reference Figure 3 , a first hard mask layer 511 is formed on the substrate 101. In some embodiments, the first hard mask layer 511 may be formed of a material having an etching selectivity to the substrate 101. In some embodiments, the first hard mask layer 511 may be formed of a material having an etching selectivity to the substrate 101 and the isolation layer 107. In some embodiments, the first hard mask layer 511 may be formed of, for example, silicon nitride, boron nitride, silicon boron nitride, boron phosphide, or silicon boron carbon nitride. In some embodiments, the first hard mask layer 511 may be formed by, for example, atomic layer deposition, chemical vapor deposition, or other applicable deposition processes.

[0096] In some embodiments, the first hard mask layer 511 may be formed by a film forming process and a treatment process. Specifically, in the film forming process, a first precursor (which may be a boron-based precursor) may be introduced onto the substrate 101 to form a boron-based layer. Subsequently, in the treatment process, a second precursor which is a nitrogen-based precursor may be introduced to react with the boron-based layer and convert the boron-based layer into the first hard mask layer 511.

[0097] In some embodiments, the first precursor may be, for example, diborane, borazine, or an alkyl-substituted derivative of borazine. In some embodiments, the first precursor may be introduced at a flow rate between about 5 standard cubic centimeters per minute (sccm) to about 50 standard liters per minute (slm) or between about 10 sccm and about 1 slm. In some embodiments, the first precursor may be introduced by a diluent gas such as nitrogen, hydrogen, argon, or a combination thereof. The diluent gas may be introduced at a flow rate between about 5 sccm and about 50 slm or between about 1 slm and about 10 slm.

[0098] In some embodiments, the film forming process may be performed without plasma assistance. In this case, the substrate temperature of the film forming process may be between about 100° C. and about 1000° C. For example, the substrate temperature of the film forming process may be between about 300° C. and about 500° C. The process pressure of the film forming process may be between about 10 mTorr and about 760 Torr. For example, the process pressure of the film forming process may be between about 2 Torr and about 10 Torr.

[0099] In some embodiments, the film forming process may be performed in the presence of plasma. In this case, the substrate temperature of the film forming process may be between about 100°C and about 1000°C. For example, the substrate temperature of the film forming process may be between about 300°C and about 500°C. The process pressure of the film forming process may be between about 10 mTorr and about 760 Torr. For example, the process pressure of the film forming process may be between about 2 Torr and about 10 Torr. The plasma may be generated by an RF power between 2W and 5000W. For example, the RF power may be between 30W and 1000W.

[0100] In some embodiments, the second precursor can be, for example, ammonia or hydrazine. In some embodiments, the second precursor can be introduced at a flow rate between about 5 sccm and about 50 slm or between about 10 sccm and about 1 slm.

[0101] In some embodiments, an oxygen-based precursor may be introduced with the second precursor during the treatment process. The oxygen-based precursor may be, for example, oxygen, nitric oxide, nitrous oxide, carbon dioxide, or water.

[0102] In some embodiments, a silicon-based precursor may be introduced during the process with the second precursor. The silicon-based precursor may be, for example, silane, trisilylamine, trimethylsilane, or a silazane (eg, hexamethylcyclotrisilazane).

[0103] In some embodiments, a phosphorus-based precursor may be introduced during the process with the second precursor. The phosphorus-based precursor may be, for example, phosphine.

[0104] In some embodiments, an oxygen-based precursor, a silicon-based precursor, or a phosphorus-based precursor may be introduced together with the second precursor during the treatment process.

[0105] In some embodiments, the treatment process may be performed with the assistance of a plasma process, a UV curing process, a thermal annealing process, or a combination thereof.

[0106] When the treatment process is performed with the assistance of a plasma process, the plasma of the plasma treatment can be generated by RF power. In some embodiments, the RF power can be between about 2W and about 5000W at a single low frequency between about 100 kilohertz (kHz) and about 1 megahertz (MHz). In some embodiments, the RF power can be between about 30W and about 1000W at a single high frequency greater than about 13.6MHz. In this case, the substrate temperature of the treatment process can be between about 20°C and about 1000°C. The process pressure of the treatment process can be between about 10mTorr and about 760Torr.

[0107] When the treatment is performed with the aid of a UV curing process, in this case, the substrate temperature of the treatment process can be between about 20°C and about 1000°C. The process pressure of the treatment process can be between about 10mTorr and about 760Torr. UV curing can be provided by any UV source, such as a mercury microwave arc lamp, a pulsed xenon flash lamp, or an array of high-efficiency UV light-emitting diodes. The UV source can have a wavelength between about 170 nanometers (nm) and about 400nm. The UV source can provide a photon energy between about 0.5eV and about 10eV, or between about 1eV and about 6eV. The assistance of the UV curing process can remove hydrogen from the first hard mask layer 511. Since hydrogen may diffuse to other areas of the semiconductor element 1A and may reduce the reliability of the semiconductor element 1A, the removal of hydrogen with the assistance of the UV curing process can improve the reliability of the semiconductor element 1A. In addition, the UV curing process can increase the density of the first hard mask layer 511.

[0108] When the treatment is performed with the assistance of a thermal annealing process, in this case, the substrate temperature of the treatment process may be between about 20° C. and about 1000° C. The process pressure of the treatment process may be between about 10 mTorr and about 760 Torr.

[0109] Reference Figure 3 A first hard mask layer 721 may be formed on the first hard mask layer 511 . In some embodiments, the first hard mask layer 721 may be a photoresist and may include a pattern of a plurality of word line structures 200 .

[0110] Reference Figure 4, an etching process is performed to remove a portion of the first hard mask layer 511. In some embodiments, in the etching process, an etching rate ratio of the first hard mask layer 511 to the substrate 101 may be between about 100:1 and about 2:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1. In some embodiments, in the etching process, an etching rate ratio of the first hard mask layer 511 to the isolation layer 107 may be between about 100:1 and about 2:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1. The pattern of the first hard mask layer 721 may be transferred to the first hard mask layer 511 and may be regarded as a first pattern 513. Portions of the isolation layer 107 and portions of the substrate 101 may be exposed through the first pattern 513. After the etching process, the first hard mask layer 721 may be removed by ashing or other applicable processes.

[0111] Reference Figure 5 , a trench etching process is performed using the first hard mask layer 511 as a mask to remove a portion of the isolation layer 107 and a portion of the substrate 101, and simultaneously form a plurality of word line trenches 103-1, 103-3. In some embodiments, the word line trench 103-1 formed in the substrate 101 may be shallower than the word line trench 103-3 formed in the isolation layer 107. In some embodiments, in the trench etching process, an etching rate ratio of the isolation layer 107 to the first hard mask layer 511 may be between about 100:1 and about 5:1, between about 15:1 and about 5:1, or between about 10:1 and about 5:1. In some embodiments, in the trench etching process, an etching rate ratio of the substrate 101 to the first hard mask layer 511 may be between about 80:1 and about 5:1, between about 10:1 and about 5:1, or between about 8:1 and about 5:1.

[0112] Reference Figure 6 , a layer of first insulating material 711 may be conformally formed on the first hard mask layer 511 and in the word line trenches 103-1, 103-3. The layer of first insulating material 711 may have a U-shaped cross-sectional profile in the word line trenches 103-1, 103-3. In some embodiments, the layer of first insulating material 711 may have a thickness in a range of about 1 nm to about 7 nm, including about 1 nm, about 2 nm, about 3 nm, about 4 nm, about 5 nm, about 6 nm, or about 7 nm.

[0113] In some embodiments, the layer of the first insulating material 711 can be formed by a thermal oxidation process. For example, the layer of the first insulating material 711 can be formed by oxidizing the surface of the word line trenches 103-1, 103-3. In some embodiments, the layer of the first insulating material 711 can be formed by a deposition process such as chemical vapor deposition or atomic layer deposition. The first insulating material 711 may include a high-k dielectric material, an oxide, a nitride, an oxynitride, or a combination thereof. In some embodiments, after depositing a liner polysilicon layer (not shown for clarity), the layer of the first insulating material 711 can be formed by free radical oxidation of the liner polysilicon layer. In some embodiments, after forming a liner silicon nitride layer (not shown for clarity), the layer of the first insulating material 711 can be formed by free radical oxidation of the liner silicon nitride layer.

[0114] In some embodiments, the high-k dielectric material may include a hafnium-containing material. The hafnium-containing material may be, for example, hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, or a combination thereof. In some embodiments, the high-k dielectric material may be, for example, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, silicon zirconium oxide, zirconium silicon oxynitride, aluminum oxide, or a combination thereof.

[0115] Reference Figure 7 , a plurality of word line bottom conductive layers 203 are formed in the word line trenches 103-1, 103-3 respectively. For example, a conductive material (not shown) may be formed to fill the word line trenches 103-1, 103-3. An etch-back process is then performed to partially remove the conductive material formed in the word line trenches 103-1, 103-3 and simultaneously form the word line bottom conductive layer 203. In some embodiments, the conductive material may be a work function material, such as titanium, titanium nitride, silicon, silicon germanium, or a combination thereof. It should be noted that the term "work function" refers to the overall chemical potential of a material (e.g., a metal) relative to a vacuum level.

[0116] For example, in the present embodiment, the conductive material is titanium nitride and can be formed by chemical vapor deposition. In some embodiments, the deposition of the conductive material can include a source gas introduction step, a first purge step, a reactant flow step, and a second purge step. The source gas introduction step, the first purge step, the reactant flow step, and the second purge step can be regarded as one cycle. Multiple cycles are performed to fill the word line trenches 103-1, 103-3.

[0117] In detail, Figure 6The intermediate semiconductor element shown can be loaded into a reaction chamber. In the source gas introduction step, a source gas containing a precursor and a reactant can be introduced into the reaction chamber containing the intermediate semiconductor element. The precursor and the reactant diffuse through the boundary layer and reach the surface of the intermediate semiconductor element. The precursor and the reactant can be adsorbed on the above-mentioned surface and then migrate on the above-mentioned surface. The adsorbed precursor and the adsorbed reactant can react on the above-mentioned surface and form solid by-products. The solid by-products can form nuclei on the above-mentioned surface. The nuclei can grow into multiple islands, and these islands can merge into a continuous film on the above-mentioned surface. In the first purge step, a purge gas such as argon can be injected into the reaction chamber to purge out gaseous by-products, unreacted precursors and unreacted reactants.

[0118] In the reactant flow step, only reactants may be introduced into the reaction chamber to convert the continuous film into a titanium nitride layer. In the second purge step, a purge gas such as argon may be injected into the reaction chamber to purge out gaseous byproducts and unreacted reactants.

[0119] In some embodiments, the deposition of the conductive material using chemical vapor deposition can be performed with the assistance of plasma. The plasma source can be, for example, argon, hydrogen, or a combination thereof.

[0120] For example, the precursor may be titanium tetrachloride. The reactant may be ammonia. Due to the incomplete reaction between titanium tetrachloride and ammonia, the titanium tetrachloride and ammonia may react on the surface and form a titanium nitride layer containing high chloride contamination. The ammonia in the reactant flow step may reduce the chloride content of the titanium nitride layer.

[0121] In some embodiments, during the etch-back process, an etch rate ratio of the wordline bottom conductive layer 203 to the first insulating material 711 may be between about 100:1 and about 5:1, between about 15:1 and about 5:1, or between about 10:1 and about 5:1.

[0122] Reference Figure 8, a plurality of word line top conductive layers 205 are formed in the plurality of word line trenches 103-1, 103-3. In some embodiments, the word line top conductive layer 205 may be formed of, for example, polysilicon, polycrystalline germanium, polycrystalline silicon germanium, doped polysilicon, doped polycrystalline germanium, doped polycrystalline silicon germanium, or a combination thereof. In some embodiments, the word line top conductive layer 205 may be doped with a p-type dopant or an n-type dopant. In some embodiments, a conductive material such as polysilicon, polycrystalline germanium, or polycrystalline silicon germanium may be deposited into the word line trenches 103-1, 103-3. An etch-back process may then be performed to remove a portion of the conductive layer to form the word line top conductive layer 205. In some embodiments, the dopant may be incorporated into the deposition process of the conductive material. In some embodiments, an implantation process is used to dope the dopant after the etch-back process.

[0123] The term "p-type dopant" refers to an impurity that creates a valence electron defect when added to an intrinsic semiconductor material. In silicon-containing semiconductor materials, p-type dopants include, but are not limited to, boron, aluminum, gallium, or indium. The term "n-type dopant" refers to an impurity that contributes free electrons to the intrinsic semiconductor material when added to the intrinsic semiconductor material. In silicon-containing materials, n-type dopants include, but are not limited to, antimony, arsenic, or phosphorus.

[0124] Reference Fig. 9 A word line capping layer 207 is formed on the first hard mask layer 511 to completely fill the word line trenches 103-1, 103-3. In some embodiments, the word line capping layer 207 may be formed of, for example, silicon nitride, silicon oxynitride, silicon oxynitride, or other applicable dielectric materials. In some embodiments, the word line capping layer 207 may be formed by, for example, chemical vapor deposition, plasma enhanced chemical vapor deposition, or other applicable deposition processes. A planarization process, such as chemical mechanical polishing, is performed to remove excess material and provide a substantially flat surface for subsequent processing steps.

[0125] It should be noted that silicon oxynitride in the present invention refers to a substance containing silicon, nitrogen and oxygen, wherein the proportion of oxygen is greater than the proportion of nitrogen. Silicon oxynitride refers to a substance containing silicon, oxygen and nitrogen, wherein the proportion of nitrogen is greater than the proportion of oxygen.

[0126] Reference Fig.10, a mask layer (not shown for clarity) may be formed over the array region AR of the substrate 101 to cover the word line capping layer 207 formed over the array region AR of the substrate 101. An etching process is performed to remove the word line capping layer 207, the layer of the first insulating material 711, and the first hard mask layer 511 formed over the array region AR of the substrate 101. The remaining first insulating material 711 may be considered as the word line dielectric layer 201. The word line dielectric layer 201, the word line bottom conductive layer 203, the word line top conductive layer 205, and the word line capping layer 207 together constitute the word line structure 200.

[0127] Reference Figure 1 and Figures 11 to 16 In step S13 , a bottom layer 531 is formed above the substrate 101 , a first protective layer 521 is formed on the bottom layer 531 , and a plurality of openings 523 are formed to expose a portion of the peripheral region PR of the substrate 101 .

[0128] Reference Fig.11 , the bottom layer 531 can be formed on the word line cover layer 207 and on the peripheral region PR of the substrate 101. In some embodiments, a planarization process is performed to remove excess material and provide a substantially flat surface for subsequent processing steps. In some embodiments, the bottom layer 531 may include a self-planarizing material, such as spin-on glass or spin-on low-k dielectric material. The use of a self-planarizing dielectric material can avoid the need to perform a subsequent planarization step. In some embodiments, the bottom layer 531 is configured as an anti-reflective layer. In some embodiments, the bottom layer 531 is composed of a thin film structure of alternating layers with contrasting refractive indices. The thickness T1 of the bottom layer 531 can be selected to produce destructive interference in a light beam reflected from an interface and constructive interference in a corresponding transmitted light beam. By way of example, but not limitation, the bottom layer 531 can be formed of, for example, an oxide, a sulfide, a fluoride, a nitride, a selenide, or a combination thereof. In some embodiments, the bottom layer 531 can improve the resolution of the lithography process. In some embodiments, the bottom layer 531 may be formed by a deposition process, including, for example, chemical vapor deposition, plasma enhanced chemical vapor deposition, evaporation, spin coating, or other suitable deposition processes.

[0129] Reference Fig.12 , a second hard mask layer 723 is formed on the bottom layer 531. The second hard mask layer 723 may be formed only over the peripheral region PR of the substrate 101. In some embodiments, the second hard mask layer 723 is a photoresist layer and includes a pattern of a plurality of programmable insulating layers 401 to be shown later.

[0130] Reference Fig.13, a first protective layer 521 may be formed to cover the bottom layer 531 and the second hard mask layer 723. In some embodiments, the first protective layer 521 is formed of a material having an etching selectivity to the bottom layer 531. In some embodiments, the first protective layer 521 is configured as a protective layer of the bottom layer 531 for subsequent semiconductor processes. In some embodiments, the first protective layer 521 may be formed of, for example, an oxide. In some embodiments, the first protective layer 521 may be a carbon film. The term "carbon film" is used herein to describe a material whose mass is mainly carbon, whose structure is mainly defined by carbon atoms, or whose physical and chemical properties are determined by its carbon content. The term "carbon film" is intended to exclude materials that simply contain mixtures or compounds of carbon, such as dielectric materials such as carbon-doped silicon oxynitride, carbon-doped silicon oxide, or carbon-doped polysilicon. In some embodiments, the first protective layer 521 may be composed of carbon and hydrogen. In some embodiments, the first protective layer 521 may be composed of carbon, hydrogen, and oxygen. In some embodiments, the first protective layer 521 may be composed of carbon, hydrogen, and fluorine.

[0131] In some embodiments, the carbon film may be deposited by a process comprising introducing into a process chamber a process gas mixture consisting of one or more hydrocarbon compounds having the formula C x H y , wherein x ranges from 2 to 4, and y ranges from 2 to 10. The hydrocarbon compound may be, for example, propylene, propyne, propane, butane, butene, butadiene or acetylene, or a combination thereof.

[0132] In some embodiments, a fluorine-doped first protective layer 521 can be formed by adding a fluorine source during a high-density plasma chemical vapor deposition process. The fluorine source can be, for example, octafluorocyclobutane, tetrafluoromethane, hexafluoroethane, octafluoropropane, trifluoromethane, hexafluorobenzene, or a combination thereof. The flow rate of the fluorine source can be between slightly greater than 0 and about 150 sccm. The flow ratio of the fluorine source to the carbon source is important for the doping level and thermal stability of the first protective layer 521. For an unbiased process, the flow rate ratio of the fluorine source to the carbon source can be between about 0.2 and about 2. For a biased process, the flow rate ratio of the fluorine source to the carbon source can be between about 0.7 and about 1.3.

[0133] In some embodiments, an annealing process is performed after the HDPCVD process to enhance the thermal stability of the first protective layer 521. The annealing process may be performed in a vacuum or in an inert atmosphere composed of a gas such as argon or nitrogen at a temperature between about 300° C. and about 450° C. for about 30 minutes.

[0134] The thickness and uniformity of the first protective layer 521 formed by the high-density plasma chemical vapor deposition process can be well controlled. For example, the standard deviation of the thickness of the first protective layer 521 can be less than 4%. In addition, the first protective layer 521 formed by the high-density plasma chemical vapor deposition process can be thermally stable at high temperatures up to about 400°C. Thermal stability means that the first protective layer 521 will not suffer weight loss, deformation, or chemical reaction when exposed to an etching environment with a temperature between about 200°C and about 400°C. The thermal stability of the first protective layer 521 at high temperatures will allow it to be used as a mask for etching operations performed at temperatures above 200°C. In addition, the anti-etching properties of the first protective layer 521 are adjusted by adjusting the doping level of fluorine. The anti-etching properties of the first protective layer 521 will decrease as the doping level of fluorine increases.

[0135] Reference Fig.14 , a recess process is performed to reduce the thickness of the first protection layer 521. In some embodiments, the recess process may include an etching process, a planarization process or a combination thereof. After the recess process, the second hard mask layer 723 will be exposed.

[0136] Reference Fig.15 , the second hard mask layer 723 is removed by an ashing process or other applicable semiconductor process. The mask layer (not shown) covering the array region AR of the substrate 101 can also be removed by an ashing process. After removing the second hard mask layer 723, an opening 523 is formed along the first protective layer 521 to expose a portion of the bottom layer 531 above the peripheral region PR of the substrate 101.

[0137] Reference Fig.16 An etching process is performed using the first protective layer 521 as a mask layer to remove a portion of the bottom layer 531. The etching process may extend the opening 523 to the bottom layer 531. Portions of the top surface 101TS of the peripheral region PR of the substrate 101 may be exposed through the opening 523.

[0138] Reference Figure 1 , Fig.17 and Fig.18 In step S15 , a valley etching process is performed to form a plurality of valleys 105 on the peripheral region PR of the substrate 101 .

[0139] Reference Fig.17In some embodiments, the valley etching process may be a wet etching process. In some embodiments, the valley etching process may include an etchant such as potassium hydroxide or sodium hydroxide. In some embodiments, when the crystal orientation of the substrate 101 is <110> When the valley etching process is performed using potassium hydroxide, isopropyl alcohol and water at a temperature between about 80° C. and 82° C. In some embodiments, when the crystal orientation of the substrate 101 is <110> When the valley etching process is performed, sodium hydroxide may be used to perform the valley etching process. After the valley etching process, a valley 105 is formed on the top surface 101TS of the peripheral region PR of the substrate 101. The valley 105 may include a V-shaped cross-sectional profile. In some embodiments, the valley 105 may be considered as a valley-shaped groove or a valley-shaped trench. In some embodiments, the crystal orientation of the valley 105 is <111> .

[0140] Reference Fig.18 , the first protective layer 521 and the bottom layer 531 are removed by a removal process. In some embodiments, in the removal process, the removal rate ratio of the first protective layer 521 to the substrate 101 may be between about 100:1 and about 5:1, between about 15:1 and about 5:1, or between about 10:1 and about 5:1. In some embodiments, in the removal process, the removal rate ratio of the bottom layer 531 to the substrate 101 may be between about 100:1 and about 5:1, between about 15:1 and about 5:1, or between about 10:1 and about 5:1.

[0141] Reference Figure 1 and Figures 19 to 24 In step S17 , a plurality of programmable insulating layers 401 are formed on the valleys 105 , a plurality of programmable top electrodes 403 are formed on the programmable insulating layers 401 , and a plurality of peripheral gate structures 300 are formed on the peripheral region PR of the substrate 101 .

[0142] Reference Fig.19, a layer of a second insulating material 713 is conformally formed on the top surface 101TS of the peripheral region PR of the substrate 101 and on the valleys 105. In some embodiments, the layer of the second insulating material 713 may include, for example, oxides, nitrides, oxynitrides, silicates (e.g., metal silicates), aluminates, titanates, nitrides, high-k dielectric materials, or combinations thereof. In some embodiments, the layer of the second insulating material 713 may be formed by a suitable deposition process, such as atomic layer deposition, chemical vapor deposition, plasma enhanced chemical vapor deposition, evaporation, chemical solution deposition, or other suitable deposition processes. In some embodiments, the layer of the second insulating material 713 may be formed by oxidizing the top surface 101TS of the substrate 101 and the plurality of valleys 105. In some embodiments, the thickness of the valleys 105 may vary depending on the deposition process and the composition and amount of the materials used. For example, the thickness of the layer of the second insulating material 713 may be between about 10 angstroms and about 50 angstroms. In some embodiments, the layer of the second insulating material 713 may include a multilayer structure. For example, the layer of the second insulating material 713 may be an oxide-nitride-oxide (ONO) structure. For another example, the layer of the second insulating material 713 may include a bottom layer formed of silicon oxide and a top layer formed of a high-k dielectric material.

[0143] Examples of high-k dielectric materials (dielectric constant greater than 7.0) include, but are not limited to, metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanate, barium titanium oxide, titanium strontium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. High-k dielectric materials may also include dopants such as lanthanum and aluminum.

[0144] In some embodiments, an interface layer (not shown) is optionally formed between the substrate 101 and the layer of the second insulating material 713. The interface layer can be formed of, for example, silicon oxide, silicon nitride, silicon oxynitride, other semiconductor oxides, or a combination thereof. The interface layer can be formed to any suitable thickness using any suitable process, including thermal growth, atomic layer deposition, chemical vapor deposition, high-density plasma chemical vapor deposition, spin-on deposition, or other suitable deposition processes. For example, the thickness of the interface layer can be between about 7 angstroms and 12 angstroms or between about 8 angstroms and 10 angstroms. The interface layer can promote the formation of the layer of the second insulating material 713.

[0145] Reference Fig.19 , the layer of second insulating material 713 formed on the valley 105 may include a V-shaped cross-sectional profile. In some embodiments, the top surface 713TS of the layer of second insulating material 713 may be at a vertical level VL1 that is lower than the vertical level VL2 of the top surface 511TS of the first hard mask layer 511 or the vertical level VL3 of the top surface 201TS of the word line dielectric layer 201.

[0146] Reference Fig. 20 , a layer of a first conductive material 715 is formed on the layer of the second insulating material 713. In some embodiments, the layer of the first conductive material 715 may be formed of, for example, polysilicon, polycrystalline germanium, polycrystalline silicon germanium, doped polysilicon, doped polycrystalline germanium, doped polycrystalline silicon germanium, or other suitable conductive materials. In some embodiments, the layer of the first conductive material 715 may be doped with a p-type dopant or an n-type dopant. In some embodiments, the layer of the first conductive material 715 formed in the valley 105 may include a triangular cross-sectional profile.

[0147] Reference Fig.21 , a layer of a second conductive material 717 is formed on the layer of the first conductive material 715. In some embodiments, the second conductive material 717 can be, for example, tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (e.g., titanium nitride), transition metal aluminides, or combinations thereof.

[0148] Reference Fig.21 , a planarization process such as chemical mechanical polishing is performed until the top surface 207TS of the word line cap layer 207 is exposed to remove excess material and provide a substantially flat surface for subsequent processing steps. That is, the top surface 717TS of the layer of second conductive material 717 and the top surface 207TS of the word line cap layer 207 can be substantially coplanar.

[0149] Reference Fig. 22 A third hard mask layer 725 is formed on the layer of the second conductive material 717 and on the word line cap layer 207. In some embodiments, the third hard mask layer 725 is a photoresist layer and includes a pattern having the programmable insulating layer 401 and the peripheral gate structure 300. Portions of the second conductive material 717, the first conductive material 715, and the second insulating material 713 formed above the valley 105 may be masked by the third hard mask layer 725.

[0150] Reference Fig.23, an etching process is performed using the third hard mask layer 725 as a mask to remove the second conductive material 717, the first conductive material 715, and the second insulating material 713 that are not masked by the third hard mask layer 725. In some embodiments, the etching process may be a multi-stage etching process. For example, the etching process may be a two-stage anisotropic dry etching process. The etching chemicals in each stage may be different to provide different etching selectivities. In some embodiments, in the first stage of the etching process, the etching rate ratio of the second conductive material 717 to the first conductive material 715 may be between about 100:1 and about 1.05:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1. In some embodiments, in the second stage of the etching process, the etching rate ratio of the first conductive material 715 to the second insulating material 713 may be between about 100:1 and about 1.05:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1.

[0151] Reference Fig.23 , the remaining second insulating material 713 may be transformed into a programmable insulating layer 401 and a plurality of gate dielectric layers 301. The programmable insulating layer 401 is conformally formed on the valley 105. The programmable insulating layer 401 may include a V-shaped cross-sectional profile. The gate dielectric layer 301 may be formed on the peripheral region PR of the substrate 101 and separated from the programmable insulating layer 401. The gate dielectric layer 301 includes a cross-sectional profile different from that of the programmable insulating layer 401. In the present embodiment, the gate dielectric layer 301 may include a linear cross-sectional profile. In some embodiments, the thickness T2 of the programmable insulating layer 401 and the thickness T3 of the gate dielectric layer 301 may be substantially the same. In some embodiments, the thickness T2 of the programmable insulating layer 401 and the thickness T3 of the gate dielectric layer 301 may be different from each other. In some embodiments, the width W1 of the programmable insulating layer 401 may be greater than or equal to the width W2 of the valley 105. In some embodiments, a ratio of a width W1 of the programmable insulating layer 401 to a height H1 of the programmable insulating layer 401 may be between about 3:1 and about 1:1.

[0152] Reference Fig.23, the remaining first conductive material 715 can be transformed into a plurality of bottom portions 403-1 and a plurality of gate bottom conductive layers 303. For the sake of brevity, clarity and convenience of description, only one bottom portion 403-1 and one gate bottom conductive layer 303 are described. The bottom portion 403-1 is formed on the corresponding programmable insulating layer 401. In some embodiments, the width W3 of the bottom portion 403-1 and the width W1 of the programmable insulating layer 401 can be substantially the same. In some embodiments, the bottom portion 403-1 can include a triangular cross-sectional profile. In some embodiments, at least a triangular cross-sectional profile is included where the bottom portion of the bottom portion 403-1 contacts the programmable insulating layer 401. The gate bottom conductive layer 303 can be formed on the corresponding gate dielectric layer 301. In some embodiments, the top surface 303TS of the gate bottom conductive layer 303 and the top surface 403-1TS of the bottom portion 403-1 can be substantially coplanar.

[0153] Reference Fig.23 , the remaining second conductive material 717 can be transformed into a plurality of top portions 403-3 and a plurality of gate top conductive layers 305. For the sake of brevity, clarity and convenience of description, only one top portion 403-3 and one gate top conductive layer 305 are described. The top portion 403-3 can be formed on the corresponding bottom portion 403-1. The top portion 403-3 can have the same width W3 as the bottom portion 403-1. The top portion 403-3 and the bottom portion 403-1 together constitute a top electrode 403. The top electrode 403 and the programmable insulating layer 401 together constitute a programmable structure 400. In some embodiments, the programmable structure 400 can be used as an anti-fuse.

[0154] The antifuse is non-conductive in the native unprogrammed state and becomes conductive when programmed. For example, the antifuse can be composed of a thin dielectric layer sandwiched between two conductors. In some embodiments, the substrate 101 can serve as a lower conductor of the programmable structure 400. The top electrode 403 can be used as an upper conductor of the programmable structure 400. The programmable insulating layer 401 can be used as a dielectric layer sandwiched between the lower conductor and the upper conductor. In the present embodiment, the programmable insulating layer 401 includes a V-shaped cross-sectional profile so that the top electrode 403 can include a tip portion that contacts the programmable insulating layer 401. During the programming process, charge accumulation may more easily occur at the tip portion of the top electrode 403. Therefore, the voltage required to program the programmable structure 400 (referred to as the programming voltage) can be reduced. The reduction in voltage helps prevent potential damage to other components of the semiconductor element 1A that may be caused by a high programming voltage.

[0155] Reference Fig.23, the gate top conductive layer 305 may be formed on the corresponding gate bottom conductive layer 303. The gate dielectric layer 301, the gate bottom conductive layer 303, and the gate top conductive layer 305 together constitute the peripheral gate structure 300. In some embodiments, the top surface 305TS of the gate top conductive layer 305 (i.e., the top surface of the peripheral gate structure 300), the top surface 403-3TS of the top portion 403-3 (i.e., the top surface of the top electrode 403), and the top surface 207TS of the word line cap layer 207 (i.e., the top surface of the word line structure 200) may be substantially coplanar.

[0156] Reference Fig.24 , the third hard mask layer 725 can be removed by an ashing process or other applicable semiconductor process. When programming the programmable structure 400, a programming voltage is applied to the top electrode 403, and the substrate 101 can be grounded so that the programmable insulating layer 401 sandwiched between the top electrode 403 and the substrate 101 can be compressed under the programming voltage. As a result, the tip portion (shown in a dotted circle) of the programmable insulating layer 401 will break to form a continuous path connecting the top electrode 403 and the substrate 101. In other words, the tip portion of the programmable insulating layer 401 can be burned off, and the programmable structure 400 is programmed. Due to the use of the programmable insulating layer 401 including a V-shaped cross-sectional profile, the programming voltage can be reduced. For example, the programming voltage can be between about +4.0 volts and about +5.5 volts, between about +4.0 volts and about +5.0 volts, or between about +4.0 volts and about +4.5 volts. The reduction in the programming voltage helps prevent potential damage to other components of the semiconductor element 1A that may be caused by a high programming voltage.

[0157] Figure 25 to Figure 29 2 is a cross-sectional view illustrating semiconductor devices 1B, 1C, 1D, 1E and 1F in some embodiments of the present disclosure.

[0158] Reference Fig.25 , the semiconductor element 1B may have Fig.24 The structure shown is similar to the structure. Fig.25 Zhongyu Fig.24 The same or similar elements have been marked with the same or similar marks, and repeated descriptions are omitted.

[0159] The semiconductor element 1B may include a plurality of bottom conductive layers 611. For the sake of brevity, clarity and convenience of description, only one bottom conductive layer 611 is used for illustration. The bottom conductive layer 611 may be disposed in the peripheral region PR of the substrate 101 and disposed below the corresponding programmable insulating layer 401. In some embodiments, the bottom conductive layer 611 is configured as a lower conductor of the programmable structure 400. In some embodiments, the bottom conductive layer 611 may be formed of, for example, doped silicon, doped germanium, or doped silicon germanium. In some embodiments, the bottom conductive layer 611 may be doped with an n-type dopant or a p-type dopant and may have a first conductivity type, such as a p-type or an n-type. In some embodiments, the width W4 of the bottom conductive layer 611 may be greater than or equal to the width W1 of the programmable insulating layer 401.

[0160] When programming the programmable structure 400, a programming voltage is applied to the top electrode 403, and the bottom conductive layer 611 is grounded so that the programmable insulating layer 401 sandwiched between the top electrode 403 and the bottom conductive layer 611 can be compressed under the programming voltage. Therefore, the tip portion (shown in a dotted circle) of the programmable insulating layer 401 will break to form a continuous path connecting the top electrode 403 and the bottom conductive layer 611. In other words, the tip portion of the programmable insulating layer 401 can be burned out, and the programmable structure 400 is programmed. Due to the use of the programmable insulating layer 401 including a V-shaped cross-sectional profile, the programming voltage can be reduced. For example, the programming voltage can be between about +4.0 volts and about +5.5 volts, between about +4.0 volts and about +5.0 volts, or between about +4.0 volts and about +4.5 volts. The reduction of the programming voltage helps to prevent potential damage to other components of the semiconductor element 1B that may be caused by a high programming voltage.

[0161] Reference Fig.26 , the semiconductor element 1C may have Fig.25 The structure shown is similar to the structure. Fig.26 Zhongyu Fig.25 The same or similar elements have been marked with like symbols, and repeated descriptions are omitted.

[0162] The semiconductor element 1C may include a plurality of encapsulating insulating layers 613. For the sake of brevity, clarity, and convenience of description, only one encapsulating insulating layer 613 is used for illustration. In some embodiments, the encapsulating insulating layer 613 is disposed in the peripheral region PR of the substrate 101 and may surround the corresponding bottom conductive layer 611. In some embodiments, the encapsulating insulating layer 613 is configured to electrically isolate the bottom conductive layer 611 from the substrate 101. In some embodiments, the encapsulating insulating layer 613 may be formed of, for example, silicon oxide, silicon nitride, or other applicable insulating materials.

[0163] Reference Fig. 27 , the semiconductor element 1D may have Fig.25 The structure shown is similar to the structure. Fig. 27 Zhongyu Fig.25 The same or similar elements have been marked with like symbols, and repeated descriptions are omitted.

[0164] The semiconductor element 1D includes a well 109. The well 109 may be disposed in the peripheral region PR of the substrate 101. A bottom conductive layer 611 is formed in the well 109. The well 109 may be doped with an n-type dopant or a p-type dopant. The well 109 has a second conductivity type different from the first conductivity type of the bottom conductive layer 611. The interface between the bottom conductive layer 611 and the well 109 may be regarded as a PN junction.

[0165] Reference Fig.28 , the semiconductor element 1E may have Fig. 27 The structure shown is similar to the structure. Fig.28 Zhongyu Fig. 27 The same or similar elements have been marked with like symbols, and repeated descriptions are omitted.

[0166] The semiconductor element 1E includes a bias conductive layer 615. The bias conductive layer 615 is disposed in the well 109 and is separated from the bottom conductive layer 611. In some embodiments, the bias conductive layer 615 is doped with the same type of dopant as the bottom conductive layer 611. That is, the bias conductive layer 615 may have the same conductivity type (i.e., the first conductivity type) as the bottom conductive layer 611. The bias conductive layer 615 may be configured to apply a bias voltage. The value of the bias voltage may be less than the value of the baseline voltage (e.g., the ground voltage of the bottom conductive layer 611). For example, the value of the bias voltage may be, for example, -1 volt, -2 volt, -3 volt, or any value between -0.5 volt and -3 volt. When the bias voltage is applied to the bias conductive layer 615 and the baseline voltage is applied to the bottom conductive layer 611, a depletion region (not shown) may be formed around the bottom conductive layer 611. The depletion region may be used as an electrical isolation of the bottom conductive layer 611.

[0167] Reference Fig.29 , the semiconductor element 1F may have Fig.24 The structure shown is similar to the structure. Fig.29 Zhongyu Fig.24 The same or similar elements have been marked with the same or similar marks, and repeated descriptions are omitted.

[0168] In the semiconductor element 1F, a recess 403R is provided on the top surface 403-1TS of the bottom portion 403-1. The top portion 403-3 may further include a tip portion (shown by a dotted circle) extending to the recess 403R.

[0169] One aspect of the present disclosure provides a semiconductor device, comprising a substrate; a valley, which is concavely disposed on a top surface of the substrate; a programmable insulating layer, which is conformally disposed on the valley and comprises a V-shaped cross-sectional profile; and a top electrode, which is disposed on the programmable insulating layer. The programmable insulating layer is configured to be blown under a programming voltage.

[0170] Another aspect of the present disclosure provides a semiconductor device, comprising a substrate including an array region and a peripheral region adjacent to the array region; a valley, which is concavely disposed on a top surface of the peripheral region of the substrate; a programmable insulating layer, which is conformally disposed on the valley and includes a V-shaped cross-sectional profile; a top electrode, which is disposed on the programmable insulating layer; and a peripheral gate structure, which is disposed on the top surface of the peripheral region of the substrate. The programmable insulating layer is configured to be blown at a programming voltage.

[0171] Another aspect of the present disclosure provides a method for preparing a semiconductor element, including providing a substrate; forming a bottom layer on the substrate; forming a mask layer on the bottom layer; forming a first protective layer on the bottom layer and covering the mask layer; removing a portion of the first protective layer to expose the mask layer; removing the mask layer to expose a portion of the bottom layer; using the first protective layer as a mask, removing a portion of the bottom layer to form an opening exposing a portion of the substrate; performing a valley etching process to remove a portion of the substrate and form a valley on a top surface of the substrate; conformally forming a programmable insulating layer on the valley; and forming a top electrode on the programmable insulating layer. The programmable insulating layer includes a V-shaped cross-sectional profile and is configured to be burned at a programming voltage.

[0172] Due to the design of the semiconductor element of the present disclosure, the programming voltage can be reduced by adopting the programmable insulating layer 401 including a V-shaped cross-sectional profile. The reduction in programming voltage helps prevent potential damage to other elements of the semiconductor element 1A that may be caused by a high programming voltage.

[0173] Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and replacements may be made without departing from the spirit and scope of the present disclosure as defined in the claims. For example, many of the above processes may be implemented in different ways, and other processes or combinations thereof may be used to replace many of the above processes.

[0174] Furthermore, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, material compositions, means, methods, and steps described in the specification. A person skilled in the art can understand from the disclosure of the present disclosure that existing or future developed processes, machines, manufactures, material compositions, means, methods, or steps that have the same functions or achieve substantially the same results as the corresponding embodiments described herein can be used according to the present disclosure. Accordingly, such processes, machines, manufactures, material compositions, means, methods, or steps are included in the scope of the patent application of the present application.

Claims

1. A semiconductor element, comprising: a base; a valley, which is concavely disposed on a top surface of the base; a programmable insulating layer conformally disposed on the valley and comprising a V-shaped cross-sectional profile; and a top electrode disposed on the programmable insulating layer; The programmable insulating layer is configured to be burned under a programming voltage. 2 . The semiconductor device as claimed in claim 1 , wherein the top electrode comprises a bottom portion disposed on the programmable insulating layer, and a top portion disposed on the bottom portion.

3. The semiconductor device as claimed in claim 2, wherein the programmable insulating layer comprises oxide, nitride, oxynitride, silicate, aluminate, titanate, nitride, high-k dielectric material or a combination thereof. 4 . The semiconductor device as claimed in claim 3 , further comprising a bottom conductive layer disposed in the substrate and contacting the programmable insulating layer. 5 . The semiconductor device as claimed in claim 4 , wherein the bottom portion comprises doped polysilicon, doped polycrystalline germanium, or doped polycrystalline silicon germanium.

6. The semiconductor device as claimed in claim 5, wherein the crystal orientation of the substrate is <110> , <100> or <111> .

7. The semiconductor device of claim 6, wherein the top portion comprises tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbide, metal nitride, transition metal aluminide, or a combination thereof. 8 . The semiconductor device as claimed in claim 7 , wherein a width of the bottom conductive layer is greater than or equal to a width of the programmable insulating layer. 9 . The semiconductor device as claimed in claim 8 , wherein the bottom conductive layer comprises an n-type dopant or a p-type dopant. 10 . The semiconductor device as claimed in claim 1 , wherein a ratio of a width of the programmable insulating layer to a height of the programmable insulating layer is between about 3:1 and about 1:

1.

11. A method for preparing a semiconductor element, comprising: providing a substrate; forming a bottom layer on the substrate; forming a mask layer on the bottom layer; forming a first protective layer on the bottom layer and covering the mask layer; removing a portion of the first protective layer to expose the mask layer; removing the mask layer to expose a portion of the bottom layer; Using the first protective layer as a mask, a portion of the bottom layer is removed to form an opening exposing a portion of the substrate; Performing a valley etching process to remove a portion of the substrate and form a valley on a top surface of the substrate; conformally forming a programmable insulating layer on the valley; and forming a top electrode on the programmable insulating layer; The programmable insulating layer includes a V-shaped cross-sectional profile and is configured to be burned under a programming voltage.

12. The method for preparing a semiconductor device as claimed in claim 11, wherein the crystal orientation of the substrate is <110> , <100> or <111> . 13 . The method for manufacturing a semiconductor device as claimed in claim 12 , wherein the valley etching process is a wet etching process. 14 . The method for manufacturing a semiconductor device as claimed in claim 13 , wherein the valley etching process comprises potassium hydroxide or sodium hydroxide. 15 . The method for fabricating a semiconductor device as claimed in claim 13 , wherein the programmable insulating layer comprises oxide, nitride, oxynitride, silicate, aluminate, titanate, nitride, high-k dielectric material or a combination thereof. 16 . The method for manufacturing a semiconductor device as claimed in claim 11 , wherein a ratio of a width of the programmable insulating layer to a height of the programmable insulating layer is between about 3:1 and about 1:1.

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