L-shaped gate three-dimensional HK groove LDMOS transistor

Abstract

The invention provides a three-dimensional HK groove LDMOS transistor with an L-shaped grid electrode. The transistor comprises a substrate layer, a buried oxide layer, a silicon film layer and a device top layer which are sequentially stacked from bottom to top. The silicon film layer comprises a drift region, and a grid electrode, a source region, an HK thin film, an oxidation groove, a silicon body and a drain region which are arranged above the drift region. The drain region is located at the corner of the top surface of the drift region; the cross sections of the oxidation groove, the source region and the grid electrode are L-shaped, and are sequentially arranged in a semi-surrounding structure along the direction far away from the drain region. And the silicon body has the same shape as the cross section of the source region and is arranged between the source region and the drift region. And the HK thin film wraps the periphery of the oxidation groove. By using the L-shaped semi-surrounded structure, the area of the grid electrode is greatly expanded, so that the current circulation path is expanded, the current in the device is increased, and the on-state resistance of the device is effectively reduced.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor high-voltage power integrated circuit special devices, and in particular relates to a three-dimensional HK-Trench LDMOS transistor with an L-shaped gate. Background Art

[0002] With the rapid development of the digital, information and intelligent technology era, various electronic products are constantly pouring into social life. Moreover, the hard-core updates and upgrades of various types of chips in electronic products are constantly driving the development of technology. In recent years, the country has vigorously developed the semiconductor industry. In key areas such as equipment manufacturing, rail transportation, national defense, solar energy, wind energy, new energy, laser and other modern processing technologies, high-voltage power semiconductor devices as core power electronic devices have been widely used and popularized. The direction of modern high-voltage power semiconductor devices is mainly concentrated in high current, high voltage, high frequency, integration and intelligence to meet the demand for power electronic devices in the field of high frequency and high voltage. Lateral double diffused metal oxide semiconductor (LDMOS) is used as a core power device and is widely used because it is easier to integrate with TTL chips and low-voltage MOSFETs into power integrated circuits. However, due to BV and R on The silicon limit problem derived from the mutual limitation of the two is the bottleneck that prevents the performance of LDMOS devices from being further improved. In the design of lateral LDMOS devices, RESURF technology, field plate technology and super junction technology can effectively reduce the R of the device while increasing the breakdown voltage. on , effectively improving the silicon limit problem. However, due to its large chip area, the lateral LDMOS device has limitations in reducing the device's specific on-resistance. Based on this idea, trench technology was introduced into the device, which greatly reduced the distance from the source to the drain in the lateral direction in a manner similar to a folded drift region, so that the device can effectively reduce the chip area while greatly improving the device's specific on-resistance. This paper proposes a three-dimensional trench LDMOS device with an L-shaped gate and HK dielectric and a new structural layout. Compared with the traditional trench LDMOS with HK composite dielectric film, the L-shaped gate can greatly expand the current flow path under the same chip area. At the same time, the HK composite dielectric trench assists in depleting the drift region, increases the doping concentration of the drift region, enhances the RESURF effect inside the device, and reduces the device's R while increasing the breakdown voltage. on In addition, the process complexity is hardly increased when making L-shaped and HK composite dielectric trenches, and the performance of trench LDMOS devices can be improved in a relatively simple structural design. Summary of the invention

[0003] The object of the present invention is to provide a three-dimensional lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor based on a silicon-on-insulator (SOI) substrate with an L-shaped gate and an HK dielectric trench.

[0004] The three-dimensional HK trench LDMOS transistor with an L-shaped gate provided by the present invention comprises a substrate layer, a buried oxide layer, a silicon film layer and a device top layer stacked in sequence from bottom to top. The silicon film layer comprises a drift region, and a gate, a source region, an HK film, an oxidation trench, a silicon body and a drain region arranged above the drift region. The drain region is located at the corner of the top surface of the drift region; the cross-sections of the oxidation trench, the source region and the gate are all L-shaped, and are arranged in a semi-enclosed structure in sequence along the direction away from the drain region. The silicon body has the same cross-sectional shape as the source region and is arranged between the source region and the drift region. The HK film is wrapped around the oxidation trench.

[0005] Preferably, the cross section of the three-dimensional HK trench LDMOS transistor is a 6.5 μm×6.5 μm square.

[0006] Preferably, the oxidation groove wrapping the HK film has a depth of 6.5 μm-8.5 μm (preferably 7.5 μm), a lateral width of 2.7 μm-4.5 μm (preferably 3.5 μm), and a spacing of 0.6 μm-1 μm (preferably 0.8 μm) from the outer side of the gate.

[0007] Preferably, the HK film wraps the sidewalls and bottom of the oxidation groove; the K value of the HK film is 100-500 (preferably 500 μm), the sidewall thickness is 200nm-700nm (preferably 500nm), and the bottom thickness is 440nm-720nm (preferably 560nm).

[0008] Preferably, the gate is made of polysilicon, the doping type is N-type, and the doping concentration is 1×10 19 cm -3 ~1×10 20 cm -3 . .

[0009] Preferably, the drift region is doped with N-type doping and the doping concentration is 7×10 15 cm -3 ~1.4×10 16 cm -3 .

[0010] Preferably, the top layer of the device includes a gate electrode, a source electrode and a drain electrode, all of which are L-shaped; the gate electrode is arranged on the top of the gate; the source electrode is arranged on the top of the source region; and the drain electrode is arranged on the top of the drain region.

[0011] Preferably, the doping type of the substrate layer is P type, and the doping concentration is 1×10 14 cm -3 ~7×10 14 cm -3 of silicon material.

[0012] Preferably, the buried oxide layer is made of silicon dioxide with a thickness of 0.3 μm to 1 μm.

[0013] Preferably, the gate is isolated from the source region, the silicon body and the drift region by a gate oxide layer; the source region near the gate is made of silicon material, the region near the gate is doped with N type, and the region near the oxidation trench is doped with P type.

[0014] Preferably, the thickness of the gate oxide layer is 0.05 μm; the lateral width of the gate is 0.25 μm, and the longitudinal thickness is 1.15 μm.

[0015] The present invention has the following beneficial effects: 1. The present invention adopts an L-shaped gate, and arranges the drain region, oxidation trench, source region, and gate in an L-shaped semi-enclosed structure in sequence, which greatly expands the gate area set by the traditional LDMOS device, so that the gate area of ​​the device proposed by the present invention is almost twice that of the traditional structure, thereby expanding the current flow path, increasing the current inside the device, and effectively reducing the on-state resistance R of the device. on .

[0016] 2. The HK film wrapped around the oxide trench used in the present invention can adjust the electric flux distribution in the device body, so that the drift region can accommodate more charges, enhance the RESURF effect inside the device, and increase the breakdown voltage of the device while increasing the doping concentration of the drift region. The higher drift region concentration also significantly reduces the on-state resistance R of the device. on。 BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a diagram of the three-dimensional device structure of Example 1 of the present invention.

[0018] Figure 2 This is a side structural diagram of Example 1 of the present invention.

[0019] Figure 3 This is a three-dimensional device structure diagram of comparative example 1 of the present invention.

[0020] Figure 4 This is a comparison diagram of the electric fields of Example 1 of the present invention and Comparative Example 1 (part a is the comparison of the lateral electric field on the surface of the silicon film, and part b is the comparison of the electric fields along the directions of O1, O2, O3, and O4).

[0021] Figure 5 These are potential distribution diagrams of Example 1 and Comparative Example 1 of the present invention (Part a is the xoy surface potential distribution diagram of Example 1, and Part b is the xoy surface potential distribution diagram of Comparative Example 1).

[0022] Figure 6 These are the three-dimensional electric field diagrams of the device surfaces of Example 1 and Comparative Example 1 of the present invention (part a is the three-dimensional electric field diagram of the surface of Example 1, and part b is the three-dimensional electric field diagram of the surface of Comparative Example 1).

[0023] Figure 7 It is a comparison diagram of the longitudinal electric field below the drain terminal of Example 1 of the present invention and Comparative Example 1, and a distribution diagram of the hole density on the surface of the buried oxide layer along the x-direction (Part a is a comparison diagram of the longitudinal electric field below the drain terminal of Example 1 and Comparative Example 1, and Part b is a distribution diagram of the hole density on the surface of the buried oxide layer along the x-direction of Example 1 and Comparative Example 1).

[0024] Figure 8 It is a comparison diagram of the effect of drift region concentration on device performance of Example 1 and Comparative Example 1 (Part a is a comparison diagram of the effect of drift region concentration on device performance of Comparative Example 1, and Part b is a comparison diagram of the effect of drift region concentration on device performance of Example 1).

[0025] Fig. 9 This is a comparison chart of the effect of ambient temperature on device performance in Example 1 and Comparative Example 1.

[0026] Fig.10 It is a comparison diagram of the influence of the position of point O1 on the left side of the groove, the groove depth and the width of the groove along the x-direction on the device performance of Example 1 (part a is a comparison diagram of the influence of the position of point O1 on the left side of the groove on the device performance of Example 1, part b is a comparison diagram of the influence of the groove depth on the device performance of Example 1, and part c is a comparison diagram of the influence of the width of the groove along the x-direction on the device performance of Example 1).

[0027] Fig.11 This is a comparison chart of the effect of HK film thickness on device performance in Example 1 (part a is a comparison chart of the effect of HK film sidewall thickness on device performance, and part b is a comparison chart of the effect of HK film bottom thickness on device performance).

[0028] Fig.12 This is a comparison chart of the effect of the K value of the HK film in Example 1 on the device performance.

[0029] Fig.13This is a comparison chart of the effect of interface charge on device performance between Silicon / HK and HK / SiO2 in Example 1.

[0030] Fig.14 The output characteristic curve diagram of Example 1 and Comparative Example 1.

[0031] Fig.15 The transfer characteristic curves and transconductance curves of Example 1 and Comparative Example 1 are shown.

[0032] Fig.16 It is a performance comparison chart of Example 1 and related achievements in the field. DETAILED DESCRIPTION

[0033] The present invention is further described below with reference to the accompanying drawings and examples.

[0034] like Figure 1 and Figure 2 As shown, the three-dimensional HK trench LDMOS transistor with an L-shaped gate includes a substrate layer 10, a buried oxide layer 6, a silicon film layer and a device top layer which are stacked in sequence from bottom to top.

[0035] The overall x-direction and z-direction dimensions of the LDMOS transistor are both 6.5 μm, and the overall thickness is 6.5 μm; the buried oxide layer has a thickness of 0.3 μm and a width of 6.5 μm; and the substrate layer has a thickness of 5 μm and a width of 6.5 μm.

[0036] The substrate layer 10 is disposed at the bottom of the LDMOS transistor and has a P-type doping type and a doping concentration of 7×10 14 cm -3 The substrate layer 10 is made of silicon material, and the width of the substrate layer 10 is 6.5 μm. The substrate layer 10 is provided with a buried oxide layer 6, and the buried oxide layer 6 is made of SiO2 with a thickness of 0.3 μm.

[0037] The silicon film layer is located above the buried oxide layer 6; the silicon film layer includes a drift region 5, and a gate 4, a source region 1, an HK film 11, an oxidation trench 3, a silicon body 2 and a drain region 12 arranged above the drift region 5. The drain region 12 is located at the corner of the top surface of the drift region; the cross sections of the oxidation trench 3, the source region 1, the silicon body 2 and the gate 4 are all L-shaped; starting from the location of the drain region 12, the oxidation trench 3, the source region 1 and the gate 4 are arranged in sequence in a direction away from the drain region 12, and the turning positions are connected into a straight line, and the cross-sectional area size gradually expands, presenting a structure that is similar to a fan-shaped and gradually diffuses.

[0038] The top surfaces of the oxidation trench 3 , the source region 1 , and the gate 4 are flush; the cross-sectional shapes of the source region 1 and the silicon body 2 are the same. The silicon body 2 is disposed between the source region 1 and the drift region 5 .

[0039] The bottom surface and inner and outer side surfaces of the oxidation trench 3 are all covered with a HK film 11. The HK film 11 separates the oxidation trench 3 from the source region 1, the silicon body 2, the drain region 12 and the drift region 5.

[0040] The gate 4 is separated from the source region 1 , the silicon body 2 , and the drift region 5 by a gate oxide layer.

[0041] The gate 4 is made of polysilicon, with an N-type doping concentration of 1×10 20 cm -3 , surrounding the outside of the source region 1; the gate oxide layer is a SiO2 layer with a thickness of 0.05μm; the lateral width of the gate 4 is 0.25μm and the longitudinal thickness is 1.15μm.

[0042] The doping concentration of the source region 1 near the gate 4 is 1×10 20 cm -3 , the doping type is N-type silicon material; the area of ​​the source region 1 close to the half width of the oxidation trench 3 is doped with a concentration of 1×10 20 cm -3 , the doping type is P-type silicon material. The width of the source region 1 is 0.5 μm, and the thickness is 0.5 μm.

[0043] The HK film 11 is made of HK material (High-k material, high dielectric constant material) with a sidewall thickness of 500 nm, a bottom thickness of 560 nm, and a K value of 500, and surrounds the outside of the oxidation trench 3 .

[0044] The oxidation trench 3 is made of silicon dioxide material with a width of 2.5 μm and a thickness of 6.94 μm; the silicon body 2 is made of silicon material with a width of 0.5 μm and a thickness of 0.5 μm, and the doping type is P type with a doping concentration of 1×10 17 cm -3 .

[0045] The doping concentration of the drain region 12 is 1×10 20 cm -3 , the doping type is N-type, the width is 2.2μm, the thickness is 0.5μm; the doping concentration in the drift region is 1.2×10 16 cm -3 , the doping type is N type; The top layer of the device includes a gate electrode 7 , a source electrode 8 and a drain electrode 9 ; the gate electrode 7 is located above the gate 4 , the source electrode 8 is located above the source region 1 , and the drain electrode 9 is located above the drain region 12 .

[0046] Comparative Example 1 like Figure 3As shown, a silicon-on-insulator LDMOS transistor (CHKT SOI) is shown. The difference between this comparative example and Example 1 is that: the structure is a two-dimensional structure device, and the cross sections of the oxidation trench 3, the source region 1, the silicon body 2, and the gate 4 are all linear; the oxidation trench 3, the source region 1, and the gate 4 are arranged in sequence along the direction away from the drain region 12, and are arranged in sequence along the x direction, and the structural distribution of different cross sections in the z direction is exactly the same.

[0047] According to the test, the optimal doping concentration of the drift region 5 in the structure of this comparative example is 4.6×10 15 cm -3 .

[0048] The horizontal direction is set as the X-axis direction, the vertical direction (i.e., the device thickness direction) is set as the Y-axis direction, the direction of the three-dimensional device extension is set as the Z-direction, and the topmost point of the outer longitudinal interface of the gate 4 is set as the origin O. Based on the three-dimensional Sentaurus TCAD software simulation, a performance comparison test is conducted on Example 1 and Comparative Example 1. In the simulation study, the substrate layer 10 and the source electrode 1 are both grounded.

[0049] According to the test results, the following description is provided to show that Example 1 is significantly superior to Comparative Example 1: According to the above parameters, simulation is performed to obtain curves of the electric field on the silicon film layer of the LDMOS transistor provided in Example 1 (LG-HKT SOI) and Comparative Example 1 (CHKT SOI) as a function of the lateral position. Figure 4 As shown in part a of Figure 4 It can be seen from part a of : Example 1 can introduce a higher electric field on the surface of the silicon film layer, and has a stronger lateral withstand voltage capability than Comparative Example 1, so that it will not be limited by the lateral breakdown voltage, and the breakdown voltage of the device depends on the more real internal withstand voltage; and from Figure 4 It can be seen from part b that the electric field surrounding the trench in Example 1, i.e., the electric field of O1O2O3O4, is significantly higher than that in Comparative Example 1. Therefore, for the trench device, the electric field distribution at the interface can more directly reflect the breakdown voltage of the device.

[0050] The device potential distribution diagrams of Example 1 (LG-HKT SOI) and Comparative Example 1 (CHKT SOI) are shown in FIG. Figure 5 As shown in part a and part b of . It can be seen from the figure that the potential distribution of Example 1 is more uniform than that of Comparative Example 1, and thus has a stronger RESURF effect, effectively improving the breakdown voltage of the device.

[0051] The three-dimensional electric field diagrams of the device surfaces of Example 1 (LG-HKT SOI) and Comparative Example 1 (CHKT SOI) are shown in FIG. Figure 6The L-shaped gate in Example 1 effectively alleviates the problem of lower electric field distribution in Comparative Example 1, making the electric field distribution on the device surface more uniform and better regulating the surface electric field.

[0052] The longitudinal electric field comparison diagram below the drain terminal of the device of Example 1 (LG-HKT SOI) and Comparative Example 1 (CHKT SOI) is shown in FIG. Figure 7 As shown in part a of FIG. 1 , it can be seen from the figure that the electric field of Example 1 in the silicon film layer is higher than that of Comparative Example 1, while the electric field in the buried oxide layer is lower than that in Comparative Example 1. This is because the hole density distribution at the interface between the buried oxide layer and the silicon film layer in Comparative Example 1 is significantly higher than that in Example 1. Specifically, the hole density distribution is Figure 7 is described in part b of .

[0053] Figure 8 Part a and part b of the figure describe the influence of the drift region concentration on the breakdown voltage, on-resistance and FOM value of Example 1 and Comparative Example 1. It can be seen that when the drift region concentration of Example 1 is 7×10 15 cm -3 -1.4×10 16 cm -3 The best performance is achieved when the concentration in the drift region is 2.5×10 15 -7.5×10 15 cm -3 Compared with comparative example 1, embodiment 1 has the best performance. The breakdown voltage is increased by 11.3%, the on-resistance is reduced by 38%, and it has a higher FOM value.

[0054] Fig. 9 A comparison diagram of the effect of ambient temperature on the performance of Example 1 and Comparative Example 1 is described. As can be seen from the figure, compared with Comparative Example 1, Example 1 has more stable performance under different ambient temperatures, and is therefore more adaptable to extreme environments.

[0055] Example 2 The process of determining the optimal values ​​of key parameters in the three-dimensional HK trench LDMOS transistor with an L-shaped gate provided in Example 1 is as follows: By changing the doping concentration of the drift region of the LDMOS transistor provided in Example 1, the position of the left side of the trench, the trench depth, the lateral width of the trench, the side wall thickness of the HK film, the bottom thickness of the HK film, the K value of the HK film, and the interface charge between Silicon / HK and HK / SiO2, the influence of key parameters on the performance of the device such as breakdown voltage and on-resistance is studied.

[0056] Fig.10Part a, part b, and part c respectively describe the influence of the position of the left side of the trench, the trench depth, and the lateral width of the trench on the breakdown voltage, on-resistance, and FOM value of the device. Combining the three figures, it can be seen that the device has better performance when the trench is located at 0.6-1μm, the depth is 6.5-8.5μm, and the lateral width is 2.7-4.5μm. The position of the left side of the trench means the distance from the oxidation trench 3 to the coordinate origin O (that is, the distance between the oxidation trench 3 and the outer side of the gate 4).

[0057] Fig.11 Part A, Part B, Fig.12 The effects of HK film sidewall thickness, bottom thickness and K value on device performance are described respectively. It can be seen from the figure that the device has the best performance when the sidewall thickness is 200-700nm, the bottom thickness is 440-720nm and the K value is 100-500.

[0058] Fig.13 The effect of the interface charge between silicon and HK and the interface charge between HK and the oxidation trench on the device performance is described. It can be seen from the figure that an appropriate amount of electrons helps to increase the breakdown voltage of the device, while an increase in the hole concentration is more conducive to reducing the on-resistance of the device but will significantly reduce the breakdown voltage of the device. Therefore, considering the above, when the interface charge at the two locations is -10×10 11 -4×10 4 cm -2 The device has the best performance when

[0059] Fig.14 and Fig.15 The output characteristic curve and transfer characteristic curve of Example 1 and Comparative Example 1 are described respectively. Fig.14 It can be seen that Example 1 has a larger output current and thus has a lower on-resistance, while Fig.15 It can be seen that Example 1 has a larger transconductance, which means that it has a stronger gate control capability. Therefore, based on the above two figures, Example 1 has better performance than Comparative Example 1.

[0060] Fig.16 The embodiment 1 describes the breakdown voltage and on-resistance relationship diagram of other devices in the same field, SCDT LDMOS, P.HK LDMOS, DC-NT LDMOS, SFP LDMOS, STDP LDMOS, BSJ-PT LDMOS, 3DVLD LDMOS, EP-DG LDMOS, and DDE LDMOS. Fig.16 It can be seen that the design concept of the present invention is superior, and the performance exceeds the traditional TripleRESURF curve. Compared with other devices in the relevant field, it has a lower on-resistance and better overall performance.

Claims

1. A three-dimensional HK trench LDMOS transistor with an L-shaped gate, comprising a substrate layer (10), a buried oxide layer (6), a silicon film layer and a device top layer stacked in sequence from bottom to top; the silicon film layer comprises a drift region (5), and a gate (4), a source region (1), an HK film (11), an oxidation trench (3), a silicon body (2) and a drain region (12) arranged above the drift region (5); characterized in that: The drain region (12) is located at the corner of the top surface of the drift region (5); the cross-sections of the oxidation trench (3), the source region (1), and the gate (4) are all L-shaped, and are arranged in a semi-enclosed structure in a direction away from the drain region (12); the silicon body (2) has the same cross-sectional shape as the source region (1), and is arranged between the source region (1) and the drift region (5); and the HK film (11) is wrapped around the oxidation trench (3).

2. The L-shaped gate three-dimensional HK trench LDMOS transistor according to claim 1, characterized in that: The cross section of the three-dimensional HK trench LDMOS transistor is a 6.5 μm×6.5 μm square.

3. The L-shaped gate three-dimensional HK trench LDMOS transistor according to claim 2, characterized in that: The oxidation groove (3) wraps around the HK film (11) to a depth of 6.5 μm-8.5 μm, a lateral width of 2.7 μm-4.5 μm, and a spacing from the outer side surface of the gate (4) of 0.6 μm-1 μm.

4. The L-shaped gate three-dimensional HK trench LDMOS transistor according to claim 2, characterized in that: The HK film (11) wraps the sidewall and bottom of the oxidation groove (3); the K value of the HK film (11) is 100-500, the sidewall thickness is 200nm-700nm, and the bottom thickness is 440nm-720nm.

5. The L-shaped gate three-dimensional HK trench LDMOS transistor according to claim 1, characterized in that: The gate (4) is made of polysilicon material, the doping type is N-type, and the doping concentration is 1×10 19 cm -3 ~1×10 20 cm -3 .

6. The L-shaped gate three-dimensional HK trench LDMOS transistor according to claim 1, characterized in that: The doping type of the drift region (5) is N-type, and the doping concentration is 7×10 15 cm -3 ~1.4×10 16 cm -3 .

7. The L-shaped gate three-dimensional HK trench LDMOS transistor according to claim 1, characterized in that: The top layer of the device comprises a gate electrode (7), a source electrode (8) and a drain electrode (9) all of which are L-shaped; the gate electrode (7) is arranged on the top of the gate (4); the source electrode (8) is arranged on the top of the source region (1); and the drain electrode (9) is arranged on the top of the drain region (12).

8. The L-shaped gate three-dimensional HK trench LDMOS transistor according to claim 1, characterized in that: The doping type of the substrate layer (10) is P type, and the doping concentration is 1×10 14 cm -3 ~7×10 14 cm -3 of silicon material.

9. The L-shaped gate three-dimensional HK trench LDMOS transistor according to claim 1, characterized in that: The buried oxide layer (6) is made of silicon dioxide with a thickness of 0.3 μm to 1 μm.

10. The L-shaped gate three-dimensional HK trench LDMOS transistor according to claim 1, characterized in that: The gate (4) is isolated from the source region (1), the silicon body (2) and the drift region (5) by a gate oxide layer; the source region (1) near the gate (4) is made of silicon material, the region near the gate (4) is doped with N type, and the region near the oxidation trench (3) is doped with P type.

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