Image sensor and manufacturing method thereof

Abstract

The invention relates to an image sensor and a manufacturing method thereof. In the image sensor, a back channel structure comprises a bonding pad channel formed corresponding to the bonding pad area and an annular channel surrounding the pixel area, the peripheral circuit area and the bonding pad area are located on the outer side of the annular channel, and a doped area isolation structure is further arranged on the inner side of the annular channel. The annular channel forms physical isolation between the pixel area and the peripheral circuit area, dark current generated by the peripheral circuit area can be effectively prevented from entering the pixel area, effective isolation between the peripheral circuit area and the pixel area is achieved, the annular channel and the bonding pad channel can be synchronously formed through a back face channel technology, and the pixel area is not damaged. And the cost and the manufacturing complexity are not obviously increased.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an image sensor and a manufacturing method thereof. Background Art

[0002] Image sensors use photoelectric conversion devices to convert the light incident on the light-receiving surface into electrical signals in proportion. Compared with photosensitive elements of point light sources such as photodiodes and phototransistors, image sensors have many small units arranged on their light-receiving surfaces. Each small unit is a pixel with a photoelectric conversion function. Multiple pixels are used to form a pixel array for radiation sensing, which can form an image.

[0003] Currently, the most common image sensor manufactured using semiconductor technology is the CMOS image sensor, which has at least one photosensitive diode and three to six transistors in each pixel, resulting in a relatively small proportion of the photosensitive area on the chip. With the development of technology, the demand for increasing the number of pixels per unit area has become more urgent, so the area of ​​a single pixel is designed to be smaller and smaller, and the full well charge of the CMOS pixel is low, resulting in the problem of reduced sensitivity and reduced dynamic range of the CMOS image sensor.

[0004] Vertical charge transferred-pixel sensor (VPS) is a new type of image sensor technology (such as the imaging technology described in Chinese patents CN102938409A, CN111540758A and CN104900667A). It uses a process similar to floating gate NOR flash to manufacture pixel arrays. Under the irradiation of an external light source, photoelectrons moving in a direction perpendicular to the light-receiving surface will be generated in the pixels arranged on the light-receiving surface, causing the potential change of the floating gate (FG) in the pixel, and imaging is characterized by the potential change. Compared with CMOS image sensors, VPS image sensors can achieve higher signal-to-noise ratio and higher full well charge at the same pixel size, making them have very broad application prospects in many fields (such as medical microscopy, genetic testing, etc.).

[0005] When manufacturing image sensors using semiconductor processes, a logic circuit (periphery logic area) is usually formed on the same substrate as the pixel array. The logic circuit and the pixel array are distributed in different areas of the substrate and can be connected to each other through interconnection lines. However, studies have found that the pixel array (especially the VPS image sensor) is easily affected by the dark current of the logic circuit and is prone to defects, such as white pixel defects. How to effectively isolate the peripheral circuit area where the logic circuit is set from the pixel area where the pixel array is set without significantly increasing the cost and manufacturing complexity is of great significance to the production and application of image sensors. Summary of the invention

[0006] In order to effectively isolate the peripheral circuit area and the pixel area of ​​an image sensor without significantly increasing the cost and manufacturing complexity, the present invention provides an image sensor and a method for manufacturing the image sensor.

[0007] In one aspect, the present invention provides an image sensor, comprising:

[0008] A substrate, comprising a pixel region, a peripheral circuit region and a pad region, wherein the pixel region is provided with a plurality of light-sensitive pixels, and the substrate has a front side and a back side opposite to the front side;

[0009] A back channel structure is arranged on the back side of the substrate, the back channel structure comprises a pad channel formed corresponding to the pad area and a ring channel surrounding the pixel area, the peripheral circuit area and the pad area are located outside the ring channel;

[0010] A doping region isolation structure is arranged inside the ring channel, and the doping region isolation structure comprises two trench isolations respectively embedded in the front side of the substrate and the back side of the substrate and vertically aligned, and an ion doping region located between the two trench isolations.

[0011] Optionally, the image sensor includes a first trench isolation, which is embedded in the front side of the substrate and does not penetrate the substrate, the first trench isolation surrounds the pixel area, the peripheral circuit area and the pad area are located outside the first trench isolation, and the ring channel extends downward from the back side of the substrate to expose the first trench isolation.

[0012] Optionally, the trench isolation in the doped region isolation structure embedded in the front side of the substrate and the first trench isolation are isolated by the substrate; or, the trench isolation in the doped region isolation structure embedded in the front side of the substrate and the first trench isolation are an integrated structure.

[0013] Optionally, the substrate on both sides of the trench isolation embedded in the back side of the substrate in the doping region isolation structure has p-type doping, and the doping type of the ion doping region is n-type; or, the substrate on both sides of the trench isolation embedded in the back side of the substrate in the doping region isolation structure has n-type doping, and the doping type of the ion doping region is p-type.

[0014] Optionally, the trench isolation embedded in the back side of the substrate in the doped region isolation structure includes a high-k dielectric layer provided at an interface in contact with the substrate.

[0015] Optionally, the image sensor includes:

[0016] An interconnection structure, arranged on the front side of the substrate;

[0017] a second trench isolation, the second trench isolation being located in the pad region, wherein the pad channel comprises an upper through hole and a lower through hole, the upper through hole extending downward from the back surface of the substrate to expose the second trench isolation, and the lower through hole extending downward from the bottom surface of the upper through hole to expose the interconnect structure;

[0018] a passivation layer covering the inner surface of the ring channel and the inner surface of the upper through hole, wherein the lower through hole penetrates the passivation layer and exposes the interconnection structure; and

[0019] A pad is located in the pad channel, and the pad passes through the lower through hole from the upper through hole to be electrically connected to the interconnection structure.

[0020] Optionally, with the back side of the substrate as a reference, the depth of the ring channel and the upper through hole in the substrate are the same.

[0021] Optionally, the passivation layer only covers the inner surface of the ring channel but does not fill the ring channel; or, the passivation layer fills the ring channel.

[0022] Optionally, the image sensor is a VPS image sensor.

[0023] In one aspect, the present invention provides a method for manufacturing an image sensor, comprising:

[0024] Providing a substrate, the substrate comprising a pixel region, a peripheral circuit region and a pad region, the substrate having a front side and a back side opposite to the front side;

[0025] Fabricate front trench isolation, a plurality of photosensitive pixels and an interconnection structure on the front side of the substrate, wherein the plurality of photosensitive pixels are located in the pixel area;

[0026] bonding the front side of the substrate to a carrier;

[0027] A back channel structure and a back trench isolation are fabricated on the back side of the substrate, wherein the back channel structure comprises a pad channel formed corresponding to the pad area and a ring channel surrounding the pixel area, and the peripheral circuit area and the pad area are located outside the ring channel;

[0028] The front trench isolation and the back trench isolation include two trench isolations located inside the ring channel and vertically aligned, an ion doping region is formed in the substrate between the two trench isolations, and the two trench isolations and the ion doping region form a doping region isolation structure.

[0029] Optionally, the front trench isolation includes a first trench isolation embedded in the front side of the substrate and not penetrating the substrate, the first trench isolation surrounds the pixel area, the peripheral circuit area and the pad area are located outside the first trench isolation, and the ring channel extends downward from the back side of the substrate to expose the first trench isolation.

[0030] Optionally, forming a trench isolation located on the back side of the substrate in the doped region isolation structure includes:

[0031] Making a back side isolation trench on the back side of the substrate, wherein the bottom surface of the back side isolation trench exposes the ion doping region; and

[0032] A high-k dielectric layer and a non-high-k isolation dielectric are fabricated on the back side of the substrate. The high-k dielectric layer conformally covers the back side of the substrate and the inner surface of the back isolation trench, and the non-high-k isolation dielectric fills the back isolation trench.

[0033] The image sensor provided by the present invention comprises a substrate, a back channel structure and a doped region isolation structure arranged on the inner side of the ring channel, wherein the back channel structure comprises a pad channel formed corresponding to the pad area and a ring channel surrounding the pixel area, the peripheral circuit area and the pad area are located outside the ring channel, the ring channel forms a physical isolation between the pixel area and the peripheral circuit area, and can effectively block the dark current generated by the peripheral circuit area from entering the pixel area, thereby realizing effective isolation between the peripheral circuit area and the pixel area, and the ring channel and the pad channel are both back channel structures, which can be formed simultaneously through the back channel process, and will not significantly increase the cost and manufacturing complexity.

[0034] In the manufacturing method of the image sensor provided by the present invention, the back channel structure manufactured on the back side of the substrate includes a pad channel formed corresponding to the pad area and a ring channel surrounding the pixel area, the peripheral circuit area and the pad area are located outside the ring channel, and the front trench isolation and the back trench isolation include two trench isolations located inside the ring channel and vertically aligned, an ion doping area is formed in the substrate between the two trench isolations, and the two trench isolations and the ion doping area form a doping area isolation structure. The manufacturing method utilizes the manufacturing process of the pad channel to simultaneously form effective isolation between the peripheral circuit area and the pixel area, has low cost, and does not significantly increase the manufacturing complexity. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1A A plan view of a VPS image sensor including a doped region isolation structure is shown.

[0036] Figure 1B yes Figure 1A Schematic cross-sectional view of the isolation structure of the mid-doped region.

[0037] Figure 2A FIG. 4 is a plan view of an image sensor according to an embodiment of the present invention.

[0038] Figure 2B yes Figure 2A A cross-sectional schematic diagram of an image sensor is shown.

[0039] Figure 3 FIG. 4 is a plan view of an image sensor according to another embodiment of the present invention.

[0040] Figure 4 It is a schematic flow chart of a method for manufacturing an image sensor according to an embodiment of the present invention.

[0041] Figure 5 FIG. 4 is a schematic cross-sectional view of a substrate used in a method for manufacturing an image sensor according to an embodiment of the present invention.

[0042] Figure 6 It is a cross-sectional schematic diagram of a method for manufacturing an image sensor according to an embodiment of the present invention after forming front trench isolation, photosensitive pixels and interconnection structures.

[0043] Fig. 6A It is a cross-sectional schematic diagram of a method for manufacturing an image sensor according to another embodiment of the present invention after forming front trench isolation, photosensitive pixels and interconnection structures.

[0044] Figure 7 It is a cross-sectional schematic diagram of a method for manufacturing an image sensor according to an embodiment of the present invention after forming backside trench isolation.

[0045] Figure 8It is a cross-sectional schematic diagram of a method for manufacturing an image sensor according to an embodiment of the present invention after forming upper through holes of a ring channel and a pad channel.

[0046] Fig. 9 FIG. 4 is a cross-sectional schematic diagram of a method for manufacturing an image sensor according to an embodiment of the present invention after forming a passivation layer.

[0047] Fig. 9A FIG. 4 is a cross-sectional schematic diagram of a method for manufacturing an image sensor according to another embodiment of the present invention after forming a passivation layer.

[0048] Fig.10 It is a cross-sectional schematic diagram of a method for manufacturing an image sensor according to an embodiment of the present invention after forming a lower through hole of a pad channel.

[0049] Fig.11 FIG. 1 is a cross-sectional schematic diagram of a method for manufacturing an image sensor after forming a bonding pad according to an embodiment of the present invention.

[0050] Fig.11A FIG. 4 is a cross-sectional schematic diagram of a method for manufacturing an image sensor according to another embodiment of the present invention after forming a bonding pad.

[0051] Description of reference numerals:

[0052] 100-substrate; 100a-front side; 100b-back side; 10-pixel area; 20-peripheral circuit area; 30-pad area; 110-first trench isolation; 120-second trench isolation; 130-third trench isolation; 140-fourth trench isolation; 151-ring channel; 15-pad channel; 152-upper through hole; 154-lower through hole; 153-passivation layer; 160-pad; 141-high-k dielectric layer; 101-high-k dielectric layer; 142-non-high-k isolation dielectric; 200-carrier; 201-buffer layer. DETAILED DESCRIPTION

[0053] Figure 1A The schematic diagram of a VPS image sensor including a doped region isolation structure is shown in FIG. Figure 1A Similar to the CMOS image sensor, in the substrate 100 for setting the photosensitive pixels of the VPS image sensor, the peripheral circuit area 20 and the pad area 30 are set outside the pixel area 10, wherein the pixel area 10 is used to set the photosensitive pixels, the peripheral circuit area 20 is used to set the logic circuit of the image sensor or other circuit elements set as needed, and the pad area 30 is used to set the pads (PAD) for connecting to the external circuit. In order to isolate the pixel area 10 and the peripheral circuit area 20 in the VPS image sensor, a doping region isolation structure is set in the gap between the pixel area 10 and the peripheral circuit area 20, and the doping region isolation structure is as shown in FIG. Figure 1AThe area enclosed by the dotted circle is shown in the figure.

[0054] Figure 1B yes Figure 1A Schematic diagram of the cross section of the doped region isolation structure. Figure 1A and Figure 1B , between the pixel region 10 and the peripheral circuit region 20, a shallow trench isolation (STI) is provided on the front side 100a of the substrate 100, and a deep trench isolation (DTI) is provided on the back side 100b of the substrate 100, and the shallow trench isolation and the deep trench isolation overlap in the orthographic projection of the front side 100a of the substrate 100, that is, at least a portion of the shallow trench isolation and the deep trench isolation are vertically aligned. There is an n-type doped region ( Figure 1B DNW), from the vertical direction (i.e., thickness direction) of the substrate 100, the shallow trench isolation, the n-type doped region and the deep trench isolation are arranged in sequence, and the substrates on both sides of the n-type doped region are p-type doped ( Figure 1B In the figure, it is shown as p-sub. In addition, the pixel area 10 is also provided with a p-well (PW) in the p-type substrate. The shallow trench isolation and the deep trench isolation provide physical isolation, while the n-type doped area is isolated by heterotypic doping. However, the isolation effect of the doped area isolation structure provided between the pixel area 10 and the peripheral circuit area 20 is poor. The doped area isolation structure is difficult to effectively block the leakage current of the peripheral circuit area 20 from entering the pixel area 10, resulting in white pixel defects in the pixel area 10. The main reason is that, on the one hand, what needs to be avoided between the pixel area 10 and the peripheral circuit area 20 is the dark current. Different from the isolation of photocharges between pixels, the n-type doped area provided between the p-type substrates is better for isolating photocharges. However, the dark current is formed by the movement of carriers and is highly correlated with the doping concentration. Under certain conditions, the dark current may still pass through the interface between the p-type area and the n-type doped area. On the other hand, as Figure 1A and Figure 1B As shown, in order to avoid crosstalk between pixels, in the above-mentioned deep trench isolation, a high-k dielectric layer 101 is uniformly set at the interface with the substrate (k in this article refers to the dielectric constant, and the "high-k material" refers to a dielectric constant higher than that of silicon oxide (the dielectric constant of silicon oxide used in traditional devices is about 4), such as aluminum oxide and tantalum oxide (TaO), etc.). However, Figure 1B As shown, the study found that the high-k material layer has negative charges, which will cause the n-type doped region to be inverted and become p-type in the area contacting the deep trench isolation. The p-type inversion layer plays a "bridging" role for the p-type regions on both sides of the n-type doped region, promoting the flow of dark current, making it easy for leakage current to enter the pixel region 10 to form defects. Due to the bridging effect of the high-k material layer 101, even in the setting Figure 1BWhen the shallow trench isolation and the deep trench isolation are connected up and down as shown, it is still difficult to completely block the leakage current from flowing between the pixel area 10 and the peripheral circuit area 20 .

[0055] It should be noted that the problem of the adverse effect of leakage current in the peripheral circuit area on the pixel area is not only a problem faced by VPS image sensors, but also image sensors using other image sensing principles (such as CCD image sensors, CMOS image sensors or other active or passive image sensors) will also encounter this problem. In order to solve the problem of isolation between the pixel area and the peripheral circuit area in the image sensor without significantly increasing the cost and manufacturing complexity, the inventor proposed the present invention. The image sensor and its manufacturing method of the present invention are further described in detail below in conjunction with the drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be understood that the drawings of the specification are all in a very simplified form and are all in non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It should be understood that spatial relative terms are intended to include different orientations in use or operation other than the orientation of the device described in the figure. For example, if the structure in the figure is inverted or positioned in other different ways (such as rotation), the exemplary term "on..." may also include "under..." and other orientation relationships, and the exemplary term "extending downward" may also include "extending upward" and other orientation relationships. The “upper through hole” may also be located below the “lower through hole” or in other positions.

[0056] Figure 2A FIG. 4 is a plan view of an image sensor according to an embodiment of the present invention. Figure 2B yes Figure 2A The cross-sectional diagram of the image sensor shown in FIG. Figure 2A and Figure 2B , an embodiment of the present invention relates to an image sensor, the image sensor comprising:

[0057] A substrate 100, the substrate comprising a pixel region 10, a peripheral circuit region 20 and a pad region 30, the pixel region 10 being provided with a plurality of photosensitive pixels, the substrate 100 having a front side 100a and a back side 100b opposite to the front side 100a;

[0058] A front trench isolation, embedded in the front side 100a of the substrate 100 and not penetrating the substrate 100, the front trench isolation comprising a first trench isolation 110 and a second trench isolation 120, the first trench isolation 110 surrounds the pixel area 10, the peripheral circuit area 20 and the pad area 30 are located at the periphery of the first trench isolation 110, and the second trench isolation 120 is located at the pad area 30;

[0059] An interconnection structure, disposed on the front side 100a of the substrate 100;

[0060] A back channel structure is provided on the back side 100b of the substrate 100, the back channel structure includes a pad channel 15 and a ring channel 151 surrounding the pixel region 10, the ring channel 151 extends downward from the back side 100b of the substrate 100 to expose the first trench isolation 110, the pad channel 15 includes an upper through hole 152 and a lower through hole 154, the upper through hole 152 extends downward from the back side 100b of the substrate 100 to expose the second trench isolation 120, and the lower through hole 154 extends downward from the bottom surface of the upper through hole 152 to expose the interconnect structure (such as Figure 2B The metal layer M1 shown in FIG.

[0061] a passivation layer 153, covering the inner surface of the ring channel 151 and the inner surface of the upper through hole 152, the passivation layer 153 also exposing the interconnection structure (the interconnection structure may be exposed through the lower through hole 154, the passivation layer 153, for example, does not cover the lower through hole 154 or only covers the side surface of the lower through hole 154);

[0062] The pad 160 is located in the pad channel 15 , and the pad 160 is electrically connected to the interconnection structure.

[0063] The image sensor in the embodiment of the present invention is a VPS image sensor, but may also be a CCD image sensor, a CMOS image sensor or other active or passive image sensors.

[0064] The ring channel 151 and the upper through hole 152 can be formed on the back side of the substrate 100 by the same photolithography and etching process, so the ring channel 151 and the upper through hole 152 have the same depth in the substrate 100 (with the back side 100 b of the substrate 100 as a reference).

[0065] Figure 2B In the cross-sectional view shown, the passivation layer 153 only covers the inner surface of the ring channel 151, but does not fill the ring channel 151. The pixel area 10 and the peripheral circuit area 20 on both sides of the ring channel 151 are isolated by the passivation layer 153 and the air layer in the ring channel 151. The present invention is not limited to this. In other embodiments, the passivation layer 153 can fill the ring channel 151. In addition, as Figure 2B As shown, the passivation layer 153 also covers the back side 100 b of the substrate 100 .

[0066] Figure 3 FIG. 4 is a plan view of an image sensor according to another embodiment of the present invention. Fig.11 FIG. 1 is a cross-sectional schematic diagram of a method for manufacturing an image sensor after forming a bonding pad according to an embodiment of the present invention. Fig.11AFIG. 1 is a cross-sectional schematic diagram of a method for manufacturing an image sensor according to another embodiment of the present invention after forming a bonding pad. Figure 3 , Fig.11 and Fig.11A In the image sensor of some embodiments of the present invention, in addition to the above-mentioned ring channel 151 and passivation layer 153 for isolation between the pixel area 10 and the peripheral circuit area 20, a doped region isolation structure is further provided on the inner side of the ring channel 151, and the doped region isolation structure includes a third trench isolation 130 embedded in the front side 100a of the substrate 100, a fourth trench isolation 140 embedded in the back side 100b of the substrate 100 and vertically aligned with the third trench isolation 130, and an ion doping region (not shown) located between the third trench isolation 130 and the fourth trench isolation 140. In the image sensor, the doped region isolation structure is arranged between the pixel region 10 and the peripheral circuit region 20, and is surrounded by the first trench isolation 110 and the ring channel 151, that is, the pixel region 10 and the peripheral circuit region 20 are physically isolated by the first trench isolation 110 and the ring channel 151 and the passivation layer 153 in the ring channel 151, and are also isolated by the doped region isolation structure, so the isolation effect is better.

[0067] It should be noted that Fig.11 The doping region isolation structure shown can also be set in the pixel region 10 (not shown) to separate adjacent photosensitive pixels. However, it is not limited thereto. In another embodiment, the doping region isolation structure is only set in the pixel region 10, and the pixel region 10 and the peripheral circuit region 20 are isolated only by the above-mentioned ring channel 151 and the passivation layer 153.

[0068] In the above doped region isolation structure, if the substrate 100 on both sides of the fourth trench isolation 140 has p-type doping, the doping type of the ion doped region is n-type. Alternatively, if the substrate on both sides of the fourth trench isolation 140 has n-type doping, the doping type of the ion doped region is p-type.

[0069] Reference Fig.11 and Fig.11A The fourth trench isolation 140 may include a back isolation trench disposed on the back side 100b of the substrate 100, and a high-k dielectric layer 141 and a non-high-k isolation dielectric 142 disposed in the back isolation trench, wherein the high-k dielectric layer 141 contacts the substrate 100, and the non-high-k dielectric layer 142 (such as a silicon oxide layer) covers the high-k dielectric layer 141 and fills the back isolation trench. The high-k dielectric layer 141 also covers the back side 100b of the substrate 100, but is not disposed in the ring channel 151 and the pad channel 14, so as to avoid increasing the leakage current and causing the isolation effect to deteriorate.

[0070] The third trench isolation 130 and the aforementioned first trench isolation 110 are both disposed between the pixel region 10 and the peripheral circuit region 20 , and both surround the pixel region 10 . Fig.11 In the illustrated embodiment, the first trench isolation 110 and the third trench isolation 130 are isolated by the substrate 100 in the lateral direction (in the direction parallel to the front surface 100a of the substrate 100). However, it is not limited thereto. In other embodiments, the first trench isolation 110 and the third trench isolation 130 may be connected, for example, an integral structure, and the integral structure may also be regarded as a first trench isolation 110 that is wider and extends to the setting range of the third trench isolation 130, or may also be regarded as a third trench isolation 130 that is wider and extends to the setting range of the first trench isolation 110, such as Fig.11A As shown. For example, the first trench isolation 110 is as follows Fig.11 The first trench isolation 110 shown is wide, and the positive projections of the above-mentioned ring channel 151 and the fourth trench isolation 140 on the front side 100a of the substrate 100 overlap with the first trench isolation 110. The passivation layer 153 is in contact with the first trench isolation 110 through the ring channel 151, and an ion implantation region for isolation is provided between the fourth trench isolation 140 and the first trench isolation 110 (that is, isolation is performed using an impurity region isolation structure), and the fourth trench isolation 140 can surround the pixel area 10 in a closed or non-closed manner.

[0071] In the image sensor introduced in the above embodiment, the back channel structure includes a pad channel 15 and a ring channel 151 surrounding the pixel area 10, the ring channel 151 extends downward from the back side 100b of the substrate 100 to expose the first trench isolation 110, and the passivation layer 153 covers the inner surface of the ring channel 151, that is, the passivation layer 153 located in the ring channel 151 is connected up and down with the first trench isolation 110 surrounding the pixel area 10, forming a physical full isolation between the pixel area 10 and the peripheral circuit area 20, which can effectively block the dark current generated by the peripheral circuit area 20 from entering the pixel area 10, thereby achieving effective isolation between the peripheral circuit area 20 and the pixel area 10, and the ring channel 151 and the pad channel 15 with the pad 160 are both back channel structures, which can be formed simultaneously through the back channel process without significantly increasing the cost and manufacturing complexity.

[0072] In order to better implement the above scheme of the embodiment of the present invention, a method for manufacturing an image sensor is also provided below, which can manufacture the above image sensor. It should be noted that the order of the steps in the method presented in this article is not necessarily the only order to perform these steps, and some of the steps described may be omitted and / or some other steps not described in this article may be added to the method.

[0073] Figure 4FIG. 1 is a flow chart of a method for manufacturing an image sensor according to an embodiment of the present invention. Figure 4 The manufacturing method of the image sensor according to the embodiment of the present invention comprises the following steps:

[0074] S1: providing a substrate, wherein the substrate comprises a pixel region, a peripheral circuit region and a pad region, and the substrate has a front side and a back side opposite to the front side;

[0075] S2: manufacturing a front trench isolation, a photosensitive pixel and an interconnection structure on the front side of the substrate, wherein the photosensitive pixel is located in the pixel region, the front trench isolation does not penetrate the substrate and includes a first trench isolation and a second trench isolation, the first trench isolation surrounds the pixel region, the peripheral circuit region and the pad region are located at the periphery of the first trench isolation, the second trench isolation is located in the pad region, and the interconnection structure is formed on one side of the front side of the substrate;

[0076] S3: bonding the front side of the substrate to a carrier;

[0077] S4: manufacturing a back channel structure on the back side of the substrate, including: forming a ring channel surrounding the pixel area and an upper through hole located in the pad area, wherein the ring channel extends downward from the back side of the substrate to expose the first trench isolation, and the upper through hole extends downward from the back side of the substrate to expose the second trench isolation; then depositing a passivation layer on the back side of the substrate, wherein the passivation layer covers the back side of the substrate, the inner surface of the ring channel and conformally covers the inner surface of the upper through hole, and then forming a lower through hole on the bottom surface of the upper through hole, wherein the lower through hole extends downward from the bottom surface of the upper through hole to expose the interconnection structure, and the upper through hole and the lower through hole constitute a pad channel;

[0078] S5: forming a pad in the pad channel, wherein the pad is electrically connected to the interconnection structure.

[0079] Figures 5 to 11A FIG. 1 is a cross-sectional schematic diagram of an image sensor in various manufacturing stages of a method for manufacturing an image sensor according to an embodiment of the present invention. Figure 4 and Figures 5 to 11A A method for manufacturing an image sensor according to an embodiment of the present invention is described.

[0080] Specifically, the image sensor manufactured here is, for example, a VPS image sensor, in which a plurality of photosensitive pixels are arranged in the pixel area of ​​the p-type substrate, each photosensitive pixel includes a MOS capacitor for photosensitization formed on one side of the substrate (called the front side) and a read transistor for reading the amount of photogenerated charge, the substrate of the MOS capacitor and the read transistor is separated by shallow trench isolation (STI), and the source / drain region is arranged in the substrate on one side of the read transistor; the MOS capacitor and the read transistor both include a bottom insulating medium, a floating gate, a top insulating medium and a control gate sequentially stacked on the front side of the substrate, and the floating gate is connected between the MOS capacitor and the read transistor. The working mode of the VPS image sensor is as follows: in the light sensing stage, a negative bias is applied to the substrate, and a positive bias is applied to the control gate, so that a continuous depletion region is formed in the substrate of each photosensitive pixel, when light is incident from the other side of the substrate (called the back side), the photons reaching the depletion region excite the photogenerated charge under appropriate conditions, and migrate to the floating gate under the drive of the electric field, causing the potential of the floating gate to change, and in the reading stage, the amount of photogenerated charge in the floating gate can be read by controlling the read transistor. Regarding the structure and working principle of the VPS image sensor, reference may be made to the disclosures in the art (such as Chinese patents CN102938409A, CN111540758A, CN104900667A, CN107180844A and CN107658321A, etc.), which will not be described in detail here.

[0081] It should be noted that the embodiment of the present invention focuses on describing the isolation problem between the pixel area and the peripheral circuit area in the image sensor. This problem also exists in other types of image sensors. In the absence of conflict, the manufacturing method of the image sensor described below is also applicable to other types of image sensors.

[0082] First, refer to Figure 5 , perform step S1, provide a substrate 100, the substrate 100 includes a pixel region 10, a peripheral circuit region 20 and a pad region 30, the substrate 100 has a front side 100a and a back side 100b opposite to the front side 100a. The pixel region 10 is used to set the photosensitive pixel, the peripheral circuit region 20 is used to set the logic circuit of the image sensor (such as an application-specific integrated circuit (ASIC) device or a system on chip (SOC) device) or other circuit elements set as needed (such as a reference pixel for establishing a light intensity baseline), and the pad region 30 is used to set one or more pads (PAD) for connecting to an external device. Figure 5 The positions of the pixel region 10 , the peripheral circuit region 20 and the pad region 30 are only for illustration and may vary in actual applications. Figure 5The dashed lines in the figure represent approximate boundaries between the pixel region 10, the peripheral circuit region 20 and the pad region 30, but it should be understood that these regions are not drawn to scale and that they may extend vertically as far as Figure 5 The substrate 100 is shown with a front side 100a above and a back side 100b below.

[0083] The material of the substrate 100 can be silicon, germanium, silicon germanium, silicon carbide, gallium oxide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide or indium antimonide, etc., and can also be silicon on insulator (SOI) or germanium on insulator (GOI), or can also be other materials, such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP or GaInAsP, etc., or can also be a combination of the above materials. The substrate 100 can include a doped epitaxial layer, a gradient semiconductor layer and a semiconductor layer located on other semiconductor layers of different types (such as a silicon layer on a germanium silicon layer). Certain doping ions can also be injected into the substrate 100 according to design requirements to change electrical parameters. In this embodiment, the substrate 100 is, for example, a silicon substrate with p-type doping. In other embodiments, the substrate 100 can also have n-type doping. Here, the front side 100 a of the substrate 100 is a side surface used when manufacturing photosensitive pixels, and the back side 100 b of the substrate 100 is opposite to the front side 100 a , and the back side 100 b is a side surface of the substrate 100 where radiation to be sensed enters.

[0084] Next, refer to Figure 6 , perform step S2, and make front trench isolation, photosensitive pixels and interconnection structure on the front side 100a of the substrate 100. Figure 6 The specific structure of the photosensitive pixels and the interconnection structure is not shown.

[0085] The photosensitive pixel is formed in the pixel area 10 to sense radiation projected onto the back side 100b of the pixel area 10. It can be formed using a manufacturing method disclosed in the art. For a VPS image sensor, its photosensitive pixel includes the above-mentioned MOS capacitor and a read transistor. For a CMOS image sensor, its photosensitive pixel includes a photodiode, a reset transistor, a source follower transistor, and a transfer transistor. The interconnect structure is formed above the front side 100a, and it may include a multi-layer patterned conductive layer and a conductive plug isolated by a dielectric material. The conductive layer and the conductive plug provide interconnection between various doped regions, circuits, and input / outputs of the image sensor. The interconnect structure has a metal layer (such as a metal layer) relatively close to the front side 100a of the substrate 100. Figure 6 M1), the electrical properties of the interconnect structure can be subsequently led out from the back side 100b of the substrate 100 through the metal layer.

[0086] The front trench isolation formed in step S1 is formed on the substrate 100 but does not penetrate the substrate 100. In this embodiment, the front trench isolation is a shallow trench isolation (STI, which is usually embedded in the substrate at a depth of In some other embodiments, the front trench isolation is a deep trench isolation (DTI, which is usually embedded in the substrate at a depth of The front trench isolation can be embedded in the front surface 100a of the substrate 100 by using the method disclosed in the art. According to the design requirements, a trench can be first made in a specified area of ​​the front surface 100a of the substrate 100, and then an isolation dielectric can be filled in the trench. The isolation dielectric can be made of silicon oxide, silicon nitride or other insulating materials. Figure 6 As shown, in the embodiment of the present invention, the front trench isolation includes a first trench isolation 110 and a second trench isolation 120. The first trench isolation 110 and the second trench isolation 120 can be formed by the same trench isolation process and thus have substantially the same depth. The first trench isolation 110 surrounds the pixel area 10, that is, the first trench isolation 110 is annular. The peripheral circuit area 20 and the pad area 30 are located at the periphery of the first trench isolation 110, and the second trench isolation 120 is located at the pad area 30, so as to facilitate the subsequent manufacture of pads on the back side 100b of the substrate 100.

[0087] In addition to forming the first trench isolation 110 and the second trench isolation 120, step S1 may further form a front trench isolation in the pixel region 10 that does not penetrate the substrate 100 to separate adjacent photosensitive pixels and isolate the MOS capacitor and the read transistor in each photosensitive pixel. In addition, in some embodiments, in order to ensure the isolation effect between the pixel region 10 and the peripheral circuit region 20, as shown in FIG. Figure 6 As shown, a third trench isolation 130 (for example, STI) may be formed between the pixel region 10 and the peripheral circuit region 20 on the inner side of the first trench isolation 110, that is, the front trench isolation also includes the third trench isolation 130 and the trench isolation of the pixel region 10, so that the aforementioned isolation region doping structure may be formed at the third trench isolation 130 and the trench isolation between the photosensitive pixels in the pixel region 10. However, it is not limited thereto. Fig. 6A As shown, in some embodiments, a wider first trench isolation 110 (the width of which can cover the range of the third trench isolation 130) can be manufactured, so that the first trench isolation 110 can be reused to construct a physical full isolation and doping region isolation structure. The following process is also applicable to Fig. 6A The structure shown.

[0088] Still refer to Figure 6For example, when manufacturing the above-mentioned front trench isolation, before etching the substrate 100 to form the isolation trench and filling the isolation dielectric, ion implantation may be performed on the front isolation trench opened on the front side 100a of the substrate 100 for forming the front trench isolation of the doped region isolation structure (such as the third trench isolation 130 and the front trench isolation in the pixel region 10), so as to form a doped region for isolation (not shown) in the substrate 100 below the front isolation trench after thermal annealing. In this embodiment, the substrate 100 is p-type doped (the dopant is, for example, boron or boron difluoride), and the doped region for isolation is n-type (the dopant is, for example, phosphorus or arsenic). In other embodiments, the substrate is n-type doped, and the doped region for isolation is p-type. In some embodiments, the doped region for isolation can be formed by ion implantation and thermal annealing before the front isolation trench is opened or after the front trench isolation is formed.

[0089] Next, refer to Figure 7 , perform step S3 to bond the front side 100a of the substrate 100 to a carrier 200. The substrate 100 and the carrier 200 can be bonded together by bonding processes such as metal bonding, melt bonding or adhesion. The carrier 200 can protect the device formed on the front side 100a, and facilitate the process on the back side 100b of the substrate 100. The material of the carrier 200 is similar to that of the substrate 100, and may include silicon material, or the carrier 200 may also be made of glass or other suitable materials. A buffer layer 201 with an electrical isolation function may be formed between the substrate 100 and the carrier 200. After bonding, the substrate 100 can be thinned from the back side 100b using a disclosed thinning process, and the degree of thinning can be set according to design requirements. In order to reflect the association, 100b is still used here to represent the back side of the substrate 100 after thinning.

[0090] In order to form a doped region isolation structure between the pixel region 10 and / or the pixel region 10 and the peripheral circuit region 20, refer to Figure 7, step S3 may also include the step of manufacturing back trench isolation. The manufacturing of back trench isolation is performed after the substrate 100 is turned over so that the back side 100b is facing upward. The back trench isolation is, for example, deep trench isolation (DTI), and the back trench isolation can be manufactured by the following process: first, a back isolation trench is manufactured on the back side 100b of the substrate 100, and the bottom surface of the back isolation trench exposes the above-mentioned doping region for isolation; then, a high-k dielectric layer 141 and a non-high-k isolation dielectric 142 are sequentially formed on the back side 100b of the substrate 100, the high-k dielectric layer 141 conformally covers the back side 100b of the substrate 100 and the inner surface of the back isolation trench, and the non-high-k isolation dielectric 142 (such as silicon oxide) covers the high-k dielectric layer 141 in the back isolation trench and fills the back isolation trench. The material of the high-k dielectric layer may include at least one of Al2O3, Ta2O5, ZrO2, LaO, BaZrO, AlO, HfZrO, HfZrON, HfLaO, HfSiON, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba, Sr)TiO3 (BST), Si3N4, TiO2, nitride oxide or other suitable materials. The thickness range of the high-k dielectric layer 141 is, for example, The high-k dielectric layer can be formed by a suitable process such as CVD, ALD or PVD. In the pixel region 10, by providing a high-k dielectric layer 141 in the back isolation trench, it can absorb charges (such as photogenerated charges) moving near the high-k dielectric layer, which helps to reduce crosstalk between adjacent photosensitive pixels.

[0091] In this embodiment, the back trench isolation formed between the pixel region 10 and the peripheral circuit region 20 and vertically aligned with the third trench isolation 130 is called the fourth trench isolation 140, which includes a portion of the high-k dielectric layer 141 and a portion of the non-high-k isolation dielectric 142. The n-type doped region used for isolation is located in the relative region of the third trench isolation 130 and the fourth trench isolation 140, and can play a certain isolation role for the p-type doped regions on both sides.

[0092] Then, step S4 is performed to fabricate a back channel structure on the back side 100b of the substrate 100. Specifically, the fabrication of the back channel structure includes the following process:

[0093] First, if Figure 8 As shown, an annular channel 151 surrounding the pixel region 10 and an upper through hole 152 located in the pad region 30 are formed by an etching process (which may be the same etching), the annular channel 151 extends downward from the back surface 100b of the substrate 100 to expose the first trench isolation 110, and the upper through hole 152 extends downward from the back surface 100b of the substrate 100 to expose the second trench isolation 120;

[0094] Then, if Fig. 9 As shown, a passivation layer 153 is deposited on the back side 100b of the substrate 100, the passivation layer 153 covers the back side 100b of the substrate 100, the inner surface of the ring channel 151 and conformally covers the inner surface of the upper through hole 152, the passivation layer 153 is, for example, silicon oxide, and the thickness of the passivation layer 153 is set as required, such as Fig. 9 In the embodiment, the passivation layer 153 only covers the inner surface of the ring channel 151 but does not fill the ring channel 151, but is not limited thereto. In another embodiment, Fig. 9A As shown, since the channel width of the ring channel 151 is narrow and / or the passivation layer 153 is thick, the passivation layer 153 can fill the ring channel 151;

[0095] Then, in Fig. 9 Based on the structure shown, Fig.10 As shown, a lower through hole 154 is formed on the bottom surface of the upper through hole 152, and the lower through hole 154 extends downward from the bottom surface of the upper through hole 152 to expose the interconnection structure formed on the front side 100a (here, for example, the metal layer M1 in the interconnection structure is exposed). When the lower through hole 154 is formed, the area outside the lower through hole pattern needs to be covered with a mask (not shown) for protection to avoid being etched. The upper through hole 152 and the lower through hole 154 constitute a pad channel 15, and the pad channel 15 and the ring channel 151 constitute a back channel structure;

[0096] Then, if Fig.11 As shown, a pad 160 is formed in the pad channel 15. Specifically, a conductive material (such as aluminum) can be deposited on the back side 100b of the substrate 100, so that the conductive material deposited in the pad channel 15 fills the lower through hole 154 and reaches a thickness that meets the design requirements in the upper through hole 152. Then, the conductive material in other areas is removed by photolithography and etching processes, and only the conductive material in a set range in the pad channel 15 is retained. This part of the conductive material is used as the pad 160, and the pad 160 passes through the lower through hole 154 and is electrically connected to the above interconnection structure. Fig. 6A The structure of the reused first trench isolation 110 after forming the pad 160 is as shown in FIG. Fig.11A shown.

[0097] The image sensor manufactured through the above steps can be electrically connected to an external device through the pad 160. The position and number of the pad channel 15 and the pad 160 can be set as needed, and can be one or more. In the image sensor, in the pixel area 10, a doping region isolation structure can be used to isolate adjacent pixels, and between the pixel area 10 and the peripheral circuit area 20, a ring channel 151 and a passivation layer 153 that can be manufactured simultaneously with the pad channel are used for isolation. The passivation layer 153 can be made of non-high-k materials such as silicon oxide and silicon nitride, which has a good isolation effect and can save process.

[0098] In the manufacturing method of the image sensor provided by the embodiment of the present invention, in the process of manufacturing the pad channel 15, a ring channel 151 surrounding the pixel area 10 is formed at the same time, and a passivation layer 153 is formed in the ring channel 151 and the upper through hole 152. In the etching process used when forming the lower through hole 154 and the pad 160, the passivation layer 153 can protect and block the non-etched area, and the passivation layer 153 is connected to the first trench isolation 110 exposed by the ring channel 151 from top to bottom, forming a physical full isolation between the pixel area 10 and the peripheral circuit area 20, which can effectively block the dark current generated by the peripheral circuit area 20 from entering the pixel area 10. The manufacturing method uses the manufacturing process of the pad channel 15 to form an effective isolation between the peripheral circuit area 20 and the pixel area 10 at the same time, with low cost and without significantly increasing the manufacturing complexity.

[0099] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referenced to each other.

[0100] The above description is only a description of the preferred embodiment of the present invention, and is not any limitation on the scope of rights of the present invention. Any technical personnel in this field can make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. An image sensor, characterized in that: include: A substrate, comprising a pixel region, a peripheral circuit region and a pad region, wherein the pixel region is provided with a plurality of light-sensitive pixels, and the substrate has a front side and a back side opposite to the front side; A back channel structure is arranged on the back side of the substrate, the back channel structure comprises a pad channel formed corresponding to the pad area and a ring channel surrounding the pixel area, the peripheral circuit area and the pad area are located outside the ring channel; A doping region isolation structure is arranged inside the ring channel, and the doping region isolation structure comprises two trench isolations respectively embedded in the front side of the substrate and the back side of the substrate and vertically aligned, and an ion doping region located between the two trench isolations.

2. The image sensor according to claim 1, wherein: include: A first trench isolation is embedded in the front side of the substrate and does not penetrate the substrate. The first trench isolation surrounds the pixel area. The peripheral circuit area and the pad area are located at the periphery of the first trench isolation. The ring channel extends downward from the back side of the substrate to expose the first trench isolation.

3. The image sensor according to claim 2, wherein: The trench isolation in the doped region isolation structure embedded in the front side of the substrate and the first trench isolation are isolated by the substrate; or, the trench isolation in the doped region isolation structure embedded in the front side of the substrate and the first trench isolation are an integrated structure.

4. The image sensor according to claim 1, wherein: The substrate on both sides of the trench isolation embedded in the back side of the substrate in the doped region isolation structure has p-type doping, and the doping type of the ion doped region is n-type; or, the substrate on both sides of the trench isolation embedded in the back side of the substrate in the doped region isolation structure has n-type doping, and the doping type of the ion doped region is p-type.

5. The image sensor according to claim 1, wherein: The doped region isolation structure is only disposed in the pixel region; or, the doped region isolation structure is disposed in the pixel region and between the pixel region and the peripheral circuit region.

6. The image sensor according to claim 1, wherein: The trench isolation embedded in the back side of the substrate in the doped region isolation structure includes a high-k dielectric layer arranged at an interface in contact with the substrate.

7. The image sensor according to claim 1, wherein: include: An interconnection structure, arranged on the front side of the substrate; a second trench isolation, the second trench isolation being located in the pad region, wherein the pad channel comprises an upper through hole and a lower through hole, the upper through hole extending downward from the back surface of the substrate to expose the second trench isolation, and the lower through hole extending downward from the bottom surface of the upper through hole to expose the interconnect structure; a passivation layer covering the inner surface of the ring channel and the inner surface of the upper through hole, wherein the lower through hole penetrates the passivation layer and exposes the interconnection structure; and A pad is located in the pad channel, and the pad passes through the lower through hole from the upper through hole to be electrically connected to the interconnection structure.

8. The image sensor according to claim 7, wherein: Taking the back surface of the substrate as a reference, the depth of the ring channel and the upper through hole in the substrate is the same.

9. The image sensor according to claim 7, wherein: The passivation layer only covers the inner surface of the ring channel but does not fill the ring channel; or, the passivation layer fills the ring channel.

10. The image sensor according to any one of claims 1 to 9, characterized in that: The image sensor is a VPS image sensor.

11. A method for manufacturing an image sensor, characterized in that: include: Providing a substrate, the substrate comprising a pixel region, a peripheral circuit region and a pad region, the substrate having a front side and a back side opposite to the front side; Fabricate front trench isolation, a plurality of photosensitive pixels and an interconnection structure on the front side of the substrate, wherein the plurality of photosensitive pixels are located in the pixel area; bonding the front side of the substrate to a carrier; A back channel structure and a back trench isolation are fabricated on the back side of the substrate, wherein the back channel structure comprises a pad channel formed corresponding to the pad area and a ring channel surrounding the pixel area, and the peripheral circuit area and the pad area are located outside the ring channel; The front trench isolation and the back trench isolation include two trench isolations located inside the ring channel and vertically aligned, an ion doping region is formed in the substrate between the two trench isolations, and the two trench isolations and the ion doping region form a doping region isolation structure.

12. The manufacturing method according to claim 11, characterized in that: The front trench isolation includes a first trench isolation embedded in the front side of the substrate and not penetrating the substrate, the first trench isolation surrounds the pixel area, the peripheral circuit area and the pad area are located at the periphery of the first trench isolation, and the ring channel extends downward from the back side of the substrate to expose the first trench isolation.

13. The manufacturing method according to claim 11, characterized in that: Forming the trench isolation located on the back side of the substrate in the doped region isolation structure includes: Making a back side isolation trench on the back side of the substrate, wherein the bottom surface of the back side isolation trench exposes the ion doping region; and A high-k dielectric layer and a non-high-k isolation dielectric are fabricated on the back side of the substrate. The high-k dielectric layer conformally covers the back side of the substrate and the inner surface of the back isolation trench, and the non-high-k isolation dielectric fills the back isolation trench.

Images