Solar cell and preparation method thereof

Abstract

The invention relates to a solar cell and a preparation method thereof. The preparation method comprises the following steps: S1, cleaning and polishing a substrate silicon wafer; s2, forming a dielectric region and a polycrystalline silicon layer; s3, forming a dopant source layer and a mask layer of the first conductive type impurities; s4, one-step co-doping of impurities of different conductive types; s5, forming a dielectric layer; and S6, metallization. The dopant source layer of the first conductive type impurity and the mask layer are sequentially deposited, so that the dopant source layer of the first conductive type impurity can only serve as a doping source in a large probability and can be made into an extremely thin high-concentration layer, and the oxygen content of the silicon substrate is reduced; recombination is reduced, so that recombination of carriers in the solar cell is reduced, the photoelectric conversion efficiency is improved, and the light-induced degradation phenomenon can be reduced; the dopant source layer of the first conductive type impurity can be made into an extremely thin high-concentration layer, so that low-temperature boron doping can be matched.

Description

Technical Field

[0001] The present invention relates to the field of solar cells, and in particular to a solar cell and a preparation method thereof. Background Art

[0002] The pursuit of high-efficiency cells is a development trend in the photovoltaic industry. The solution takes both cost and process into consideration. The current mainstream product is still the PERC (passivated emitter rear surface fully doped) cell, but its efficiency has become a bottleneck, and a new cell structure, TOPCon (tunneling oxide passivated contact) cell, has been introduced. This structure provides good surface passivation for the back of the silicon substrate. The ultra-thin oxide layer allows majority electrons to tunnel into the polysilicon layer while blocking minority hole recombination. Then, electrons are transported laterally in the polysilicon layer and collected by metal, which greatly reduces the metal contact recombination current and improves the open circuit voltage and short circuit current of the cell.

[0003] The conventional process preparation routes of TOPCon batteries are limited by the different doping sources, temperatures and times of the P and N regions. Usually, boron doping is performed first and then phosphorus doping is performed. However, such a preparation route has the following shortcomings: ① It is necessary to grow a thicker BSG before phosphorus doping, usually with a thickness greater than 100nm, to block alkali polishing and alkali washing in RCA. However, thicker BSG will cause a higher oxygen content in the silicon wafer and severe BO recombination, resulting in a decrease in photoelectric conversion efficiency and photoinduced degradation. On the other hand, it cannot be cleaned within the limited pickling time, which will also cause recombination and further affect the conversion efficiency of the battery. ② It needs to undergo two high-temperature processes (phosphorus doping process and boron doping process) and two de-plating processes during the battery preparation process. The process is cumbersome, the process time is long, and the equipment investment cost is high. Summary of the invention

[0004] The present invention aims at the above problems, makes up for the deficiencies of the prior art, and provides a solar cell and a preparation method to solve the problems arising from the above background technology.

[0005] A first aspect of the present invention provides a method for preparing a solar cell, comprising the following steps: S1 cleans and polishes the substrate silicon wafer; S2 forms a dielectric region and a polysilicon layer; S3: forming a dopant source layer of first conductivity type impurities and a mask layer; S4 co-doping of impurities of different conductivity types in one step; S5 forms a dielectric layer; S6 Metallization.

[0006] Preferably, the thickness of the dopant source layer of the first conductive type impurities is 5nm-60nm, for example, 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, etc. More preferably, the thickness of the dopant source layer of the first conductive type impurities is 20-40nm.

[0007] In the present invention, the thickness of the dopant source layer of the first conductive type impurity is 5-60nm. When the thickness is less than 5nm, the doping concentration is too low, resulting in a decrease in the photoelectric conversion efficiency; when the thickness is greater than 60nm, the oxygen content of the silicon wafer will be high, resulting in serious recombination, resulting in a decrease in the photoelectric conversion efficiency and photoinduced degradation.

[0008] Preferably, the solar cell includes a substrate silicon wafer, the substrate silicon wafer having a front side facing the sun during normal operation and a back side opposite to the front side, the back side of the substrate silicon wafer being sequentially provided with the dielectric region and the polysilicon layer in a direction away from the substrate silicon wafer, and the dopant source layer of the first conductive type impurities being located outside the polysilicon layer.

[0009] Preferably, it also includes a texturing step, wherein the texturing step forms a front texturing surface on the front side of the substrate silicon wafer, or the texturing step forms a front texturing surface on the front side of the substrate silicon wafer and a back partial texturing surface on the back side, and the morphology and size of the front texturing surface and the back partial texturing surface are the same or different.

[0010] Preferably, the texturing step is performed before the dielectric region is formed in S2, and the texturing step also includes a first mask preparation step before the texturing step, wherein the first mask step forms a first mask layer on the back side of the substrate silicon wafer; or, the texturing step is performed after the dopant source layer of the first conductive type impurities is formed in S3.

[0011] Preferably, the S3 is formed in the doping source layer of the first conductive type impurities by CVD, with a formation temperature of 300°C-800°C and a time of 1min-90min. The forming raw materials include a boron source gas or a phosphorus source gas, and the boron source gas is at least one of BH3, TMB, BCl3, and BBr3, and the phosphorus source gas is at least one of PH3 and POCl3.

[0012] Preferably, the forming raw material also includes other gases, and the other gases are one or more gases of SiH4, N2O, NH3, Ar.

[0013] Preferably, the S3 dopant source layer of the first conductive type impurities is a silicon-containing compound layer containing first conductive type impurities, and the first conductive type impurities are boron, gallium or phosphorus.

[0014] Preferably, the mask layer of the S3 first conductivity type impurities is a composite film composed of one or more of silicon nitride, silicon oxynitride and silicon oxide, and the thickness of the mask layer is 2-200 nm.

[0015] By adopting the above technical solution, the mask layer is formed on the outside of the first dopant source layer. Its effects are as follows: ① Increase the temperature window and diffusion uniformity of the one-step co-diffusion: By forming the mask layer on the outside of the first dopant source layer, the mask thickness can be adjusted to match the dopant gas ratio and thickness of the first dopant source layer to different diffusion temperatures, and only a thinner first dopant source layer is needed to meet the doping concentration of the first conductive dopant in the poly or c-Si layer. The relatively thin dopant source layer is conducive to forming a uniform film thickness (when performing one-step co-diffusion, the first dopant source layer and the mask layer together prevent the second dopant from diffusing into the first doping region, so a thicker dopant source layer is not needed); ② Improve the uniformity of the intra-chip and inter-chip doping concentration of the first doping region of the polysilicon layer: Because of the mask process, the first dopant source layer is deposited more uniformly, and the mask layer helps to prevent the second dopant source layer from diffusing into the first doping region during one-step co-diffusion. The above advantages comprehensively improve the uniformity of the intra-chip and inter-chip doping concentration of the first doping region of the polysilicon layer. ③ Increase the film opening process window to ensure the uniformity within and between wafers after the film opening process: Because there is a mask layer on the outside of the first dopant source layer, the film opening depth can be controlled by adjusting the ratio of each gas in the mask layer and the formation thickness to protect the c-Si area in the film opening area from damage, thereby ensuring the uniformity within and between wafers after the film opening process.

[0016] Preferably, the doping temperature in the one-step co-doping of S4 impurities of different conductive types is 600°C-1000°C, more preferably, the doping temperature is 600°C-980°C, and the doping time is 5min-180min, and the doping time does not include the time required for heating and cooling.

[0017] Preferably, in the one-step co-doping of different conductive type impurities in S4, a doping source of a second conductive type impurity with electrical properties opposite to the first conductive type impurity is used to simultaneously form a first conductive type impurity region and a second conductive type impurity region, the first conductive type impurity region and the second conductive type impurity region have opposite electrical properties, and the one-step co-doping of different conductive type impurities is performed at least once.

[0018] Preferably, the doping source of the second conductive type impurity is a boron source gas or a phosphorus source gas, the boron source gas is at least one of BH3, TMB, BCl3, and BBr3, and the phosphorus source gas is at least one of PH3 and POCl3.

[0019] Preferably, after the S4 is co-doped with impurities of different conductive types in one step, it also includes a laser selective doping step, the wavelength of the laser selective doping step is 200nm-1064nm, the power is ≥1W, the scanning speed is 5m / s-50m / s, the frequency is 200kHz-2000kHz, and the laser selective doping obtains a local heavily doped region of the conductive type impurity region.

[0020] Preferably, after the laser selective doping, the step of removing the dopant source layer of the first conductive type impurities is also included, and the step of removing the dopant source layer of the first conductive type impurities is performed by pickling with hydrofluoric acid at a concentration of 0.5%-50% and the pickling time is 10s-1200s.

[0021] A second aspect of the present invention provides a solar cell, comprising a substrate silicon wafer; the substrate silicon wafer has a front side facing the sun during normal operation and a back side opposite to the front side, the front side of the substrate silicon wafer is provided with a front velvet surface, a second conductive type impurity region, a second dielectric layer, and a front metal electrode; the back side of the substrate silicon wafer is provided with a first dielectric region, a first conductive type impurity region, a first dielectric layer, and a back metal electrode; The first dielectric region is a first tunneling oxide layer; the first conductive type impurity region is a c-Si region or a polysilicon layer doped with first conductive type impurities, and the second conductive type impurity region is a c-Si region or a polysilicon layer doped with second conductive type impurities; The dopant source layer of the first conductive type impurities serves as a doping source of the c-Si region or the polysilicon layer of the first conductive type impurities, and the thickness of the dopant source layer of the first conductive type impurities is 5nm-60nm; The second conductive type impurity region and the first conductive type impurity region are simultaneously formed in one or more different conductive type impurity one-step co-doping steps; In the step of co-doping impurities of different conductivity types, at least once, a doping source having a second conductivity type impurity with electrical properties opposite to that of the first conductivity type is used, and part of the doping source is doped into part of the substrate silicon wafer; The first conductive type impurity region on the back side of the substrate silicon wafer has opposite electrical properties to the second conductive type impurity region on the front side of the substrate silicon wafer, and a local area of ​​the back metal electrode is connected to the back side of the substrate silicon wafer through the first dielectric layer.

[0022] Preferably, a second dielectric region is provided on the upper edge of the front velvet surface in a direction away from the substrate silicon wafer; a back local velvet surface and an edge velvet surface are provided on the lower edge of the first dielectric region in a direction close to the substrate silicon wafer, and a heavily doped region is also provided in the first conductive type impurity region and / or the second conductive type impurity region.

[0023] Preferably, the c-Si region is formed by film opening and cleaning, and the film opening method is at least one of laser, etching slurry, and photolithography; and the polysilicon layer is formed by CVD deposition.

[0024] A second aspect of the present invention further provides a solar cell, the solar cell comprising a substrate silicon wafer, the substrate silicon wafer having a front side facing the sun during normal operation and a back side opposite to the front side, the front side of the substrate silicon wafer being provided with a front velvet surface, a second conductive type impurity region, a second dielectric layer, and a front metal electrode in sequence from the inside to the outside; the back side of the substrate silicon wafer being provided with a first dielectric region, a first conductive type impurity region, a first dielectric layer, and a back metal electrode in sequence from the inside to the outside; The local area of ​​the front metal electrode penetrates the second dielectric layer to form an ohmic contact with the second conductive type impurity region; the local area of ​​the back metal electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity region; The first dielectric region is a first tunneling oxide layer; the first conductive type impurity region is a c-Si region or a polysilicon layer doped with first conductive type impurities; and the second conductive type impurity region is a c-Si region or a polysilicon layer doped with second conductive type impurities.

[0025] Compared with the prior art, the present invention has the following beneficial effects: The present invention deposits a dopant source layer and a mask layer of first conductive type impurities in sequence, and the following dopant source layer of first conductive type impurities can most likely only serve as a doping source, and can be made into an extremely thin high-concentration layer, so that the oxygen content of the silicon substrate is reduced, the recombination effect inside the battery is reduced, thereby improving the photoelectric conversion efficiency, and reducing the light-induced decay phenomenon; the present invention first forms a dopant source layer of first conductive type impurities, and when different conductive type impurities are co-doped in one step, the formed dopant source layer of first conductive type impurities can be used as a doping source, so that the first conductive type impurity region and the second conductive type impurity region are simultaneously doped with different conductive type impurities at high temperature in one step, and only one high-temperature doping is required, and the number of high-temperature doping times is reduced; on the other hand, the present invention only removes the dopant source layer of first conductive type impurities and RCA cleaning once, and the number of cleaning times is reduced, shortening the process and time of solar cells, and no more thermal processes, heating / cooling processes, and wet processes are required, simplifying the process steps and time of solar cells, and improving the output of battery cells, thereby saving production costs and facilitating large-scale production. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 This is a schematic diagram of the TOPCon battery structure in Example 1; Figure 2 This is a process flow chart of TOPCon battery preparation in Example 1; Figure 3 This is a schematic diagram of the TOPCon battery structure in Example 9; Figure 4 This is a process flow chart of TOPCon battery preparation in Example 9 and Examples 15-16; Figure 5 Schematic diagram of the TOPCon battery structure in Example 15; Figure 6 Schematic diagram of the TOPCon battery structure in Example 16.

[0027] In the figure: 1-front metal electrode, 2-second dielectric layer, 3-second conductivity type impurity polysilicon layer, 4-N-type silicon wafer, 5-first tunneling oxide layer, 6-first conductivity type impurity polysilicon layer, 7-first dielectric layer, 8-back metal electrode, 9-second conductivity type impurity polysilicon layer heavily doped region, 10-second tunneling oxide layer, 11-second conductivity type impurity c-Si region, 12-first conductivity type impurity c-Si region, 13-first conductivity type impurity polysilicon layer heavily doped region. DETAILED DESCRIPTION

[0028] The following will be combined with the accompanying drawings in the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work belong to the protection scope of the present invention.

[0029] A method for preparing a solar cell comprises the following steps: S1 cleans and polishes the substrate silicon wafer; S2 forms a dielectric region and a polysilicon layer; S3: forming a dopant source layer of first conductivity type impurities and a mask layer; S4 co-doping of impurities of different conductivity types in one step; S5 forms a dielectric layer; S6 Metallization.

[0030] The present invention deposits a dopant source layer and a mask layer of first conductive type impurities in sequence, and the following dopant source layer of first conductive type impurities can most likely only serve as a doping source and can be made into an extremely thin high-concentration layer, so that the oxygen content of the silicon substrate is reduced, the recombination effect inside the battery is reduced, thereby improving the photoelectric conversion efficiency and reducing the light-induced decay phenomenon; the present invention first forms a dopant source layer of first conductive type impurities, and when different conductive type impurities are co-doped in one step, the formed dopant source layer of first conductive type impurities can be used as a doping source, so that the first conductive type impurity region and the second conductive type impurity region are doped with different conductive type impurities at high temperature in one step, and there is only one high-temperature doping, and the number of high-temperature doping times is reduced; on the other hand, the present invention only removes the dopant source layer of first conductive type impurities and RCA cleaning once, and the number of cleaning times is reduced, shortening the process and time of solar cells, and no more thermal processes, heating / cooling processes, and wet processes are required, simplifying the process steps and time of solar cells, and improving the output of battery cells, thereby saving production costs and facilitating large-scale production.

[0031] As a preferred embodiment, the thickness of the dopant source layer of the first conductive type impurity is 5nm-60nm. For example: 5nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, etc. More preferably, the thickness of the dopant source layer of the first conductive type impurity is 20-40nm.

[0032] In the present invention, the thickness of the dopant source layer of the first conductive type impurity is 5-60nm. When the thickness is less than 5nm, the doping concentration is too low, resulting in a decrease in the photoelectric conversion efficiency; when the thickness is greater than 60nm, the oxygen content of the silicon wafer will be high, resulting in serious recombination, resulting in a decrease in the photoelectric conversion efficiency and photoinduced degradation.

[0033] As a preferred embodiment, the solar cell includes a substrate silicon wafer, the substrate silicon wafer having a front side facing the sun during normal operation and a back side opposite to the front side, the back side of the substrate silicon wafer being sequentially provided with the dielectric region and the polysilicon layer in a direction away from the substrate silicon wafer, and the dopant source layer of the first conductive type impurities being located outside the polysilicon layer.

[0034] As a preferred implementation, the substrate silicon base in S1 is N-type or P-type, has a resistivity of 0.1-3.0 Ωcm, and a thickness of 100-200 μm.

[0035] As a preferred implementation manner, the cleaning and polishing in S1 utilizes acid and alkali chemicals to remove organic contamination and metal impurities on the surface of the silicon substrate, and performs etching and polishing on the surface of the single crystal silicon substrate.

[0036] As a preferred embodiment, it also includes a texturing step, wherein the texturing step forms a front side texturing surface on the front side of the substrate silicon wafer, or the texturing step forms a front side texturing surface on the front side of the substrate silicon wafer and a back side partial texturing surface on the back side, and the morphology and size of the front side texturing surface and the back side partial texturing surface are the same or different.

[0037] As a preferred embodiment, the texturing step is performed before the dielectric region is formed in S2, and the texturing step also includes a first masking step, wherein the first masking step forms a first masking layer on the back of the substrate silicon wafer; or, the texturing step is performed after the dopant source layer of the first conductive type impurity is formed in S3. As a preferred embodiment, the texturing is performed by etching with one or more of 0.5-2wt% KOH and NaOH, and the etching time is 400s-600s.

[0038] As a preferred embodiment, the texturing step further includes a film opening step, wherein the film opening adopts at least one of laser, etching slurry, and photolithography. More preferably, laser film opening is adopted, and the parameters of laser film opening are set as follows: wavelength 355nm-1064nm, power ≥1W, scanning speed 5-50m / s, frequency 200kHz-2000kHz, and the film opening step forms a c-Si region.

[0039] As a preferred embodiment, the tunneling oxide layer and the Poly layer are formed by CVD in S2. In the CVD furnace tube, O2 is used as the oxidant, the oxidation temperature is 550-650°C, and the time is 2-4min to form a tunneling oxide layer with a thickness of 1-3nm; SiH4 is used as the reaction gas and N2 is used as the dilution gas, the formation temperature is 550-650°C, and the time is 20-150min to form a polysilicon layer on the surface of the tunneling oxide layer with a thickness of 50-400nm. The CVD method is PECVD or LPCVD.

[0040] As a preferred embodiment, the S3 forms the dopant source layer of the first conductive type impurities, and is formed by CVD, with a formation temperature of 300°C-800°C and a time of 1min-90min. The forming raw materials include a boron source gas or a phosphorus source gas, and the boron source gas is at least one of BH3, TMB, BCl3, and BBr3; the phosphorus source gas is at least one of PH3 and POCl3; and the CVD method is PECVD or LPCVD.

[0041] As a preferred embodiment, the forming raw material also includes other gases, and the other gases are one or more gases of SiH4, N2O, NH3, Ar.

[0042] As a preferred implementation, the S3 first conductive type impurity dopant source layer is a silicon compound layer containing first conductive impurities, and the first conductive impurities are boron, gallium or phosphorus.

[0043] As a preferred embodiment, the mask layer is formed by CVD in S3, and a mask layer is formed on the dopant source layer of the first conductive type impurity through chemical reaction and plasma reaction in the CVD furnace tube; the mask layer is a composite film composed of one or more of silicon nitride, silicon oxynitride, and silicon oxide, and its thickness is 2-200nm.

[0044] By adopting the above technical solution, the mask layer is formed on the outside of the first dopant source layer. Its effects are as follows: ① Increase the temperature window and diffusion uniformity of the one-step co-diffusion: By forming the mask layer on the outside of the first dopant source layer, the mask thickness can be adjusted to match the dopant gas ratio and thickness of the first dopant source layer to different diffusion temperatures, and only a thinner first dopant source layer is needed to meet the doping concentration of the first conductive dopant in the poly or c-Si layer. The relatively thin dopant source layer is conducive to forming a uniform film thickness (when performing one-step co-diffusion, the first dopant source layer and the mask layer together prevent the second dopant from diffusing into the first doping region, so a thicker dopant source layer is not needed); ② Improve the uniformity of the intra-chip and inter-chip doping concentration of the first doping region of the polysilicon layer: Because of the mask process, the first dopant source layer is deposited more uniformly, and the mask layer helps to prevent the second dopant source layer from diffusing into the first doping region during one-step co-diffusion. The above advantages comprehensively improve the uniformity of the intra-chip and inter-chip doping concentration of the first doping region of the polysilicon layer. ③ Increase the film opening process window to ensure the uniformity within and between wafers after the film opening process: Because there is a mask layer on the outside of the first dopant source layer, the film opening depth can be controlled by adjusting the ratio of each gas in the mask layer and the formation thickness to protect the c-Si area in the film opening area from damage, thereby ensuring the uniformity within and between wafers after the film opening process.

[0045] As a preferred embodiment, the S4 different conductive type impurities are co-doped in one step, the silicon wafer is placed in a doping tube for doping, a doping source of a second conductive type impurity with electrical properties opposite to the first conductive type impurity is used, and the doping temperature is 600℃-1000℃. As a more preferred embodiment, the doping temperature is 600℃-980℃, and the doping time is 5min-180min. The dopant source layer of the first conductive type impurity formed on the back of the silicon wafer can be used as a doping source and as a barrier layer for doping with another element during doping, so that the first conductive type impurities and the second conductive type impurity regions are doped at high temperature in one step to form a first conductive type impurity region and a second conductive type impurity region. The first conductive type impurity region and the second conductive type impurity region have opposite electrical properties, and the different conductive type impurities are co-doped in one step at least once.

[0046] As a preferred embodiment, the doping source of the second conductive type impurity is a boron source gas or a phosphorus source gas, the boron source gas is at least one of BH3, TMB, BCl3, and BBr3, and the phosphorus source gas is at least one of PH3 and POCl3.

[0047] As a preferred embodiment, after the S4 is co-doped with impurities of different conductive types in one step, it also includes laser selective doping, and the wavelength of the laser selective doping is 200nm-1064nm, the power is ≥1W, the scanning speed is 5-50m / s, and the frequency is 200kHz-2000kHz. The laser selective doping obtains a local heavily doped area of ​​the conductive type impurity area.

[0048] As a preferred embodiment, after the laser selective doping, the process also includes removing the dopant source layer of the first conductive type impurities, wherein the dopant source layer of the first conductive type impurities is removed by pickling with hydrofluoric acid at a concentration of 0.5%-50% for a pickling time of 10s-1200s; and then the silicon wafer is cleaned according to RCA standards to remove surface contaminants.

[0049] As a preferred embodiment, the S5 forms a dielectric layer, which is at least composed of an anti-reflection film. A 50-120nm anti-reflection film layer is formed by CVD. The reflective film layer is a composite film composed of one or more of silicon nitride, silicon oxynitride, and silicon oxide.

[0050] As a preferred implementation, the dielectric layer further includes a passivation film layer, the thickness of the passivation film layer is 2-15 nm, and the passivation film layer is aluminum oxide.

[0051] As a preferred embodiment, the S6 metallization is performed by providing a back metal electrode and a front metal electrode on a silicon substrate, and the electrode layer is preferably a silver electrode layer, to obtain the TOPCon battery structure.

[0052] As a preferred implementation, the forming of the polysilicon layer in S2, the forming of the dopant source layer of the first conductive type impurities in S3, the doping in S4 and the forming of the dielectric layer in S5 are dual insertion mode.

[0053] Since many working sections of the present invention are changed from a single-insertion mode to a double-insertion mode, production costs are saved, output is increased, and large-scale production is facilitated.

[0054] This embodiment also provides a solar cell, comprising a substrate silicon wafer; the substrate silicon wafer has a front side facing the sun during normal operation and a back side opposite to the front side, the front side of the substrate silicon wafer is provided with a front velvet surface, a second conductive type impurity region, a second dielectric layer, and a front metal electrode; the back side of the substrate silicon wafer is provided with a first dielectric region, a first conductive type impurity region, a first dielectric layer, and a back metal electrode; The first dielectric region is a first tunneling oxide layer, the first conductive type impurity region is a c-Si region or a polysilicon layer doped with first conductive type impurities, and the second conductive type impurity region is a c-Si region or a polysilicon layer doped with second conductive type impurities; The dopant source layer of the first conductive type impurities serves as a doping source of the c-Si region or the polysilicon layer of the first conductive type impurities, and the thickness of the dopant source layer of the first conductive type impurities is 5nm-60nm; The second conductive type impurity region and the first conductive type impurity region are simultaneously formed in one or more different conductive type impurity one-step co-doping steps; In the step of co-doping impurities of different conductivity types, at least once, a doping source having a second conductivity type impurity with electrical properties opposite to that of the first conductivity type is used, and part of the doping source is doped into part of the substrate silicon wafer; The first conductive type impurity region on the back side of the substrate silicon wafer has opposite electrical properties to the second conductive type impurity region on the front side of the substrate silicon wafer, and a local area of ​​the back metal electrode is connected to the back side of the substrate silicon wafer through the first dielectric layer.

[0055] As a preferred embodiment, a second dielectric region is further arranged on the upper edge of the front velvet surface in a direction away from the substrate silicon wafer; a back local velvet surface and an edge velvet surface are further arranged on the lower edge of the first dielectric region in a direction close to the substrate silicon wafer, and a heavily doped region is also arranged in the first conductive type impurity region and / or the second conductive type impurity region.

[0056] As a preferred embodiment, the c-Si region is formed by film opening and cleaning, and the film opening method is at least one of laser, etching slurry, and photolithography; the polysilicon layer is formed by CVD deposition.

[0057] This embodiment also provides another solar cell structure, the solar cell includes a substrate silicon wafer, the substrate silicon wafer has a front side facing the sun during normal operation and a back side opposite to the front side, the front side of the substrate silicon wafer is sequentially provided with a front velvet surface, a second conductive type impurity region, a second dielectric layer, and a front metal electrode from the inside to the outside; the back side of the substrate silicon wafer is sequentially provided with a first dielectric region, a first conductive type impurity region, a first dielectric layer, and a back metal electrode from the inside to the outside; The local area of ​​the front metal electrode penetrates the second dielectric layer to form an ohmic contact with the second conductive type impurity region; the local area of ​​the back metal electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity region; The first dielectric region is a first tunneling oxide layer; the first conductive type impurity region is a c-Si region or a polysilicon layer doped with first conductive type impurities, and the second conductive type impurity region is a c-Si region or a polysilicon layer doped with second conductive type impurities.

[0058] The solar cell and the preparation method thereof of the present invention are further described below through specific examples and comparative examples.

[0059] Example 1

[0060] like Figure 1 As shown, an N-type TOPCon battery includes an N-type silicon wafer 4, the N-type silicon wafer 4 is a substrate silicon wafer, and the front side of the N-type silicon wafer 4 is sequentially provided with a second conductive type impurity polysilicon layer 3, a second dielectric layer 2, and a front metal electrode 1 from the inside to the outside; the back side of the N-type silicon wafer 4 is sequentially provided with a first tunneling oxide layer 5, a first conductive type impurity polysilicon layer 6, a first dielectric layer 7, and a back metal electrode 8 from the inside to the outside; The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 30 nm.

[0061] like Figure 2 As shown, the method for preparing the N-type TOPCon battery in this embodiment includes the following steps: 1. Select a P-doped N-type silicon substrate with a resistivity of 1.5Ωcm and a thickness of 150μm; use acid and alkali chemicals to eliminate organic contamination and metal impurities on the surface of the silicon substrate, and perform corrosion polishing on the surface of the single crystal silicon substrate.

[0062] 2. In a PECVD furnace tube, N2O is used as an oxidant, the oxidation temperature is 600°C, and the time is 3 minutes. A first tunneling oxide layer with a thickness of 3nm is formed on the back of the silicon substrate; SiH4 is used as a reaction gas, Ar is used as a dilution gas, the formation temperature is 600°C, and the time is 90 minutes. A polysilicon layer with a thickness of 250nm is formed on the surface of the first tunneling oxide layer.

[0063] 3. In a PECVD furnace tube, PH3, SiH4, N2O, and NH3 are used as raw materials, the formation temperature is 600°C, and the time is 50 minutes. A phosphorus-containing silicon oxide compound layer with a thickness of 30 nm is formed on the polysilicon layer, and a silicon oxide mask layer with a thickness of 100 nm is formed on the phosphorus-containing silicon oxide compound layer.

[0064] 4. Use 1.3% NaOH solution for etching for 500 seconds to prepare a velvet surface on the front side of the silicon substrate.

[0065] 5. Place the silicon substrate into a boron-doped tube for one-step co-doping of boron and phosphorus. The doping temperature is 800°C, the doping time is 100 min, and the boron doping source is BBr3 to form a second conductive type impurity polysilicon layer. The phosphorus-containing silicon oxide layer on the back is used as a doping source for the first conductive type impurities to obtain a first conductive type impurity polysilicon layer, which can also be used as a boron-doped barrier layer. The number of one-step co-doping of boron and phosphorus is 2 times.

[0066] 6. Place the silicon substrate in 25% HF for pickling for 600 seconds to remove the phosphorus-containing silicon oxide layer, boron-containing silicon oxide layer and mask layer of the silicon substrate; then perform RCA standard cleaning on the silicon substrate to remove surface contaminants.

[0067] 7. The ALD atomic layer formation method is adopted, TMA is used as a precursor, and the reaction temperature is controlled at 300°C to form a dense Al2O3 passivation layer with a thickness of 10nm on the front and back sides of the silicon substrate. The PECVD method is used to form a 100nm SiO2 anti-reflection layer on the front and back sides of the silicon substrate. The passivation layer and the anti-reflection layer form a dielectric layer.

[0068] 8. Print Ag paste on the front and back sides of the silicon substrate, and after drying and sintering, obtain the back metal electrode and the front metal electrode.

[0069] Example 2

[0070] An N-type TOPCon battery, comprising an N-type silicon wafer, wherein a second conductive type impurity polysilicon layer, a heavily doped region of the second conductive type impurity polysilicon layer, a second dielectric layer, and a front metal electrode are sequentially arranged on the front side of the N-type silicon wafer from inside to outside; and a first tunneling oxide layer, a first conductive type impurity polysilicon layer, a first dielectric layer, and a back metal electrode are sequentially arranged on the back side of the N-type silicon wafer from inside to outside; A local area of ​​the front metal electrode penetrates the second dielectric layer to form an ohmic contact with the heavily doped area of ​​the second conductive type impurity polysilicon layer; a local area of ​​the back metal electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon layer.

[0071] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 30 nm.

[0072] The method for preparing the N-type TOPCon battery in this embodiment includes the following steps: 1. Select a P-doped N-type silicon wafer with a resistivity of 1.5Ωcm and a thickness of 150μm; use acid and alkali chemicals to remove organic contamination and metal impurities on the surface of the silicon wafer, and corrode and polish the surface of the single crystal silicon wafer.

[0073] 2. In the LPCVD furnace tube, N2O is used as the oxidant, the oxidation temperature is 500℃, and the time is 300s. A first tunneling oxide layer with a thickness of 3nm is formed on the back of the silicon wafer; SiH4 is used as the reaction gas and Ar is used as the dilution gas. The formation temperature is 500℃ and the time is 1800s. A polysilicon layer with a thickness of 250nm is formed on the surface of the first tunneling oxide layer.

[0074] 3. In an LPCVD furnace tube, using PH3, SiH4, N2O, Ar, and NH3 as raw materials, a temperature of 600°C and a time of 50 minutes are formed to form a 30nm thick phosphorus-containing silicon oxide layer on the polysilicon layer, and a 100nm thick silicon oxide mask layer is formed on the phosphorus-containing silicon oxide layer.

[0075] 4. Use 1.3% NaOH solution for etching for 500s to form a front pyramid velvet surface on the front of the silicon wafer (not shown in the figure).

[0076] 5. Place the silicon wafer in a boron-doped tube for boron-phosphorus co-doping. The doping temperature is 950°C, the doping time is 100 minutes, the boron doping source is BBr3, and a second conductive type impurity polysilicon layer is formed on the front of the silicon wafer. The phosphorus-containing silicon oxide compound layer on the back can be used as a doping source for the first conductive type impurity polysilicon layer to form the first conductive type impurity polysilicon layer, and can also be used as a boron-doped barrier layer. The number of boron-phosphorus co-doping steps is 2 times. During laser selective doping, the wavelength is set to 532nm, the scanning speed is 25m / s, and the frequency is 1000kHz. The metal contact area forms a heavily doped area of ​​the second conductive type impurity polysilicon layer, and the non-metal contact opening area forms the second conductive type impurity polysilicon.

[0077] 6. Place the silicon wafer in 25% HF for pickling for 600 seconds to remove the phosphorus-containing silicon oxide layer, boron-containing silicon oxide layer and mask layer of the silicon wafer; then perform RCA standard cleaning on the silicon wafer to remove surface contaminants.

[0078] 7. The ALD atomic layer formation method is adopted, TMA is used as the precursor, and the reaction temperature is controlled at 300°C to form a dense Al2O3 passivation layer with a thickness of 8nm on the front and back of the silicon wafer. The LPCVD method is then used to form an 80nm SiNx anti-reflection layer on the front and back of the silicon wafer. The passivation layer and the anti-reflection layer form a dielectric layer.

[0079] 8. Print Ag paste on the front and back of the silicon wafer, and after drying and sintering, obtain the front and back metal electrodes.

[0080] Example 3 An N-type TOPCon battery, comprising a polished N-type silicon wafer, wherein a front velvet surface, a second conductive type impurity polysilicon layer, a second dielectric layer, and a front metal electrode are sequentially arranged on the front side of the polished N-type silicon wafer from the inside to the outside; and a first tunneling oxide layer, a first conductive type impurity polysilicon layer, a first dielectric layer, and a back metal electrode are sequentially arranged on the back side of the polished N-type silicon wafer from the inside to the outside; A local area of ​​the front metal electrode penetrates the second dielectric layer to form an ohmic contact with the second conductive type impurity polysilicon layer; a local area of ​​the back metal electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon layer.

[0081] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 30 nm.

[0082] The method for preparing the N-type TOPCon battery in this embodiment includes the following steps: 1. Select a P-doped N-type silicon wafer with a resistivity of 1.5Ωcm and a thickness of 150μm; use acid and alkali chemicals to remove organic contamination and metal impurities on the surface of the silicon wafer, and corrode and polish the surface of the single crystal silicon wafer.

[0083] 2. In the LPCVD furnace tube, a first mask layer is formed on the back of the silicon wafer through chemical reaction and plasma reaction; the first mask layer is SiO2, and its thickness is 100nm.

[0084] 3. Use 1.3% NaOH solution for etching for 500s to form a front pyramid velvet surface on the front of the silicon wafer.

[0085] 4. In a PECVD furnace tube, N2O is used as an oxidant, the oxidation temperature is 500°C, and the time is 300s. A first tunneling oxide layer with a thickness of 3nm is formed on the back of the silicon wafer; SiH4 is used as a reaction gas, Ar is used as a diluent gas, the formation temperature is 500°C, and the time is 1800s. A polysilicon layer with a thickness of 250nm is formed on the surface of the first tunneling oxide layer.

[0086] 5. In an LPCVD furnace tube, using PH3, SiH4, N2O, Ar, and NH3 as raw materials, a temperature of 600°C and a time of 50 min are formed to form a 30 nm thick phosphorus-containing silicon oxide compound layer on the polysilicon layer, and a 100 nm thick silicon oxide mask layer is formed on the phosphorus-containing silicon oxide compound layer.

[0087] 6. Place the silicon wafer in a boron doping tube for boron-phosphorus co-doping, the doping temperature is 800°C, the doping time is 100 minutes, the boron doping source is BBr3, and the second conductive type impurity polysilicon layer is formed on the front of the silicon wafer. The phosphorus-containing silicon oxide compound layer on the back can be used as a doping source for the first conductive type impurity polysilicon layer to form the first conductive type impurity polysilicon layer, and can also be used as a barrier layer for boron doping. The number of boron-phosphorus co-doping in one step is 2 times.

[0088] 7. Place the silicon wafer in 25% HF for pickling for 600 seconds to remove the phosphorus-containing silicon oxide layer, boron-containing silicon oxide layer and mask layer of the silicon wafer; then perform RCA standard cleaning on the silicon wafer to remove surface contaminants.

[0089] 8. Use LPCVD to form an 80nm SiNx anti-reflection layer on the front and back of the silicon wafer, and the passivation layer and the anti-reflection layer form a dielectric layer.

[0090] 9. Print Ag paste on the front and back of the silicon wafer, and after drying and sintering, obtain the front and back metal electrodes.

[0091] Example 4 An N-type TOPCon battery comprises an N-type silicon wafer, wherein a second conductive type impurity polysilicon layer, a second dielectric layer, and a front metal electrode are sequentially arranged on the front side of the N-type silicon wafer from the inside to the outside; and a first tunneling oxide layer, a first conductive type impurity polysilicon layer, a first dielectric layer, and a back metal electrode are sequentially arranged on the back side of the N-type silicon wafer from the inside to the outside; A local area of ​​the front metal electrode penetrates the second dielectric layer to form an ohmic contact with the second conductive type impurity polysilicon layer; a local area of ​​the back metal electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon layer.

[0092] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 5 nm.

[0093] The method for preparing the N-type TOPCon battery in this embodiment includes the following steps: 1. Select a P-doped N-type silicon wafer with a resistivity of 0.1Ωcm and a thickness of 100μm; use acid and alkali chemicals to remove organic contamination and metal impurities on the surface of the silicon wafer, and corrode and polish the surface of the single crystal silicon wafer.

[0094] 2. In a PECVD furnace tube, N2O is used as an oxidant, the oxidation temperature is 300°C, and the time is 600s. A first tunneling oxide layer with a thickness of 2nm is formed on the back of the silicon wafer; SiH4 is used as a reaction gas, Ar is used as a diluent gas, the formation temperature is 300°C, and the time is 3600s. A polysilicon layer with a thickness of 50nm is formed on the surface of the first tunneling oxide layer.

[0095] 3. In a PECVD furnace tube, POCl3, SiH4, N2O, Ar, and NH3 are used as raw materials, the temperature is 300°C, and the time is 1 min. A 5 nm thick phosphorus-containing silicon oxide compound layer is formed on the polysilicon layer, and a 200 nm thick silicon oxide mask layer is deposited on the phosphorus-containing silicon compound layer.

[0096] 4. Use 0.5% NaOH solution for etching for 600s to form a pyramid velvet surface on the front side of the silicon wafer.

[0097] 5. Place the silicon wafer in step 4 into a boron doping tube for one-step co-doping of boron and phosphorus. The doping temperature is 600°C, the doping time is 180 minutes, the boron doping source is BBr3, and a second conductive type impurity polysilicon layer is formed on the front of the silicon wafer. The phosphorus-containing silicon oxide compound layer on the back can be used as a doping source for the first conductive type impurity polysilicon layer to form the first conductive type impurity polysilicon layer, and can also be used as a barrier layer for boron doping. The number of one-step co-doping of boron and phosphorus is 4 times.

[0098] 6. Place the silicon wafer in 0.5% HF for pickling for 1200 seconds to remove the phosphorus-containing silicon oxide layer, boron-containing silicon oxide layer and mask layer of the silicon wafer; then perform RCA standard cleaning on the silicon wafer to remove surface contaminants.

[0099] 7. The ALD atomic layer formation method is adopted, TMA is used as the precursor, and the reaction temperature is controlled at 300°C to form a dense Al2O3 passivation layer with a thickness of 2nm on the front and back of the silicon wafer. The LPCVD method is then used to form a 50nm SiNx anti-reflection layer on the front and back of the silicon wafer. The passivation layer and the anti-reflection layer form a dielectric layer.

[0100] 8. Print Ag paste on the front and back of the silicon wafer, and after drying and sintering, obtain the front and back metal electrodes.

[0101] Example 5 An N-type TOPCon battery comprises an N-type silicon wafer, wherein a second conductive type impurity polysilicon layer, a second dielectric layer, and a front metal electrode are sequentially arranged on the front side of the N-type silicon wafer from the inside to the outside; and a first tunneling oxide layer, a first conductive type impurity polysilicon layer, a first dielectric layer, and a back metal electrode are sequentially arranged on the back side of the N-type silicon wafer from the inside to the outside; A local area of ​​the front metal electrode penetrates the second dielectric layer to form an ohmic contact with the second conductive type impurity polysilicon layer; a local area of ​​the back metal electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon layer.

[0102] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 60 nm.

[0103] The method for preparing the N-type TOPCon battery in this embodiment includes the following steps: 1. Select a P-doped N-type single crystal silicon wafer with a resistivity of 3Ωcm and a thickness of 200μm; use acid and alkali chemicals to remove organic contamination and metal impurities on the surface of the silicon wafer, and corrode and polish the surface of the single crystal silicon wafer.

[0104] 2. In the LPCVD furnace tube, N2O is used as the oxidant, the oxidation temperature is 650°C, and the time is 60s. A first tunneling oxide layer with a thickness of 4nm is formed on the back of the silicon wafer. SiH4 is used as the reaction gas and Ar is used as the dilution gas. The formation temperature is 650°C and the time is 300s. A polysilicon layer with a thickness of 400nm is formed on the surface of the first tunneling oxide layer.

[0105] 3. In an LPCVD furnace tube, using PH3, SiH4, N2O, Ar, and NH3 as raw materials, a temperature of 800°C and a time of 90 minutes are formed to form a 60nm thick phosphorus-containing silicon oxide compound layer on the polysilicon layer, and a 2nm thick silicon oxide mask layer is deposited on the phosphorus-containing silicon compound layer.

[0106] 4. Use 2% NaOH solution for etching for 400s to prepare a pyramid velvet surface on the front side of the silicon wafer.

[0107] 5. Place the silicon wafer in a boron doping tube for boron-phosphorus co-doping, the doping temperature is 1000°C, the doping time is 5 minutes, the boron doping source is BBr3, and the second conductive type impurity polysilicon layer is formed on the front of the silicon wafer. The phosphorus-containing silicon oxide compound layer on the back can be used as a doping source for the first conductive type impurity polysilicon layer to form the first conductive type impurity polysilicon layer, and can also be used as a barrier layer for boron doping. The number of boron-phosphorus co-doping in one step is 1.

[0108] 6. Place the silicon wafer in 50% HF for pickling for 10 seconds to remove the phosphorus-containing silicon oxide layer, boron-containing silicon oxide layer and mask layer of the silicon wafer; then perform RCA standard cleaning on the silicon wafer to remove surface contaminants.

[0109] 7. The ALD atomic layer formation method is adopted, TMA is used as the precursor, and the reaction temperature is controlled at 300°C to form a dense Al2O3 passivation layer with a thickness of 15nm on the front and back of the silicon wafer. The LPCVD method is then used to form a 120nm SiNx anti-reflection layer on the front and back of the silicon wafer. The passivation layer and the anti-reflection layer form a dielectric layer.

[0110] 8. Print Ag paste on the front and back of the silicon wafer, and after drying and sintering, obtain the front and back metal electrodes.

[0111] Example 6 A P-type TOPCon cell, comprising a P-type silicon wafer, wherein a second conductive type impurity polysilicon layer, a second dielectric layer, and a front metal electrode are sequentially arranged on the front side of the P-type silicon wafer from the inside to the outside; and a first tunneling oxide layer, a first conductive type impurity polysilicon layer, a first dielectric layer, and a back metal electrode are sequentially arranged on the back side of the P-type silicon wafer from the inside to the outside; A local area of ​​the front metal electrode penetrates the second dielectric layer to form an ohmic contact with the second conductive type impurity polysilicon layer; a local area of ​​the back metal electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon layer.

[0112] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is boron, and the thickness of the dopant source layer of the first conductive type impurity is 30 nm.

[0113] The preparation method of this embodiment is different from that of embodiment 1 in that: 1. The single crystal silicon wafer is B-doped P-type single crystal silicon wafer; 3. Using BH3, SiH4, N2O, Ar, and NH3 as raw materials, a boron-containing silicon oxide layer with a thickness of 30 nm is formed; 5. Place the silicon wafer in a phosphorus-doped tube for boron-phosphorus co-doping, the doping temperature is 800°C, the doping time is 100 min, the phosphorus doping source is POCl3, and a second conductive type impurity polysilicon layer is formed on the front side of the silicon wafer; the boron-containing silicon oxide compound layer on the back side can be used as a doping source for the first conductive type impurity polysilicon layer to form the first conductive type impurity polysilicon layer, and can also be used as a phosphorus-doped barrier layer; The rest are the same.

[0114] Example 7 An N-type TOPCon battery comprises an N-type silicon wafer, wherein a second conductive type impurity polysilicon layer, a second dielectric layer, and a front metal electrode are sequentially arranged on the front side of the N-type silicon wafer from the inside to the outside; and a first tunneling oxide layer, a first conductive type impurity polysilicon layer, a first dielectric layer, and a back metal electrode are sequentially arranged on the back side of the N-type silicon wafer from the inside to the outside; A local area of ​​the front metal electrode penetrates the second dielectric layer to form an ohmic contact with the second conductive type impurity polysilicon layer; a local area of ​​the back metal electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon layer.

[0115] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 3 nm.

[0116] The preparation method of this embodiment is different from that of embodiment 4 in that: 3. A 3 nm thick phosphorus-containing silicon oxide layer is formed; The rest are the same.

[0117] Example 8 An N-type TOPCon battery comprises an N-type silicon wafer, wherein a second conductive type impurity polysilicon layer, a second dielectric layer, and a front metal electrode are sequentially arranged on the front side of the N-type silicon wafer from the inside to the outside; and a first tunneling oxide layer, a first conductive type impurity polysilicon layer, a first dielectric layer, and a back metal electrode are sequentially arranged on the back side of the N-type silicon wafer from the inside to the outside; A local area of ​​the front metal electrode penetrates the second dielectric layer to form an ohmic contact with the second conductive type impurity polysilicon layer; a local area of ​​the back metal electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon layer.

[0118] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 62 nm.

[0119] The preparation method of this embodiment is different from that of embodiment 5 in that: 3. A phosphorus-containing silicon oxide layer with a thickness of 62 nm is formed; The rest are the same.

[0120] Example 9 like Figure 3 As shown, an N-type TOPCon battery comprises an N-type silicon wafer 4, wherein the front side of the N-type silicon wafer 4 is provided with a second tunneling oxide layer 10, a second conductive type impurity polysilicon layer heavily doped region 9, a second conductive type impurity c-Si region 11, a second dielectric layer 2, and a front metal electrode 1 in sequence from the inside to the outside; the back side of the N-type silicon wafer 4 is provided with a first tunneling oxide layer 5, a first conductive type impurity polysilicon layer 6, a first dielectric layer 7, and a back metal electrode 8 in sequence from the inside to the outside; A local area of ​​the front metal electrode penetrates the second dielectric layer to form an ohmic contact with the heavily doped area of ​​the second conductive type impurity polysilicon layer; a local area of ​​the back metal electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon layer.

[0121] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 30 nm.

[0122] like Figure 4 As shown, the preparation method of this embodiment is different from that of embodiment 1 in that: 2. In a PECVD furnace tube, N2O is used as an oxidant, the oxidation temperature is 500°C, and the time is 300s. A second tunneling oxide layer and a first tunneling oxide layer with a thickness of 3nm are formed on the front and back sides of the silicon wafer respectively; SiH4 is used as a reaction gas, Ar is used as a diluent gas, the formation temperature is 500°C, and the time is 1800s. A polysilicon layer with a thickness of 250nm is formed on the surface of the tunneling oxide layer; 4. Laser film opening is first used before texturing. The non-metallic contact area on the front of the silicon wafer is laser opened to form a c-Si area. The parameters of laser film opening are set as follows: wavelength 600nm, power ≥1W, scanning speed 25m / s, frequency 1000kHz; 5. During laser selective doping, the wavelength is set to 532nm, the scanning speed is 25m / s, and the frequency is 1000kHz. The metal contact area forms a heavily doped region of the second conductive type impurity polysilicon layer, and the non-metal contact open film area forms a second conductive type impurity c-Si region; The rest are the same.

[0123] Example 10 An N-type TOPCon battery comprises an N-type silicon wafer, wherein a second conductive type impurity c-Si region, a second dielectric layer, a second tunneling oxide layer, a second conductive type impurity polysilicon layer heavily doped region, and a front metal electrode are sequentially arranged on the front side of the N-type silicon wafer from inside to outside; and a first tunneling oxide layer, a first conductive type impurity polysilicon layer, a first dielectric layer, and a back metal electrode are sequentially arranged on the back side of the N-type silicon wafer from inside to outside; A local area of ​​the front metal electrode penetrates the second dielectric layer to form an ohmic contact with the heavily doped area of ​​the second conductive type impurity polysilicon layer; a local area of ​​the back metal electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon layer.

[0124] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 5 nm.

[0125] The preparation method of this embodiment is different from that of embodiment 4 in that: 2. In a PECVD furnace tube, N2O is used as an oxidant, the oxidation temperature is 300°C, and the time is 600s. A second tunneling oxide layer and a first tunneling oxide layer with a thickness of 2nm are formed on the front and back sides of the silicon wafer respectively; SiH4 is used as a reaction gas, Ar is used as a diluent gas, the formation temperature is 300°C, and the time is 3600s. A polysilicon layer with a thickness of 50nm is formed on the surface of the tunneling oxide layer; 4. Laser film opening is first used before texturing. The non-metallic contact area on the front of the silicon wafer is laser-opened to form a c-Si area. The parameters of laser film opening are set as follows: wavelength 355nm, power ≥1W, scanning speed 5m / s, frequency 2000kHz; 5. During laser selective doping, the wavelength is set to 1064nm, the scanning speed is 50m / s, and the frequency is 2000kHz. The metal contact area forms a heavily doped area of ​​the second conductive type impurity polysilicon layer, and the non-metal contact open film area forms a second conductive type impurity c-Si area; The rest are the same.

[0126] Embodiment 11 An N-type TOPCon battery comprises an N-type silicon wafer, wherein a second conductive type impurity c-Si region, a second dielectric layer, a second tunneling oxide layer, a second conductive type impurity polysilicon layer heavily doped region, and a front metal electrode are sequentially arranged on the front side of the N-type silicon wafer from inside to outside; and a first tunneling oxide layer, a first conductive type impurity polysilicon layer, a first dielectric layer, and a back metal electrode are sequentially arranged on the back side of the N-type silicon wafer from inside to outside; A local area of ​​the front metal electrode penetrates the second dielectric layer to form an ohmic contact with the heavily doped area of ​​the second conductive type impurity polysilicon layer; a local area of ​​the back metal electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon layer.

[0127] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 60 nm.

[0128] The preparation method of this embodiment is different from that of embodiment 5 in that: 2. In a PECVD furnace tube, N2O is used as an oxidant, the oxidation temperature is 650°C, and the time is 60s. A second tunneling oxide layer and a first tunneling oxide layer with a thickness of 4nm are formed on the front and back sides of the silicon wafer respectively; SiH4 is used as a reaction gas and Ar is used as a diluent gas. The formation temperature is 650°C and the time is 300s. A polysilicon layer with a thickness of 400nm is formed on the surface of the tunneling oxide layer; 4. Laser film opening is first used before texturing. The non-metallic contact area on the front of the silicon wafer is laser opened to form a c-Si area. The parameters of laser film opening are set as follows: wavelength 1064nm, power ≥1W, scanning speed 50m / s, frequency 200kHz; 5. During laser selective doping, the wavelength is set to 200nm, the scanning speed is 5m / s, and the frequency is 200kHz. The metal contact area forms a heavily doped area of ​​the second conductive type impurity polysilicon layer, and the non-metal contact open film area forms a second conductive type impurity c-Si area; The rest are the same.

[0129] Example 12 A P-type TOPCon battery comprises a P-type silicon wafer, wherein the front side of the P-type silicon wafer is provided with a second conductive type impurity c-Si region, a second dielectric layer, a second tunneling oxide layer, a second conductive type impurity polysilicon layer heavily doped region, and a front metal electrode in sequence from the inside to the outside; and the back side of the P-type silicon wafer is provided with a first tunneling oxide layer, a first conductive type impurity polysilicon layer, a first dielectric layer, and a back metal electrode in sequence from the inside to the outside; A local area of ​​the front metal electrode penetrates the second dielectric layer to form an ohmic contact with the heavily doped area of ​​the second conductive type impurity polysilicon layer; a local area of ​​the back metal electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon layer.

[0130] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is boron, and the thickness of the dopant source layer of the first conductive type impurity is 30 nm.

[0131] The preparation method of this embodiment is different from that of embodiment 9 in that: 1. The single crystal silicon wafer is B-doped P-type single crystal silicon wafer; 3. Using BH3, SiH4, N2O, Ar, and NH3 as raw materials, a boron-containing silicon-oxygen compound layer with a thickness of 30 nm is formed; 5. The doping source is POCl3. During laser selective doping, the wavelength is set to 532nm, the scanning speed is 25m / s, and the frequency is 1000kHz. The metal contact area forms a heavily doped area of ​​the second conductive type impurity polysilicon layer, and the non-metal contact open film area forms a second conductive type impurity c-Si area; Example 13

[0132] An N-type TOPCon battery comprises an N-type silicon wafer, wherein a second conductive type impurity c-Si region, a second dielectric layer, a second tunneling oxide layer, a second conductive type impurity polysilicon layer heavily doped region, and a front metal electrode are sequentially arranged on the front side of the N-type silicon wafer from inside to outside; and a first tunneling oxide layer, a first conductive type impurity polysilicon layer, a first dielectric layer, and a back metal electrode are sequentially arranged on the back side of the N-type silicon wafer from inside to outside; A local area of ​​the front metal electrode penetrates the second dielectric layer to form an ohmic contact with the heavily doped area of ​​the second conductive type impurity polysilicon layer; a local area of ​​the back metal electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon layer.

[0133] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 3 nm.

[0134] The preparation method of this embodiment is different from that of embodiment 10 in that: 3. The thickness of the phosphorus-containing silicon oxide compound layer formed in the process is 3 nm; The rest are the same.

[0135] Embodiment 14 An N-type TOPCon battery comprises an N-type silicon wafer, wherein a second conductive type impurity c-Si region, a second dielectric layer, a second tunneling oxide layer, a second conductive type impurity polysilicon layer heavily doped region, and a front metal electrode are sequentially arranged on the front side of the N-type silicon wafer from inside to outside; and a first tunneling oxide layer, a first conductive type impurity polysilicon layer, a first dielectric layer, and a back metal electrode are sequentially arranged on the back side of the N-type silicon wafer from inside to outside; A local area of ​​the front metal electrode penetrates the second dielectric layer to form an ohmic contact with the heavily doped area of ​​the second conductive type impurity polysilicon layer; a local area of ​​the back metal electrode penetrates the first dielectric layer to form an ohmic contact with the first conductive type impurity polysilicon layer.

[0136] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 62 nm.

[0137] The preparation method of this embodiment is different from that of embodiment 11 in that: 3. The thickness of the phosphorus-containing silicon oxide layer formed in the process is 62 nm; The rest are the same.

[0138] Embodiment 15 like Figure 5 As shown, an N-type TOPCon battery comprises an N-type silicon wafer 4, wherein a second conductive type impurity polysilicon layer 3, a second dielectric layer 2, and a front metal electrode 1 are sequentially arranged on the front side of the N-type silicon wafer 4 from the inside to the outside; a first conductive type impurity c-Si region 12, a first dielectric layer 7, a first tunneling oxide layer 5, a first conductive type impurity polysilicon layer heavily doped region 13, and a back metal electrode 8 are sequentially arranged on the back side of the N-type silicon wafer 4 from the inside to the outside, wherein the first tunneling oxide layer 5 is directly in contact with the back side of the N-type silicon wafer 4, and the first conductive type impurity polysilicon layer heavily doped region 13 is arranged on the outside of the first tunneling oxide layer 5; A local area of ​​the front metal electrode penetrates the second dielectric layer to form an ohmic contact with the second conductive type impurity polysilicon layer; a local area of ​​the back metal electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped area of ​​the first conductive type impurity polysilicon layer.

[0139] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 30 nm.

[0140] The preparation method of this embodiment is different from that of embodiment 9 in that: 4. First use laser opening and then texturing to open the non-metallic contact area on the back of the silicon wafer to form a c-Si area. The parameters of laser opening are set as follows: wavelength 600nm, power ≥1W, scanning speed 25m / s, frequency 1000kHz; then use 1.3% NaOH solution for etching, the etching time is 500s, and a front pyramid velvet surface is formed on the front and back of the silicon wafer (not marked in the figure), and then use acid and alkali solution to polish the local pyramid velvet on the back to make the local pyramid velvet on the back smooth and flat.

[0141] 5. During laser selective doping, the wavelength is set to 532nm, the scanning speed is 25m / s, and the frequency is 1000kHz. The metal contact area on the back of the silicon wafer forms a heavily doped area of ​​the second conductive type impurity polysilicon layer, and the film-opening area on the back of the silicon wafer with non-metallic contact forms a second conductive type impurity c-Si area; The rest are the same.

[0142] Example 16 like Figure 6 As shown, an N-type TOPCon battery comprises an N-type silicon wafer 4, wherein the front side of the N-type silicon wafer 4 is provided with a second conductive type impurity c-Si region 11, a second dielectric layer 2, a second tunneling oxide layer 10, a second conductive type impurity polysilicon layer heavily doped region 9, and a front metal electrode 1 in sequence from the inside to the outside; the back side of the N-type silicon wafer 4 is provided with a first conductive type impurity c-Si region 12, a first dielectric layer 7, a first tunneling oxide layer 5, a first conductive type impurity polysilicon layer heavily doped region 13, and a back metal electrode 8 in sequence from the inside to the outside; A local area of ​​the front metal electrode penetrates the second dielectric layer to form an ohmic contact with the heavily doped area of ​​the second conductive type impurity polysilicon layer; a local area of ​​the back metal electrode penetrates the first dielectric layer to form an ohmic contact with the heavily doped area of ​​the first conductive type impurity polysilicon layer.

[0143] The dopant source layer of the first conductive type impurity is a silicon oxide compound layer containing the first conductive type impurity, the first conductive type impurity is phosphorus, and the thickness of the dopant source layer of the first conductive type impurity is 30 nm.

[0144] The preparation method of this embodiment is different from that of embodiment 15 in that: 4. First use laser opening and then texturing to open the non-metallic contact areas on the front and back of the silicon wafer to form c-Si areas. The parameters of laser opening are set as follows: wavelength 600nm, power ≥1W, scanning speed 25m / s, frequency 1000kHz; then use 1.3% NaOH solution for etching, the etching time is 500s, and a front pyramid velvet surface is formed on the front and back of the silicon wafer (not marked in the figure), and then use acid and alkali solution to polish the local pyramid velvet on the back to make the local pyramid velvet on the back smooth and flat.

[0145] 5. During laser selective doping, the wavelength is set to 532nm, the scanning speed is 25m / s, and the frequency is 1000kHz. The metal contact areas on the front and back sides of the silicon wafer respectively form a heavily doped area of ​​the second conductive type impurity polysilicon layer and a heavily doped area of ​​the first conductive type impurity polysilicon layer. The film opening areas on the front and back sides of the silicon wafer that are in non-metallic contact form a second conductive type impurity c-Si area and a first conductive type impurity c-Si area respectively. The rest are the same.

[0146] Comparative Example 1 The preparation method of this comparative example is different from that of Example 1 in that no mask layer is deposited in step 3, and the rest are the same.

[0147] Comparative Example 2 This comparative example is a conventional method for preparing a TOPCon battery: ① Select a P-doped N-type silicon wafer with a resistivity of 1.5Ωcm and a thickness of 150μm; use acid and alkali chemicals to eliminate organic contamination and metal impurities on the surface of the silicon wafer; ② Use 1.3% NaOH solution for etching for 60 minutes to prepare a velvet surface on the front side of the silicon wafer; ③ Place the silicon wafer into a boron doping tube for boron doping at a doping temperature of 1000°C for 180 minutes. The boron doping source is BBr3, and a 150nm BSG layer is formed on the silicon wafer. ④ Etch the silicon wafer on one side to remove the BSG on the front side and retain the BSG barrier layer on the back side; perform corrosion polishing on the surface of the single crystal silicon wafer for 60 minutes; ⑤ In the LPCVD furnace, N2O is used as the oxidant, the oxidation temperature is 600℃, the time is 3min, and a tunneling oxide layer with a thickness of 3nm is formed on the back of the silicon wafer; SiH4 is used as the reaction gas and Ar is used as the diluent gas, the formation temperature is 600℃, the time is 90min, and a polysilicon layer with a thickness of 250nm is formed on the surface of the tunneling oxide layer; ⑥Put the silicon wafer into a phosphorus-doped tube for phosphorus doping. The doping temperature is 1000°C, the doping time is 150 minutes, and the boron doping source is BBr3; ⑦ Place the silicon wafer in 25% HF for pickling for 600 seconds to remove the phosphorus-containing silicon oxide layer and the boron-containing silicon oxide layer of the silicon wafer; then perform RCA standard cleaning on the silicon wafer to remove surface contaminants.

[0148] ⑧ The ALD atomic layer formation method is adopted, TMA is used as the precursor, and the reaction temperature is controlled at 300°C to form a dense Al2O3 passivation layer with a thickness of 10nm on the front and back of the silicon wafer. The PECVD method is then used to form a 100nm SiNx anti-reflection layer on the front and back of the silicon wafer. The passivation layer and the anti-reflection layer form a dielectric layer.

[0149] ⑨ Print Ag paste on the front and back of the silicon wafer, and after drying and sintering, obtain the front and back metal electrodes.

[0150] The batteries in Examples 1-16 and Comparative Examples 1-2 were tested under the same conditions. The test results are shown in Table 1.

[0151] Table 1 Test results of battery of embodiment and comparative example

[0152] As can be seen from Table 1, from the comparison of the test data of Examples 1-16 and Comparative Example 1, it can be seen that when the solar cell deposits a mask on the dopant source layer of the first conductive type impurity, for the dopant source of the first conductive type impurity of the same thickness, the doping concentration can be relatively high, which will increase the open circuit voltage, short circuit current, and fill factor of the battery, thereby improving the conversion efficiency of the battery. From the comparison of the test data of Examples 1-16 and Comparative Example 2, it can be seen that when the solar cell deposits the dopant source layer and mask layer of the first conductive type impurity, the open circuit voltage, short circuit current, and fill factor of the battery are all improved, thereby improving the conversion efficiency of the battery; the process time for battery preparation is shortened. From the test data of Examples 1-6 and 7-8, it can be seen that when the thickness of the dopant source layer of the first conductive type impurity is 5-60nm, the open circuit voltage, short circuit current, fill factor and conversion efficiency of the battery are better; from the test data of Examples 9-12 and 13-14, it can be seen that when the thickness of the dopant source layer of the first conductive type impurity is 5-60nm, the open circuit voltage, short circuit current, fill factor and conversion efficiency of the battery are better.

[0153] The present invention is further described above with the aid of specific embodiments. However, it should be understood that the specific description here should not be construed as limiting the essence and scope of the present invention. Various modifications made to the above embodiments by ordinary technicians in the field after reading this specification are all within the scope of protection of the present invention.

Claims

1. A method for preparing a solar cell, characterized in that: The steps include: S1 cleans and polishes the substrate silicon wafer; S2 forms a dielectric region and a polysilicon layer; S3: forming a dopant source layer of first conductivity type impurities and a mask layer; S4 co-doping of impurities of different conductivity types in one step; S5 forms a dielectric layer; S6 Metallization.

2. The method for preparing a solar cell according to claim 1, characterized in that: The thickness of the dopant source layer of the first conductive type impurities is 5nm-60nm.

3. The method for preparing a solar cell according to claim 1, characterized in that: The solar cell includes a substrate silicon wafer, which has a front side facing the sun during normal operation and a back side opposite to the front side, the back side of the substrate silicon wafer being sequentially provided with the dielectric region and the polysilicon layer in a direction away from the substrate silicon wafer, and the dopant source layer of the first conductive type impurities being outside the polysilicon layer.

4. The method for preparing a solar cell according to claim 1, characterized in that: It also includes a texturing step, wherein the texturing step forms a front texturing surface on the front side of the substrate silicon wafer, or the texturing step forms a front texturing surface on the front side of the substrate silicon wafer and a partial back texturing surface on the back side, and the morphology and size of the front texturing surface and the partial back texturing surface are the same or different.

5. The method for preparing a solar cell according to claim 4, characterized in that: The texturing step is performed before the dielectric region is formed in S2, and the texturing step also includes a first mask preparation step before the texturing step, wherein the first mask formation step forms a first mask layer on the back side of the substrate silicon wafer; or, the texturing step is performed after the dopant source layer of the first conductive type impurities is formed in S3.

6. The method for preparing a solar cell according to claim 1, characterized in that: In the step S3, a dopant source layer of first conductive type impurities is formed by CVD at a temperature of 300° C. to 800° C. and the raw materials include boron source gas or phosphorus source gas; The boron source gas is at least one of BH3, TMB, BCl3, and BBr3; The phosphorus source gas is at least one of PH3 and POCl3.

7. The method for preparing a solar cell according to claim 1, characterized in that: The S3 dopant source layer of the first conductive type impurities is a silicon compound layer containing first conductive type impurities, and the first conductive type impurities are boron, gallium or phosphorus.

8. The method for preparing a solar cell according to claim 1, characterized in that: The S3 mask layer of the first conductive type impurities is a composite film composed of one or more of silicon nitride, silicon oxynitride, and silicon oxide, and the thickness of the mask layer is 2nm-200nm.

9. The method for preparing a solar cell according to claim 1, characterized in that: The doping temperature in the one-step co-doping of S4 impurities of different conductivity types is 600° C.-1000° C., and the doping time is 5 min-180 min.

10. The method for preparing a solar cell according to claim 1, characterized in that: In the S4 one-step co-doping of different conductive type impurities, a doping source of a second conductive type impurity with electrical properties opposite to the first conductive type impurity is used to simultaneously form a first conductive type impurity region and a second conductive type impurity region, the first conductive type impurity region and the second conductive type impurity region have opposite electrical properties, and the one-step co-doping of different conductive type impurities is performed at least once.

11. The method for preparing a solar cell according to claim 1, characterized in that: After the S4 co-doping of different conductive type impurities in one step, it also includes a laser selective doping step, the wavelength of the laser selective doping step is 200nm-1064nm, the power is ≥1W, the scanning speed is 5m / s-50m / s, the frequency is 200kHz-2000kHz, and the laser selective doping obtains a local heavily doped area of ​​the conductive type impurity area.

12. The method for preparing a solar cell according to claim 11, characterized in that: After the laser selective doping, the method further includes removing the dopant source layer of the first conductive type impurities, wherein the dopant source layer of the first conductive type impurities is removed by pickling with hydrofluoric acid having a concentration of 0.5%-50% for a pickling time of 10s-1200s.

13. A solar cell prepared by the method for preparing a solar cell according to any one of claims 1 to 12, characterized in that: The invention comprises a substrate silicon wafer; the substrate silicon wafer has a front side facing the sun during normal operation and a back side opposite to the front side, the front side of the substrate silicon wafer is provided with a front velvet surface, a second conductive type impurity region, a second dielectric layer, and a front metal electrode; the back side of the substrate silicon wafer is provided with a first dielectric region, a first conductive type impurity region, a first dielectric layer, and a back metal electrode; The first dielectric region is a first tunneling oxide layer; the first conductive type impurity region is a c-Si region or a polysilicon layer doped with first conductive type impurities, and the second conductive type impurity region is a c-Si region or a polysilicon layer doped with second conductive type impurities; The dopant source layer of the first conductive type impurities serves as a doping source of the c-Si region or the polysilicon layer of the first conductive type impurities, and the thickness of the dopant source layer of the first conductive type impurities is 5nm-60nm; The second conductive type impurity region and the first conductive type impurity region are simultaneously formed in one or more different conductive type impurity one-step co-doping steps; In the step of co-doping impurities of different conductivity types, at least once, a doping source having a second conductivity type impurity with electrical properties opposite to that of the first conductivity type is used, and part of the doping source is doped into part of the substrate silicon wafer; The first conductive type impurity region on the back side of the substrate silicon wafer has opposite electrical properties to the second conductive type impurity region on the front side of the substrate silicon wafer, and a local area of ​​the back metal electrode is connected to the back side of the substrate silicon wafer through the first dielectric layer.

14. A solar cell according to claim 13, characterized in that: A second dielectric region is also arranged on the upper edge of the front velvet surface in a direction away from the substrate silicon wafer; a back local velvet surface and an edge velvet surface are also arranged on the lower edge of the first dielectric region close to the substrate silicon wafer, and a heavily doped region is also arranged in the first conductive type impurity region and / or the second conductive type impurity region.

15. The solar cell according to claim 13, characterized in that: The c-Si region is formed by film opening and cleaning, and the film opening method is at least one of laser, etching slurry, and photolithography; the polysilicon layer is formed by CVD deposition.

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