Semiconductor device and electronic apparatus

Abstract

A semiconductor device having a small circuit scale and reduced power consumption is provided. According to one embodiment of the present invention, a semiconductor device includes a first calculation unit that performs a digital calculation and a second calculation unit that performs an analog calculation. In the calculation of the convolutional neural network, the calculation of the convolutional layer is executed in the first calculation unit, and the calculation of the fully connected layer is executed in the second calculation unit. Convolution layers repeatedly use the same filter value in many cases, and therefore, the first calculation unit adopts a configuration in which the same filter value is used as one input and the data to be subjected to convolution processing is used as a plurality of inputs, and a plurality of product-sum calculations are executed simultaneously. Furthermore, the fully connected layer requires a weight coefficient for the product of the number of input data and the number of output data, so that the second calculation unit maintains the weight coefficient for each of the calculation units arranged in a matrix, and outputs the output data from each column direction by transmitting the input data in each row direction.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device and an electronic device.

[0002] In addition, one embodiment of the present invention is not limited to the above-mentioned technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a driving method or a manufacturing method. In addition, one embodiment of the present invention relates to a process, a machine, a product or a composition. Therefore, specifically, as examples of the technical field of one embodiment of the present invention disclosed in this specification, semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, camera devices, storage devices, signal processing devices, sensors, processors, electronic devices, systems, their driving methods, their manufacturing methods or their inspection methods can be cited. Background Art

[0003] Nowadays, the development of integrated circuits modeled on the structure of the human brain is becoming increasingly popular. The integrated circuit is assembled with electronic circuits that are the structure of the brain and include circuits that are equivalent to the "neurons" and "synapses" of the human brain. Therefore, such integrated circuits are sometimes referred to as "neuro-morphic", "brain-morphic" or "brain-inspired". The integrated circuit has a non-Neumann architecture, and compared with the Neumann architecture, which has higher power consumption as the processing speed increases, it can be expected to perform parallel processing with extremely low power consumption.

[0004] A data processing model that mimics a neural network and includes "neurons" and "synapses" is called an artificial neural network (ANN). For example, Non-Patent Documents 1 and 2 disclose a computing device that uses SRAM (Static Random Access Memory) to form an artificial neural network.

[0005] In addition, there are studies on using a computing device constituting an artificial neural network, for example, to correct an image displayed on a display device. For example, Patent Document 1 discloses a display device in which a computing circuit constituting an artificial neural network is used to adjust the brightness, color tone, etc. of a displayed image according to the preferences of a person viewing the image. [Prior technical literature] [Patent Document]

[0006] [Patent Document 1] Japanese Patent Application Publication No. 2018-36639 [Non-patent literature]

[0007] [Non-patent document 1] M. Kang et al., “IEEE Journal Of Solid-State Circuits”, 2018, Volume 53, No. 2, p. 642-655. [Non-patent document 2] J. Zhang et al., “IEEE Journal Of Solid-State Circuits”, 2017, Volume 52, No. 4, p. 915-924. Summary of the invention Technical problem to be solved by the invention

[0008] As a method for extracting features from an image and recognizing an image, for example, a method using a convolutional neural network, which is one of the artificial neural networks, can be cited. A convolutional neural network, for example, includes a convolutional layer, a pooling layer, and a fully connected layer. By inputting image data into a multi-layer structure composed of these layers, feature extraction and image recognition can be performed on the image.

[0009] The convolution layer is a layer for extracting low-order features. Specifically, in the convolution layer, a product-sum operation is performed on the image data in the region selected from the input image and the filter (sometimes referred to as the convolution kernel). In addition, in the convolution layer, the region is staggered by the number of steps and the product-sum operation is performed sequentially, so the data obtained in the convolution layer is, for example, a two-dimensional arrangement (rows and columns) or a three-dimensional arrangement of data.

[0010] In the convolution layer, the smaller the number of steps and the greater the number of filters, the larger the number of multiplication operations of the product-sum operation. When the number of multiplication operations is large, the update frequency of the filter value (the value included in the filter) input to the operation circuit also increases, so the power required for the update also increases. In addition, in order to cope with the large number of multiplication operations, a method of using a large number of operation circuits can also be considered, but this will lead to an increase in circuit area.

[0011] In addition, the fully connected layer is a layer for high-order feature extraction. Specifically, in the fully connected layer, for one output channel, the product-sum operation of all input channel data and the corresponding weight coefficients is performed to calculate the value of the activation function with the result as the input value. In addition, there are multiple output channels, so the number of weight coefficients in the fully connected layer is (number of input channels) × (number of output channels).

[0012] That is, the more input channels and output channels there are, the larger the number of weight coefficients (the number of multiplication operations of the product-sum operation). Therefore, in the operation of the fully connected layer, a large number of storage circuits are required to store the weight coefficients, resulting in an increase in the circuit area.

[0013] In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device with reduced power consumption. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device with a small circuit area. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device that can perform operations continuously. In addition, one of the purposes of one embodiment of the present invention is to provide a novel semiconductor device. In addition, one of the purposes of one embodiment of the present invention is to provide an electronic device including the above-mentioned semiconductor device.

[0014] Note that the purpose of one embodiment of the present invention is not limited to the above-mentioned purpose. The above-mentioned purpose does not prevent the existence of other purposes. In addition, other purposes are purposes that are not mentioned above but will be described in the following description. Those skilled in the art can derive and appropriately extract the purposes not mentioned above from the description of the specification or the drawings. In addition, one embodiment of the present invention achieves at least one of the above-mentioned purpose and other purposes without having to achieve all of the above-mentioned purpose and other purposes. Solutions to technical problems (1) One embodiment of the present invention is a semiconductor device including a first operation unit, a second operation unit, and a storage unit. The first operation unit includes a first wiring and an operation circuit, the second operation unit includes a second wiring, a first circuit, a second circuit, a third circuit, and a plurality of operation units, and the storage unit includes a first storage circuit unit, a second storage circuit unit, and a third storage circuit unit.

[0016] The first input terminal of the operation circuit is electrically connected to the first wiring, the second input terminal of the operation circuit is electrically connected to the second storage circuit unit, and the second wiring is electrically connected to the first circuit, the third circuit, and the plurality of operation units.

[0017] The first wiring is used as a wiring for sequentially transmitting the plurality of first digital data. In addition, the second storage circuit unit has a function of reading out the plurality of second digital data and sequentially transmitting them to the second input terminal of the operation circuit. In addition, the operation circuit has a function of performing a first product-sum operation of the plurality of first digital data and the plurality of second digital data and a function of transmitting third digital data as a result of the first product-sum operation to the first storage circuit unit.

[0018] The first storage circuit unit has a function of holding a plurality of third digital data, and the third storage circuit unit has a function of reading out a plurality of fourth digital data and sequentially sending them to the first circuit. In addition, the first circuit has a function of sequentially generating a first current corresponding to the fourth digital data and causing each first current to flow through a plurality of operation units. The operation unit has a function of maintaining a first potential corresponding to the first current. The first storage circuit unit has a function of reading out a plurality of third digital data and sending them to the second circuit, and the second circuit has a function of generating a plurality of second currents corresponding to the plurality of third digital data and causing each second current to flow through a plurality of operation units. In addition, the operation unit has a function of changing the first potential according to the amount of the second current and generating a third current equivalent to the product of the fourth digital data and the third digital data and causing it to flow through the second wiring. The third circuit has a function of obtaining the sum of the amounts of the plurality of third currents generated by the plurality of operation units from the second wiring and performing a function-type operation with the sum of the third currents as an input value to generate the first data as a result of the function-type operation. (2) In addition, one embodiment of the present invention may also adopt the following structure, wherein in the above (1), a plurality of first wirings and a plurality of operation circuits are included. In particular, the first input terminal of each of the plurality of operation circuits is preferably electrically connected to each of the plurality of first wirings in a one-to-one manner. In addition, the second input terminal of each of the plurality of operation circuits is preferably electrically connected to each other. In addition, the output terminal of each of the plurality of operation circuits is preferably electrically connected to the first storage circuit unit. (3) In addition, one embodiment of the present invention may also adopt the following structure, wherein in the above (2), the first operation unit includes a processing circuit. In particular, the first storage circuit unit preferably has a function of sending the third digital data to the processing circuit. In addition, the processing circuit preferably has a function of performing pooling processing on the third digital data and a function of sending the third digital data after the pooling processing to the first storage circuit unit. (4) In addition, one embodiment of the present invention may adopt the following structure, wherein in the above (3), the first operation unit includes a switching circuit. In particular, the switching circuit preferably includes a plurality of first input terminals, a plurality of second input terminals, and a plurality of output terminals. In addition, it is preferred that each of the plurality of second input terminals of the switching circuit is electrically connected to the first storage circuit unit, and each of the plurality of output terminals of the switching circuit is electrically connected to each of the plurality of first wirings in a one-to-one manner. In addition, it is preferred that the switching circuit has a function of making the plurality of first input terminals of the switching circuit and one of the plurality of second input terminals of the switching circuit and the plurality of output terminals of the switching circuit conductive and making the plurality of first input terminals of the switching circuit and the other of the plurality of second input terminals of the switching circuit and the plurality of output terminals of the switching circuit non-conductive. Furthermore, it is preferred that the first storage circuit unit has a function of reading out the plurality of third digital data and sending them to the first input terminal of the operation circuit through the switching circuit, and the operation circuit has a function of performing a second product-sum operation of the plurality of third digital data held by the first storage circuit unit and the plurality of second digital data held by the second storage circuit unit, and a function of sending the result of the second product-sum operation as digital data to the first storage circuit unit. (5) In addition, one embodiment of the present invention may also adopt the following structure: in the above (4), the third circuit includes an analog-to-digital conversion circuit. In particular, the analog-to-digital conversion circuit preferably has a function of converting the first data into fifth digital data, and the third circuit preferably has a function of sending the fifth digital data to the first storage circuit unit. (6) In addition, one embodiment of the present invention may adopt a structure in which any one of (1) to (5) above includes a first layer, a second layer located above the first layer, and a third layer located above the second layer. In particular, it is preferable to adopt a structure in which the first layer includes a computing unit, a first circuit, a second circuit, and a third circuit, the second layer includes a first storage circuit unit, a second storage circuit unit, and a third storage circuit unit, and the third layer includes a plurality of computing units. (7) In one embodiment of the present invention, in the above (6), the first layer includes a transistor including silicon in a channel formation region, and the second layer and the third layer both include transistors including an oxide semiconductor in a channel formation region.

[0025] In particular, the oxide semiconductor preferably contains one or more selected from indium, zinc, and element M. Note that element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, magnesium, and antimony. (8) Furthermore, one embodiment of the present invention is an electronic device including the semiconductor device described in (7) above and a housing. Effects of the Invention

[0027] According to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with a small circuit area can be provided. In addition, according to one embodiment of the present invention, a semiconductor device capable of performing operations continuously can be provided. In addition, according to one embodiment of the present invention, a novel semiconductor device can be provided. In addition, according to one embodiment of the present invention, an electronic device including the above-mentioned semiconductor device can be provided.

[0028] Note that the effects of one embodiment of the present invention are not limited to the above effects. The above effects do not prevent the existence of other effects. In addition, other effects are effects that are not mentioned above but will be described in the following description. Those skilled in the art can derive and appropriately extract the effects that are not mentioned above from the description of the specification or drawings, etc. In addition, one embodiment of the present invention has at least one of the above effects and other effects. Therefore, one embodiment of the present invention sometimes does not have the effects listed above depending on the circumstances. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a block diagram illustrating a structural example of a semiconductor device. Figure 2A and Figure 2B is a block diagram illustrating a configuration example of a circuit included in a semiconductor device. Figure 3A and Figure 3B is a block diagram illustrating a configuration example of a circuit included in a semiconductor device. Figure 4A is a block diagram illustrating a configuration example of a circuit included in a semiconductor device. Figure 4B and Figure 4C is a circuit diagram illustrating a structural example of a memory cell. FIG. 5A to FIG. 5C A circuit diagram illustrating a configuration example of a circuit included in a semiconductor device. Figure 6 is a circuit diagram showing a configuration example of a circuit included in a semiconductor device. FIG. 7A to FIG. 7C A circuit diagram illustrating a configuration example of a circuit included in a semiconductor device. FIG. 8A to FIG. 8D A circuit diagram illustrating a configuration example of a circuit included in a semiconductor device. 9A to 9C is a block diagram illustrating a configuration example of a circuit included in a semiconductor device. Fig.10 is a diagram showing an example of a convolutional neural network. Fig.11 This is a diagram illustrating an example of convolution processing. Fig.12 This is a diagram illustrating an example of convolution processing. Fig.13 is a timing chart showing an operation example of convolution processing in a semiconductor device. Fig.14A and Fig. 14B This is a diagram illustrating an example of pooling processing. Fig.15A and Fig. 15B is a block diagram illustrating a configuration example of a circuit included in a semiconductor device. Fig.16 It is a perspective schematic diagram showing a structural example of a semiconductor device. Fig.17 is a block diagram showing a structural example of a semiconductor device. Fig.18 is a block diagram showing a structural example of a semiconductor device. Fig.19 is a schematic cross-sectional view showing a structural example of a semiconductor device. Fig. 20 is a schematic cross-sectional view showing a structural example of a semiconductor device. Fig.21 It is a perspective schematic diagram showing a structural example of a semiconductor device. Fig.22A and Fig. 22B It is a diagram showing an example of an electronic component. Fig.23A and Fig. 23B is a diagram showing an example of an electronic device, FIG. 23C to FIG. 23E This is a diagram showing an example of a large computer. Fig.24 is a diagram showing an example of space equipment. Fig.25 This is a diagram showing an example of a storage system that can be applied to a data center. Fig.26 This is a top view of an actually manufactured semiconductor device. Fig. 27 This is a top view of an actually manufactured semiconductor device. Modes for Carrying Out the Invention

[0030] In this specification, etc., a semiconductor device refers to a device that utilizes semiconductor characteristics, a circuit including a semiconductor element (e.g., a transistor, a diode, a photodiode), and a device including the circuit. In addition, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip having an integrated circuit, and an electronic component containing a chip in a package are all examples of a semiconductor device. In addition, for example, a storage device, a display device, a light-emitting device, a lighting device, and an electronic device are sometimes semiconductor devices themselves, or sometimes include a semiconductor device.

[0031] In addition, in this specification, when it is described that "X is connected to Y", it means that the following cases are disclosed in this specification, etc.: a case where X is electrically connected to Y; a case where X is functionally connected to Y; and a case where X is directly connected to Y. Therefore, it is not limited to the connection relationship shown in the drawings or text, and other connection relationships are also within the scope described in the drawings or text. X and Y are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, and layers).

[0032] As an example of a case where X and Y are electrically connected, one or more elements (such as switches, transistors, capacitors, inductors, resistors, diodes, display devices, light-emitting devices, loads, etc.) that can electrically connect X and Y may be connected between X and Y. In addition, the switch has a function of controlling on or off. In other words, whether current flows is controlled by making the switch in a conducting state (on state) or a non-conducting state (off state).

[0033] As an example of a case where X and Y are functionally connected, for example, one or more circuits capable of functionally connecting X and Y (for example, a logic circuit (for example, an inverter, a NAND circuit, a NOR circuit), a signal conversion circuit (for example, a digital-to-analog conversion circuit, an analog-to-digital conversion circuit, a gamma correction circuit), a potential level conversion circuit (for example, a power supply circuit such as a boost circuit and a buck circuit), a level shift circuit that changes the potential level of a signal), a voltage source, a current source, a switching circuit, an amplifier circuit (for example, a circuit capable of increasing signal amplitude or current amount, an operational amplifier, a differential amplifier circuit, a source follower circuit, a buffer circuit), a signal generation circuit, a storage circuit, a control circuit, etc.) may be connected between X and Y. Note that, for example, even if another circuit is interposed between X and Y, when a signal output from X is transmitted to Y, X and Y can be said to be functionally connected.

[0034] Furthermore, when it is clearly stated that “X is electrically connected to Y”, the following cases are included: a case where X is electrically connected to Y (in other words, a case where X and Y are connected with another element or another circuit interposed therebetween); and a case where X and Y are directly connected (in other words, a case where X and Y are connected without another element or another circuit interposed therebetween).

[0035] In addition, in this specification, a circuit structure in which a wiring (wiring for supplying a fixed potential or wiring for transmitting a signal) is electrically connected to a plurality of elements is adopted. For example, in this specification, a case in which X is directly connected to a wiring and Y is directly electrically connected to the wiring is sometimes described as "X and Y are directly connected".

[0036] In addition, for example, it can be expressed as "X, Y, the source of the transistor (sometimes referred to as one of the first terminal and the second terminal) and the drain of the transistor (sometimes referred to as the other of the first terminal and the second terminal) are electrically connected to each other, and X, the source of the transistor, the drain of the transistor, and Y are electrically connected in sequence." Or, it can be expressed as "the source of the transistor is electrically connected to X, the drain of the transistor is electrically connected to Y, and X, the source of the transistor, the drain of the transistor, and Y are electrically connected in sequence." Or, it can be expressed as "X is electrically connected to Y through the source and drain of the transistor, and X, the source of the transistor, the drain of the transistor, and Y are connected to each other in sequence." By specifying the connection order in the circuit structure using the same expression method as these examples, the source and drain of the transistor can be distinguished to determine the technical scope. Note that this expression method is an example and is not limited to the above expression method. Here, X and Y are objects (for example, devices, elements, circuits, wiring, electrodes, terminals, conductive films or layers, etc.).

[0037] In addition, even if independent components are electrically connected to each other on a circuit diagram, one component may have the functions of multiple components. For example, when a portion of a wiring is used as an electrode, one conductive film has the functions of both wiring and electrode. Therefore, the category of "electrically connected" in this specification also includes the case where one conductive film has the functions of multiple components.

[0038] In this specification, etc., a "resistance element" may be, for example, a circuit element having a resistance value higher than 0Ω or a wiring having a resistance value higher than 0Ω. Therefore, in this specification, etc., a "resistance element" includes a wiring having a resistance value, a transistor, a diode, or a coil through which current flows between a source and a drain. Therefore, a "resistance element" may sometimes be referred to as a "resistance", "load", or "region having a resistance value". In contrast, "resistance", "load", or "region having a resistance value" etc. may sometimes be referred to as a "resistance element". As for the resistance value, for example, it is preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. In addition, for example, it may be 1 Ω or more and 1×10 9 Ω or less.

[0039] In this specification, etc., a "capacitor element" may be, for example, a circuit element having an electrostatic capacitance value higher than 0F, a wiring area having an electrostatic capacitance value higher than 0F, a parasitic capacitance, or a gate capacitance of a transistor. In addition, "capacitor element", "parasitic capacitance" or "gate capacitance" etc. may sometimes be referred to as a "capacitor". In contrast, a "capacitor" may sometimes be referred to as a "capacitor element", "parasitic capacitance" or "gate capacitance". In addition, a "capacitor" (a "capacitor" including three or more terminals) includes an insulator and a pair of conductors clamping the insulator. Thus, the "pair of conductors" of the "capacitor" may be referred to as a "pair of electrodes", "a pair of conductive areas", "a pair of areas" or "a pair of terminals". In addition, "one of a pair of terminals" and "the other of a pair of terminals" are sometimes referred to as a first terminal and a second terminal, respectively. In addition, the electrostatic capacitance value may be, for example, greater than 0.05fF and less than 10pF. In addition, for example, it may also be greater than 1pF and less than 10μF.

[0040] In this specification, etc., a transistor includes three terminals: a gate, a source, and a drain. The gate is used as a control terminal to control the conduction state of the transistor. The two terminals used as the source or drain are the input and output terminals of the transistor. Depending on the conductivity type of the transistor (n-channel type or p-channel type) and the level of the potential applied to the three terminals of the transistor, one of the two input and output terminals is used as the source and the other is used as the drain. Therefore, in this specification, etc., the source and the drain can be interchanged. In this specification, etc., when describing the connection relationship of the transistor, the expressions "one of the source and the drain" (sometimes referred to as the first electrode or the first terminal) and "the other of the source and the drain" (sometimes referred to as the second electrode or the second terminal) are used. In addition, depending on the structure of the transistor, a back gate is sometimes included in addition to the above three terminals. In this case, in this specification, etc., one of the gate and the back gate of the transistor is sometimes referred to as the first gate, and the other of the gate and the back gate of the transistor is sometimes referred to as the second gate. In addition, in the same transistor, "gate" and "back gate" can sometimes be interchanged. In addition, when a transistor includes three or more gates, each gate may be referred to as a first gate, a second gate, a third gate, etc. in this specification and the like.

[0041] For example, in this specification, a multi-gate structure transistor having more than two gate electrodes can be used as an example of a transistor. When a multi-gate structure is used, since the channel forming regions are connected in series, a structure in which multiple transistors are connected in series is formed. Therefore, by adopting a multi-gate structure, the off-state current can be reduced, and the voltage resistance of the transistor can be improved (improving reliability). Alternatively, by utilizing a multi-gate structure, when the transistor operates in a saturation region, even if the voltage between the drain and the source changes, the change in the current between the drain and the source is not too large, so that a voltage-current characteristic with a flat tilt angle can be obtained. When utilizing a voltage-current characteristic with a flat tilt angle, an ideal current source circuit or an active load with an extremely high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with good characteristics can be realized.

[0042] In addition, a circuit diagram showing a circuit element sometimes includes a case where the circuit element has a plurality of circuit elements. For example, a circuit diagram showing a resistor includes a case where two or more resistors are connected in series. In addition, for example, a circuit diagram showing a capacitor includes a case where two or more capacitors are connected in parallel. In addition, for example, a circuit diagram showing a transistor includes a case where two or more transistors are connected in series and the gates of each transistor are electrically connected to each other. Similarly, for example, a circuit diagram showing a switch includes a case where the switch has two or more transistors, the two or more transistors are electrically connected in series or in parallel and the gates of each transistor are electrically connected to each other.

[0043] In this specification, etc., a node may be referred to as a terminal, wiring, electrode, conductive layer, conductor, impurity region, etc. depending on the circuit structure and device structure. In addition, a terminal, wiring, etc. may also be referred to as a node.

[0044] In addition, in this specification, "voltage" and "potential" can be appropriately interchanged. "Voltage" refers to the potential difference from the reference potential. For example, when the reference potential is the ground potential (ground potential), "voltage" can also be called "potential". The ground potential does not necessarily mean 0V. In addition, the potential is relative, and the potential supplied to the wiring, the potential applied to the circuit, the potential output from the circuit, etc., etc., also changes according to the change of the reference potential.

[0045] In addition, in this specification, "high-level potential" and "low-level potential" do not mean specific potentials. For example, when two wirings are both recorded as "wirings used to supply high-level potentials", the high-level potentials supplied to the two wirings may be different from each other. Similarly, when two wirings are both recorded as "wirings used to supply low-level potentials", the low-level potentials supplied to the two wirings may be different from each other.

[0046] In addition, "electric current" refers to the migration phenomenon (conduction) of electric charge. For example, the record of "conduction of a positively charged body" can be replaced by the record of "conduction of a negatively charged body in the opposite direction". Therefore, in this specification, etc., in the absence of special instructions, "electric current" refers to the migration phenomenon (conduction) of electric charge when carriers migrate. Here, electrons, holes, anions, cations, and complex ions can be cited as carriers, and the carriers are different according to the system (for example, semiconductors, metals, electrolytes, and vacuum) through which the current flows. In addition, the "direction of electric current" in wiring, etc. is the direction in which positively charged carriers migrate, and is recorded as a positive current amount. In other words, the direction in which negatively charged carriers migrate is opposite to the direction of electric current, and is recorded as a negative current amount. Therefore, in this specification, etc., in the absence of special instructions, regarding the positive and negative of the electric current (or the direction of the electric current), the record of "the electric current flows from element A to element B" can be replaced by the record of "the electric current flows from element B to element A". In addition, the record of "the electric current is input to element A" can be replaced by the record of "the electric current is output from element A".

[0047] In addition, in this specification, etc., ordinal numbers such as "first", "second", and "third" are added to avoid confusion between constituent elements. Therefore, the ordinal numbers do not limit the number of constituent elements. In addition, the ordinal numbers do not limit the order of the constituent elements. For example, in this specification, etc., the "first" constituent element in one embodiment may be referred to as the "second" constituent element in other embodiments or claims. In addition, for example, in this specification, etc., the constituent element referred to by "first" in one embodiment may be omitted in other embodiments or claims.

[0048] In this specification, etc., for the sake of convenience, words and phrases indicating configurations such as "upper" and "lower" are sometimes used to illustrate the positional relationship of constituent elements with reference to the drawings. In addition, the positional relationship of constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, the words and phrases described in the specification, etc. are not limited, and the words and phrases can be appropriately replaced according to the situation. For example, if it is an expression of "an insulator located on the top surface of a conductor", by rotating the direction of the illustrated drawing by 180 degrees, it can be replaced with "an insulator located on the bottom surface of a conductor".

[0049] In addition, the terms "above" or "below" are not limited to the case where the positional relationship of the components is "directly above" or "directly below" and in direct contact. For example, if it is an expression "electrode B on insulating layer A", it is not necessarily necessary that electrode B is formed in direct contact with insulating layer A, and the case where other components are included between insulating layer A and electrode B may also be included. In addition, similarly, for example, if it is an expression "electrode B above insulating layer A", it is not necessarily necessary that electrode B is formed in direct contact with insulating layer A, and the case where other components are included between insulating layer A and electrode B may also be included. In addition, similarly, for example, if it is an expression "electrode B below insulating layer A", it is not necessarily necessary that electrode B is formed in direct contact with below insulating layer A, and the case where other components are included between insulating layer A and electrode B may also be included.

[0050] In addition, in this specification, etc., words such as "row" and "column" are sometimes used to describe the components configured in a matrix and their positional relationship. In addition, the positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, it is not limited to the words described in the specification, etc., and the words can be appropriately replaced according to the situation. For example, by rotating the direction of the drawing by 90 degrees, the expression of "row direction" can sometimes be replaced by "column direction".

[0051] In addition, in this specification, etc., words such as "film" and "layer" can be interchanged depending on the situation. For example, "conductive layer" can sometimes be interchanged with "conductive film". In addition, "insulating film" can sometimes be interchanged with "insulating layer". In addition, other words can be used instead of words such as "film" and "layer" depending on the situation or condition. For example, "conductive layer" or "conductive film" can sometimes be interchanged with "conductive body". In addition, for example, "insulating layer" or "insulating film" can sometimes be interchanged with "insulator".

[0052] Note that in this specification, etc., the words "electrode", "wiring" and "terminal" do not functionally limit their constituent elements. For example, sometimes an "electrode" is used as a part of a "wiring", and vice versa. Furthermore, the words "electrode" or "wiring" also include the case where a plurality of "electrodes" or "wirings" are formed as one. In addition, for example, sometimes a "terminal" is used as a part of a "wiring" or "electrode", and vice versa. Furthermore, the word "terminal" also includes the case where one or more selected from "electrode", "wiring" and "terminal" are formed as one. Therefore, for example, an "electrode" can be a part of a "wiring" or a "terminal", and for example, a "terminal" can be a part of a "wiring" or an "electrode". In addition, the words "electrode", "wiring" or "terminal" are sometimes replaced with words such as "region" depending on the situation.

[0053] In this specification, etc., depending on the situation or conditions, the words "wiring", "signal line" or "power line" can be interchanged with each other. For example, "wiring" can sometimes be converted to "signal line". In addition, for example, "wiring" can sometimes be converted to "power line". Vice versa, "signal line" or "power line" can sometimes be converted to "wiring". "Power line" can sometimes be converted to "signal line". Vice versa, "signal line" can sometimes be converted to "power line". In addition, depending on the situation or conditions, "potential" applied to the wiring can sometimes be converted to "signal". Vice versa, "signal" can sometimes be converted to "potential".

[0054] In addition, in this specification, etc., sometimes the working method of the semiconductor device is described with reference to a timing diagram. In addition, the timing diagram used in this specification, etc. shows an ideal working example, and is not limited to the period, signal (for example, potential or current) and timing shown in the timing diagram unless otherwise specified. In the timing diagram of this specification, etc., the size and timing of the signal (for example, potential or current) input to each wiring (including nodes) in the timing diagram can be changed according to the situation. For example, even if two periods with equal intervals are shown in the timing diagram, the lengths of the two periods are sometimes different. In addition, for example, even if one of the two periods is shown to be long and the other is short, the lengths of the two periods may sometimes be the same, or sometimes one of the two periods may be short and the other may be long.

[0055] In this specification, etc., a flowchart is sometimes used to illustrate the working method of a semiconductor device. In addition, in this specification, etc., the processing shown in the flowchart is classified by work and shown as independent steps. However, in actual processing, it is difficult to classify the processing shown in the flowchart by work, and sometimes one step involves multiple steps or multiple steps involve one step. Therefore, the processing shown in the flowchart is not limited to the steps described in the specification, and can be appropriately replaced according to the situation. Specifically, the order of steps can be exchanged, steps can be added, and steps can be deleted according to the situation.

[0056] In this specification, etc., metal oxide refers to the oxide of metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors) and oxide semiconductors (Oxide Semiconductor, also referred to as OS), etc. For example, when the channel formation region of a transistor contains a metal oxide, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, when the metal oxide can constitute the channel formation region of a transistor having at least one of an amplification function, a rectification function and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. In addition, an OS transistor can be referred to as a transistor containing a metal oxide or an oxide semiconductor.

[0057] In addition, in this specification and the like, a metal oxide containing nitrogen may also be referred to as a metal oxide (metal oxide). In addition, a metal oxide containing nitrogen may also be referred to as a metal oxynitride (metal oxynitride).

[0058] In addition, in this specification, etc., impurities of a semiconductor refer to substances other than the main components constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 at.% is an impurity. When impurities are contained, one or more selected from the group consisting of an increase in the defect state density in the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity sometimes occur. When the semiconductor is an oxide semiconductor, as impurities that change the semiconductor properties, there are, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, or transition metals other than the main components, in particular, for example, hydrogen (contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen.

[0059] In this specification, etc., a switch refers to an element that has a function of controlling whether to allow current to flow by changing to a conducting state (on state) or a non-conducting state (off state). Alternatively, a switch refers to an element that has a function of selecting and switching a current path. Therefore, a switch sometimes includes two or more terminals for allowing current to flow in addition to a control terminal. As an example of a switch, an electric switch or a mechanical switch can be used. In other words, a switch is not limited to a specific element as long as it can control the current.

[0060] Examples of electrical switches include transistors (e.g., bipolar transistors or MOS transistors), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, metal-insulator-metal (MIM: Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor: Metal-Insulator-Semiconductor) diodes, or diode-connected transistors (transistors with gate and drain in the on state)), or logic circuits in which these elements are combined. When a transistor is used as a switch, the "on state" of the transistor refers to, for example, a state in which the source electrode and the drain electrode of the transistor are electrically short-circuited or a state in which current can flow between the source electrode and the drain electrode. In addition, the "non-conducting state" of the transistor refers to a state in which the source electrode and the drain electrode of the transistor are electrically disconnected. When the transistor is used only as a switch, there is no particular restriction on the polarity (conductivity type) of the transistor.

[0061] An example of a mechanical switch is a switch using MEMS (micro-electromechanical system) technology. This switch has a mechanically movable electrode and operates by controlling conduction and non-conduction by moving the electrode.

[0062] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°. Therefore, it also includes a state where the angle is greater than -5° and less than 5°. "Approximately parallel" refers to a state where the angle formed by two straight lines is greater than -30° and less than 30°. In addition, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°. Therefore, it also includes a state where the angle is greater than 85° and less than 95°. "Approximately perpendicular" refers to a state where the angle formed by two straight lines is greater than 60° and less than 120°.

[0063] In this specification, etc., the structure described in each embodiment can be appropriately combined with the structure described in other embodiments to constitute one mode of the present invention. In addition, when a plurality of structural examples are described in one embodiment, these structural examples can be appropriately combined.

[0064] In addition, the content (or part thereof) described in a certain embodiment may be applied / combined / replaced with other content (or part thereof) described in the embodiment and at least one of the content (or part thereof) described in one or more other embodiments.

[0065] Note that the contents described in the embodiments refer to the contents described in each embodiment using various drawings or the contents described in the text described in the specification.

[0066] In addition, more figures can be formed by combining a figure (or a part thereof) shown in a certain embodiment with other parts of the figure, other figures (or a part thereof) shown in the embodiment, and at least one of the figures (or a part thereof) shown in one or more other embodiments.

[0067] The embodiments described in this specification are described with reference to the accompanying drawings. However, a person skilled in the art can easily understand the fact that the embodiments can be implemented in a plurality of different forms, and the methods and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the embodiments. Note that in the structure of the invention in the embodiments, the same symbols are sometimes used in different drawings to represent the same parts or parts with the same functions, and repeated descriptions are omitted. In stereograms, etc., for the sake of clarity, the illustration of some constituent elements is sometimes omitted.

[0068] In this specification, etc., when the same symbol is used for multiple elements and it is necessary to distinguish them, a symbol such as "_1", "[n]", "[m, n]" is sometimes added to the symbol for identification. In addition, in the drawings, etc., when a symbol is added to a symbol for identification, such as "_1", "[n]", "[m, n]", etc., if it is not necessary to distinguish them in this specification, etc., a symbol such as "_1", "[n]", "[m, n]" is sometimes not added for identification.

[0069] In the drawings, the size, thickness of a layer or area is sometimes exaggerated for the sake of clarity. Therefore, the present invention is not limited to the dimensions in the drawings. In addition, in the drawings, ideal examples are schematically shown, and the shapes or values ​​shown in the drawings are not limited. For example, the unevenness of signals, voltages or currents caused by noise or timing deviations may be included.

[0070] (Implementation Method 1) In this embodiment, a semiconductor device which is one embodiment of the present invention is described.

[0071] <Structural Example of Semiconductor Device> Figure 1 A structural example of a semiconductor device CDV which is one embodiment of the present invention is shown.

[0072] The semiconductor device CDV is used as an accelerator for executing a program (e.g., a convolution kernel program). The program is called by a host program stored in an external storage device of the semiconductor device CDV. The semiconductor device CDV can perform parallel processing of row and column operations in graphics processing, parallel processing of product and sum operations in neural networks, or parallel processing of floating-point operations in chemical technology calculations.

[0073] In particular, the semiconductor device CDV can perform model operations of a convolutional neural network. A convolutional neural network includes, for example, a convolutional layer, a pooling layer, and a fully connected layer. By inputting an image into a multi-layer structure composed of these layers, features of the image can be extracted and recognized.

[0074] The semiconductor device CDV includes, for example, a computing part DGP, a computing part ANP, and a storage part MEM.

[0075] The operation unit DGP is a digital operation circuit that performs operation by receiving input data as digital data and outputs the operation result as digital data. Specifically, the operation unit DGP has a function of performing a product-sum operation in a convolution layer of a convolutional neural network and outputting the product-sum operation result as digital data.

[0076] The operation unit ANP is an analog operation circuit that performs operation by receiving input data as digital data and outputs the operation result as analog data. Specifically, the operation unit ANP has a function of performing a product-sum operation in a fully connected layer of a convolutional neural network and outputting the product-sum operation result as analog data.

[0077] The storage unit MEM is used, for example, as a storage circuit for storing input data used to perform operations in the operation unit DGP or the operation unit ANP. In addition, the storage unit MEM is used, for example, as a storage circuit for storing output data as a result of operations performed by the operation unit DGP or the operation unit ANP. Note that in this embodiment, the storage unit MEM is described as a storage circuit for holding digital data. In addition, when the operation result output from the operation unit ANP is stored in the storage unit MEM, the analog data as the output data of the operation unit ANP is converted into digital data by a digital-to-analog conversion circuit or the like, and the digital data is stored in the storage unit MEM.

[0078] The computing portion DGP includes, for example, a switching circuit D10 , a computing circuit D20 , and a processing circuit D30 .

[0079] The storage unit MEM includes, for example, storage circuit units ME11 to ME13 .

[0080] The arithmetic unit ANP includes, for example, a cell array CA, a circuit WCS, a circuit XCS, and a circuit ITS.

[0081] An input terminal TM1i of the switching circuit D10 is electrically connected to the wiring ILA, an input terminal TM2i of the switching circuit D10 is electrically connected to the wiring ILB, and an output terminal TMo of the switching circuit D10 is electrically connected to the wiring MLA.

[0082] The input terminal TN1i of the arithmetic circuit D20 is electrically connected to the wiring MLA, the input terminal TN2i of the arithmetic circuit D20 is electrically connected to the wiring MLB, and the output terminal TNo of the arithmetic circuit D20 is electrically connected to the wiring CNL.

[0083] The processing circuit D30 is electrically connected to the wiring POL.

[0084] The memory circuit portion ME11 is electrically connected to the wiring ILB. In addition, the memory circuit portion ME11 is electrically connected to the wiring CNL. In addition, the memory circuit portion ME11 is electrically connected to the wiring POL. In addition, the memory circuit portion ME11 is electrically connected to the wiring IXL_1 to the wiring IXL_m (m is an integer greater than 1). In addition, the memory circuit portion ME12 is electrically connected to the wiring MLB. In addition, the memory circuit portion ME13 is electrically connected to the wiring IWL_1 to the wiring IWL_n (n is an integer greater than 1).

[0085] Each of the plurality of input terminals of the circuit WCS is electrically connected to the wirings IWL_1 to IWL_n. In addition, each of the plurality of output terminals of the circuit WCS is electrically connected to the wirings WCL_1 to WCL_n.

[0086] Each of the plurality of input terminals of the circuit XCS is electrically connected to the wirings IXL_1 to IXL_m. In addition, each of the plurality of output terminals of the circuit XCS is electrically connected to the wirings XCL_1 to XCL_m.

[0087] exist Figure 1 In the embodiment, the wirings WCL_1 to WCL_n extend in the column direction of the cell array CA. In addition, the wirings XCL_1 to XCL_m extend in the row direction of the cell array CA.

[0088] In addition, the cell array CA includes a plurality of operation units, which are configured in a matrix shape, for example, in the cell array CA. The details will be described later, and the operation unit of the i-th row and j-th column (i is an integer greater than 1 and less than m, and j is an integer greater than 1 and less than n) of the cell array CA is electrically connected to the wiring WCL_j and the wiring XCL_i.

[0089] Each of the plurality of input terminals of the circuit ITS is electrically connected to the wirings WCL_1 to WCL_n. In addition, each of the plurality of output terminals of the circuit ITS is electrically connected to the wirings OL_1 to OL_n.

[0090] The wiring ILA is used, for example, as a wiring for inputting input data from outside the semiconductor device CDV to the input terminal TM1i of the switching circuit D10. Note that the input data here may be, for example, an image. Figure 1 In the example, the input data is recorded as image P in .

[0091] The wiring ILB is used, for example, as a wiring for inputting input data read from the storage circuit unit ME11 to the input terminal TM2i of the switching circuit D10. Note that the input data here may be, for example, data that has been processed by convolution or data that has been processed by pooling. Figure 1 In the example, the input data is recorded as "P Cin or P Pin ”,P Cin represents the convolution processed data, P Pin Represents the data after pooling.

[0092] The wiring MLA is used, for example, as a wiring for inputting digital data output from the output terminal TMo of the switching circuit D10 to the input terminal TN1i of the operation circuit D20. Figure 1 In the example, the digital data is recorded as "Pin , P Cin or P Pin ”.

[0093] The wiring MLB is used, for example, as a wiring for inputting digital data read from the storage circuit unit ME12 to the input terminal TN2i of the operation circuit D20. Note that the digital data here may be, for example, a filter value used for performing a convolution operation in the operation circuit D20. Figure 1 In the example, the filter value is recorded as K.

[0094] The wiring CNL is used, for example, as a wiring for inputting digital data output from the output terminal TNo of the operation circuit D20 to the memory circuit unit ME13. Note that the digital data here may be, for example, data resulting from convolution processing in the operation circuit D20. Figure 1 In the example, the data is recorded as P Cout .

[0095] The wiring POL is used, for example, as a wiring for inputting digital data read out from the memory circuit unit ME11 to the processing circuit D30. Note that the digital data here may be, for example, data subjected to pooling processing in the processing circuit D30. Figure 1 In the example, the data is recorded as P C .

[0096] In addition, the wiring POL may also be used as a wiring for transmitting digital data processed by the processing circuit D30 to the memory circuit unit ME11. Note that the digital data here may be, for example, data that has been pooled in the processing circuit D30. Figure 1 In the example, the data is recorded as P Pout .

[0097] The wiring IWL_1 is used, for example, as a wiring for inputting input data read from the storage circuit unit ME13 to the circuit WCS. Similarly, the wiring IWL_n is used, for example, as a wiring for inputting input data read from the storage circuit unit ME13 to the circuit WCS. Note that the input data here may be, for example, one of a multiplier and a multiplicand used to calculate the product of the fully connected layer and the product of the operation in the cell array CA. In particular, one of the multiplier and the multiplicand here is a weight coefficient. In addition, Figure 1 In the example, the input data is recorded as W out (1) and W out (n).

[0098] Wiring IXL_1 is used, for example, as a wiring for inputting input data read out from the storage circuit unit ME11 to the circuit XCS. Similarly, wiring IXL_m is used, for example, as a wiring for inputting input data read out from the storage circuit unit ME11 to the circuit XCS. Note that the input data here can be, for example, the other of the multiplier and the multiplicand used to calculate the product and the product of the calculation of the fully connected layer in the cell array CA. In particular, the other of the multiplier and the multiplicand here is the value of the signal input to the neuron in the fully connected layer. In addition, in Figure 1 In the example, the input data is recorded as X in (1) and X in (m).

[0099] The wiring OL_1 is used, for example, as a wiring for inputting digital data output from the output terminal of the first column of the circuit ITS to the memory circuit unit ME11. Similarly, the wiring OL_n is used, for example, as a wiring for inputting digital data output from the output terminal of the nth column of the circuit ITS to the memory circuit unit ME11. Note that the digital data here is, for example, the value of a signal output from a neuron in the fully connected layer. In addition, Figure 1 In the example, the digital data is recorded as X out (1) and X out (n).

[0100] [Switching circuit D10] The switching circuit D10 has a function of, for example, selecting one of the input terminal TM1i and the input terminal TM2i and outputting data input to the selected terminal to the output terminal TMo. In other words, the switching circuit D10 has a function of making one of the input terminal TM1i and the input terminal TM2i and the output terminal TMo conductive and making the other of the input terminal TM1i and the input terminal TM2i and the output terminal TMo non-conductive.

[0101] Notice, Figure 1 Although the switching circuit D10 has one input terminal TM1i and one input terminal TM2i, the switching circuit D10 may have a plurality of input terminals TM1i and TM2i instead of one. Figure 1 Although the switching circuit D10 has one output terminal TMo, the switching circuit D10 may have a plurality of output terminals TMo.

[0102] [Calculation circuit D20] The operation circuit D20 has a function of, for example, calculating the product of the digital data input to the input terminal TN1i and the digital data input to the input terminal TN1i. In addition, the operation circuit D20 has a function of adding a plurality of calculated products and outputting digital data corresponding to the value (the result of the sum of the products) to the output terminal TNo.

[0103] Figure 2A An example of the operation circuit D20 is shown. Figure 2A The operation circuit D20 shown includes a multiplication circuit MP, an addition circuit AP and a register RG.

[0104] In the operation circuit D20, the multiplication circuit MP performs multiplication on the digital data (for example, the image P) input from the wiring MLA. in 、Data P Cin or data P Pin ) and the digital data (e.g., filter value K) input from the wiring MLB. In addition, the operation result of the multiplication circuit MP is input to the addition circuit AP, and the output result of the addition circuit AP is held in the register RG. After the output result of the addition circuit AP is held in the register RG, when other product operations are performed in the multiplication circuit MP, the value of the product is added to the value held in the register RG in the addition circuit AP, and the result is input to the register RG. The sum-of-product operation is performed by repeatedly performing the above-mentioned operation. In addition, the sum-of-product operation result is output to the wiring CNL as digital data. Note that the register RG is controlled by the clock signal input to the wiring CLKL and the reset signal input to the wiring RSTL.

[0105] For example, in Figure 2A When the arithmetic circuit D20 adopts a structure that performs product-sum operation on 8-bit input data, Figure 2A The digital data processed by the operation circuit D20 can be Figure 2B Specifically, when 8-bit digital data from the wiring MLA and 8-bit digital data from the wiring MLB are input to the multiplication circuit MP, the multiplication circuit MP outputs 16-bit digital data as a multiplication result. In addition, when 16-bit digital data from the multiplication circuit MP and 17+α-bit digital data output from the register RG are input to the addition circuit AP, the addition circuit AP outputs 17+α-bit digital data as an addition result. Note that α represents the number of bits that increase when the addition circuit AP performs the addition operation.

[0106] Note that Figure 1In the semiconductor device CDV, the operation circuit D20 has a structure that performs product and sum operations based on data sent to the wiring MLA and the wiring MLB respectively, but for example, when a convolution process is performed in the operation circuit D20, the same filter value (sometimes referred to as a weight coefficient or a multiplier or a multiplicand) is sometimes repeatedly used.

[0107] Therefore, the following instructions set up multiple Figure 2A The operation circuit D20 shown has a structure that simultaneously performs a plurality of product-sum operations using a plurality of identical filter values.

[0108] Figure 3A It is shown Figure 1 The switching circuit D10 and the operation circuit D20 are shown as an example of a structure. Note that Figure 3A The memory circuit portion ME12 is also shown.

[0109] exist Figure 3A In the embodiment, the operation circuit D20 includes, for example, operation circuits D20_1 to D20_k.

[0110] Note that the operation circuits D20_1 to D20_k can be used, for example. Figure 2A Specifically, the operation circuits D20_1 to D20_k can be used Figure 3B The calculation circuit D20_h shown in FIG. 20_h (h is an integer greater than or equal to 1 and less than or equal to k). Figure 2A and Figure 2B Description of the operation circuit D20.

[0111] In addition, the wiring ILA includes, for example, the wiring ILA_1 to the wiring ILA_k. In addition, the wiring ILB includes, for example, the wiring ILB_1 to the wiring ILB_k. In addition, the wiring MLA includes, for example, the wiring MLA_1 to the wiring MLA_k. In addition, the wiring CNL includes, for example, the wiring CNL_1 to the wiring CNL_k.

[0112] Each of the plurality of output terminals TMo of the switching circuit D10 is electrically connected to the wirings MLA_1 to MLA_k in a one-to-one manner.

[0113] The input terminal TN1i of the operation circuit D20_1 is electrically connected to the wiring MLA_1, the input terminal TN2i of the operation circuit D20_1 is electrically connected to the wiring MLB, and the output terminal TNo of the operation circuit D20_1 is electrically connected to the wiring CNL_1. In addition, the input terminal TN1i of the operation circuit D20_k is electrically connected to the wiring MLA_k, the input terminal TN2i of the operation circuit D20_k is electrically connected to the wiring MLB, and the output terminal TNo of the operation circuit D20_k is electrically connected to the wiring CNL_k.

[0114] In other words, the input terminal TN1i of each of the arithmetic circuits D20_1 to D20_k is electrically connected to each of the plurality of output terminals TNo of the switching circuit D10 in a one-to-one manner.

[0115] Image P in A part of the area (described later as A in (x)) are transmitted together to each of the wirings ILA_1 to ILA_k. Specifically, for example, the image P which is the object of the convolution processing performed in the operation circuits D20_1 to D20_k in A plurality of digital data included in a portion of the area within is transmitted to each of the wirings ILA_1 to ILA_k.

[0116] In addition, data P Cin A plurality of digital data or data P included in a part of the area within Pin A plurality of digital data included in a part of the area within is transmitted to each of the wiring ILB_1 to the wiring ILB_k. Specifically, for example, the data P which is the object of the convolution processing performed in the operation circuit D20_1 to the operation circuit D20_k Cin A plurality of digital data or data P included in a part of the area within Pin A plurality of digital data included in a portion of the area within is transmitted to each of the wirings ILB_1 to ILB_k.

[0117] Here, the switching circuit D10 has, for example, the following functions: selects one of the input terminal TM1i electrically connected to the wiring ILA_1 and the input terminal TM2i electrically connected to the wiring ILB_1, and outputs the data input to the selected terminal to the output terminal TMo electrically connected to the wiring MLA_1. Similarly, the switching circuit D10 has, for example, the following functions: selects one of the input terminal TM1i electrically connected to the wiring ILA_k and the input terminal TM2i electrically connected to the wiring ILB_k, and outputs the data input to the selected terminal to the output terminal TMo electrically connected to the wiring MLA_k.

[0118] The wiring MLA_1 is used, for example, as a wiring for inputting digital data output from the first output terminal TMo of the switching circuit D10 to the input terminal TN1i of the operation circuit D20_1. Similarly, the wiring MLA_k is used, for example, as a wiring for inputting digital data output from the k-th output terminal TMo of the switching circuit D10 to the input terminal TN1i of the operation circuit D20_k. Note that Figure 3A In the above-mentioned image P, the digital data are recorded as A(1) and A(k) respectively.in The digital data in a part of the area within the data P Cin Digital data in a portion of the area or included in the data P Pin Digital data in a part of the area within.

[0119] The wiring CNL_1 is used, for example, as a wiring for inputting digital data output from the output terminal TNo of the operation circuit D20_1 to the memory circuit portion ME13. Similarly, the wiring CNL_k is used, for example, as a wiring for inputting digital data output from the output terminal TNo of the operation circuit D20_k to the memory circuit portion ME13. Note that the digital data here may be, for example, data resulting from convolution processing in the operation circuit D20. Figure 3A In the example, the data is recorded as P Cout (1) and P Cout (k). Note that the above P Cout It can be P Cout (1) and P Cout (k) combination.

[0120] By Figure 3A The switching circuit D10 and the operation circuit D20 shown in the figure are applied to Figure 1 The semiconductor device CDV can input a plurality of identical filter values ​​to each of the operation circuits D20_1 to D20_k, and can simultaneously perform product-sum operations in each of the operation circuits D20_1 to D20_k. Figure 3A In the switching circuit D10 and the operation circuit D20 shown, the order of inputting data will be described later.

[0121] [Processing circuit D30] The processing circuit D30 has, for example, a function for processing the data P read from the memory circuit unit ME11. C In addition, the processing circuit D30 also has the function of processing the data P output by the pooling process. Pout The processing circuit D30 may have a function of performing arithmetic processing of a function (for example, an activation function) and a normalization arithmetic processing (constantization) in addition to the pooling processing.

[0122] [Memory Circuit Section ME11 to Memory Circuit Section ME13] The memory circuit unit ME11 is used as a memory unit for storing input data (for example, data P) input to the operation circuit D20 in the semiconductor device CDV. Cin or P Pin ) and the output data (e.g., data P) outputted from the operation circuit D20 Cout). In addition, the storage circuit section ME12 is used as a storage device for storing input data (for example, filter value K) input to the operation circuit D20. In addition, the storage circuit section ME13 is used as a storage device for storing W as input data input to the circuit WCS. out (1) to W out (n) (e.g., weight coefficients).

[0123] It is particularly preferable that the memory circuit unit ME12 is disposed near the operation circuit D20, for example, to read out the filter value K and send it to the operation circuit D20. For example, the memory circuit unit ME12 is preferably stacked above or below the operation circuit D20.

[0124] In addition, it is preferable that the memory circuit unit ME13 is disposed, for example, near the circuit WCS to read out the weight coefficient and send it to the circuit WCS. For example, the memory circuit unit ME13 is preferably stacked above or below the circuit WCS.

[0125] Figure 4A The memory circuit MEX is a circuit configuration example that can be applied to each of the memory circuit portion ME11 to the memory circuit portion ME13 included in the semiconductor device CDV.

[0126] in addition, Figure 4A The cell array MEA and the memory cells MC[1,1], MC[u,1], MC[1,v], and MC[u,v] in the cell array MEA are arranged in a matrix of u rows and v columns (u is an integer greater than 1, and v is an integer greater than 1). Figure 4A The wiring WWL_1 to the wiring WWL_u, the wiring RWL_1 to the wiring RWL_u, the wiring WBL_1 to the wiring WBL_v, and the wiring RBL_1 to the wiring RBL_v are shown. Figure 4A Circuit WWD, circuit RBD, circuit WBD and circuit RBD are shown. In addition, Figure 4A The wiring DIL electrically connected to the circuit WBD and the wiring DOL electrically connected to the circuit RBD are shown.

[0127] The memory cell MC[1,1] arranged in the first row and the first column is electrically connected to the wiring WWL_1, the wiring RWL_1, the wiring WBL_1, and the wiring RBL_1. In addition, the memory cell MC[u,1] arranged in the u-th row and the first column is electrically connected to the wiring WWL_u, the wiring RWL_u, the wiring WBL_1, and the wiring RBL_1. In addition, the memory cell MC[1,v] arranged in the first row and the v-th column is electrically connected to the wiring WWL_1, the wiring RWL_1, the wiring WBL_v, and the wiring RBL_v. In addition, the memory cell MC[u,v] arranged in the u-th row and the v-th column is electrically connected to the wiring WWL_u, the wiring RWL_u, the wiring WBL_v, and the wiring RBL_v.

[0128] The circuit WWD is electrically connected to each of the wirings WWL_1 to WWL_u. In addition, the circuit RWD is electrically connected to each of the wirings RWL_1 to RWL_u. In addition, the circuit WBD is electrically connected to each of the wirings WBL_1 to WBL_v. In addition, the circuit RBD is electrically connected to each of the wirings RBL_1 to RBL_v.

[0129] The circuit WWD is used, for example, as a write word line driver circuit. The circuit RWD is used, for example, as a read word line driver circuit. The circuit WBD is used, for example, as a write bit line driver circuit. The circuit RBD is used, for example, as a read bit line driver circuit.

[0130] In addition, the circuit WBD has a function of receiving input data sent to the wiring DIL and sending the input data to one selected from the wirings WBL_1 to WBL_v. In addition, the circuit WBD has a function of selecting one of the wirings RBL_1 to RBL_v and sending read data from the memory cell MC flowing through the selected wiring to the wiring DOL.

[0131] For example, in Figure 1 The memory circuit unit ME11 uses Figure 4A When the storage circuit MEX is shown, the wiring ILB and Figure 4A The wiring DOL is electrically connected. Figure 1 The storage circuit unit ME12 uses Figure 4A When the memory circuit MEX is shown, the wiring MLB and Figure 4A The wiring DOL is electrically connected. Figure 1 The memory circuit unit ME11 uses Figure 4A When the memory circuit MEX is shown, the wiring CNL and Figure 4A The wiring DIL is electrically connected.

[0132] For example, in Figure 1 The storage circuit unit ME13 uses Figure 4AIn the case of the memory circuit MEX shown in FIG. 1 , any one of the wirings IWL_1 to IWL_n is connected to Figure 4A The wiring DOL is electrically connected. Figure 1 The memory circuit unit ME11 uses Figure 4A In the case of the storage circuit MEX shown in FIG. 1 , any one of the wirings IXL_1 to IXL_m is connected to Figure 4A The wiring DOL is electrically connected. Figure 1 The memory circuit unit ME11 uses Figure 4A In the storage circuit MEX shown in FIG. 1 , wiring OL_1 to wiring OL_n are connected to Figure 4A The wiring DIL is electrically connected.

[0133] Next, a memory cell applicable to the memory cell MC[1,1] to the memory cell MC[u,v] will be described.

[0134] Figure 4B 1 is a diagram for explaining an example of a circuit configuration of each of the memory cells MC[1,1] to MC[u,v] applicable to the memory circuit MEX. Figure 4B In the embodiment, the memory cell MC includes a transistor M1, a transistor M2, a transistor M3 and a capacitor C1. Figure 4B The memory cell MC shown has a structure of a gain unit including three transistors. In particular, when the transistors M1 and M3 are OS transistors, the memory cell MC is sometimes referred to as NOSRAM (registered trademark) (Nonvolatile Oxide Semiconductor Random Access Memory).

[0135] Transistor M1 and transistor M3 are preferably OS transistors, for example. In particular, as the metal oxide contained in the channel formation region of the OS transistor, for example, indium oxide, gallium oxide and zinc oxide can be cited. In addition, the metal oxide preferably contains one or more selected from indium, element M and zinc. Note that element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, magnesium and antimony. In particular, element M is preferably one or more selected from aluminum, gallium, yttrium and tin. Note that metal oxides containing indium, element M and zinc are sometimes referred to as In-M-Zn oxides.

[0136] In particular, as a metal oxide for the semiconductor layer, an oxide containing indium (In), gallium (Ga) and zinc (Zn) (also referred to as IGZO) is preferably used. Alternatively, an oxide containing indium, tin and zinc (also referred to as ITZO (registered trademark)) is preferably used. Alternatively, an oxide containing indium (In), gallium (Ga), tin (Sn) and zinc (Zn) is preferably used. Alternatively, an oxide containing indium (In), aluminum (Al) and zinc (Zn) (also referred to as IAZO) is preferably used. Alternatively, an oxide containing indium (In), aluminum (Al), gallium (Ga) and zinc (Zn) (also referred to as IAGZO) is preferably used.

[0137] In addition, the metal oxide contained in the channel formation region of the OS transistor preferably has a stacked structure of multiple oxide layers with different chemical compositions. For example, consider an oxide layer with a two-layer structure having a first layer and a second layer located directly above the first layer. The atomic number ratio of the element M relative to the metal element of the main component in the metal oxide used for the first layer is preferably greater than the atomic number ratio of the element M relative to the metal element of the main component in the metal oxide used for the second layer. In addition, the atomic number ratio of the element M relative to In in the metal oxide used for the first layer is preferably greater than the atomic number ratio of the element M relative to In in the metal oxide used for the second layer. By adopting this structure, it is possible to suppress the diffusion of impurities and oxygen from the structure formed below the first layer to the second layer.

[0138] Furthermore, the atomic number ratio of In to element M in the metal oxide used in the second layer is preferably greater than the atomic number ratio of In to element M in the metal oxide used in the first layer. With this structure, the OS transistor can obtain large on-state current and high frequency characteristics.

[0139] Specifically, for example, as the metal oxide for the first layer, a metal oxide having a composition of In:M:Zn=1:3:2 [atomic ratio] or a composition close thereto, In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto, or In:M:Zn=1:1:0.5 [atomic ratio] or a composition close thereto may be used. Furthermore, as the metal oxide for the second layer, a metal oxide having a composition of In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:1.2 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:2 [atomic ratio] or a composition close thereto, or In:M:Zn=4:2:3 [atomic ratio] or a composition close thereto may be used. Note that the nearby composition includes a range of ±30% of the desired atomic ratio.

[0140] In addition, as one or more selected from the transistors M1 to M3, a transistor including silicon in a channel formation region (hereinafter referred to as a Si transistor) may be used in addition to the OS transistor. As silicon, for example, amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, or single crystal silicon may be used.

[0141] In addition, as one or more selected from the transistors M1 to M3, in addition to the OS transistor and the Si transistor, for example, a transistor containing germanium or the like in the channel formation region, a transistor containing compound semiconductors such as zinc selenide, cadmium sulfide, gallium arsenide, indium phosphide, gallium nitride or silicon germanium in the channel formation region, a transistor containing carbon nanotubes in the channel formation region, or a transistor containing an organic semiconductor in the channel formation region can also be used.

[0142] By using an OS transistor as one or more of the transistors M1 to M3, the leakage current of the selected transistor can be suppressed, so the power consumption of the operation circuit can be reduced. Specifically, when the transistor M1 is in a non-conducting state, the leakage current from the holding node (for example, the first terminal of the transistor M1, the first terminal of the capacitor C1, and the gate of the transistor M2) to the wiring WBL can be made very small, so the refresh work of the potential of the holding node can be reduced. In addition, by reducing the refresh work, the power consumption of the operation circuit can be reduced.

[0143] In addition, the circuit WWD, the circuit RWD, the circuit WBD, and the circuit RBD preferably all include CMOS circuits. In addition, the CMOS circuit preferably includes Si transistors. For example, when manufacturing p-channel transistors, Si transistors are preferably used compared to OS transistors from the viewpoint of reliability. Therefore, it is preferred that the circuit WWD, the circuit RWD, the circuit WBD, and the circuit RBD are manufactured on a semiconductor substrate made of silicon, and the memory cell MC is manufactured above the circuit WWD, the circuit RWD, the circuit WBD, and the circuit RBD.

[0144] In addition, when a semiconductor device is highly integrated on a chip, heat is sometimes generated in the chip due to circuit driving. Due to this heat, the temperature of the transistor increases, so the characteristics of the transistor change, which may lead to changes in field effect mobility, a decrease in operating frequency, etc. The heat resistance of OS transistors is higher than that of Si transistors, so it is not easy to cause changes in field effect mobility caused by temperature changes, and it is not easy to cause a decrease in operating frequency. In addition, in OS transistors, even if the temperature increases, it is easy to maintain the characteristic that the drain current increases exponentially with respect to the voltage between the gate and the source. Therefore, by using OS transistors, it is easy to perform calculations, processing, etc. even in a high temperature environment. Therefore, when a driving circuit such as circuit WWD, circuit RWD, circuit WBD and circuit RBD is manufactured on a semiconductor substrate made of silicon to form a semiconductor device with high resistance to the heat caused by the driving circuit, an OS transistor is preferably used as a transistor included in the circuit arranged above the driving circuit.

[0145] Figure 4B It is shown that transistors M1 to M3 include back gates. Although the connection structure of the back gate is not shown, the electrical connection object of the back gate can be determined when designing. For example, in a transistor including a back gate, in order to increase the on-state current of the transistor, the gate and the back gate can be electrically connected. That is to say, for example, the gate of transistor M1 can also be electrically connected to the back gate. In addition, for example, in a transistor including a back gate, in order to change the threshold voltage of the transistor or reduce the off-state current of the transistor, a wiring for electrically connecting the back gate of the transistor to an external circuit can also be provided to supply a potential to the back gate of the transistor through the external circuit.

[0146] In addition, although Figure 4B The transistors M1 to M3 shown include back gates, but the semiconductor device of one embodiment of the present invention is not limited thereto. For example, Figure 4B The transistors M1 to M3 shown may also be structures without back gates, that is, transistors with single gate structures. In addition, there may also be a structure in which some transistors include back gates and other transistors do not include back gates.

[0147] In addition, although Figure 4B Although the transistors M1 to M3 are shown as n-channel transistors, the semiconductor device of one embodiment of the present invention is not limited thereto. For example, n-channel transistors may be used as the transistors M2 and M3 and the transistor M1 may be replaced by a p-channel transistor.

[0148] Note that the above-described modification examples of the structure and polarity of the transistors are not limited to the transistors M1 to M3 , and are also applicable to transistors described in other parts of the specification and transistors shown in other drawings.

[0149] The first terminal of transistor M1 is electrically connected to the gate of transistor M2 and the first terminal of capacitor C1, the second terminal of transistor M1 is electrically connected to wiring WBL, and the gate of transistor M1 is electrically connected to wiring WWL. In addition, the first terminal of transistor M2 is electrically connected to the first terminal of transistor M3, and the second terminal of transistor M2 is electrically connected to wiring CVLB. The second terminal of transistor M3 is electrically connected to wiring RBL, and the gate of transistor M3 is electrically connected to wiring RWL.

[0150] Figure 4B The wiring WWL shown is equivalent to Figure 4A Any one of the wiring WWL_1 to the wiring WWL_u shown. In addition, Figure 4B The wiring RWL shown is equivalent to Figure 4A Any of the wirings RWL_1 to RWL_u shown. Figure 4B The wiring WBL shown is equivalent to Figure 4A Any one of the wirings WBL_1 to WBL_v shown. Figure 4B The wiring RBL shown is equivalent to Figure 4A Any one of the wirings RBL_1 to RBL_v shown.

[0151] In addition, the wiring CVLA is used as a wiring for supplying a fixed potential. The fixed potential may be, for example, a high level potential, a low level potential, a ground potential, or a negative potential. Similarly, the wiring CVLB is also used as a wiring for supplying the fixed potential mentioned above. In addition, the potential sent to the wiring CVLA and the wiring CVLB may be, for example, a variable potential (for example, also referred to as a pulse voltage or a pulse signal) instead of a fixed potential.

[0152] exist Figure 4B In the memory cell MC shown in FIG. 1 , by using an OS transistor as the transistor M1 , the current (sometimes referred to as leakage current) flowing between the source and drain of the transistor M1 in the off state can be made extremely small. Figure 4B The memory cell MC shown in the figure uses an OS transistor as the transistor M1 and retains charges corresponding to data in the memory circuit by utilizing the characteristic that leakage current is extremely small, thereby being used as a nonvolatile memory.

[0153] In addition, Figure 4B In addition to the memory cell MC, for example, Figure 4C The memory cell MC shown is used for Figure 4AThe memory cell MC[1, 1] to the memory cell MC[u, v] of the memory circuit MEX. Figure 4C The storage cell MC and Figure 4B The memory cell MC of FIG. 1 is different in that the wiring WBL and the wiring RBL are combined into one wiring BL. Figure 4B Compared with the structure of the memory cell MC shown in FIG. Figure 4C The structure of the memory cell MC shown can reduce the number of wirings extending in the column direction, thereby reducing the circuit area. In addition, the storage density of the memory unit can be increased depending on the situation.

[0154] Available for Figure 4A The circuit structure of the storage circuit MEX is not limited to Figure 4B and Figure 4C For example, the memory cell MC shown in FIG. Figure 5A The memory cell MC shown is used for Figure 4A The storage circuit MEX. Figure 5A In FIG. 1 , the memory cell MC includes a transistor M1 and a capacitor C1. Figure 5A The memory cell MC shown includes a transistor. In this way, a circuit composed of a transistor and a capacitor is sometimes called a DRAM (Dinamic Random Access Memory). In particular, when the transistor M1 is an OS transistor, the memory cell MC is sometimes called a NOSRAM (registered trademark) (Nonvolatile Oxide Semiconductor Random Access Memory).

[0155] Figure 5A The memory cell MC including the transistor M1 and the capacitor C1 is shown. The above-mentioned OS transistor can be used as the transistor M1.

[0156] exist Figure 5A In the embodiment, a first terminal of the transistor M1 is electrically connected to a first terminal of the capacitor C1, a second terminal of the transistor M1 is electrically connected to a wiring WBL, and a gate of the transistor M1 is electrically connected to a wiring WWL. In addition, a second terminal of the capacitor C1 is electrically connected to a wiring CVLA.

[0157] Figure 5A The wiring WWL shown is used as a write word line and a read word line. Figure 5A The memory cell MC is used as Figure 4A When the memory cell MC of the memory circuit MEX is Figure 4A The circuit WWD shown is preferably used as a write word line driver circuit and a read word line driver circuit. Figure 4AThe circuit RWD and the wirings RWL_1 to RWL_u may not be provided in the storage circuit MEX.

[0158] in addition, Figure 5A The wiring WBL shown is used as a write bit line and a read bit line. Figure 5A The memory cell MC is used as Figure 4A When the memory cell MC of the memory circuit MEX is Figure 4A Each of the wirings WBL_1 to WBL_v shown is preferably electrically connected to the circuit RBD. Figure 4A The wirings RBL_1 to RBL_v may not be provided in the storage circuit MEX.

[0159] In addition, as can be used Figure 4A The circuit structure of the storage circuit MEX is, for example, Figure 5B As shown in the memory cell MC, a circuit equivalent to a 2T (2-transistor) type NOSRAM can also be used. Figure 5B The memory circuit MEX including the transistor M1, the transistor M2, and the capacitor C1 is shown. In addition, the above-mentioned OS transistor can be used as the transistor M1 and the transistor M2.

[0160] exist Figure 5B In the embodiment, the first terminal of transistor M1 is electrically connected to the gate of transistor M2 and the first terminal of capacitor C1, the second terminal of transistor M1 is electrically connected to wiring WBL, and the gate of transistor M1 is electrically connected to wiring WWL. The first terminal of transistor M2 is electrically connected to wiring RBL, and the second terminal of transistor M2 is electrically connected to wiring SL. In addition, the second terminal of capacitor C1 is electrically connected to wiring RWL.

[0161] Figure 5B The wiring WWL shown is used as a write word line, Figure 5B The wiring RWL shown is used as a read word line. Figure 5B The wiring WBL shown is used as a write bit line, Figure 5B The wiring RBL shown is used as a read bit line.

[0162] in addition, Figure 5B The wiring SL shown is used as a source line. In addition, a fixed potential or a variable potential may be supplied to the wiring SL. In addition, an arbitrary amount of current may be supplied to the wiring SL.

[0163] As can be used Figure 4A The circuit structure of the storage circuit MEX is, for example, Figure 5C As shown in the memory cell MC, a NOSRAM circuit including three transistors may be used in combination. Figure 5CThe memory cell MC includes a memory cell MCP and a memory cell MCN. The memory cell MCP and the memory cell MCN each hold logically different data. That is, the memory cell MCP and the memory cell MCN are used as complementary memory cells.

[0164] The structures of the storage unit MCP and the storage unit MCN can be referred to Figure 4B Note that the following shows the memory cell MC. Figure 5C The memory cell MCP and the memory cell MCN are shown Figure 4B Different parts of a memory cell MC are shown.

[0165] The gate of each transistor M1 included in the memory cell MCP and the memory cell MCN is electrically connected to the wiring WWL. In addition, the second terminal of each capacitor C1 included in the memory cell MCP and the memory cell MCN is electrically connected to the wiring CVLA. In addition, the gate of each transistor M3 included in the memory cell MCP and the memory cell MCN is electrically connected to the wiring RWL. In addition, the second terminal of the transistor M2 included in the memory cell MCP and the memory cell MCN is electrically connected to the wiring CVLB.

[0166] In the memory cell MCP, the second terminal of the transistor M1 is electrically connected to the wiring WBLP. In addition, the second terminal of the transistor M3 is electrically connected to the wiring RBLP.

[0167] In the memory cell MCN, the second terminal of the transistor M1 is electrically connected to the wiring WBLN, and the second terminal of the transistor M3 is electrically connected to the wiring RBLN.

[0168] Figure 5C The wiring WBLP and the wiring WBLN shown are used as write bit lines. Figure 5C The memory cell MC is used as Figure 4A When the memory cell MC of the memory circuit MEX is Figure 5C The wiring WBLP and the wiring WBLN are equivalent to Figure 4A The wiring WBL shown. In addition, Figure 5C The wiring RBLP and the wiring RBLN shown are used as write bit lines. Figure 5C The memory cell MC is used as Figure 4A When the memory cell MC of the memory circuit MEX is Figure 5C The wiring RBLP and wiring RBLN are equivalent to Figure 4A The wiring RBL is shown.

[0169] [Cell Array CA] Next, the cell array CA included in the arithmetic unit ANP will be described.

[0170] Figure 6 The summary shows Figure 1 FIG. 1 is a diagram of a cell array CA, a circuit WSD, a circuit WCS, a circuit WSD, a circuit XCS, and a circuit ITS in an arithmetic unit ANP of FIG. 1 . In particular, Figure 6 A cell array CA, a circuit WCS, a circuit XCS, and a circuit ITS are shown.

[0171] The cell array CA has a function of performing product-sum operations on the first data written to the operation units IM and the second data sent from the circuit XCS to the operation units. Note that in this embodiment, the first data and the second data are positive values ​​or "0".

[0172] The cell array CA includes, for example, operation units IM[1, 1] to IM[m, n] and driving units IMD_1 to IMD_m.

[0173] Note that the structures of the arithmetic units IM[1,1] to IM[m,n] are identical to each other. Therefore, the addresses of the same contents in the arithmetic units IM[1,1] to IM[m,n] are sometimes omitted. Similarly, the structures of the drive units IMD_1 to IMD_m are identical to each other, and the addresses of the same contents in the drive units IMD_1 to IMD_m are sometimes omitted.

[0174] The operation unit IM[1,1] to the operation unit IM[m,n] are used as a unit for performing a multiplication operation, for example. In addition, the driving unit IMD_1 to the driving unit IMD_m have, for example, a function of holding a potential corresponding to reference data to perform operations in the operation unit IM[1,1] to the operation unit IM[m,n]. Note that the reference data will be described in detail later.

[0175] The operation unit IM includes, for example, a transistor F1, a transistor F2, a transistor F5, and a capacitor C5. In addition, the driving unit IMD includes, for example, a transistor F1d, a transistor F2d, a transistor F5d, and a capacitor C5d.

[0176] In particular, the structures (e.g., channel length, channel width, and shape) of the transistors F1 included in the operation units IM[1,1] to IM[m,n] are preferably identical to each other, the structures of the transistors F2 included in the operation units IM[1,1] to IM[m,n] are preferably identical to each other, and the structures of the transistors F5 included in the operation units IM[1,1] to IM[m,n] are preferably identical to each other. In addition, the structures of the transistors F1d included in the drive units IMD_1 to IMD_m are preferably identical to each other, the structures of the transistors F2d included in the drive units IMD_1 to IMD_m are preferably identical to each other, and the structures of the transistors F5d included in the drive units IMD_1 to IMD_m are preferably identical to each other. In addition, the structures of the transistors F1 and F1d are preferably identical to each other, the structures of the transistors F2 and F2d are preferably identical to each other, and the structures of the transistors F5 and F5d are preferably identical to each other.

[0177] When the structures of transistors are identical to each other, the electrical characteristics of each transistor can be made substantially equal. Therefore, when the structures of transistors F1 included in operation units IM[1,1] to IM[m,n] are identical, the structures of transistors F2 included in operation units IM[1,1] to IM[m,n] are identical, and the structures of transistors F5 included in operation units IM[1,1] to IM[m,n] are identical, operation units IM[1,1] to IM[m,n] can perform almost the same operation under the same conditions. Here, the same conditions refer to, for example, the potentials of the source, drain, and gate of transistor F1, the potentials of the source, drain, and gate of transistor F2, the potentials of the source, drain, and gate of transistor F5, and the voltages input to operation units IM[1,1] to IM[m,n]. Similarly, when the transistors F1d included in the driving units IMD_1 to IMD_m are of the same structure, the transistors F2d included in the driving units IMD_1 to IMD_m are of the same structure, and the transistors F5d included in the driving units IMD_1 to IMD_m are of the same structure, the driving units IMD_1 to IMD_m can perform almost the same operation under the same conditions. Here, the same conditions refer to, for example, the potentials of the source, drain, and gate of the transistor F1d, the potentials of the source, drain, and gate of the transistor F2d, the potentials of the source, drain, and gate of the transistor F5d, and the voltages input to the driving units IMD_1 to IMD_m.

[0178] In addition, unless otherwise stated, the case where the transistor F1 and the transistor F1d work as a switching element is included. That is, the following case is included: the gate voltage, source voltage, and drain voltage of each of the above transistors are appropriately biased so that the transistor works as a switching element. Note that one embodiment of the present invention is not limited to this. For example, the transistor F1 and the transistor F1d can work in the linear region or the saturation region when they are in the on state, and can also work in the linear region sometimes and in the saturation region sometimes.

[0179] In addition, unless otherwise specified, the transistor F2 and the transistor F2d are included in the case where they operate in the subthreshold region (in other words, in the transistor F2 or the transistor F2d, the gate-source voltage is lower than the threshold voltage, and more preferably, the drain current increases exponentially relative to the gate-source voltage). In other words, the following cases are included: the gate voltage, source voltage, and drain voltage of the above-mentioned transistors are appropriately biased so that the transistor operates in the subthreshold region. Therefore, the transistor F2 and the transistor F2d are included in the case where the off-state current flows between the source and the drain.

[0180] In addition, the transistor F5 and the transistor F5d are used as clamp transistors (sometimes referred to as clamp FETs), for example. Therefore, each gate of the transistor F5 and the transistor F5d is preferably supplied with a fixed potential. In addition, by providing the transistor F5 (transistor F5d), drain-induced barrier lowering (DIBL) in the transistor F2 (transistor F2d) can be prevented, and its details will be described later.

[0181] On the other hand, when the drain induced barrier lowering (DIBL) in the transistor F2 (transistor F2d) can be ignored, the transistor F5 (transistor F5d) may not be provided in the arithmetic unit IM (drive unit IMD).

[0182] In addition, transistors F1, F1d, F2, F2d, F5, and F5d may all be transistors that can be used as transistors M1 to M3. In particular, transistors F1, F1d, F2, F2d, F5, and F5d are preferably all OS transistors.

[0183] By using an OS transistor as one or both of the transistor F1 and the transistor F1d, the leakage current of one or both of the transistor F1 and the transistor F1d can be suppressed, thereby reducing the power consumption of the operation circuit. Specifically, when one or both of the transistor F1 and the transistor F1d are in a non-conducting state, the leakage current from the holding node (for example, the node N or the node Nd described later) to the write word line can be made very small, so the refresh work of the potential of the holding node can be reduced. In addition, the power consumption of the product-sum operation circuit can be reduced by reducing the refresh work. In addition, by making the leakage current from the holding node to any of the wiring WCL and the wiring XCL very small, the unit can maintain the potential of the holding node for a long time, thereby improving the calculation accuracy of the operation circuit.

[0184] Furthermore, by using an OS transistor as one or both of the transistor F2 and the transistor F2d, it is possible to operate the transistors in a wider current range in the subthreshold region, thereby reducing current consumption.

[0185] In addition, by using OS transistors as transistors F2, transistor F2d, transistor F5, and transistor F5d, transistors F2, transistor F2d, transistor F5, and transistor F5d can be manufactured simultaneously with transistor F1 and transistor F1d, thereby sometimes shortening the manufacturing process of the operation circuit. In addition, Si transistors can be used as transistors F2, transistor F2d, transistor F5, and transistor F5d in addition to OS transistors.

[0186] In the arithmetic units IM[1,1] to IM[m,n], the first terminal of the transistor F1 is electrically connected to the gate of the transistor F2. The first terminal of the transistor F2 is electrically connected to the wiring VE0. The first terminal of the capacitor C5 is electrically connected to the gate of the transistor F2. The second terminal of the transistor F2 is electrically connected to the first terminal of the transistor F5. In addition, the second terminal of the transistor F5 is electrically connected to the second terminal of the transistor F1, and the gate of the transistor F5 is electrically connected to the wiring VE1.

[0187] In addition, in the arithmetic units IM[1,1] to IM[m,n], the second terminal of the transistor F2 is electrically connected in series with the wiring WCL via the first terminal and the second terminal of the transistor F5, thereby preventing the wiring WCL from directly applying a high-level potential to the second terminal of the transistor F2. Thus, the drain-induced barrier lowering in the transistor F2 can be prevented.

[0188] In the operation unit IM[1,1] to the operation unit IM[m,n], if the second terminal of the transistor F2 is directly electrically connected to the wiring WCL (that is, the transistor F5 is not provided), sometimes a high-level potential is directly applied to the second terminal of the transistor F2 from the wiring WCL, and a drain-induced barrier lowering occurs in the transistor F2. When the drain-induced barrier lowering occurs in the transistor F2, the threshold voltage of the transistor F2 decreases, so sometimes the voltage range of the subthreshold region of the transistor F2 changes. Therefore, when the transistor F5 is not provided in the operation unit IM[1,1] to the operation unit IM[m,n], sometimes the current flowing through the subthreshold region of the transistor F2 fluctuates.

[0189] In the driving units IMD_1 to IMD_m, the first terminal of the transistor F1d is electrically connected to the gate of the transistor F2d. The first terminal of the transistor F2d is electrically connected to the wiring VE0. The first terminal of the capacitor C5d is electrically connected to the gate of the transistor F2d. The second terminal of the transistor F2d is electrically connected to the first terminal of the transistor F5d. In addition, the second terminal of the transistor F5d is electrically connected to the second terminal of the transistor F1d, and the gate of the transistor F5d is electrically connected to the wiring VE1.

[0190] Similar to the transistor F5 in each of the operation units IM[1,1] to IM[m,n], the transistor F5d in the drive units IMD_1 to IMD_m also has a function of preventing the drain-induced barrier lowering in the transistor F2d.

[0191] Wiring VE0 is used as wiring for allowing current to flow between the first terminal and the second terminal of each transistor F2 of operation unit IM[1,1] to operation unit IM[m,n]. In addition, wiring VE0 is used as wiring for allowing current to flow between the first terminal and the second terminal of transistor F2d of drive unit IMD_1 to drive unit IMD_m. As an example, wiring VE0 is used as wiring for supplying a fixed potential. The fixed potential may be, for example, a low level potential or a ground potential.

[0192] Wiring VE1 is used as wiring for applying a potential to the gates of transistors F5 of operation units IM[1,1] to IM[m,n] and the gates of transistors F5d of drive units IMD_1 to IMD_m. Note that this potential is preferably within the range in which transistors F5 and F5d are used as clamp transistors.

[0193] In the arithmetic unit IM[1, 1], the second terminal of the transistor F1 and the second terminal of the transistor F5 are electrically connected to the wiring WCL_1, and the gate of the transistor F1 is electrically connected to the wiring WSL_1. The second terminal of the capacitor C5 is electrically connected to the wiring XCL_1. Figure 6In the illustrated operation unit IM[1, 1], a connection portion between the first terminal of the transistor F1, the gate of the transistor F2, and the first terminal of the capacitor C5 is represented as a node N[1, 1].

[0194] In the arithmetic unit IM[m, 1], the second terminal of the transistor F1 and the second terminal of the transistor F5 are electrically connected to the wiring WCL_1, and the gate of the transistor F1 is electrically connected to the wiring WSL_m. The second terminal of the capacitor C5 is electrically connected to the wiring XCL_m. Figure 6 In the illustrated operation unit IM[m, 1], a connection portion between the first terminal of the transistor F1, the gate of the transistor F2, and the first terminal of the capacitor C5 is represented as a node N[m, 1].

[0195] In the arithmetic unit IM[1,n], the second terminal of the transistor F1 and the second terminal of the transistor F5 are electrically connected to the wiring WCL_n, and the gate of the transistor F1 is electrically connected to the wiring WSL_1. The second terminal of the capacitor C5 is electrically connected to the wiring XCL_1. Figure 6 In the illustrated arithmetic unit IM[1,n], a connection portion between the first terminal of the transistor F1, the gate of the transistor F2, and the first terminal of the capacitor C5 is represented as a node N[1,n].

[0196] In the arithmetic unit IM[m,n], the second terminal of the transistor F1 and the second terminal of the transistor F5 are electrically connected to the wiring WCL_n, and the gate of the transistor F1 is electrically connected to the wiring WSL_m. The second terminal of the capacitor C5 is electrically connected to the wiring XCL_m. Figure 6 In the illustrated arithmetic unit IM[m,n], a connection portion between the first terminal of the transistor F1, the gate of the transistor F2, and the first terminal of the capacitor C5 is represented as a node N[m,n].

[0197] In the driving unit IMD_1, the second terminal of the transistor F1d and the second terminal of the transistor F5d are electrically connected to the wiring XCL_1, and the gate of the transistor F1d is electrically connected to the wiring WSL_1. The second terminal of the capacitor C5d is electrically connected to the wiring XCL_1. Figure 6 In the driving unit IMD_1 shown in the figure, a connection portion between the first terminal of the transistor F1d, the gate of the transistor F2d, and the first terminal of the capacitor C5d is represented as a node Nd[1].

[0198] In the driving unit IMD_m, the second terminal of the transistor F1d and the second terminal of the transistor F5d are electrically connected to the wiring XCL_m, and the gate of the transistor F1d is electrically connected to the wiring WSL_1. The second terminal of the capacitor C5d is electrically connected to the wiring XCL_m. Figure 6In the driving unit IMD_m shown in the figure, a connection portion between the first terminal of the transistor F1d, the gate of the transistor F2d, and the first terminal of the capacitor C5d is represented as a node Nd[s].

[0199] The node N[1,1], the node N[1,n], the node N[m,1], the node N[m,n], the node Nd[1], and the node Nd[m] are used as holding nodes of each unit.

[0200] In the operation unit IM[1,1] to the operation unit IM[m,n], for example, when the transistor F1 and the transistor F5 are in the on state, the gate of the transistor F2 and the second terminal are in the on state. When the fixed potential supplied by the wiring VE0 is set to the ground potential (GND), the transistor F1 is in the on state and the current of the current amount I flows from the wiring WCL to the second terminal of the transistor F2, the potential of the gate (node ​​N) of the transistor F2 is determined according to the current amount I. Note that since the transistor F1 is in the on state, ideally, the potential of the second terminal of the transistor F2 is equal to the potential of the gate (node ​​N) of the transistor F2. Here, by turning off the transistor F1, the potential of the gate (node ​​N) of the transistor F2 is maintained by the capacitor C5. Thus, the transistor F2 can make the current of the current amount I corresponding to the ground potential of the first terminal of the transistor F2 and the potential of the gate (node ​​N) of the transistor F2 flow between the source and the drain of the transistor F2. In this specification, etc., this operation is referred to as "setting (programming) the amount of current flowing between the source and drain of the transistor F2 of the operation unit IM to 1" or the like.

[0201] Note that in the above description, by replacing transistor F1 with transistor F1d, transistor F2 with transistor F2d, and node N with node Nd, the amount of current flowing between the source and drain of transistor F2d can be similarly set in driving units IMD_1 to IMD_m.

[0202] [Circuit WSD] For example, the circuit WSD has a function of supplying a predetermined signal to each of the wirings WSL_1 to WSL_m when writing first data to the operation unit IM included in the cell array CA, thereby selecting a row of the cell array CA to which the first data is written.

[0203] For example, in Figure 6In the circuit WSD, a high-level potential is supplied to the wiring WSL_1 and a low-level potential is supplied to the wiring WSL_2 (not shown) to the wiring WSL_m, thereby turning on the transistor F1 and the transistor F1d including the gate electrically connected to the wiring WSL1[1], and turning off the transistor F1 and the transistor F1d including the gate electrically connected to each of the wirings WSL_2 to WSL_m.

[0204] [Circuit WCS] The circuit WCS has the following functions, for example: obtaining first data as digital data from the storage circuit unit ME11, converting the first data into analog data (current), and supplying the first data converted into analog data to the operation unit IM included in the cell array CA. For example, when the circuit WCS writes the first data to the operation unit IM[1,1] included in the cell array CA, after the operation units IM[1,1] to the operation unit IM[1,n] of the first row of the cell array CA are selected by the above-mentioned circuit WSD, the circuit WCS supplies the first data to the operation units of the first column of the cell array CA through the wiring WCL_1.

[0205] The circuit WCS includes, for example, a circuit SWCA and circuits WCSa_1 to WCSa_n.

[0206] The circuit SWCA has a function of, for example, making the wiring WCL_1 and the circuit WCSa_1 conductive or non-conductive. Also, the circuit SWCA has a function of making the wiring WCL_n and the circuit WCSa_n conductive or non-conductive.

[0207] The circuit SWCA includes, for example, switches SA_1 to SA_n.

[0208] The first terminal of the switch SA_1 is electrically connected to the wiring WCL_1, the second terminal of the switch SA_1 is electrically connected to the circuit WCSa_1, and the control terminal of the switch SA_1 is electrically connected to the wiring SWLA. Similarly, the first terminal of the switch SA_n is electrically connected to the wiring WCL_n, the second terminal of the switch SA_n is electrically connected to the circuit WCSa_n, and the control terminal of the switch SA_n is electrically connected to the wiring SWLA.

[0209] As each of the switches SA_1 to SA_n, for example, an analog switch or an electric switch such as a transistor can be used. In particular, as each of the switches SA_1 to SA_n, it is preferable to use the above-mentioned transistor as the electric switch, and it is particularly preferable to use an OS transistor. Note that when an electric switch is used as each of the switches SA_1 to SA_n, as the electric switch, for example, a Si transistor can be used in addition to an OS transistor. In addition, as each of the switches SA_1 to SA_n, for example, a mechanical switch can also be used.

[0210] Note that in this specification, etc. Figure 6 Each of the switches SA_1 to SA_n shown is in an on state when a high-level potential is supplied to the control terminal and is in an off state when a low-level potential is supplied to the control terminal.

[0211] As an example, the wiring SWLA is used as a wiring for switching the on state and the off state of the switches SA_1 to SA_n. Therefore, the wiring SWLA is supplied with a high-level potential or a low-level potential.

[0212] As described above, the circuit SWCA is used as a circuit for bringing the circuit WCSa_1 and the wiring WCL_1 into a conductive state or a non-conductive state, and is used as a circuit for bringing the circuit WCSa_n and the wiring WCL_n into a conductive state or a non-conductive state.

[0213] In addition, the circuit WCSa_1 is electrically connected to the wiring IWL_1, and the circuit WCSa_n is electrically connected to the wiring IWL_n.

[0214] The circuit WCSa_1, for example, has a function of obtaining first data from the wiring IWL_1 and supplying a signal corresponding to the first data to the wiring WCL_1. Specifically, the circuit WCSa_1 supplies the first data to be accommodated in any one of the operation units IM[1, 1] to the operation unit IM[m, 1] configured in the first column of the cell array CA when the switch SA_1 is in an on state. Similarly, the circuit WCSa_n, for example, has a function of obtaining first data from the wiring IWL_n and supplying a signal corresponding to the first data to the wiring WCL_n. Specifically, the circuit WCSa_n supplies the first data to be accommodated in any one of the operation units IM[1, n] to the operation unit IM[m, n] configured in the nth column of the cell array CA when the switch SA_n is in an on state. Note that in Figure 6 In the cell array CA, the signal is preferably analog data (current amount).

[0215] For example, the circuit WCSa_j (j is an integer greater than or equal to 1 and less than or equal to n) may have Fig. 7A The structure shown. Note that Fig. 7A In FIG. 1 , in order to show the electrical connection between the circuit WCSa_j and its peripheral circuits, the circuit SWCA, the switch SA_j, the wiring SWLA, and the wiring WCL_j are also shown.

[0216] therefore, Fig. 7A The switch SA_j shown can be Figure 6 Similarly, the wiring WCL_j can be extended to be arranged at any one of the switches SA_1 to SA_n included in the circuit SWCA. Figure 6 Any one of the wirings WCL_1 to WCL_n in the cell array CA.

[0217] That is, the wiring WCL_j is electrically connected to the circuit WCSa_j through the switch SA_j.

[0218] Fig. 7A The circuit WCSa_j shown includes, for example, a switch SWW. The first terminal of the switch SWW is electrically connected to the second terminal of the switch SA_j, and the second terminal of the switch SWW is electrically connected to the wiring VINIL1. The wiring VINIL1 is used as a wiring for supplying a potential for initialization to the wiring WCL_j, and the potential for initialization may be a ground potential (GND), a low-level potential, or a high-level potential. Note that the switch SWW is in an on state only when the potential for initialization is supplied to the wiring WCL_j, and is in an off state otherwise.

[0219] As the switch SWW, for example, an electric switch (such as an analog switch or a transistor) can be used. In addition, when a transistor is used as the switch SWW, for example, the transistor can be a transistor having the same structure as the transistor F1 or the transistor F2. In addition, in addition to the electric switch, a mechanical switch can also be used.

[0220] Also, as an example, Fig. 7A The circuit WCSa_j includes a plurality of current sources CS. Specifically, the circuit WCSa_j has a M The first data output of the circuit WCSa_j is a function of the current value (M is an integer greater than 1). M -1 current source CS. The circuit WCSa_j includes, for example, one current source CS that outputs information corresponding to the value of the first bit as a current, two current sources CS that output information corresponding to the value of the second bit as a current, and 2 M-1 A current source CS outputs information corresponding to the value of the Mth bit as a current.

[0221] exist Fig. 7AIn the embodiment, each current source CS includes a terminal U1 and a terminal U2. The terminal U1 of each current source CS is electrically connected to the second terminal of the switch SA_j included in the circuit SWCA. In addition, the terminal U2 of one current source CS is electrically connected to the wiring DW[1], and the terminals U2 of two current sources CS are electrically connected to the wiring DW[2], respectively. K-1 The terminals U2 of the current sources CS are electrically connected to the wirings DW[M], respectively.

[0222] The multiple current sources CS in the circuit WCSa_j have the same amount I Wut Note that, in fact, in the manufacturing stage of the semiconductor device CDV, errors may occur due to fluctuations in the electrical characteristics of the transistors in each current source CS. Therefore, the amount of constant current I output by each terminal U1 of the multiple current sources CS is Wut The error of is preferably within 10%, more preferably within 5%, and further preferably within 1%. Note that in this embodiment, it is assumed that the amount of constant current I output from the terminal U1 of the plurality of current sources CS in the circuit WCSa_j is Wut There is no error between them.

[0223] The wiring DW[1] to the wiring DW[M] correspond to the above-mentioned wiring IWL_j and are used as wiring for obtaining the first data as digital data from the outside. Specifically, the wiring DW[1] to the wiring DW[M] are used to transmit the current source CS electrically connected to them to output I Wut For example, when the wiring DW[1] is supplied with a high-level potential, the current source CS electrically connected to the wiring DW[1] makes I Wut The current flows through the second terminal of the switch SA_j. When the wiring DW[1] is supplied with a low-level potential, the current source CS electrically connected to the wiring DW[1] does not output I Wut For example, when the wiring DW[2] is supplied with a high-level potential, the two current sources CS electrically connected to the wiring DW[2] make a total of 2I Wut A constant current flows through the second terminal of the switch SA_j, and when the wiring DW[2] is supplied with a low-level potential, the current source CS electrically connected to the wiring DW[2] does not output a total of 2I Wut For example, when the wiring DW[M] is supplied with a high-level potential, the 2 M-1 The current source CS makes a total of 2 M-1 I Wut A constant current flows through the second terminal of the switch SA_j, and when the wiring DW[M] is supplied with a low-level potential, the current source CS electrically connected to the wiring DW[M] does not output a total of 2 M-1 I Wut of constant current.

[0224] The current supplied by one current source CS electrically connected to the wiring DW[1] corresponds to the value of the first bit, the current supplied by two current sources CS electrically connected to the wiring DW[2] corresponds to the value of the second bit, and the current supplied by two current sources CS electrically connected to the wiring DW[M] corresponds to the value of the second bit. M-1 The current supplied by the current source CS is equivalent to the value of the Mth bit. Here, consider the circuit WCSa_j when M is 2. For example, when the value of the first bit is "1" and the value of the second bit is "0", the wiring DW[1] is supplied with a high level potential and the wiring DW[2] is supplied with a low level potential. At this time, as a constant current, I Wut Flows from the circuit WCSa_j to the second terminal of the switch SA_j of the circuit SWCA. In addition, for example, when the value of the first bit is "0" and the value of the second bit is "1", the wiring DW[1] is supplied with a low level potential and the wiring DW[2] is supplied with a high level potential. At this time, as a constant current, 2I Wut Flows from the circuit WCSa_j to the second terminal of the switch SA_j of the circuit SWCA. For example, when the value of the first bit is "1" and the value of the second bit is "1", the wiring DW[1] and the wiring DW[2] are supplied with a high level potential. At this time, as a constant current, 3I Wut The constant current flows from the circuit WCSa_j to the second terminal of the switch SA_j of the circuit SWCA. In addition, for example, when the value of the first bit is "0" and the value of the second bit is "0", the wiring DW[1] and the wiring DW[2] are supplied with a low-level potential. At this time, the constant current does not flow from the circuit WCSa to the second terminal of the switch SA_j of the circuit SWCA.

[0225] Notice, Fig. 7A The circuit WCSa_j is shown when M is an integer greater than 3, but when M is 1, Fig. 7A The circuit WCSa_j may be configured without providing a current source CS electrically connected to the wiring DW[2] to the wiring DW[M]. In addition, when M is 2, Fig. 7A The circuit WCSa_j may be configured such that the current source CS electrically connected from the wiring DW[3] (not shown) to the wiring DW[M] is not provided.

[0226] Next, a specific configuration example of the current source CS will be described.

[0227] Fig. 8A The current source CS1 shown is applicable to Fig. 7A In the circuit WCSa, the current source CS1 includes a transistor Tr1 and a transistor Tr2.

[0228] The first terminal of transistor Tr1 is electrically connected to wiring VDDL, and the second terminal of transistor Tr1 is electrically connected to the gate of transistor Tr1, the back gate of transistor Tr1, and the first terminal of transistor Tr2. The second terminal of transistor Tr2 is electrically connected to terminal U1, and the gate of transistor Tr2 is electrically connected to terminal U2. In addition, terminal U2 is electrically connected to wiring DW.

[0229] Wiring DW is Fig. 7A Any one of the wiring DW[1] to the wiring DW[M].

[0230] The wiring VDDL is used as a wiring for supplying a fixed potential. The fixed potential may be, for example, a high-level potential.

[0231] When the fixed potential supplied by the wiring VDDL is set to a high-level potential, a high-level potential is input to the first terminal of the transistor Tr1. In addition, the potential of the second terminal of the transistor Tr1 is set to a potential lower than the high-level potential. At this time, the first terminal of the transistor Tr1 is used as a drain, and the second terminal of the transistor Tr1 is used as a source. In addition, the gate of the transistor Tr1 and the second terminal of the transistor Tr1 are electrically connected, so the voltage between the gate and the source of the transistor Tr1 is 0V. Therefore, when the threshold voltage of the transistor Tr1 is within an appropriate range, a current (drain current) in the current range of the subthreshold region flows between the first terminal and the second terminal of the transistor Tr1. In the case where the transistor Tr1 is an OS transistor, the amount of current is preferably, for example, 1.0×10 -8 A or less, more preferably 1.0×10 -12 A is less than or equal to 1.0×10 -15 A or less. In addition, for example, the current is more preferably in a range that increases exponentially with respect to the voltage between the gate and the source. That is, the transistor Tr1 is used as a current source that allows a current in the current range when operating in the subthreshold region to flow. This current is equivalent to the above-mentioned I Wut Or the following I Xut .

[0232] Transistor Tr2 is used as a switching element. In addition, when the potential of the first terminal of transistor Tr2 is higher than the potential of the second terminal of transistor Tr2, the first terminal of transistor Tr2 is used as a drain, and the second terminal of transistor Tr2 is used as a source. In addition, the back gate of transistor Tr2 and the second terminal of transistor Tr2 are electrically connected, so the voltage between the back gate and the source is 0V. Therefore, when the threshold voltage of transistor Tr2 is within an appropriate range, transistor Tr2 is in an open state when a high level potential is input to the gate of transistor Tr2, and transistor Tr2 is in a closed state when a low level potential is input to the gate of transistor Tr2. Specifically, when transistor Tr2 is in an open state, the current in the current range of the above-mentioned subthreshold region flows from the second terminal of transistor Tr1 to terminal U1, and when transistor Tr2 is in a closed state, the current does not flow from the second terminal of transistor Tr1 to terminal U1.

[0233] Note that it can be used Fig. 7A The circuit of the current source CS in the circuit WCSa_j is not limited to Fig. 8A For example, the current source CS1 has a structure in which the back gate of the transistor Tr2 and the second terminal of the transistor Tr2 are electrically connected, but a structure in which the back gate of the transistor Tr2 is electrically connected to other wiring may also be adopted. Figure 8B An example of such a structure is shown. Figure 8B The current source CS2 shown has a structure in which the back gate of the transistor Tr2 is electrically connected to the wiring VTHL. In the current source CS2, since the wiring VTHL is electrically connected to an external circuit, etc., the external circuit can be used to supply a predetermined potential to the wiring VTHL to supply the predetermined potential to the back gate of the transistor Tr2. As a result, the threshold voltage of the transistor Tr2 can be changed. In particular, by increasing the threshold voltage of the transistor Tr2, the off-state current of the transistor Tr2 can be reduced.

[0234] In addition, for example, the current source CS1 has a structure in which the back gate of the transistor Tr1 and the second terminal of the transistor Tr1 are electrically connected, but a structure in which the voltage between the back gate and the second terminal of the transistor Tr2 is held by a capacitor may be adopted. Figure 8C An example of such a structure is shown. Figure 8CThe current source CS3 shown includes a transistor Tr3 and a capacitor C7 in addition to the transistor Tr1 and the transistor Tr2. The current source CS3 is different from the current source CS1 in that the second terminal of the transistor Tr1 is electrically connected to the back gate of the transistor Tr1 through the capacitor C7; and the back gate of the transistor Tr1 is electrically connected to the first terminal of the transistor Tr3. In addition, the current source CS3 has a structure in which the second terminal of the transistor Tr3 is electrically connected to the wiring VTL and the gate of the transistor Tr3 is electrically connected to the wiring VWL. In the current source CS3, by supplying a high level potential to the wiring VWL to turn on the transistor Tr3, the wiring VTL and the back gate of the transistor Tr1 can be turned on. At this time, a predetermined potential can be input from the wiring VTL to the back gate of the transistor Tr1. And, by supplying a low level potential to the wiring VWL to turn off the transistor Tr3, the voltage between the second terminal of the transistor Tr1 and the back gate of the transistor Tr1 can be maintained by the capacitor C7. That is, by determining the voltage supplied to the back gate of the transistor Tr1 by the wiring VTL, the threshold voltage of the transistor Tr1 can be changed, and the threshold voltage of the transistor Tr1 can be fixed by the transistor Tr3 and the capacitor C7.

[0235] In addition, for example, it can be used Fig. 7A The circuit structure of the current source CS in the circuit WCSa_j can also be Fig.8D The current source CS4 is shown. The current source CS4 has a Figure 8C The back gate of the transistor Tr2 in the current source CS3 is electrically connected to the wiring VTHL but not electrically connected to the second terminal of the transistor Tr2. Figure 8B Similarly to the current source CS2, the current source CS4 can change the threshold voltage of the transistor Tr2 according to the potential supplied by the wiring VTHL.

[0236] In the current source CS4, when a large current flows between the first terminal and the second terminal of the transistor Tr1, in order to make the current flow from the terminal U1 to the outside of the current source CS4, it is necessary to increase the on-state current of the transistor Tr2. In this case, in the current source CS4, by supplying a high-level potential to the wiring VTHL, the threshold voltage of the transistor Tr2 is reduced and the on-state current of the transistor Tr2 is increased, so that the large current flowing between the first terminal and the second terminal of the transistor Tr1 can flow from the terminal U1 to the outside of the current source CS4.

[0237] By Fig. 7A The current source CS in the circuit WCSa_j is used as FIG. 8A to FIG. 8DThe circuit WCSa can output a current corresponding to the M-bit first data by any of the current sources CS1 to CS4 shown. In addition, the current amount can be, for example, the current amount flowing between the first terminal and the second terminal when the transistor F1 operates in the subthreshold region.

[0238] In addition, as Fig. 7A The circuit WCSa_j can also be used Figure 7B The circuit shown is WCSa_j. Figure 7B The circuit WCSa_j has wiring DW[1] to wiring DW[M], each of which is connected to a Fig. 8A In addition, when the channel width of transistor Tr1[1] is w[1], the channel width of transistor Tr1[2] is w[2], and the channel width of transistor Tr1[M] is w[M], the ratio of the channel widths is w[1]:w[2]:w[M]=1:2:2 M-1 The current flowing between the source and drain of a transistor operating in the subthreshold region is proportional to the channel width and is therefore Fig. 7A The circuit WCSa is similar, Figure 7B The illustrated circuit WCSa_j may output a current corresponding to M bits of first data.

[0239] Note that transistors that can be used for transistor F1 or transistor F2 can be used as transistor Tr1 (including transistor Tr1[1] to transistor Tr1[M]), transistor Tr2 (including transistor Tr2[1] to transistor Tr2[M]), and transistor Tr3, for example. In particular, it is preferable to use OS transistors as transistor Tr1 (including transistor Tr1[1] to transistor Tr1[M]), transistor Tr2 (including transistor Tr2[1] to transistor Tr2[M]), and transistor Tr3.

[0240] [Circuit XCS] The circuit XCS has the following functions, for example: obtaining the second data as digital data from the memory circuit unit ME11, converting the second data into analog data (current amount), and supplying the second data to the operation units included in the cell array CA. For example, when the circuit XCS supplies the second data to the operation units IM[1,1] to IM[1,n] in the first row of the cell array CA, the circuit XCS supplies the second data to the operation units in the first row of the cell array CA through the wiring XCL_1.

[0241] The circuit XCS includes, for example, a circuit XCSa_1 to a circuit XCSa_m.

[0242] Furthermore, the circuit XCSa_1 is electrically connected to the wiring IXL_1, and the circuit XCSa_m is electrically connected to the wiring IXL_m.

[0243] Each of the wirings IXL_1 to IXL_m is used as a wiring for transmitting second data which is digital data from the memory circuit part ME11 to each of the circuits XCSa_1 to XCSa_m.

[0244] Each of the circuits XCSa_1 to XCSa_m has, for example, a function of obtaining reference data described later from each of the wirings IXL_1 to IXL_m and supplying a signal corresponding to the reference data to the wirings XCL_1 to XCL_m. Alternatively, each of the circuits XCSa_1 to XCSa_m has, for example, a function of obtaining second data from each of the wirings IXL_1 to IXL_m and supplying a signal corresponding to the second data. Note that Figure 6 In the cell array CA, each of the above-mentioned signals is preferably analog data (current amount).

[0245] Figure 7C It is shown that it can be used Figure 6 A block diagram of an example of a circuit XCSa_i (i is an integer greater than 1 and less than m) of a circuit XCS. Note that Figure 7C The circuit XCSa_i corresponding to any one of the circuits XCSa_1 to XCSa_m is shown in the abstract. Figure 7C In FIG. 1 , a wiring XCL_i is also shown to show the electrical connection between the circuit XCS and its surrounding circuits. Therefore, the wiring XCL_i is electrically connected to the circuit XCSa_i.

[0246] Figure 7C The circuit XCSa_i shown includes, for example, a switch SWX. A first terminal of the switch SWX is electrically connected to the wiring XCL_i, and a second terminal of the switch SWX is electrically connected to the wiring VINIL2. The wiring VINIL2 is used as a wiring for supplying a potential for initialization to the wiring XCL_i, and the potential for initialization may be a ground potential (GND), a low-level potential, or a high-level potential. In addition, the potential for initialization supplied by the wiring VINIL2 may be equal to the potential supplied by the wiring VINIL1. Note that the switch SWX is in an open state only when the potential for initialization is supplied to the wiring XCL_i, and is in a closed state otherwise.

[0247] The switch SWX may be, for example, a switch that can be used for the switch SWW.

[0248] in addition, Figure 7C The circuit structure of the circuit XCSa_i can be adopted with Fig. 7A Specifically, the circuit XCSa_i has a function of outputting reference data as a current and a function of outputting L bits (2L The second data output of the circuit XCSa_i is a function of the current amount. L -1 current source CS. The circuit XCSa_i includes one current source CS that outputs information corresponding to the value of the first bit as a current, two current sources CS that output information corresponding to the value of the second bit as a current, and 2 L-1 A current source CS outputs information corresponding to the value of the Lth bit as a current.

[0249] In addition, as reference data that the circuit XCSa_i outputs as current, for example, information that the value of the first bit is "1" and the values ​​of the second bit and subsequent bits are "0" may be used.

[0250] exist Figure 7C In the example, the terminal U2 of one current source CS is electrically connected to the wiring DX[1], and the terminals U2 of the two current sources CS are electrically connected to the wiring DX[2], respectively. L-1 The terminals U2 of the current sources CS are electrically connected to the wiring DX[L], respectively.

[0251] The multiple current sources CS in the circuit XCSa_i have the same quantity I Xut The constant current is output from terminal U1. Xut In addition, the wiring DX[1] to the wiring DX[L] are equivalent to the above-mentioned wiring IXL_i, and are used as wiring to obtain reference data or second data as digital data from the outside. Specifically, the wiring DX[1] to the wiring DX[L] are used to transmit the current source CS electrically connected to them to output I Xut That is, the circuit XCSa_i has a function of causing a current amount corresponding to L bits of information transmitted from the wiring DX[1] to the wiring DX[L] to flow through the wiring IXL_i.

[0252] Specifically, consider the circuit XCSa_i when L is 2. For example, when the value of the first bit is "1" and the value of the second bit is "0", the wiring DX[1] is supplied with a high level potential and the wiring DX[2] is supplied with a low level potential. At this time, as a constant current, I Xut Flows from the circuit XCSa_i to the wiring XCL_i. In addition, for example, when the value of the first bit is "0" and the value of the second bit is "1", the wiring DX[1] is supplied with a low level potential and the wiring DX[2] is supplied with a high level potential. At this time, as a constant current, 2I Xut Flows from the circuit XCSa_i to the wiring XCL_i. For example, when the value of the first bit is "1" and the value of the second bit is "1", the wiring DX[1] and the wiring DX[2] are supplied with a high level potential. At this time, 3I XutFlows from the circuit XCSa_i to the wiring XCL_i. In addition, for example, when the value of the first bit is "0" and the value of the second bit is "0", the wiring DX[1] and the wiring DX[2] are supplied with a low level potential. At this time, the constant current does not flow from the circuit XCSa_i to the wiring XCL_i. Note that at this time, in this specification, etc., it is sometimes recorded that the current with a current amount of 0 flows from the circuit XCSa_i to the wiring XCL_i. In addition, the current amounts 0 and I output by the circuit XCSa_i are Xut , 2I Xut 、3I Xut The second data output by the circuit XCSa_i may be, in particular, the current I output by the circuit XCSa_i. Xut It can be the reference data output by the circuit XCSa_i.

[0253] When an error occurs due to fluctuations in the electrical characteristics of the transistors in each current source CS of the circuit XCSa_i, the amount of constant current I outputted from each terminal U1 of the plurality of current sources CS is Xut The error is preferably within 10%, more preferably within 5%, and further preferably within 1%. Note that in this embodiment, it is assumed that the amount of constant current I output from the terminal U1 of the plurality of current sources CS in the circuit XCSa_i is Xut The description is given without any error.

[0254] In addition, similarly to the current source CS of the circuit WCSa_j, the current source CS of the circuit XCSa_i can be used. FIG. 8A to FIG. 8D In this case, the wiring DX[1] to the wiring DX[L] can be used instead of any one of the current sources CS1 to CS4. FIG. 8A to FIG. 8D The wiring DW[1] to the wiring DW[M] are shown. Thus, the circuit XCSa_i can make a current in a current range of a subthreshold region flow through the wiring XCL_i as reference data or L-bit second data.

[0255] in addition, Figure 7C The circuit XCSa_i can be used with Figure 7B The circuit structure is the same as the circuit WCSa_j shown in the figure. In this case, the circuit XCSa_i is used instead. Figure 7B The circuit WCSa_j shown can be considered by replacing the wiring IWL_j with the wiring IXL_i, the wiring DW[1] with the wiring DX[1], the wiring DW[2] with the wiring DX[2], the wiring DW[M] with the wiring DX[L], the switch SWW with the switch SWX, and the wiring VINIL1 with the wiring VINIL2.

[0256] [Circuit ITS] The circuit ITS includes, for example, a function-based (e.g., nonlinear function-based) operation circuit and an analog-to-digital conversion circuit. In particular, the function-based operation circuit preferably has the following functions: performing a function-based operation with a value corresponding to the input current as an input value, and outputting digital data (voltage) corresponding to the result of the operation.

[0257] Fig. 9A A circuit configuration example of the circuit ITS is shown. Fig. 9A The circuit shown in ITS is available for Figure 1 and Figure 6 The circuit shown is an example of an ITS circuit. Note that Fig. 9A In order to show the electrical connection between the circuit ITS and its surrounding circuits, the wiring WCL_j is also shown. Figure 1 and Figure 6 Any of the wirings WCL_1 to WCL_n shown, the switch SB_j is Figure 6 The circuit SWCB shown includes any one of the switches SB_1 to SB_n.

[0258] As the switch SB_j, for example, a Figure 6 The switches SA_1 to SA_n are shown as switches. For example, the switch SB_j may use an electrical switch or a mechanical switch.

[0259] Fig. 9A The circuit ITS includes the circuit SWCB, the circuit ITSa_1 to the circuit ITSa_n. Note that Fig. 9A The circuit ITSa_j is shown as any one of the circuits ITSa_1 to ITSa_n. The circuit ITSa_j includes a conversion circuit RL_j and an analog-to-digital conversion circuit ADC.

[0260] In addition, the conversion circuit RL_j includes a terminal RTi_j and a terminal RTo_j.

[0261] The first terminal of the switch SB_j is electrically connected to the wiring WCL_j, the second terminal of the switch SB_j is electrically connected to the terminal RTi_j of the conversion circuit RL_j, and the control terminal of the switch SB_j is electrically connected to the wiring SWLB. In addition, the terminal RTo_j of the conversion circuit RL_j is electrically connected to the input terminal of the analog-to-digital conversion circuit ADC, and the output terminal of the analog-to-digital conversion circuit ADC is electrically connected to the wiring OL_j.

[0262] As an example, the wiring SWLB is used as a wiring for switching the on state and the off state of the switches SB_1 to SB_n. Therefore, the wiring SWLB is supplied with a high-level potential or a low-level potential.

[0263] Wiring OL_j( Figure 1 The wiring OL_1 to the wiring OL_n in the semiconductor device CDV are used as wiring for outputting the calculation result in the semiconductor device CDV to the memory circuit portion ME11 as digital data.

[0264] The conversion circuit RL_j may be the above-mentioned function-type operation circuit. As the function-type operation circuit, for example, an operation circuit of a nonlinear function such as a sigmoid function, a tanh function, a softmax function, a ReLU function, or a threshold function may be used. In addition, the conversion circuit RL_j may not include a function-type operation circuit but include a circuit for performing pooling processing. In addition, when using Fig. 9A In the case of a structure of, the conversion circuit RL_j preferably outputs a voltage from the terminal RTo_j.

[0265] In addition, the conversion circuit RL_j may also be a current-voltage conversion circuit.

[0266] When the conversion circuit RL_j is a current-voltage conversion circuit, it is preferred that, for example, the conversion circuit RL_j generates an analog voltage corresponding to the current input from the wiring WCL_j to the terminal RTi_j of the conversion circuit RL_j through the switch SB_j, and outputs it to the terminal RTo_j of the conversion circuit RL_j.

[0267] In addition, the analog-to-digital conversion circuit ADC preferably converts an analog voltage supplied from the terminal RTo_j of the conversion circuit RL_j into a digital signal and outputs it to the wiring OL_j.

[0268] in addition, Fig. 9B A configuration example of a circuit ITS when the conversion circuit RL_j is a current-voltage conversion circuit is shown. Fig. 9B The conversion circuit RL_j shown includes, for example, a load LE and an operational amplifier OP.

[0269] The inverting input terminal of the operational amplifier OP is electrically connected to the first terminal of the load LE and the second terminal of the switch SB_j. The non-inverting input terminal of the operational amplifier OP is electrically connected to the wiring VRL. The output terminal of the operational amplifier OP is electrically connected to the second terminal of the load LE and the terminal RTo_j.

[0270] The wiring VRL is used as a wiring for supplying a fixed potential. The fixed potential may be, for example, a ground potential (GND), a low-level potential, or the like.

[0271] In particular, when the fixed potential supplied by the wiring VRL is the ground potential (GND), the inverting input terminal of the operational amplifier OP is virtually grounded, so the analog voltage output to the wiring OL_j can be a voltage based on the ground potential (GND).

[0272] When the circuit ITS has Fig. 9B When the structure is configured, a value corresponding to the amount of current flowing from the wiring WCL_j through the switch SB_j to the terminal RTi_j of the conversion circuit RL_j can be output as an analog voltage to the terminal RTo_j. In addition, the analog voltage can be converted into a digital signal by the analog-to-digital conversion circuit ADC and output to the wiring OL_j.

[0273] Note that in the case where an analog voltage instead of a digital signal is output from the circuit ITS to the wiring OL_j, as shown in FIG. Fig. 9C As in the circuit ITS shown in FIG. 1 , the analog-to-digital conversion circuit ADC may not be provided in the circuit ITSa_j. Fig. 9C In the embodiment, it is preferable that the conversion circuit RL_j performs a function-type operation with a value corresponding to the amount of current flowing through the terminal RTi_j as an input value, and outputs the operation result as an analog current to the terminal RTo_j. At this time, for example, when the operation result of the circuit ITS is not stored in the storage circuit unit ME11 but is directly input to the analog operation circuit that performs the operation of the next fully connected layer, Fig. 9C The circuit ITS shown is effective.

[0274] <Operation Example of Semiconductor Device> The following instructions Figure 1 Note that the switching circuit D10 and the operation circuit D20 included in the semiconductor device CDV adopt Figure 3A The structure shown.

[0275] Here, the description is Fig.10 The operation of the semiconductor device CDV shown in the AlexNet operation. Fig.10 AlexNet includes input layer INLY, convolutional layers CNV1 to CNV5, pooling layers PL1, PL2, PL5, and fully connected layers FC6 to FC8. Fig.10 AlexNet is composed of input layer INLY, convolution layer CNV1, pooling layer PL1, convolution layer CNV2, pooling layer PL2, convolution layer CNV3, convolution layer CNV4, convolution layer CNV5, pooling layer PL5, fully connected layer FC6, fully connected layer FC7 and fully connected layer FC8.

[0276] [Input layer INLY] In the work of the input layer INLY, Figure 1 For example, the semiconductor device CDV is input with an image P of 224×224 pixels. in Note that one pixel includes red, green, and blue sub-pixels, and the total number of sub-pixels is three colors (red, green, and blue) × 224 × 224. In addition, the image Pin The number of channels of image P is three: red, green and blue. in The number of included image data input to the semiconductor device CDV is 3×224×224.

[0277] exist Figure 1 In the semiconductor device CDV, the wiring ILA is input into the image P in Therefore, the image P is input to the input terminal TM1i of the switching circuit D10 of the calculation unit DGP. in .

[0278] Note that in this working example, the image P in The input value of the xth row and yth column included in the zth (where z is an integer greater than or equal to 1 and less than or equal to 3) input channel in the input channel is recorded as p in [x, y, z]. Note that x represents the image P in The row address of image P in In other words, in the input layer INLY, x is an integer greater than 1 and less than 224, and y is an integer greater than 1 and less than 224.

[0279] [Convolutional layer CNV1] In the convolution layer CNV1, the image P is processed by the operation circuit D20. in Specifically, the filter (also called convolution kernel) used for convolution processing CNV1 is convolved with the image P in Area A in Includes sum-of-product operations on image data.

[0280] In the convolution layer CNV1, the filter size (also called the convolution kernel size) is set to 11, the number of output channels (also called the number of convolution kernels) is set to 96, the step size is set to 4, and the selected image P is in In addition, the number of filter values ​​in a convolution kernel is (filter size) 2 × (number of input channels). Since the image P in The number of input channels is 3, so the number of filter values ​​of a convolution kernel in the convolution layer CNV1 is 11×11×3.

[0281] Here, the sth (here, s is an integer greater than or equal to 1 and less than or equal to 96) convolution kernel in the convolution layer CNV1 is denoted by K C1 (s) In addition, the convolution kernel K C1 The included filter value is recorded as k C1 (s)[p, q, r]. Note that p represents the row address of the convolution kernel, q represents the column address of the convolution kernel, and r represents the ordinal number of the input channel. In other words, in the convolution layer CNV1, p is an integer greater than 1 and less than 11, q is an integer greater than 1 and less than 11, and r is an integer greater than 1 and less than 3.

[0282] For example, Fig.11 Shown is a selection from image P in Area A in (1) With convolution kernel K C1 (1) The product and sum operation is performed and the data p as the operation result is output C1 (1) Example (1). Area A in (x) where x is selected from the image P in In addition, the data p C1 (s) (x) s represents the ordinal number of the output channel. In addition, data p C1 (s) (x) where x corresponds to region A in The ordinal number x of (x).

[0283] In addition, since the step size is 4, the in (1) The area that drifts 4 degrees in the row direction is called area A in (2). For example, Fig.12 Shown is a selection from image P in Area A in (2) With convolution kernel K C1 (1) The product and sum operation is performed and the data p as the operation result is output C1 (1) (2) Example.

[0284] Note that in image P in When the number of pixels is 224×224 and the step size is 4, the image P is selected in The number of regions is 3025 (= 55 2 ). In addition, in this embodiment, they are respectively referred to as area A in (1) To Area A in (3025).

[0285] As described above, the selected image P is sequentially set according to the number of steps. in The region drifts, and each time the region is drifted, the region and the convolution kernel K are combined. C1 (1) The product and sum operation can obtain the matrix output data with 55 rows and 55 columns. In addition, the convolution kernel in the convolution layer CNV1 is the convolution kernel K C1(1) To convolution kernel K C1 (96) (The number of convolution kernels in convolution layer CNV1 is 96), so the result is that the output data P of 55×55×96 is output from convolution layer CNV1. C1 .

[0286] Here, in the convolution process of the convolution layer CNV1, a convolution kernel is subjected to the convolution operation with the image P in Therefore, as a structure of the operation circuit, for example, it is preferable to perform the product sum operation of the filter value included in one convolution kernel and the filter value from the image P together. in The product of the data included in each of the selected multiple regions is calculated.

[0287] For example, preferably, Figure 1 In the structure of the semiconductor device CDV shown in FIG. 3, region A in The data included in (1) is sent to the input terminal TN1i (wiring MLA_1) of the operation circuit D20_1, and the area A in The data included in (2) is sent to the input terminal TN1i (wiring MLA_2) of the operation circuit D20_2 (not shown), and the area A in The data included in (3) is sent to the input terminal TN1i (wiring MLA_3) of the operation circuit D20_3 (not shown). in The data included in (3025) is preferably sent to the wiring MLA_3025. Note that at this time, k of the wiring MLA_k and the operation circuit D20_k shown in FIG3 is preferably 3025 or more.

[0288] Fig.13 The timing diagram shows the specific order in which each data is sent. Fig.13 It is a timing diagram showing data input to wiring MLA_1 to wiring MLA_3 (input terminal TN1i of operation circuit D20) from time T01 to time T04 and its vicinity, filtered values ​​input to wiring MLB (input terminal TN2i of operation circuit D20), and data output to wiring CNL_1 to wiring CNL_3 (output terminal TNo of operation circuit D20).

[0289] First, consider the period from time T01 to time T02. When the convolution kernel K is input to the wiring MLB C1 (1) The filter value k C1 (1) [1, 1, 1] (i.e., the filter value k is read from the storage circuit unit ME12). C1 (1) [1, 1, 1]), it is preferred to input p to the wiring MLA_1in [1, 1, 1], input p to wiring MLA_2 in [1, 5, 1], input p to wiring MLA_3 in [1, 9, 1] In addition, it is preferable that when the filter value input to the wiring MLB is from k C1 (1) [1, 1, 1] becomes k C1 (1) [1, 2, 1] (i.e., the filter value k is read from the storage circuit unit ME12). C1 (1) [1, 2, 1]), the wiring MLA_1 is input to p in [1, 2, 1], wiring MLA_2 is input to p in [1, 6, 1], wiring MLA_3 is input to p in [1, 10, 1].

[0290] Thus, in area A in (1) To Area A in Each of the data included in (3025) is related to the convolution kernel K C1 (1) When the calculation of the product of the included filter values ​​is completed, the calculation circuit D20_1 outputs the area A to the wiring CNL_1. in (1) With convolution kernel K C1 (1) The product of the sum of the p C1 (1) (1) In addition, the operation circuit D20_2 outputs the area A to the wiring CNL_2. in (2) With convolution kernel K C1 (1) The product of the sum of the p C1 (1) (2) In addition, the operation circuit D20_3 outputs the wiring CNL_3 as the area A in (3) and convolution kernel K C1 (1) The product of the sum of the p C1 (1) (3).

[0291] In addition, the p-type signals output to the wirings CNL_1 to CNL_3025 are C1 (1) (1) to p C1 (1) (3025) is written into the storage circuit unit ME11.

[0292] During the period from time T02 to time T03, the convolution kernel K is used in the same manner as during the period from time T01 to time T02.C1 (2) Conduct Area A in (1) To Area A in (3025) each convolution processing. At this time, the obtained data (for example, p C1 (2) (1) to p C1 (2) (3025)) is written into the storage circuit unit ME11.

[0293] In addition, at the end of the convolution kernel K C1 (2) After the convolution process, the convolution kernel is changed to convolution kernel K C1 (3) To convolution kernel K C1 (95) , use each convolution kernel to perform region A in (1) To Area A in (3025) each convolution processing. In addition, in the convolution kernel K C1 (3) To convolution kernel K C1 (95) In each of the wirings CNL_1 to CNL_3025, data outputted from the wirings CNL_1 to CNL_3025 are written into the memory circuit portion ME11 in the same manner as described above.

[0294] During the period from time T03 to time T04, the convolution kernel K is used in the same manner as during the period from time T01 to time T02. C1 (96) Conduct Area A in (1) To Area A in (3025) each convolution processing. Then, in the area A in (1) To Area A in Each of the data included in (3025) is related to the convolution kernel K C1 (96) When the calculation of the product of the included filter values ​​is completed, the calculation circuit D20_1 outputs the area A to the wiring CNL_1. in (1) With convolution kernel K C1 (96) The product of the sum of the p C1 (96) (1) In addition, the operation circuit D20_2 outputs the area A to the wiring CNL_2. in (2) With convolution kernel K C1 (96) The product of the sum of the p C1 (96) (2) In addition, the operation circuit D20_3 outputs the wiring CNL_3 as the area A in(3) and convolution kernel K C1 (96) The product of the sum of the p C1 (96) (3).

[0295] In addition, the p-type signals output to the wirings CNL_1 to CNL_3025 are C1 (96) (1) to p C1 (96) (3025) is written into the storage circuit unit ME11.

[0296] like Fig.13 As shown in the timing diagram, by sequentially sending the data included in the area corresponding to each of the multiple first terminals of the operation circuit D20 and sequentially sending the filter value included in the convolution kernel to the second terminal of the operation circuit D20, the operation circuit D20 can simultaneously perform multiple areas (the above-mentioned area A in (1) To Area A in (3025)) of each convolution process. In addition, by switching the convolution kernel in sequence and repeating the same operation, P as the output data from the convolution layer CNV1 can be obtained. C1 .

[0297] [Pooling layer PL1] In the pooling layer PL1, P which is the output data from the convolutional layer CNV1 is C1 Pooling processing is performed. Pooling processing is a process of sequentially selecting predetermined regions in data output from a convolutional layer or the like, performing predetermined processing on each region to extract feature quantities, and arranging the feature quantities in a matrix form.

[0298] like Fig.10 As shown, in the pooling layer PL1, the convolution kernel size is 3 for the data P C1 Each selected region is pooled. Note that the step size is 2 and the pooling process is maximum pooling.

[0299] For example, Fig.14A Shown in the selected data P C1 Area A of the first input channel C1in (1) (1) performs maximum pooling processing and outputs the data p as the processing result p1 (1) (1) is an example. In addition, since the convolution kernel size is 3, area A C1in (1) (1) Includes 3×3 data.

[0300] Note that area A C1in (s)(A) s represents data P C1 The ordinal number of the input channel, region A C1in (s) A in (A) represents a selection from data P C1 The ordinal number of the region, data p p1 (s) (A) s represents the ordinal number of the output channel, data p p1 (s) The A in (A) corresponds to area A C1in (s) (A)’s ordinal number A.

[0301] In addition, since the step size is 2, from area A C1in (1) (1) The area that drifts 2 degrees in the row direction is area A C1in (1) (2). For example, Fig. 14B Shows the selected data P C1 Area A C1in (1) (2) Perform maximum pooling processing and output the data p as the processing result p1 (1) (2) Example.

[0302] Note that in data P C1 When the number is 55×55×96 and the step size is 2, the data P is selected C1 The number of regions is 729 (= 27 2 ).

[0303] As described above, by sequentially selecting the data P according to the number of steps C1 The area of ​​​​the pooling process can be obtained by obtaining a matrix output data of 27 rows and 27 columns. In addition, although the data P C1 However, by similarly performing pooling processing on the second to 96th input channels, the result is that the output from the pooling layer PL1 is P as 27×27×96 output data. P1 .

[0304] exist Figure 1 In the operation of the semiconductor device CDV shown in FIG. 1 , for example, P which is output data of the convolutional layer CNV1 is read from the storage circuit unit ME11. C1 , the processing circuit D30 can perform the pooling process. In addition, the processing circuit D30 outputs the data P as the processing result when the pooling process is completed. P1 In addition, the data P output from the processing circuit D30 P1 The data is written into the memory circuit unit ME11.

[0305] [Convolutional layer CNV2] In the convolutional layer CNV2, the data P output by the pooling layer PL1 is P1 Specifically, the convolution kernel for convolution processing CNV2 and the convolution kernel selected from P are used to perform convolution processing. P1 The product and sum operation of the data included in the area.

[0306] like Fig.10 As shown, in the convolution layer CNV2, the convolution kernel size is 5 and the number of convolution kernels is 256. P1 The convolution operation is performed on the region of . Note that the stride is 1.

[0307] As described in the convolution layer CNV1, by performing convolution processing in the convolution layer CNV2, the convolution layer CNV2 outputs P as output data of 27×27×256. C2 .

[0308] exist Figure 1 In the operation of the semiconductor device CDV shown in FIG. 1 , for example, P is read as output data of the pooling layer PL1 from the storage circuit portion ME11. P1 Then, the signal input to the wiring ILB is switched in the switching circuit D10 so as to be sent to the wirings MLA_1 to MLA_p, and the input signals P are input to the plurality of input terminals of the operation circuit D20. P1 That's it.

[0309] In addition, similarly to the convolution layer CNV1, the 256 convolution kernels of the convolution layer CNV2 are sequentially read out from the storage circuit unit ME12 and P is performed in the operation circuit D20. P1 Thus, the data P output from the operation circuit D20 is C2 The data is written into the memory circuit unit ME11.

[0310] [Pooling layer PL2] In the pooling layer PL2, P which is the output data from the convolutional layer CNV2 is C2 Perform pooling.

[0311] like Fig.10 As shown, in the pooling layer PL2, the convolution kernel size is 3 for the data P C2 Each selected region is pooled. Note that the step size is 2 and the pooling process is maximum pooling.

[0312] As described in the pooling layer PL1, the pooling process is performed in the pooling layer PL2, and the output data P of 13×13×256 is output from the pooling layer PL2. P2 .

[0313] In addition, the pooling layer PL2 Figure 1 The operation of the semiconductor device CDV shown can refer to the description of the operation of the semiconductor device CDV in the pooling layer PL1.

[0314] [Convolutional layer CNV3] In the convolution layer CNV3, the data P output by the pooling layer PL2 is P2 Specifically, the convolution kernel for convolution processing CNV3 and the convolution kernel selected from P are used to perform convolution processing. P2 The product and sum operation of the data included in the area.

[0315] like Fig.10 As shown, in the convolution layer CNV3, the convolution kernel size is 3 and the number of convolution kernels is 384. P2 The convolution operation is performed on the region of . Note that the stride is 1.

[0316] As described in the convolution layer CNV1, by performing convolution processing in the convolution layer CNV3, the convolution layer CNV3 outputs P as output data of 13×13×384. C3 .

[0317] In addition, the convolutional layer CNV3 Figure 1 The operation of the semiconductor device CDV shown can refer to the description of the operation of the semiconductor device CDV in the convolutional layer CNV2.

[0318] [Convolutional layer CNV4] In the convolution layer CNV4, the data P output by the convolution layer CNV3 is C3 Specifically, the convolution kernel for convolution processing CNV4 and the convolution kernel selected from P C3 The product and sum operation of the data included in the area.

[0319] like Fig.10 As shown, in the convolution layer CNV4, the convolution kernel size is 3 and the number of convolution kernels is 384. C3 The convolution operation is performed on the region of . Note that the stride is 1.

[0320] As described in the convolution layer CNV1, by performing convolution processing in the convolution layer CNV4, the convolution layer CNV4 outputs P as output data of 13×13×384. C4 .

[0321] In addition, the convolutional layer CNV4 Figure 1 The operation of the semiconductor device CDV shown can refer to the description of the operation of the semiconductor device CDV in the convolutional layer CNV2.

[0322] [Convolutional layer CNV5] In the convolution layer CNV5, the data P output by the convolution layer CNV4 is C4 Specifically, the convolution kernel for convolution processing CNV5 and the convolution kernel selected from P C4 The product and sum operation of the data included in the area.

[0323] like Fig.10 As shown, in the convolution layer CNV5, the convolution kernel size is 3 and the number of convolution kernels is 256. C4 The convolution operation is performed on the region of . Note that the stride is 1.

[0324] As described in the convolutional layer CNV1, by performing convolution processing in the convolutional layer CNV5, the convolutional layer CNV5 outputs P as output data of 13×13×256. C5 .

[0325] In addition, the convolutional layer CNV5 Figure 1 The operation of the semiconductor device CDV shown can refer to the description of the operation of the semiconductor device CDV in the convolutional layer CNV2.

[0326] [Pooling layer PL5] In the pooling layer PL5, P which is the output data from the convolutional layer CNV5 is C5 Perform pooling.

[0327] like Fig.10 As shown, in the pooling layer PL5, the convolution kernel size is 3 for the data P C5 Each selected region is pooled. Note that the step size is 2 and the pooling process is maximum pooling.

[0328] As described in the pooling layer PL1, the pooling process is performed in the pooling layer PL5, and the pooling layer PL5 outputs P as 6×6×256 output data. P5 .

[0329] In addition, the pooling layer PL5 Figure 1 The operation of the semiconductor device CDV shown can refer to the description of the operation of the semiconductor device CDV in the pooling layer PL1.

[0330] [Fully connected layer FC6] In the fully connected layer FC6, P which is the output data from the pooling layer PL5 P5 Perform operations on fully connected neural networks.

[0331] like Fig.10As shown, in the fully connected layer FC6, the number of input channels is 9126 (= 6×6×256), and the number of output channels is 4096. In the fully connected layer, for one output channel, the product-sum operation of all input channel data and the corresponding weight coefficient (first data) is performed to calculate the value of the activation function with the result as the input value. Therefore, the number of weight coefficients (first data) required in the fully connected layer FC6 is 4096×9126.

[0332] The data of the Nth (where N is an integer greater than or equal to 1 and less than or equal to 4096) output channel of the fully connected layer FC6 is z FC6 (N), z FC6 (N) can be expressed by the following formula (1.1).

[0333] [Formula 1] z FC6 (N) = f(u FC6 (N)) …(1.1)

[0334] Note that f is the activation function of the fully connected layer FC6. As the activation function, for example, a sigmoid function, a tanh function, a softmax function, a ReLU function, or a threshold function can be cited. In addition, u FC6 (N) is as shown in the following formula (1.2).

[0335] [Formula 2]

[0336] In addition, p5 (s) (A) is the Ath data of the sth output channel output in the pooling layer PL5. In addition, w FC6(N) (s) (A) corresponds to the Nth channel and p of the fully connected layer FC6 p5 (s) (A) Weight coefficient (first data).

[0337] By using the above formula (1.1) and formula (1.2), we can find the z of the data from the first output channel to the 4096th output channel of the fully connected layer FC6. FC6 (1) to z FC6 (4096).

[0338] Next, the fully connected layer FC6 is described. Figure 1 The operation of the semiconductor device CDV is shown.

[0339] First, first data (weight coefficients) as digital data are read from the memory circuit portion ME13 and input to the wiring IWL_1 to the wiring IWL_n (here, n is preferably an integer equal to or greater than 4096, for example).

[0340] Here, in Figure 1 The circuit WCS included in the semiconductor device CDV is Fig. 7A When the circuit WCS is shown, each of the circuits WCSa_1 to WCSa_n generates a current corresponding to the value of each digital data sent to the wirings IWL_1 to IWL_n. In addition, when the switches SA_1 to SA_n of the circuit SWCA are all in the on state, the currents generated by the circuits WCSa_1 to WCSa_n flow through the wirings WCL_1 to WCL_n.

[0341] In addition, Figure 6 In the circuit WSD, for example, when the i-th row is selected in the cell array CA, the current from the wiring WCL_1 to the wiring WCL_n flows through each of the plurality of operation units IM[i, 1] to the operation unit IM[i, n] arranged in the i-th row. Here, by maintaining the potential of the gate of the transistor F2 of each of the operation units IM[i, 1] to the operation unit IM[i, n], the amount of current flowing between the source and the drain of the transistor F2 can be set. Note that the amount of current flowing to the operation units IM of the cell array CA is set for the first row to the 9126th row. Therefore, the number of rows m of the cell array CA here is preferably 9126 or more.

[0342] In addition, while the current from the wiring WCL_1 to the wiring WCL_n flows through each of the plurality of arithmetic units IM[i,1] to IM[i,n] arranged in the i-th row of the cell array CA described above, the circuit XCS causes the reference current I ref0 The gate potential of the transistor F2d of the driving unit IMD_i is maintained while flowing through the wiring XCL_i. Thus, the amount of current between the source and the drain of the transistor F2d of the driving unit IMD_i can be set to I ref0 Note that the current amount flowing to the driving unit IMD of the cell array CA is set together with the setting of the current amount of the operation unit IM. That is, when the current amount flowing to the driving unit IM of the cell array CA is set for the first row to the 9126th row, the first row to the 9126th row of the driving unit IMD are also set at the same time.

[0343] Note that the reference current I ref0 The amount is, for example, the amount of current flowing through the wiring XCL when the second data transmitted to the operation unit IM is "1".

[0344] Therefore, the amount of current I0[i,j] flowing through the transistor F2 of the operation unit IM[i,j] is expressed by the following formula (1.3).

[0345] [Formula 3] I0[i,j]=w[i,j]I ref0 …(1.3)

[0346] Note that w[i, j] is the value written to the arithmetic unit IM[i, j], which corresponds to w in the above equation (1.2). FC6(N) (s) (A) is the weight coefficient. In addition, w[i, j] is defined as the following formula (1.4). In addition, I ref0 It is shown in the following formula (1.5).

[0347] [Formula 4] w[i, j] = exp{J(V g [i, j]-V th [i, j]-V gm [i]+V thm [i])}…(1.4) I ref0 =I a exp{J(V gm [i]-V thm [i])} …(1.5)

[0348] Note that V g [i, j] represents the gate-source voltage of transistor F2 of operation unit IM[i, j], V th [i, j] represents the threshold voltage of the transistor F2 of the operation unit IM[i, j]. gm [i] represents the gate-source voltage of the transistor F2d of the driving unit IMD_i, V thm [i] represents the threshold voltage of transistor F2 of driver unit IMD_i. a Indicates V gm [i] is V thm I at [i] ref0 The current is the amount of current, and J represents the correction factor determined by temperature, device structure, etc.

[0349] Next, the second data (P) which is digital data is read from the memory circuit unit ME11. P5 ) and input it to the wiring IXL_1 to the wiring IXL_m (as described above, m is preferably an integer greater than 9126, for example).

[0350] Here, in Figure 1 The circuit XCS included in the semiconductor device CDV is Figure 7CIn the case of the circuit XCS shown, each of the circuits XCSa_1 to XCSa_m generates a current corresponding to the value of each digital data transmitted to the wirings IXL_1 to IXL_m. Thus, each current generated by the circuits XCSa_1 to XCSa_m flows through the wirings XCL_1 to XCL_m.

[0351] Each potential of the wiring XCL_1 to the wiring XCL_m is determined by the amount of current flowing through the wiring. In addition, since each potential of the wiring XCL_1 to the wiring XCL_m changes, the potential of the gate (node ​​N) of each transistor F2 of the operation unit IM[1,1] to the operation unit IM[m,n] changes. At this time, the amount of current I1[i,j] flowing through the transistor F2 of the operation unit IM[i,j] is as follows (1.6).

[0352] [Formula 5] I1[i,j]=x[i]w[i,j]I ref0 …(1.6)

[0353] Note that x[i] is the p corresponding to the above equation (1.2) sent from the circuit XCSa_i to the wiring XCL_i. p5 (s) (A) Input data. In addition, x[i] is the following formula (1.7).

[0354] [Formula 6] x[i]=exp(JpΔV[i])…(17)

[0355] ΔV[i] shows the amount of current flowing through the wiring XCL_i from I ref0 changes to correspond to p p5 (s) (A) The amount of change in the potential of the wiring XCL_i when the current is equal to or greater than (A). In addition, p is a coupling capacitance coefficient between the first terminal and the second terminal of the capacitor C1 of the calculation unit IM[i, j].

[0356] Here, Figure 1 The semiconductor device CDV includes a circuit ITS as follows: Fig. 9A The circuit ITS shown in FIG. At this time, the switches SA_1 to SA_n of the circuit SWCA included in the circuit WCS are all turned off, and the switches SB_1 to SB_n of the circuit SWCB included in the circuit ITS are all turned on. As a result, in the jth column of the cell array CA, the sum of the currents flowing through each of the operation units IM[1,j] to the operation units IM[m,j] is input to the circuit ITSa_j. At this time, the amount of current I input to the circuit ITSa_j is SUM [j] is as follows.

[0357] [Formula 7]

[0358] That is, the amount of current I flowing through the circuit ITSa_j is SUM [j] is determined based on the product and sum of the first data and the second data.

[0359] In the circuit ITSa_j, the terminal RTi_j of the conversion circuit RL_j receives the I as the product-sum result. SUM [j]. Thus, the conversion circuit RL_j performs the SUM [j] is a function operation of the input value. In addition, the conversion circuit RL_j outputs the above function operation result as an analog potential to the terminal RTo_j and inputs it to the analog-to-digital conversion circuit ADC. In addition, the analog-to-digital conversion circuit ADC converts the analog potential into digital data. In addition, the digital data is input to the storage circuit unit ME11 through the wiring OL_j. In other words, the storage circuit unit ME11 is written with the data of the first output channel to the 4096th output channel of the fully connected layer FC6 converted into digital data. FC6 (1) to z FC6 (4096).

[0360] [Fully connected layer FC7] In the fully connected layer FC7, z is the data of the output channel from the fully connected layer FC6. FC6 (1) to z FC6 (4096) Performs operations on a fully connected neural network.

[0361] like Fig.10 As shown in FIG. 1 , in the fully connected layer FC7, the number of input channels is 4096, and the number of output channels is 4096. Similar to the fully connected layer FC6, in the fully connected layer FC7, for one output channel, the product-sum operation of all input channel data and the corresponding weight coefficient (first data) is performed, and the value of the activation function with the result as the input value is calculated. Therefore, the number of weight coefficients (first data) required in the fully connected layer FC7 is 4096×4096.

[0362] Note that the product-sum operation and activation function operation in the fully connected layer FC7 can refer to the description of the fully connected layer FC6.

[0363] In the fully connected layer FC7, the z input as the data of the output channel from the fully connected layer FC6 FC6 (1) to z FC6 (4096), the output is the data z from the first output channel to the 4096th output channel of the fully connected layer FC7 FC7 (1) to zFC7 (4096).

[0364] In addition, the fully connected layer FC7 Figure 1 The operation of the semiconductor device CDV shown can refer to the description of the operation of the semiconductor device CDV in the fully connected layer FC6.

[0365] [Fully connected layer FC8] In the fully connected layer FC8, z is the data of the output channel from the fully connected layer FC7. FC7 (1) to z FC7 (4096) Performs operations on a fully connected neural network.

[0366] like Fig.10 As shown in FIG. 1 , in the fully connected layer FC8, the number of input channels is 4096, and the number of output channels is 1000. As in the fully connected layer FC6, in the fully connected layer FC8, for one output channel, the product-sum operation of all input channel data and the corresponding weight coefficient (first data) is performed, and the value of the activation function with the result as the input value is calculated. Therefore, the number of weight coefficients (first data) required in the fully connected layer FC8 is 1000×4096.

[0367] Note that the product-sum operation and activation function operation in the fully connected layer FC8 can refer to the description of the fully connected layer FC6.

[0368] In the fully connected layer FC8, the z input as the data of the output channel from the fully connected layer FC7 FC7 (1) to z FC7 (4096), the output is the data z from the first output channel to the 1000th output channel of the fully connected layer FC8 FC8 (1) to z FC8 (1000).

[0369] In addition, the fully connected layer FC8 Figure 1 The operation of the semiconductor device CDV shown can refer to the description of the operation of the semiconductor device CDV in the fully connected layer FC6.

[0370] As described above, by using the semiconductor device CDV, it is possible to Fig.10 In addition, by using the operation unit DGP of the semiconductor device CDV to perform digital operations as convolution processing, the update frequency of the filter value can be reduced compared to the conventional structure, thereby reducing the power consumption required for updating the filter value.

[0371] Furthermore, by performing analog operations using the operation unit ANP of the semiconductor device CDV as a fully connected layer, for example, large-scale operations such as product-sum operations of fully connected layers FC6 to FC8 can be performed. Specifically, a subthreshold current flows through each transistor F2 of the operation unit IM[1,1] to the operation unit IM[m,n] included in the cell array CA, so that the power consumption of one operation unit IM can be reduced. Therefore, the number of operation units IM included in the cell array CA can be increased, so that the product-sum operation of the fully connected layer can be performed in one cell array CA.

[0372] Note that in this working example, the semiconductor device CDV is described. Fig.10 The operation of AlexNet shown in FIG. 1 is performed, but the operation model performed by the semiconductor device CDV is not limited to AlexNet. For example, in the input layer INLY, the 224×224 pixel image P in The image is input to the semiconductor device CDV, but the size of the image can be arbitrarily determined. In addition, the number of convolution kernels used in the convolution layers CNV1 to CNV5 and the filter values ​​included in them can also be arbitrarily determined. In addition, the semiconductor device CDV can also use Fig.10 The AlexNet computational model works outside of convolutional neural networks.

[0373] Note that one embodiment of the present invention is not limited to the semiconductor device CDV described in this embodiment. One embodiment of the present invention may change the structure of the semiconductor device CDV described in this embodiment depending on circumstances.

[0374] For example, Figure 1 The operation part DGP of the semiconductor device CDV shown in FIG. Fig.15A The structure shown. Fig.15A The operation unit DGP shown in FIG. Figure 1 The difference between the computing unit DGP and the computing unit DGP is that: the switching circuit D10 is not provided; and the computing unit DGP includes a plurality of computing circuits D20 and a plurality of processing circuits D30. Specifically, Fig.15A The operation unit DGP shown includes operation circuits D20[1] to D20[5], processing circuits D30[1], D30[2], and D30[5].

[0375] The operation circuits D20[1] to D20[5] may refer to the description of the operation circuit D20. In addition, the processing circuits D30[1], D30[2] and D30[5] may refer to the description of the processing circuit D30.

[0376] Fig.15A The operation unit DGP shown includes corresponding Fig.10 The circuits of each of the input layer INLY, convolutional layers CNV1 to CNV5, pooling layers PL1, PL2, and PL5 of the convolutional neural network shown. For example, Fig.10 The input layer INLY shown corresponds to the wiring ILA. In addition, for example Fig.10 The convolutional layers CNV1 to CNV5 shown correspond to the operation circuits D20[1] to D20[5], respectively. Fig.10 The pooling layers PL1, PL2, and PL5 shown correspond to processing circuits D30[1], D30[2], and D30[5], respectively. Fig.15A In the operation part DGP, an operation circuit D20[1], a processing circuit D30[1], an operation circuit D20[2], a processing circuit D30[2], an operation circuit D20[3], an operation circuit D20[4], an operation circuit D20[5] and a processing circuit D30[5] are sequentially arranged between the wiring ILA and the storage circuit part ME11.

[0377] exist Figure 1 In the operation section DGP of the semiconductor device CDV shown in FIG. Fig.10 When performing operations from the convolutional layer CNV1 to the pooling layer PL5 of the convolutional neural network, the operations are performed by repeatedly operating an operation circuit D20 and a processing circuit D30. Fig.15A In the operation unit DGP shown in FIG. Fig.10 When the convolutional neural network's convolutional layer CNV1 to pooling layer PL5 is operated, the operation is performed by making the operation circuit D20 (convolutional layer CNV1) to the processing circuit D30 (pooling layer PL5) work in sequence.

[0378] Note that although Fig.15A Although not shown in the figure, in order to temporarily store the output data of each layer after the operation of each layer, the operation part DGP and the storage part MEM may also store the output data in the storage circuit part of the storage part MEM.

[0379] In addition, for example Figure 1 The arithmetic unit ANP of the semiconductor device CDV shown in FIG. Fig. 15B The structure shown. Fig. 15B The operation unit ANP shown in Figure 1 The difference between the operation part ANP of FIG. 1 and FIG. 2 is that a plurality of cell arrays CA, a plurality of circuits WCS and a plurality of circuits ITS are provided. Specifically, Fig. 15BThe illustrated arithmetic unit ANP includes cell arrays CA[6] to CA[8], circuits WCS[6] to WCS[8], a circuit XCS, and circuits ITS[6] to ITS[8].

[0380] Fig. 15B The cell arrays CA[6] to CA[8] can refer to Figure 1 A description of the cell array CA is shown. Fig. 15B Circuits WCS[6] to WCS[8] can be referenced Figure 1 The circuit shown is a description of the WCS. Fig. 15B The circuit XCS can refer to Figure 1 A description of the circuit XCS is shown.

[0381] In addition, circuit ITS[6] and circuit ITS[7] can be used Fig. 9C The circuit ITS shown. Alternatively, the circuit ITS[8] can be used Fig. 9A or Fig. 9B The circuit shown in ITS.

[0382] The memory circuit unit ME13 is electrically connected to the circuit WCS[6] via the wiring IWL[6]. The memory circuit unit ME13 is electrically connected to the circuit WCS[7] via the wiring IWL[7]. The memory circuit unit ME13 is electrically connected to the circuit WCS[8] via the wiring IWL[8].

[0383] Note that each of the wirings IWL[6] to IWL[8] may be a wiring group including a plurality of wirings. In addition, the wirings IWL[6] to IWL[8] are respectively equivalent to Figure 1 The wiring IWL_1 to the wiring IWL_n are shown.

[0384] The memory circuit unit ME11 is electrically connected to the circuit XCS via the wiring IXL. Note that the wiring IXL here may be a wiring group including a plurality of wirings. In addition, the wiring IXL is equivalent to Figure 1 The wiring IWL_1 to the wiring IWL_n are shown.

[0385] The circuit WCS[6] is electrically connected to the circuit ITS[6] via the wiring WCL[6]. In addition, the circuit WCS[7] is electrically connected to the circuit ITS[7] via the wiring WCL[7]. In addition, the circuit WCS[8] is electrically connected to the circuit ITS[8] via the wiring WCL[8].

[0386] Each of the wirings WCL[6] to WCL[8] may be a wiring group including a plurality of wirings. In addition, the wirings WCL[6] to WCL[8] are respectively equivalent to Figure 1The wirings WCL_1 to WCL_n are shown. In addition, the wiring WCL[6] extends in the column direction of the cell array CA[6], the wiring WCL[7] extends in the column direction of the cell array CA[7], and the wiring WCL[8] extends in the column direction of the cell array CA[8].

[0387] The circuit XCS is electrically connected to the wiring XCL[6]. The wiring XCL[6] may be a wiring group including a plurality of wirings. In addition, the wiring XCL[6] is equivalent to Figure 1 The wiring XCL_1 to the wiring XCL_m are shown. In addition, the wiring XCL[6] extends in the row direction of the cell array CA[6].

[0388] The circuit ITS[6] is electrically connected to the wiring XCL[7]. The wiring XCL[7] may be a wiring group including a plurality of wirings. In addition, the wiring XCL[7] is equivalent to Figure 1 The wiring XCL_1 to the wiring XCL_m are shown. In addition, the wiring XCL[7] extends in the row direction of the cell array CA[7].

[0389] The circuit ITS[7] is electrically connected to the wiring XCL[8]. The wiring XCL[8] may be a wiring group including a plurality of wirings. In addition, the wiring XCL[8] is equivalent to Figure 1 The wiring XCL_1 to the wiring XCL_m are shown. In addition, the wiring XCL[8] extends in the row direction of the cell array CA[8].

[0390] The circuit ITS[8] is electrically connected to the wiring OL[8]. In addition, the wiring OL[8] may be a wiring group including a plurality of wirings. In addition, the wiring OL[8] is equivalent to Figure 1 The wiring OL_1 to the wiring OL_n are shown.

[0391] Fig. 15B The arithmetic unit ANP shown includes Fig.10 The circuit of each of the fully connected layers FC6 to FC8 in the convolutional neural network shown. For example, Fig.10 The fully connected layer FC6 shown corresponds to the cell array CA[6] and the circuit ITS[6]. In addition, for example, Fig.10 The fully connected layer FC7 shown corresponds to the cell array CA[7] and the circuit ITS[7]. Fig.10 The fully connected layer FC8 shown corresponds to the cell array CA[8] and the circuit ITS[8].

[0392] Figure 1 The arithmetic unit ANP of the semiconductor device CDV shown in FIG. Fig.10When the fully connected layer FC6 to the fully connected layer FC8 of the convolutional neural network are operated, the operation is performed by repeatedly operating a unit array CA, a circuit WCS, a circuit XCS, and a circuit ITS. Fig. 15B The ANP performs the Fig.10 When the fully connected layer FC6 to the fully connected layer FC8 of the convolutional neural network are operated, the operation is performed by making the unit array CA and the circuit ITS corresponding to each fully connected layer work in sequence.

[0393] Fig. 15B The operation unit ANP shown in Figure 1 The difference between the arithmetic unit ANP of the semiconductor device CDV is that no analog-to-digital conversion is performed in the circuit ITS[6] and the circuit ITS[7]. In other words, Fig. 15B The arithmetic unit ANP shown has a structure in which no analog-to-digital conversion circuit is provided in the circuit ITS[6] and the circuit ITS[7]. By not providing the analog-to-digital conversion circuit in the circuit ITS[6] and the circuit ITS[7], the circuit area of ​​the semiconductor device CDV can be reduced and the power consumption can be reduced.

[0394] Note that although Fig. 15B Although not shown in the figure, in order to temporarily store the output data of each fully connected layer after the operation of each layer, the operation unit ANP and the storage unit MEM may also store the output data in the storage circuit unit of the storage unit MEM.

[0395] In addition, for example, in this working example, maximum pooling is described as the pooling process, but average pooling, Lp pooling, etc. may also be used depending on the situation.

[0396] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification. For example, the configuration, structure, method, and the like described in this embodiment mode can be appropriately combined with the configuration, structure, method, and the like described in other embodiment modes.

[0397] (Implementation Method 2) In this embodiment, a configuration example of the semiconductor device CDV described in the above embodiment will be described.

[0398] Fig.16 It is a perspective view schematically showing a semiconductor device CDV according to one embodiment of the present invention. Fig.16 The semiconductor device CDV shown in the figure includes, for example, a circuit layer PHRL, a storage layer OMEL, and an operation layer OMAL. In addition, the circuit layer PHRL is located below the storage layer OMEL, and the operation layer OMAL is located above the storage layer OMEL. In other words, Fig.16The semiconductor device CDV has a structure in which a circuit layer PHRL, a memory layer OMEL, and an operation layer OMAL are stacked in this order from the bottom.

[0399] Fig.17 It is shown Fig.16 The block diagram shows structural examples of the circuit layer PHRL, the storage layer OMEL and the operation layer OMAL.

[0400] exist Fig.17 In the example, the circuit layer PHRL includes Figure 1 The switching circuit D10, the operation circuit D20 and the processing circuit D30 are shown. In addition, the storage layer OMEL includes, for example Figure 1 The memory circuit unit ME11, the memory circuit unit ME12 and the memory circuit unit ME13 are shown. In addition, the operation layer OMAL includes, for example, a cell array CA, a circuit WCS, a circuit XCS and a circuit ITS.

[0401] Note that Fig.18 As shown, Figure 1 The circuit WCS, the circuit XCS and the circuit ITS shown may also be included in the circuit layer PHRL. Fig.18 The cell array CA, the circuit WCS, the circuit XCS, the circuit ITS, the memory circuit unit ME11 and the memory circuit unit ME13 are shown in summary. Figure 1 One or more of the circuit WCS, circuit XCS and circuit ITS shown may also be included in the memory layer OMEL.

[0402] The circuit layer PHRL can be formed, for example, by providing circuit elements such as transistors and capacitors on a substrate. In addition, as the substrate, a semiconductor substrate (for example, a single crystal substrate made of silicon or germanium) can be used. As a substrate other than a semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate containing a stainless steel foil, a tungsten substrate, a substrate containing a tungsten foil, a flexible substrate, a laminated film, a paper containing a fibrous material, or a substrate film can be used. As an example of a glass substrate, barium borosilicate glass, aluminoborosilicate glass, or soda-lime glass can be cited. In addition, as an example of a flexible substrate, a laminated film, or a substrate film, plastics represented by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyether sulfone (PES), and polytetrafluoroethylene (PTFE) can be cited. Alternatively, as another example, a synthetic resin such as an acrylic resin can be cited. Alternatively, as another example, polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride can be cited. Other examples include polyamide, polyimide, aramid, epoxy resin, inorganic vapor-deposited film, or paper. When the manufacturing process of the semiconductor device CDV includes heat treatment, it is preferable to select a material with high heat resistance as the substrate.

[0403] Note that in this embodiment mode, description is given on the assumption that a substrate included in the circuit layer PHRL is a semiconductor substrate including silicon.

[0404] By using a semiconductor substrate made of silicon as a substrate included in the circuit layer PHRL, for example, a transistor included in each of the switching circuit D10, the operation circuit D20, and the processing circuit D30 can be formed in the semiconductor substrate. In this case, the transistor is a Si transistor. Since the Si transistor has a high field effect mobility, a large on-state current can flow. As a result, the driving speed of the above-mentioned circuits can be increased, and the width of the signal range can be expanded. In addition, in the semiconductor device CDV is Fig.18 In the case of the structural example shown, since the transistors included in each of the circuits WCS, XCS and ITS can also be formed on a semiconductor substrate made of silicon, each of the circuits WCS, XCS and ITS can increase the driving speed and expand the width of the signal range, etc.

[0405] In addition, by directly forming the storage layer OMEL on the upper part of the circuit layer PHRL, a stacked structure of the circuit layer PHRL and the storage layer OMEL can be manufactured. Alternatively, the storage layer OMEL can also have a structure in which circuit elements such as transistors and capacitors are arranged on a substrate and the substrate is installed on the upper part of the circuit layer PHRL to manufacture the stacked structure.

[0406] When the storage layer OMEL is directly formed on the upper part of the circuit layer PHRL, the storage layer OMEL preferably includes an OS transistor. Since the OS transistor can be formed not only on a semiconductor substrate but also on an insulator substrate, a conductor substrate, a conductive film, an insulating film, or a semiconductor film, it is easy to be provided on a semiconductor substrate (on the circuit layer PHRL) on which a Si transistor is formed.

[0407] In addition, when a circuit element such as a transistor or a capacitor is formed on a substrate as a storage layer OMEL and the substrate is mounted on the circuit layer PHRL, a flip-chip bonding method or a wire bonding method can be used. Alternatively, a first bonding layer can be provided on one side of the circuit layer PHRL, a second bonding layer can be provided on the substrate of the storage layer OMEL, and the first bonding layer and the second bonding layer can be bonded together using one or both of a surface activated bonding method and a hydrophilic bonding method, thereby mounting the storage layer OMEL on the circuit layer PHRL. In particular, copper (Cu) is used for the conductors included in each of the first bonding layer and the second bonding layer, and bonding copper (Cu) to each other is called Cu-Cu bonding.

[0408] <Cross-sectional structure example 1> Next, explain Fig.16 and Fig.17 A specific structural example of the semiconductor device CDV is shown. Fig.19 yes Fig.16 and Fig.17 The schematic cross-sectional view of an example of the semiconductor device CDV shown.

[0409] Fig.19 FIG. 4 is a schematic cross-sectional view of the circuit layer PHRL, the storage layer OMEL and the operation layer OMAL. Fig.19 In the semiconductor device CDV, a memory layer OMEL is directly formed on the circuit layer PHRL, and an operation layer OMAL is directly formed on the memory layer OMEL.

[0410] Fig.19 The transistor 400 included in the circuit layer PHRL is shown. The transistor 400 is provided on the substrate 311 and includes: a conductor 316 used as a gate; an insulator 315 and an insulator 317 used as a gate insulator; a semiconductor region 313 including a portion of the substrate 311; and a low resistance region 314a and a low resistance region 314b used as a source region or a drain region including a portion of the substrate. The transistor 400 can be a p-channel transistor or an n-channel transistor. The substrate 311 can use, for example, a single crystal silicon substrate.

[0411] Here, in Fig.19In the transistor 400 shown, the semiconductor region 313 (a part of the substrate 311) forming the channel has a convex shape. In addition, a conductor 316 is provided in a manner that covers the side and top surfaces of the semiconductor region 313 via an insulator 315. In addition, the conductor 316 can also use a material that adjusts the work function. Because the convex portion of the semiconductor substrate is utilized, this transistor 400 is also referred to as a FIN-type transistor. In addition, an insulator for forming a mask for the convex portion can also be included in a manner that contacts the top of the convex portion. In addition, although a portion of the semiconductor substrate is processed to form a convex portion is shown here, the SOI substrate can also be processed to form a semiconductor film having a convex shape.

[0412] Notice, Fig.19 The structure of the transistor 400 shown is only an example and is not limited to the above structure. An appropriate transistor may be used according to the circuit structure or driving method.

[0413] A wiring layer including an interlayer film, wiring and a plug may also be provided between each structure. In addition, the wiring layer may be provided in multiple layers according to the design. In addition, in this specification, wiring and a plug electrically connected to the wiring may also be a component. That is, a part of the conductor is sometimes used as wiring, and a part of the conductor is sometimes used as a plug.

[0414] For example, an insulator 320, an insulator 324, and an insulator 326 are sequentially stacked as interlayer films on the transistor 400. In addition, a conductor 328 and the like are embedded in the insulator 320. In addition, a conductor 330 and the like are embedded in the insulator 324 and the insulator 326. In addition, the conductor 328 and the conductor 330 are used as contact plugs or wirings.

[0415] In addition, the insulator used as the interlayer film can also be used as a planarization film to cover the concavo-convex shape thereunder. For example, in order to improve the flatness of the top surface of the insulator 320, the top surface can also be planarized by a planarization process using a chemical mechanical polishing (CMP) method.

[0416] A wiring layer may also be provided on the insulator 326 and the conductor 330. Fig.19 In the embodiment, an insulator 350, an insulator 357, an insulator 352, and an insulator 354 are sequentially stacked on the insulator 326 and the conductor 330. A conductor 356 is formed between the insulator 350, the insulator 357, and the insulator 352. The conductor 356 is used as a contact plug or wiring.

[0417] An insulator 354 is provided on the insulator 352 and the conductor 356. The insulator 354 may also have embedded therein contact plugs or wirings for electrically connecting to an upper circuit (eg, a circuit in the memory layer OMEL or a circuit in the computing layer OMAL).

[0418] in addition, Fig.19 Schematic diagram showing a memory cell MC included in the memory layer OMEL. Specifically, Fig.19 FIG. 4 shows a transistor M1, a transistor M2, a transistor M3 and a capacitor C1 included in the memory cell MC. Note that the memory cell MC may be the memory cell MC described in the above embodiment. Figure 4C The memory cell MC is shown.

[0419] exist Fig.19 In the memory layer OMEL of the semiconductor device CDV, the transistor M1 and the capacitor C1 are located above the transistor M2 and the transistor M3.

[0420] exist Fig.19 In the storage layer OMEL, the transistor M2 and the transistor M3 are provided in a manner of using a common island-shaped semiconductor layer. Specifically, a gate insulating film and a gate electrode of the transistor M2 are formed in one of the two regions of the island-shaped semiconductor layer, and a gate insulating film and a gate electrode of the transistor M3 are formed in the other of the two regions of the island-shaped semiconductor layer.

[0421] In addition, Fig.19 In the storage layer OMEL, both transistors M2 and transistor M3 use transistors including back gates. In particular, the back gate of transistor M2 is located in a region overlapping with the gate insulating film and gate electrode of transistor M2 below the above-mentioned island-shaped semiconductor layer, and the back gate of transistor M3 is located in a region overlapping with the gate insulating film and gate electrode of transistor M3 below the above-mentioned island-shaped semiconductor layer.

[0422] In addition, one of the source electrode and the drain electrode of the transistor M2 is electrically connected to a conductor corresponding to the wiring CVLB. In addition, one of the source electrode and the drain electrode of the transistor M2 is electrically connected to a conductor corresponding to the wiring BL. In addition, as an example, the wiring CVLB and the wiring BL extend in the channel width direction of the transistor M2 or the transistor M3.

[0423] In addition, a conductor serving as a gate electrode of the transistor M3 is extended in the channel width direction and corresponds to the wiring RWL.

[0424] An insulator serving as an interlayer film is formed between the transistor M2 and the transistor M3 and the transistor M1. In addition, in the insulator, an opening is provided in a region overlapping with the gate electrode of the transistor M2 and a region overlapping with the wiring BL, and the opening is filled with a conductor. One conductor is electrically connected to one of the source electrode and the drain electrode of the transistor M1, and the other conductor is electrically connected to the other of the source electrode and the drain electrode of the transistor M1.

[0425] As described above, the transistor M1 is located above the transistor M2 and the transistor M3. In addition, a dielectric of the capacitor C1 is formed to cover the end of the island-shaped semiconductor layer of the transistor M1, and a conductor corresponding to the second terminal of the capacitor C1 is formed on the dielectric. The conductor corresponds to the wiring CVLA.

[0426] In addition, the potentials supplied to the wiring CVLA and the wiring CVLB may be equal to each other as described in Embodiment 1. When the potentials supplied to the wiring CVLA and the wiring CVLB are equal to each other, the wiring CVLA and the wiring CVLB may be electrically connected to each other (not shown).

[0427] The gate insulating film and gate electrode of the transistor M1 are formed in the region of the island-shaped semiconductor layer of the transistor M1. In particular, the conductor of the gate electrode of the transistor M1 is provided to extend in the channel width direction. In addition, the conductor corresponds to the wiring WWL.

[0428] In addition, the transistor M1 uses a transistor including a back gate similarly to the transistor M2 and the transistor M3. In particular, the back gate of the transistor M1 is located in a region overlapping with the gate insulating film and the gate electrode of the transistor M1 under the island-shaped semiconductor layer.

[0429] As described above, in transistor M1, transistor M2 and transistor M3, the gate and the back gate are configured in a manner that clamps the channel formation region of the semiconductor. The gate and the back gate are formed by a conductor. The back gate can have the same function as the gate. In addition, by changing the potential of the back gate, the threshold voltage of the transistor can be changed. The potential of the back gate can be equal to the potential of the gate, or it can be a ground potential or an arbitrary potential.

[0430] In addition, since the gate and back gate are formed of a conductor, they also have the function of preventing the electric field generated outside the transistor from affecting the semiconductor forming the channel (especially the electrostatic shielding function). That is, it is possible to prevent the electrical characteristics of the transistor from changing due to the influence of external electric fields such as static electricity. In addition, by providing a back gate, the change in the threshold voltage of the transistor before and after the bias thermal stress test (sometimes referred to as the BT test) can be reduced.

[0431] For example, by using a transistor including a back gate as the transistor M1, the influence of the external electric field can be reduced and the off state can be stably maintained. Therefore, the data written to the first terminal of the capacitor C1 can be stably maintained. By providing a back gate, the operation of the memory cell MC is stable, and the reliability of the storage layer OMEL including the memory cell MC can be improved.

[0432] As the semiconductor layer forming the channels of the transistors M1, M2, and M3, one or a combination of a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, etc. can be used. As the semiconductor material, for example, silicon or germanium can be used as described in Embodiment 1. In addition, as another example, a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, an oxide semiconductor, or a nitride semiconductor can also be used.

[0433] In addition, the transistors M1, M2, and M3 are preferably transistors (OS transistors) using an oxide semiconductor of one of the metal oxides in the semiconductor layer forming the channel. Since the band gap of the oxide semiconductor is greater than 2 eV, the off-state current is significantly small. Therefore, the power consumption of the memory cell MC can be reduced. Therefore, the power consumption of the semiconductor device CDV including the memory cell MC can be reduced.

[0434] In addition, a memory cell including an OS transistor may be referred to as an “OS memory.” In addition, a semiconductor device CDV including the memory cell may also be referred to as an “OS memory.”

[0435] In addition, the OS transistor operates stably even in a high temperature environment, and the characteristics vary little. For example, even in a high temperature environment, its off-state current hardly increases. Specifically, even in an ambient temperature above room temperature and below 200°C, its off-state current hardly increases. In addition, even in a high temperature environment, the on-state current is not easy to decrease. Therefore, the OS memory operates stably even in a high temperature environment and has high reliability.

[0436] in addition, Fig.19 The operation unit IM included in the operation layer OMAL is shown. Specifically, Fig.19 FIG. 4 shows a transistor F1, a transistor F2, a transistor F5 and a capacitor C5 included in the operation unit IM. Note that the operation unit IM may be the transistor F1, the transistor F2, the transistor F5 and the capacitor C5 described in the above embodiment. Figure 6 The arithmetic unit IM is shown.

[0437] In addition, if Fig.19As shown, the structure of the operation unit IM in the operation layer OMAL can be the same as the structure of the storage unit MC in the storage layer OMEL. Therefore, the structure of the operation unit IM in the operation layer OMAL refers to the description of the storage unit MC in the above storage layer OMEL. Note that in the description of the storage unit MC in the storage layer OMEL, the transistor M1 is replaced by the transistor F1, the transistor M2 is replaced by the transistor F2, the transistor M3 is replaced by the transistor F5, the capacitor C1 is replaced by the capacitor C5, the wiring BL is replaced by the wiring WCL, the wiring CVLA is replaced by the wiring VE0, the wiring RWL is replaced by the wiring VE1, the wiring CVLB is replaced by the wiring XCL, and the wiring WWL is replaced by the wiring WSL to describe the unit IM in the operation layer OMAL.

[0438] <Cross-sectional structure example 2> Fig. 20 is with Fig.19 Different Fig.16 and Fig.17 The schematic cross-sectional view of an example of the semiconductor device CDV shown.

[0439] Fig. 20 The storage layer OMEL and the operation layer OMAL in the semiconductor device CDV of the present invention both include a substrate. Fig.19 The CDV of semiconductor devices is different.

[0440] Fig. 20 The memory layer OMEL of the semiconductor device CDV includes a substrate BS1. In addition, a transistor M1, a transistor M2, a transistor M3, and a capacitor C1 are formed on the substrate BS1. Note that the structure of the memory cell MC formed on the substrate BS1 is similar to that of the memory cell MC formed on the substrate BS1. Fig.19 The memory cell MC of the semiconductor device CDV is the same, but can be changed according to the situation Fig. 20 The structure of the storage cell MC.

[0441] in addition, Fig. 20 The operation layer OMAL of the semiconductor device CDV includes a substrate BS2. In addition, a transistor F1, a transistor F2, a transistor F5, and a capacitor C5 are formed on the substrate BS2. Note that the structure of the unit IM formed on the substrate BS2 is similar to that of the unit IM formed on the substrate BS2. Fig.19 The semiconductor device CDV has the same computing unit, but can be changed according to the situation Fig. 20 The structure of the unit IM.

[0442] That is to say, Fig. 20 The semiconductor device CDV has a structure in which a substrate BS1 in a memory layer OMEL and a substrate BS2 in a calculation layer OMAL are mounted on a substrate 311 on which a switching circuit D10, a calculation circuit D20, and a processing circuit D30 are formed.

[0443] Note that the substrate BS1 and the substrate BS2 may be a substrate that can be used in the circuit layer PHRL (e.g., the substrate 311). For example, by using a semiconductor substrate made of silicon as both the substrate BS1 and the substrate BS2, the transistor F1, the transistor F2, the transistor F5, the transistor M1, the transistor M2, and the transistor M3 may all be Si transistors.

[0444] In addition, as a method of mounting the substrate BS1 on the substrate 311 and a method of mounting the substrate BS2 on the substrate BS1, as described above, a flip chip bonding method or a wire bonding method may be used. Alternatively, a bonding layer may be provided between the bonded substrates to use one or both of a surface activated bonding method and a hydrophilic bonding method.

[0445] Note that the semiconductor device of one embodiment of the present invention is not limited to Fig.16 , Fig.17 , Fig.19 and Fig. 20 The semiconductor device of one embodiment of the present invention may also have a structure appropriately changed. Fig.16 , Fig.17 , Fig.19 and Fig. 20 The structure formed.

[0446] Fig.21 Show Fig.16 An example of a modification of the semiconductor device CDV is shown. Fig.21 The semiconductor device CDV shown includes a storage layer OMEL1 and a storage layer OMEL2 instead of the storage layer OMEL, and includes an operation layer OMAL1 and an operation layer OMAL2 instead of the operation layer OMAL. Fig.16 The CDV of semiconductor devices is different. In other words, Fig.21 The semiconductor device CDV includes a circuit layer PHRL, a memory layer OMEL1, a memory layer OMEL2, an operation layer OMAL1, and an operation layer OMAL2.

[0447] As described above, in the semiconductor device CDV, two or four memory layers OMEL and operation layers OMAL may be provided above the circuit layer PHRL. Note that the number of memory layers OMEL and operation layers OMAL provided above the circuit layer PHRL may be three or five or more in total.

[0448] This embodiment mode can be appropriately combined with other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0449] (Implementation 3) In this embodiment, a transistor including an oxide semiconductor in a channel formation region (OS transistor) is described. In the description of the OS transistor, a comparison with a transistor including silicon in a channel formation region (also referred to as a Si transistor) is briefly described.

[0450] [OS Transistor] It is preferable to use an oxide semiconductor with a low carrier concentration for the OS transistor. For example, the carrier concentration of the channel formation region of the oxide semiconductor is 1×10 18 cm -3 Below, preferably below 1×10 17 cm -3 , more preferably less than 1×10 16 cm -3 , and more preferably less than 1×10 13 cm -3 , and further preferably less than 1×10 10 cm -3 , and is 1×10 -9 cm -3 In the case of reducing the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film can be reduced to reduce the defect state density. In this specification, etc., a state in which the impurity concentration is low and the defect state density is low is referred to as high-purity intrinsic or substantially high-purity intrinsic. In addition, an oxide semiconductor with a low carrier concentration is sometimes referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0451] Since high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors have a low defect state density, they sometimes have a low trap state density. In addition, it takes a long time for the charges captured by the trap states of the oxide semiconductor to disappear, and sometimes they act like fixed charges. Therefore, sometimes the electrical characteristics of a transistor in which a channel formation region is formed in an oxide semiconductor with a high trap state density are unstable.

[0452] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the nearby film. As impurities, hydrogen, nitrogen, etc. can be cited. Note that impurities in oxide semiconductors refer to, for example, elements other than the main components that constitute the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be said to be an impurity.

[0453] In an OS transistor, when impurities and oxygen vacancies exist in the channel formation region of an oxide semiconductor, the electrical characteristics are easily changed and reliability may be reduced. In addition, in an OS transistor, hydrogen enters the oxygen vacancies in the oxide semiconductor to form defects (hereinafter sometimes referred to as V OH), electrons that become carriers may be generated. In addition, when V O When the voltage is 0.1V, the donor concentration in the channel formation region increases. As the donor concentration in the channel formation region increases, the threshold voltage is sometimes non-uniform. Therefore, when oxygen vacancies are included in the channel formation region of the oxide semiconductor, the transistor is in a normally-on state (a state in which a channel exists and current flows in the transistor even when no voltage is applied to the gate electrode). Therefore, in the channel formation region of the oxide semiconductor, it is preferable to minimize impurities, oxygen vacancies, and V O H.

[0454] In addition, the band gap of the oxide semiconductor is preferably larger than the band gap of silicon (typically 1.1 eV), preferably 2 eV or more, more preferably 2.5 eV or more, and more preferably 3.0 eV or more. By using an oxide semiconductor with a larger band gap than silicon, the off-state current (also called Ioff) of the transistor can be reduced.

[0455] For example, in Si transistors, as the miniaturization of transistors progresses, short channel effects (Short Channel Effect: also called SCE) appear. Therefore, miniaturization of Si transistors is difficult. One of the reasons for the short channel effect is that the band gap of silicon is small. On the other hand, in OS transistors, oxide semiconductors, which are semiconductor materials with large band gaps, are used, so the short channel effect can be suppressed. In other words, OS transistors are transistors with no short channel effect or very little short channel effect.

[0456] The short channel effect refers to the degradation of electrical characteristics that occurs with the miniaturization of transistors (reduction of channel length). Specific examples of the short channel effect include a reduction in threshold voltage, an increase in subthreshold swing value (sometimes recorded as S value), and an increase in leakage current. Here, the S value refers to the change in gate voltage in the subthreshold region that changes the drain current value by one digit with a fixed drain voltage.

[0457] As an indicator of resistance to short channel effects, characteristic length is widely used. Characteristic length refers to an indicator of the curvature of the potential in the channel formation region. The smaller the characteristic length, the more rapidly the potential rises, so it can be said that the ability to resist short channel effects is high.

[0458] OS transistors are accumulation-type transistors, and Si transistors are inversion-type transistors. Therefore, compared with Si transistors, the characteristic length between the source region and the channel formation region and the characteristic length between the drain region and the channel formation region in OS transistors are smaller. Therefore, OS transistors have a higher ability to resist short channel effects than Si transistors. That is, when you want to manufacture transistors with a small channel length, OS transistors are more suitable than Si transistors.

[0459] Even when the carrier concentration of the oxide semiconductor is reduced to the point where the channel formation region is i-type or substantially i-type, the conduction band bottom of the channel formation region is lowered due to the conduction-band-lowering (CBL) effect in the short channel transistor, so the energy difference of the conduction band bottom between the source region or the drain region and the channel formation region is likely to be reduced to more than 0.1 eV and less than 0.2 eV. Thus, the OS transistor can be regarded as having n + / n - / n + The accumulation type junction-less transistor structure or n + / n - / n + The accumulation type non-junction transistor structure, in which the channel formation region is n - Type region, source region and drain region are n + Type area.

[0460] When the above structure is used as an OS transistor, good electrical characteristics can be achieved even if the semiconductor device is miniaturized or highly integrated. For example, even if the gate length of the OS transistor is less than 20nm, less than 15nm, less than 10nm, less than 7nm or less than 6nm and more than 1nm, more than 3nm or more than 5nm, good electrical characteristics can be obtained. On the other hand, in Si transistors, it is sometimes difficult to have a gate length of less than 20nm or less than 15nm due to the occurrence of short channel effects. Therefore, compared with Si transistors, OS transistors are more suitable for use as transistors with a small channel length. The gate length is the length of the gate electrode in the direction of the carrier movement channel formation region when the transistor is working, and is also the width of the bottom surface of the gate electrode when looking down at the transistor.

[0461] In addition, by miniaturizing the OS transistor, the high-frequency characteristics of the transistor can be improved. Specifically, the cutoff frequency of the transistor can be increased. When the gate length of the OS transistor is within the above range, for example, at room temperature, the cutoff frequency of the transistor can be above 50 GHz, preferably above 100 GHz, and more preferably above 150 GHz.

[0462] As described above, the OS transistor has advantages superior to the Si transistor, such as a small off-state current and the ability to manufacture a transistor with a small channel length.

[0463] This embodiment mode can be appropriately combined with other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes.

[0464] (Implementation 4) In this embodiment, electronic components, electronic devices, mainframe computers, space equipment, and data centers (also referred to as DC) that can use the semiconductor device described in the above embodiment are described. Electronic components, electronic devices, mainframe computers, space equipment, and data centers that use a semiconductor device in one embodiment of the present invention are effective in achieving high performance such as low power consumption.

[0465] [Electronic components] Fig.22A A perspective view of a substrate (circuit board 704 ) on which an electronic component 700 is mounted is shown. Fig.22A The electronic component 700 shown includes a semiconductor device 710 within a mold 711. Fig.22A 700 is partially omitted to show the inside thereof. The electronic component 700 includes a land 712 on the outside of the mold 711. The land 712 is electrically connected to the electrode pad 713, and the electrode pad 713 is electrically connected to the semiconductor device 710 through the lead 714. The electronic component 700 is mounted on, for example, a printed circuit board 702. By combining a plurality of these electronic components and electrically connecting them on the printed circuit board 702, a circuit board 704 is completed.

[0466] In addition, the semiconductor device 710 includes a driving circuit layer 715 and a storage layer 716. The storage layer 716 has a structure in which a plurality of memory cell arrays are stacked. The structure in which the driving circuit layer 715 and the storage layer 716 are stacked can adopt a monolithic stacked structure. In the monolithic stacked structure, it is possible to connect the layers without using through-electrode technologies such as TSV (Through Silicon Via) and bonding technologies such as Cu-Cu direct bonding. When the driving circuit layer 715 and the storage layer 716 are stacked in a monolithic manner, for example, a so-called on-chip memory structure in which a memory is directly formed on a processor can be realized. By adopting the on-chip memory structure, high-speed operation of the interface portion between the processor and the memory can be achieved.

[0467] In addition, by adopting an on-chip memory structure, the size of the connection wiring can be reduced compared to the technology using through-electrodes such as TSV, so the number of pins can be increased. By increasing the number of pins, parallel operation can be performed, thereby increasing the bandwidth of the memory (also called memory bandwidth).

[0468] In addition, it is preferred that multiple memory cell arrays in the storage layer 716 are formed using OS transistors, and the multiple memory cell arrays are stacked in a monolithic manner. When multiple memory cell arrays are stacked in a monolithic manner, either or both of the bandwidth of the memory and the access delay of the memory can be improved. Bandwidth refers to the amount of data transmitted per unit time, and access delay refers to the time between access and the start of data exchange. When Si transistors are used in the storage layer 716, it is more difficult to implement a monolithic stacked structure compared to OS transistors. Therefore, in a monolithic stacked structure, OS transistors are superior to Si transistors.

[0469] In addition, the semiconductor device 710 may be referred to as a bare chip. In this specification, etc., a bare chip refers to a chip obtained by forming a circuit pattern on a disc-shaped substrate (also called a wafer) in the manufacturing process of a semiconductor chip, for example, and cutting it into rectangular small pieces. As semiconductor materials that can be used for bare chips, for example, silicon (Si), silicon carbide (SiC) or gallium nitride (GaN) can be cited. For example, a bare chip obtained from a silicon substrate (also called a silicon wafer) is sometimes called a silicon chip.

[0470] then, Fig. 22B The electronic component 730 is a perspective view. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi Chip Module). In the electronic component 730, an interposer 731 is provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 are provided on the interposer 731.

[0471] The electronic component 730 shows an example of using the semiconductor device 710 as a high bandwidth memory (HBM). In addition, the semiconductor device 735 can be used in an integrated circuit such as a CPU (Central Processor Unit), a GPU (Graphics Processing Unit), or an FPGA (Field Programmable Gate Array).

[0472] The package substrate 732 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 731 may be, for example, a silicon interposer or a resin interposer.

[0473] The plug board 731 has a plurality of wirings and has the function of electrically connecting a plurality of integrated circuits with different terminal spacings. The plurality of wirings are composed of a single layer or a plurality of layers. In addition, the plug board 731 has the function of electrically connecting the integrated circuit disposed on the plug board 731 to the electrode disposed on the package substrate 732. Therefore, the plug board is sometimes referred to as a "rewiring substrate" or "intermediate substrate". In addition, sometimes a through electrode is provided in the plug board 731, and the integrated circuit is electrically connected to the package substrate 732 through the through electrode. In addition, in the case of using a silicon plug board, TSV can also be used as a through electrode.

[0474] In HBM, many wirings need to be connected to achieve a wide memory bandwidth. For this reason, it is required that fine wirings can be formed at a high density on the interposer on which the HBM is mounted. Therefore, a silicon interposer is preferably used as the interposer on which the HBM is mounted.

[0475] In addition, in SiP and MCM using silicon interposers, the reliability degradation caused by the difference in expansion coefficient between the integrated circuit and the interposer is not easy to occur. In addition, since the surface flatness of the silicon interposer is high, the connection between the integrated circuit arranged on the silicon interposer and the silicon interposer is not easy to occur. It is particularly preferred to use the silicon interposer for 2.5D packaging (2.5D mounting) in which a plurality of integrated circuits are arranged horizontally and configured on the interposer.

[0476] On the other hand, when a plurality of integrated circuits with different terminal pitches are electrically connected using silicon interposers and TSV, etc., a space such as the width of the terminal pitch is required. Therefore, when the size of the electronic component 730 is to be reduced, the width of the terminal pitch becomes a problem, and it is sometimes difficult to set up a large number of wirings required to achieve a wider memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferred. In addition, a composite structure combining a memory cell array stacked using TSV and a memory cell array stacked in a monolithic manner can also be used.

[0477] In addition, a heat sink (heat sink plate) may be provided so as to overlap with the electronic component 730. When a heat sink is provided, it is preferable to make the heights of the integrated circuits provided on the interposer 731 consistent. For example, in the electronic component 730 shown in this embodiment, it is preferable to make the heights of the semiconductor device 710 and the semiconductor device 735 consistent.

[0478] In order to mount the electronic component 730 on another substrate, an electrode 733 may be provided on the bottom of the package substrate 732 . Fig. 22BAn example of forming the electrode 733 using solder balls is shown. By arranging solder balls in a matrix at the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrode 733 can be formed using conductive pins. By arranging conductive pins in a matrix at the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0479] The electronic component 730 can be mounted on other substrates by various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0480] [Electronic equipment] then, Fig.23A A perspective view of electronic device 6500 is shown. Fig.23A The electronic device 6500 shown is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes a frame 6501, a display unit 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, a control device 6509, etc. The control device 6509 includes, for example, any one or more selected from a CPU, a GPU, and a storage device. The semiconductor device of one embodiment of the present invention can be used for the display unit 6502, the control device 6509, etc.

[0481] Fig. 23B The electronic device 6600 shown is an information terminal that can be used as a notebook personal computer. The electronic device 6600 includes a frame 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display unit 6615, a control device 6616, etc. The control device 6616 includes, for example, any one or more selected from a CPU, a GPU, and a storage device. A semiconductor device of one embodiment of the present invention can be used for the display unit 6615, the control device 6616, etc. In addition, by using a semiconductor device of one embodiment of the present invention for the above-mentioned control device 6509 and the control device 6616, power consumption can be reduced, so it is preferred.

[0482] [Mainframe computer] then, Fig.23CA perspective view of a mainframe computer 5600 is shown. Fig.23C In the illustrated mainframe computer 5600, a plurality of rack-mounted computers 5620 are housed in a rack 5610. The mainframe computer 5600 may also be referred to as a supercomputer.

[0483] Computer 5620 may have, for example, Fig.23D The structure of the stereogram is shown. Fig.23D In the embodiment, the computer 5620 includes a motherboard 5630, and the motherboard 5630 includes a plurality of slots 5631 and a plurality of connection terminals. A personal computer card 5621 is inserted into the slot 5631. The personal computer card 5621 includes a connection terminal 5623, a connection terminal 5624, and a connection terminal 5625, which are connected to the motherboard 5630.

[0484] Fig.23E The personal computer card 5621 shown is an example of a processing board including a CPU, a GPU, a storage device, etc. The personal computer card 5621 has a board 5622. In addition, the board 5622 includes a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that Fig.23E Semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 are shown. For description of these semiconductor devices, refer to the description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 described below.

[0485] The connection terminal 5629 has a shape that can be inserted into the slot 5631 of the motherboard 5630, and is used as an interface for connecting the personal computer card 5621 and the motherboard 5630. Examples of the standard of the connection terminal 5629 include PCIe and the like.

[0486] Each of the connection terminal 5623, the connection terminal 5624, and the connection terminal 5625 can be used as an interface for supplying power to the personal computer card 5621 or inputting a signal, for example. In addition, for example, it can be used as an interface for outputting a signal calculated by the personal computer card 5621, etc. As examples of the specifications of each of the connection terminal 5623, the connection terminal 5624, and the connection terminal 5625, USB (Universal Serial Bus), SATA (Serial ATA), SCSI (Small Computer System Interface), etc. can be cited. In addition, when video signals are output from the connection terminal 5623, the connection terminal 5624, and the connection terminal 5625, HDMI (registered trademark) and the like can be cited as each specification.

[0487] The semiconductor device 5626 includes a terminal (not shown) for inputting and outputting a signal. By inserting the terminal into a socket (not shown) included in the board 5622 , the semiconductor device 5626 and the board 5622 can be electrically connected.

[0488] The semiconductor device 5627 includes a plurality of terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring included in the board 5622 by reflow soldering. Examples of the semiconductor device 5627 include FPGA, GPU, and CPU. For example, the electronic component 730 can be used as the semiconductor device 5627.

[0489] The semiconductor device 5628 includes a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring included in the board 5622 by reflow soldering. As the semiconductor device 5628, for example, a memory device can be cited. As the semiconductor device 5628, for example, the electronic component 700 can be used.

[0490] The mainframe computer 5600 can be used as a parallel computer. By using the mainframe computer 5600 as a parallel computer, for example, large-scale calculations required for learning and inference of artificial intelligence can be performed.

[0491] [Space Equipment] The semiconductor device of one embodiment of the present invention can be applied to space equipment such as equipment for processing and storing information.

[0492] A semiconductor device according to one embodiment of the present invention may include an OS transistor. The OS transistor has a small change in electrical characteristics due to exposure to radiation. In other words, it has high resistance to radiation, so it can be appropriately used in an environment where radiation may be incident. For example, an OS transistor can be appropriately used when used in outer space.

[0493] exist Fig.24 In FIG. 6 , an artificial satellite 6800 is shown as an example of a space device. The artificial satellite 6800 includes a main body 6801, a solar cell panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Fig.24 An example is shown in which the outer space includes the planet 6804. Note that the outer space refers to, for example, an altitude of 100 km or more, but the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.

[0494] In addition, although Fig.24 Although not shown in the figure, a battery management system (also called BMS) or a battery control circuit may be provided in the secondary battery 6805. When an OS transistor is used for the above-mentioned battery management system or battery control circuit, power consumption is low and high reliability is achieved even in outer space, so it is preferable.

[0495] In addition, outer space is an environment where the radiation dose is more than 100 times that of the ground. Examples of radiation include: electromagnetic waves (electromagnetic radiation) represented by X-rays and gamma rays; and particle radiation represented by alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, muon rays, etc.

[0496] When sunlight shines on the solar cell panel 6802, the power required for the artificial satellite 6800 to operate is generated. However, for example, when sunlight does not shine on the solar cell panel or when the amount of sunlight shining on the solar cell panel is small, the amount of power generated is reduced. Therefore, there is a possibility that the power required for the artificial satellite 6800 to operate may not be generated. In order to operate the artificial satellite 6800 even when the generated power is small, it is preferable to provide a secondary battery 6805 in the artificial satellite 6800. In addition, the solar cell panel is sometimes referred to as a solar cell module.

[0497] The artificial satellite 6800 can generate a signal. The signal is transmitted through the antenna 6803, and a receiver on the ground or other artificial satellites can receive the signal. By receiving the signal transmitted by the artificial satellite 6800, the position of the receiver receiving the signal can be measured. Thus, the artificial satellite 6800 can constitute a satellite positioning system.

[0498] In addition, the control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, any one or more selected from a CPU, a GPU, and a storage device. In addition, it is preferable to use an OS transistor of one embodiment of the present invention for the control device 6807. Compared with Si transistors, the electrical characteristics of OS transistors due to radiation exposure change less. That is, OS transistors have high reliability and can be used appropriately even in an environment where radiation may be incident.

[0499] In addition, the artificial satellite 6800 may include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 may have a function of detecting sunlight reflected from an object on the ground. Alternatively, by including a thermal infrared sensor, the artificial satellite 6800 may have a function of detecting thermal infrared rays released from the ground. Thus, the artificial satellite 6800 may be used as an earth observation satellite, for example.

[0500] Note that although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited to this. For example, a semiconductor device according to one embodiment of the present invention can be suitably applied to space equipment such as a spacecraft, a space capsule, and a space probe.

[0501] As described above, OS transistors have superior effects compared to Si transistors, such as being able to achieve a wider memory bandwidth and having high radiation resistance.

[0502] [Data Center] For example, a semiconductor device according to one embodiment of the present invention can be applied to a storage system used in a data center or the like. A data center is required to manage data over a long period of time by ensuring data invariance. When managing data over a long period of time, it is necessary to enlarge facilities, such as installing storage and servers for storing huge amounts of data, ensuring a stable power supply to maintain data, or ensuring cooling equipment required for maintaining data.

[0503] By using a semiconductor device of one embodiment of the present invention in a storage system used in a data center, it is possible to reduce the power required for data retention and miniaturize the semiconductor device for retaining data. Therefore, it is possible to miniaturize the storage system, miniaturize the power supply for retaining data, and reduce the scale of cooling equipment. As a result, it is possible to save space in the data center.

[0504] In addition, the power consumption of the semiconductor device of one embodiment of the present invention is low, so the heat generation of the circuit can be reduced. As a result, the negative impact of the heat generation on the circuit itself, the peripheral circuits and the modules can be reduced. In addition, by using the semiconductor device of one embodiment of the present invention, a data center that can operate stably even in a high temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0505] Fig.25 A storage system that may be used in a data center is shown. Fig.25 The storage system 7000 shown includes a plurality of servers 7001sb as a host 7001 (shown as a host computer). In addition, it includes a plurality of storage devices 7003md as storage 7003 (shown as storage). The host 7001 and the storage 7003 are shown to be connected via a storage area network 7004 (shown as SAN: Storage Area Network) and a storage control circuit 7002 (shown as a storage controller).

[0506] The host 7001 is equivalent to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0507] In the storage 7003, the access speed of data is shortened by using a flash memory, that is, the time required for data storage and output is shortened, but this time is much longer than the time required for DRAM which can be used as a cache memory in the storage. In the storage system, in order to solve the problem of the long access speed of the storage 7003, a cache memory is generally provided in the storage to shorten the time required for data storage and output.

[0508] The cache memory described above is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003 and then output to the host 7001 or the storage 7003.

[0509] When an OS transistor is used as a transistor for storing data in the cache memory to hold a potential corresponding to the data, the refresh frequency can be reduced to reduce power consumption. In addition, miniaturization can be achieved by stacking memory cell arrays.

[0510] Note that by using a semiconductor device of one embodiment of the present invention for any one or more selected from electronic components, electronic devices, large computers, space equipment, and data centers, it is expected that the effect of reducing power consumption can be expected. Therefore, it is currently believed that as the energy demand for high performance or high integration of semiconductor devices increases, the emission of greenhouse gases represented by carbon dioxide (CO2) can also be reduced by using a semiconductor device of one embodiment of the present invention. In addition, a semiconductor device of one embodiment of the present invention has low power consumption, so it is also effective as a measure against global warming.

[0511] This embodiment mode can be appropriately combined with other embodiment modes described in this specification. For example, the configuration, structure, method, etc. described in this embodiment mode can be appropriately combined with the configuration, structure, method, etc. described in other embodiment modes. [Example]

[0512] <Trial Example 1> The actual trial production is equivalent to the one described in this manual, etc. Figure 1 A circuit of an arithmetic unit ANP in a semiconductor device CDV.

[0513] Fig.26 This is a top view of a bare die (chip) that is actually manufactured and includes a computing circuit. The bare die is 4 mm on one side. Fig.26 The bare chip shown has the following structure: a Si transistor of a 55nm process node is formed on a semiconductor substrate made of silicon, and an OS transistor of a 60nm process node is formed thereon. Specifically, the circuits WD, XD, RD, and GD described later are formed on the semiconductor substrate by the process of the Si transistor, and the circuit MCA described later is formed by the process of the OS transistor.

[0514] Note that the numerical values ​​of process nodes in this specification and the like sometimes do not correspond to the relationship between the minimum line width (referred to as L or line), the minimum spacing width (referred to as S or gap) and the channel length of the transistor included in the actual product. Therefore, the numerical values ​​of process nodes in this specification and the like are only an indicator showing the degree of miniaturization.

[0515] Note that the structure in which the circuits WD, XD, RD, and GD are formed on a semiconductor substrate and the circuit MCA is formed thereover is equivalent to the structure described in Embodiment 1. Fig.18 A modified example of the structure is shown, in which the circuit layer PHRL includes a circuit WCS, a circuit XCS, and a circuit ITS and the operation layer OMAL includes a cell array CA.

[0516] Fig.26 The circuit WD, the circuit XD, the circuit RD, the circuit GD, and the circuit MCA shown in the figure correspond to those of the first embodiment. Figure 6 Specifically, the circuit WD corresponds to each circuit included in the arithmetic unit ANP. Figure 6 The circuit WCS is equivalent to the circuit XD Figure 6 The circuit XCS, circuit GD is equivalent to Figure 6 The circuit WSD, circuit RD is equivalent to Figure 6 Circuit ITS. In addition, circuit MCA is equivalent to Figure 6 The cell array CA.

[0517] <Trial Example 2> In addition, a circuit having the following structure was actually produced: Fig. 15BAs shown in the operation part ANP of , in the fully connected neural network, the output data of the fully connected layer equivalent to the previous layer is directly input to the fully connected layer equivalent to the next layer.

[0518] Fig. 27 This is a top view of a bare die (chip) with two cell arrays actually manufactured. In addition, one side of the bare die is 4 mm. Fig.26 Likewise, Fig. 27 The bare chip shown has the following structure: a Si transistor of a 55nm process node is formed on a semiconductor substrate made of silicon, and an OS transistor of a 60nm process node is formed thereon. Specifically, the circuits WD, XD, RD, GD, and NLNR described later are formed on the semiconductor substrate by the process of the Si transistor, and the circuits MCA1 and MCA2 described later are formed by the process of the OS transistor.

[0519] Circuit MCA1 is equivalent to Figure 6 The cell array CA in the circuit WD includes a plurality of operation units arranged in a matrix. In addition, similar to the circuit MCA1, the circuit MCA2 also includes a plurality of operation units arranged in a matrix. The circuit WD is equivalent to Figure 6 The circuit WCS has the function of causing an analog current corresponding to the first data (for example, a weight coefficient) to flow through each of the circuits MCA1 and MCA2. In addition, the circuit GD is equivalent to Figure 6 The circuit WSD has a function of sending a selection signal for selecting a calculation unit to which the first data is written to each of the circuits MCA1 and MCA2. In addition, the circuit XD is equivalent to Figure 6 The circuit XCS has the function of causing an analog current corresponding to the second data (e.g., a signal output from a neuron in the front layer) to flow through the circuit MCA1. In addition, the circuit RD is equivalent to Figure 6 The circuit ITS has the function of performing function operations (such as nonlinear function operations) with the product-sum results calculated by the circuit MCA2 as input values ​​and the function of converting the results of the function operations into digital data and outputting the digital data to the outside of the circuit RD.

[0520] In addition, the circuit NLNR has a function of performing a function-type operation (for example, a nonlinear function-type operation) using the product-sum result calculated by the circuit MCA1 as an input value. Fig. 9C As shown in the circuit ITSa_j, the circuit NLNR does not include a digital-to-analog conversion circuit.

[0521] exist Fig. 27In the bare die (chip) shown, circuit MCA1 performs a product-sum operation (first time) of the first weight coefficient sent from circuit WD and the data sent from circuit XD. In addition, circuit NLNR performs a function-type operation with the result of the product-sum operation (first time) as an input value. In addition, circuit MCA2 performs a product-sum operation (second time) of the second weight coefficient sent from circuit WD and the operation result of circuit NLNR. In addition, circuit RD performs a function-type operation with the result of the product-sum operation (second time) as an input value, converts the operation result into digital data, and outputs the digital data to circuit RD. [Explanation of symbols]

[0522] CDV: semiconductor device, DGP: calculation unit, ANP: calculation unit, MEM: storage unit, D10: switching circuit, D20: calculation circuit, D20_1: calculation circuit, D20_k: calculation circuit, D30: processing circuit, ME11: storage circuit unit, ME12: storage circuit unit, ME13: storage circuit unit, WWD: circuit, WSD: circuit, RWD: circuit, RBD: circuit, WCS: circuit, WBD: circuit, XCS: circuit, ITS: circuit, CA: cell array, MEA: cell array, XCSa_1: circuit, XCSa_i: circuit, XCSa_m: circuit, WCSa_1: circuit, WCSa_j: circuit, WCSa_n: circuit ,ITSa_1: circuit,ITSa_j: circuit,ITSa_n: circuit,SWCA: circuit,SWCB: circuit,RL_j: conversion circuit,ADC: analog-to-digital conversion circuit,CS: current source,CS1: current source,CS2: current source,CS3: current source,ILA: wiring,ILA_1: wiring,ILA_k: wiring,ILB: wiring,ILB_1: wiring,ILB_k: wiring,MLA: wiring,MLA_1: wiring,MLA_k: wiring,MLB: wiring,CNL: wiring,CNL_1: wiring,CNL_k: wiring,POL: wiring,IXL: wiring,IXL_1: wiring,IXL_i: wiring,IXL_m: wiring, IWL_1: routing, IWL_j: routing, IWL_n: routing, WCL_1: routing, WCL_j: routing, WCL_n: routing, XCL_1: routing, XCL_i: routing, XCL_m: routing, WSL_1: routing, WSL_m: routing, OL_1: routing, OL_n: routing, RSTL: routing, CLKL: routing, DIL: routing, DOL: routing, WBL: routing, WBL_1: routing, WBL_v: routing, WWL: routing, WWL_1: routing, WWL_u: routing, RBL: routing, RBL_1: routing, RBL_v: routing, RWL: routing, RWL_1: routing, RWL_u: routing, CVL A: routing, CVLB: routing, BL: routing, SL: routing, WBLP: routing, WBLN: routing, RBLP: routing, RBLN: routing, SWLA: routing, SWLB: routing, VE0: routing, VE1: routing, VINIL1: routing, VINIL2: routing, DW: routing, DW[1]: routing, DW[2]: routing, DW[M]: routing, DX[1]: routing, DX[2]: routing, DX[L]: routing, VDDL: routing, VTHL: routing, VWL: routing, VTL: routing, VRL: routing, MP: multiplication circuit, AP: addition circuit, RG: register, MEX: storage circuit, MC: storage cell, MC[1,1]: storage unit, MC[u,1]: storage unit, MC[1,v]: storage unit, MC[u,v]: storage unit, IM[1,1]: calculation unit, IM[m,1]: calculation unit, IM[1,n]: calculation unit, IM[m,n]: calculation unit, IMD_1: drive unit, IMD_m: drive unit, MCP: storage unit, MCN: storage unit, TM1i: input terminal, TM2i: input terminal, TMo: output terminal, TN1i: input terminal, TN2i: input terminal, TNo: output terminal, U1: terminal, U2: terminal, RTi_j: terminal, RTo_j: terminal, M1: transistor, M2: transistor, M3: transistor, F1: transistor, F 1d: transistor, F2: transistor, F2d: transistor, F5: transistor, F5d: transistor, Tr1: transistor, Tr1[1]: transistor, Tr1[2]: transistor, Tr1[M]: transistor, Tr2: transistor, Tr2[1]: transistor, Tr2[M]: transistor, Tr3: transistor, C1: capacitor, C5: capacitor, C5d: capacitor, C7: capacitor, SA_1: switch, SA_j: switch, SA_n: switch, SB_1: switch, SB_j: switch, SB_n: switch, SWW: switch, SWX: switch, LE: load, OP: operational amplifier, N[1,1]: node, N[m,1]: node, N[1,n]: node, N[m,n]: node, INLY: input layer, CNV1: convolution layer, CNV2: convolution layer, CNV3: convolution layer, CNV4: convolution layer, CNV5: convolution layer, PL1: pooling layer, PL2: pooling layer, PL5: pooling layer, FC6: fully connected layer, FC7: fully connected layer, FC8: fully connected layer, PHRL: circuit layer, OMEL: storage layer, OMEL1: storage layer, OMEL2: storage layer, OMAL: operation layer, OMAL1: operation layer, OMAL2: operation layer, T01: time, T02: time, T03: time, T04: time, BS1: substrate, BS2: substrate, WD: circuit, XD: circuit, GD: circuit, RD: circuit, NL NR: Circuit, MCA: Circuit, MCA1: Circuit, MCA2: Circuit, 311: Substrate, 313: Semiconductor region, 314a: Low resistance region, 314b: Low resistance region, 315: Insulator, 316: Conductor, 317: Insulator, 320: Insulator, 324: Insulator, 326: Insulator, 328: Conductor, 330: Conductor, 350: Insulator, 352: Insulator, 354: Insulator, 356: Conductor, 357: Insulator, 400: Transistor, 700: Electronic component, 702: Printed circuit board, 704: Circuit board, 710: Semiconductor device, 711: Mold, 712: Connection pad, 713: Electrode pad, 714: Lead wire , 715: driving circuit layer, 716: storage layer, 730: electronic component, 731: plug board, 732: package substrate, 733: electrode, 735: semiconductor device, 5600: mainframe computer, 5610: rack, 5620: computer, 5621: personal computer card, 5622: board, 5623: connection terminal, 5624: connection terminal, 5625: connection terminal, 5626: semiconductor device, 5627: semiconductor device, 5628: semiconductor device, 5629: connection terminal, 5630: motherboard, 5631: slot, 6500: electronic device, 6501: frame, 6502: display unit, 6503: power button, 6504: button, 6505 : speaker, 6506: microphone, 6507: camera, 6508: light source, 6509: control device, 6600: electronic device, 6611: housing, 6612: keyboard, 6613: pointing device, 6614: external connection port, 6615: display unit, 6616: control device, 6800: artificial satellite, 6801: main body, 6802: solar panel, 6803: antenna, 6804: planet, 6805: secondary battery, 6807: control device, 7000: storage system, 7001: host, 7001sb: server, 7002: storage control circuit, 7003: storage, 7003md: storage device, 7004: storage area network. ,

Claims

1. A semiconductor device comprising: A first operation unit; A second operation unit; as well as Storage Department, The first operation unit includes a first wiring and an operation circuit. The second operation unit includes a second wiring, a first circuit, a second circuit, a third circuit and a plurality of operation units. The storage unit includes a first storage circuit unit, a second storage circuit unit and a third storage circuit unit, The first input terminal of the arithmetic circuit is electrically connected to the first wiring. The second input terminal of the arithmetic circuit is electrically connected to the second storage circuit unit. The second wiring is electrically connected to the first circuit, the third circuit, and the plurality of computing units. The first wiring is used as a wiring for sequentially transmitting a plurality of first digital data, The second storage circuit unit has a function of reading out a plurality of second digital data and sequentially sending them to the second input terminal of the operation circuit. The operation circuit has a function of performing a first product-sum operation on the plurality of first digital data and the plurality of second digital data and a function of sending third digital data as a result of the first product-sum operation to the first storage circuit unit, The first storage circuit unit has a function of storing a plurality of the third digital data. The third storage circuit unit has a function of reading out a plurality of fourth digital data and sequentially sending them to the first circuit. The first circuit has a function of sequentially generating first currents corresponding to the fourth digital data and causing each of the first currents to flow through the plurality of operation units. The operation unit has a function of holding a first potential corresponding to the amount of the first current, The first storage circuit unit has a function of reading out a plurality of the third digital data and sending the third digital data to the second circuit. The second circuit has a function of generating a plurality of second currents corresponding to the plurality of third digital data and causing each of the second currents to flow through the plurality of operation units. The arithmetic unit has a function of changing the first potential according to the amount of the second current, generating a third current having an amount equivalent to the product of the fourth digital data and the third digital data, and causing the third current to flow through the second wiring. Furthermore, the third circuit has a function of obtaining the sum of the amounts of the plurality of third currents generated by the plurality of operation units from the second wiring and performing a function operation with the sum of the amounts of the plurality of third currents as an input value to generate first data as a result of the function operation.

2. The semiconductor device according to claim 1, further comprising: a plurality of said first wirings; as well as a plurality of the arithmetic circuits, wherein the first input terminal of each of the plurality of operation circuits is electrically connected to each of the plurality of first wirings in a one-to-one manner, The second input terminals of each of the plurality of operation circuits are electrically connected to each other, Furthermore, an output terminal of each of the plurality of operation circuits is electrically connected to the first storage circuit unit.

3. The semiconductor device according to claim 2, The first computing unit includes a processing circuit. The first storage circuit unit has a function of sending the third digital data to the processing circuit. The processing circuit has a function of performing a pooling process on the third digital data and a function of transmitting the third digital data subjected to the pooling process to the first storage circuit unit.

4. The semiconductor device according to claim 3, The first operation unit includes a switching circuit. The switching circuit includes a plurality of first input terminals, a plurality of second input terminals and a plurality of output terminals. Each of the plurality of second input terminals of the switching circuit is electrically connected to the first storage circuit unit, Each of the plurality of output terminals of the switching circuit is electrically connected to each of the plurality of first wirings in a one-to-one manner, The switching circuit has a function of making a connection between the plurality of first input terminals of the switching circuit and one of the plurality of second input terminals of the switching circuit and the plurality of output terminals of the switching circuit, and making a non-conduction between the plurality of first input terminals of the switching circuit and the other of the plurality of second input terminals of the switching circuit and the plurality of output terminals of the switching circuit, The first storage circuit unit has a function of reading out a plurality of the third digital data and sending them to the first input terminal of the operation circuit through the switching circuit. The operation circuit has the function of performing a second product-sum operation on the plurality of third digital data held by the first storage circuit unit and the plurality of second digital data held by the second storage circuit unit, and the function of sending the result of the second product-sum operation as digital data to the first storage circuit unit.

5. The semiconductor device according to claim 4, The third circuit includes an analog-to-digital conversion circuit. The analog-to-digital conversion circuit has a function of converting the first data into fifth digital data. And the third circuit has a function of transmitting the fifth digital data to the first storage circuit unit.

6. The semiconductor device according to any one of claims 1 to 5, further comprising: First floor; a second layer located above the first layer; as well as The third layer is located above the second layer. The first layer includes the operation circuit, the first circuit, the second circuit and the third circuit. The second layer includes the first storage circuit portion, the second storage circuit portion, and the third storage circuit portion, And the third layer includes the multiple operation units.

7. The semiconductor device according to claim 6, wherein the first layer includes a transistor including silicon in a channel formation region, The second layer and the third layer both include transistors including an oxide semiconductor in a channel formation region, The oxide semiconductor contains one or more selected from indium, zinc and element M, The element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, magnesium and antimony.

8. An electronic device comprising: The semiconductor device according to claim 7; as well as Frame.

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