Semiconductor device and power conversion device

Abstract

A semiconductor device (100) for driving and controlling a semiconductor element (10) is provided with a current control unit (1) for causing a current to flow in a pulse form between a control terminal (G) and a negative terminal (S) of the semiconductor element (10). The peak detection circuit (5) detects a peak value of a voltage between the control terminal (G) or the negative terminal (S) and a reference potential during a current supply period by the current control unit (1). The temperature estimation unit (7) calculates the estimated temperature of the semiconductor element on the basis of the output voltage of the peak detection circuit (5) sampled by the voltage detection unit (6). The timing control unit (3) operates the current control unit (1) such that a current supply period is provided in at least one of an ON period after the semiconductor element is shifted to the ON state and an OFF period after the semiconductor element is shifted to the OFF state.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a power conversion device. Background Art

[0002] In a power converter using power semiconductor devices (power semiconductor devices) such as IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (Metal Oxide Semiconductor Field-Effect Transistors), the density of current flowing through the power semiconductor devices is being increased in order to reduce the size.

[0003] However, when the current density is increased, the energy loss of the power semiconductor element increases, resulting in an increase in the temperature of the power semiconductor element. The power semiconductor element has a maximum allowable operating temperature specified by the semiconductor material characteristics, etc. When the temperature exceeds this temperature, there is a possibility that the power semiconductor element will be damaged by thermal runaway. Therefore, in recent years, the temperature management of power semiconductor elements has become more important.

[0004] The following method is known: in order to perform such temperature management of power semiconductor elements, for example, a temperature sensor such as a thermistor is installed on a fin or the like that cools the power semiconductor element, and the temperature of the power semiconductor element is indirectly estimated. However, the thermal time constant from the power semiconductor element to the fin is generally large, so there is a possibility that a rapid change in the temperature of the power semiconductor element caused by a short-term load change cannot be measured by this method.

[0005] Japanese Patent Application Publication No. 2020-72569 (Patent Document 1) discloses a method for solving this problem. This method pre-stores information indicating the relationship between the time variation of the gate voltage during the switching operation of the semiconductor device and the temperature of the power semiconductor element, and estimates the temperature of the power semiconductor element based on the gate voltage rise time.

[0006] Prior art literature

[0007] Patent Literature

[0008] Patent Document 1: Japanese Patent Application Publication No. 2020-72569 Summary of the invention

[0009] However, the technology disclosed in Patent Document 1 requires a high-precision measurement mechanism and a high-speed processor to measure the gate voltage rise time. If such a measurement mechanism is provided, this may limit the miniaturization of the power module.

[0010] The present disclosure has been made in consideration of the above problems, and one object thereof is to provide a semiconductor device having a temperature estimation function of a power semiconductor element, which does not require a high-precision measurement mechanism and a high-speed processor in a semiconductor device for driving and controlling the power semiconductor element.

[0011] According to a certain embodiment of the present disclosure, a semiconductor device for driving and controlling a semiconductor element comprises a driver circuit, a current control unit, a timing control unit, a peak detection circuit, a voltage detection unit, and a temperature estimation unit. The semiconductor element has: a positive terminal; a negative terminal; and a control terminal, to which a driving voltage for controlling a main current flowing between the positive terminal and the negative terminal is applied. The driver circuit causes the semiconductor element to migrate between an on state and an off state by supplying a driving voltage to the control terminal. The current control unit is provided to cause a current to flow between the control terminal and the negative terminal in a pulsed manner. The timing control unit controls the timing of the current supply by the current control unit. The peak detection circuit outputs a peak value of an input voltage, i.e., a potential difference between the control terminal or the negative terminal and the reference potential relative to a reference potential during the current supply period of the current control unit. The voltage detection unit samples the output voltage of the peak detection circuit. The temperature estimation unit calculates the estimated temperature of the semiconductor element based on the detection voltage detected by the voltage detection unit. The timing control unit operates the current control unit so as to provide a current supply period in at least one of an on period after the semiconductor element transitions to an on state and an off period after the semiconductor element transitions to an off state.

[0012] According to the present disclosure, a semiconductor device can be provided that can estimate the temperature of a semiconductor element based on the peak value of the voltage between the control terminal or the negative terminal and a reference potential when current is supplied between the control terminal and the negative terminal, even without a high-speed measurement mechanism and a high-speed processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1A This is a configuration diagram showing an example of a power module according to the first embodiment.

[0014] Figure 1B It is shown Figure 1A A circuit diagram showing a configuration example of a current control unit.

[0015] Figure 2A Yes Description Figure 1B A circuit diagram of a first example of the connection position of the current control unit shown.

[0016] Figure 2B Yes Description Figure 1B A circuit diagram of a second example of the connection position of the current control unit shown.

[0017] Figure 3 It is shown Figure 1AA structural diagram of a modified example of a power module.

[0018] Figure 4 Yes Description Figure 1A A circuit diagram of a configuration example of a peak detection circuit shown in FIG.

[0019] Figure 5 This is a timing chart for explaining the temperature estimation method of the semiconductor device according to the first embodiment.

[0020] Figure 6 This is a circuit diagram for explaining the configuration of a peak detection circuit according to a variation of the first embodiment.

[0021] Figure 7 This is a timing chart for explaining a temperature estimation method of a semiconductor device using a modification of the first embodiment.

[0022] Figure 8 This is a circuit diagram for explaining a first configuration example of a peak detection circuit according to the second embodiment.

[0023] Fig. 9 This is a circuit diagram for explaining a second configuration example of the peak detection circuit according to the second embodiment.

[0024] Fig.10 This is a timing chart for explaining the temperature estimation method of the semiconductor device using the third embodiment.

[0025] Fig.11 This is a configuration diagram showing an example of a power module according to a fourth embodiment.

[0026] Fig.12 This is a timing chart for explaining a method of estimating the thermal resistance and thermal impedance of the semiconductor device using the fourth embodiment.

[0027] Fig.13 This is a flowchart for explaining the calculation process of the thermal resistance and thermal impedance of the semiconductor device according to the fourth embodiment.

[0028] Fig.14 This is a block diagram showing the configuration of a power conversion system to which the power conversion device in which the semiconductor element according to the present embodiment is mounted is applied. DETAILED DESCRIPTION

[0029] Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In addition, in the following, the same or corresponding parts in the drawings are denoted by the same reference numerals, and the description thereof will not be repeated in principle. Implementation method 1.

[0030] Figure 1A 1 is a diagram showing a configuration of an example of a power module 101 according to the first embodiment. Figure 1B It is shown Figure 1AThe circuit diagram of the configuration example of the current control unit 1 is shown below. Figure 1A as well as Figure 1B , describing the structure of the power module 101.

[0031] like Figure 1A As shown, the power module 101 includes a power semiconductor element 10 and a semiconductor device 100 for driving and controlling the power semiconductor element 10 . The semiconductor device 100 controls switching of the power semiconductor element 10 and measures the element temperature of the power semiconductor element 10 .

[0032] The power semiconductor element 10 includes a positive terminal (drain) D, a negative terminal (source) S, and a control terminal (gate) G. A main current Imt flowing between the positive terminal D and the negative terminal S is controlled by a driving voltage applied to the control terminal G.

[0033] The power semiconductor element 10 may be any element of MOSFET, IGBT, MESFET (Metal-Semiconductor Field-Effect Transistor), bipolar transistor, etc. MOSFET is used as an example for explanation below. In addition, as a material of the power semiconductor element 10, SiC, GaN, Ga2O3, diamond, etc. may also be used in addition to Si.

[0034] The semiconductor device 100 includes a gate driving unit 4, a current control unit 1, a gate wiring unit 2, a timing control unit 3, a peak detection circuit 5, a voltage detection unit 6, and a temperature estimation unit 7. Here, the gate driving unit 4 includes a driver circuit 42 as a drive control unit connected to the power semiconductor element 10 to drive the power semiconductor element 10, and a main control unit 41 to control the driver circuit 42.

[0035] The control terminal G of the power semiconductor element 10 is connected to the driver circuit 42 via the resistor element 21 provided in the gate wiring portion 2. The gate wiring portion 2 represents a series of loop wirings connecting the control terminal G of the power semiconductor element 10, the negative electrode terminal S, and the driver circuit 42. Figure 1A In the example of , it is connected between the driver circuit 42 and the control terminal G of the power semiconductor element 10 .

[0036] The current control unit 1 is connected to the driver circuit 42, and supplies current to a path formed between the control terminal G and the negative terminal S of the power semiconductor element 10 via the driver circuit 42. Figure 1BAs shown, the current control unit 1 includes a pulse current source 20 for supplying a pulsed current. More specifically, the pulse current source 20 includes, for example: a current source 11 for supplying a constant current; and a current control switch 12 connected in parallel with the current source 11. The current control switch 12 is turned on or off according to a switch control signal 31 from the timing control unit 3.

[0037] The pulse current source 20 starts outputting current when the current control switch 12 switches from on to off, and stops outputting current when the current control switch 12 switches from off to on. In this way, the output current of the current control unit 1 is controlled to be a pulse shape corresponding to the on and off of the current control switch 12.

[0038] As the current source 11, for example, a bipolar transistor, a current mirror, or a structure in which a resistor is provided on the output side of a constant voltage source may be used, and various generally known current sources may be used. In addition, the current source 11 may be configured as a current source that outputs current or as a current sink that absorbs current, depending on its circuit structure. The current control switch 12 may use a switching element that operates at a relatively high speed, such as a MOSFET, for example. When measurement accuracy is required, ultra-high-speed devices such as GaNHEMT (High Electron Mobility Transistor) may also be used as the current control switch 12.

[0039] like Figure 1B As shown, one end of each of the current source 11 and the current control switch 12 is connected to a reference potential node 90 for providing a reference potential. Here, the reference potential is, for example, a control ground of the driver circuit 42 or a power supply voltage of the driver circuit 42.

[0040] The other ends of the current source 11 and the current control switch 12 are electrically connected directly or indirectly to the control terminal G or the negative terminal S of the power semiconductor element 10. In the case of indirect connection, the other ends of the current source 11 and the current control switch 12 are connected to the control terminal G (gate) or the negative terminal S (source) of the power semiconductor element 10 via a semiconductor switch element or a resistor or the like as another electronic component mounted on the driver circuit 42.

[0041] exist Figure 2A as well as Figure 2B , circuit diagrams for explaining first and second examples of the connection position of the current control unit 1 are shown.

[0042] In more detail, Figure 2A, an example of a structure in which the other end (the side not connected to the reference potential node 90) of the current source 11 and the current control switch 12 is electrically connected to the negative terminal S of the power semiconductor element 10 is shown. Figure 2A In the embodiment, the current control unit 1 is connected to a position where a current is supplied from the negative electrode terminal S side of the power semiconductor element 10 .

[0043] On the other hand, Figure 2B , a configuration example is shown in which the other ends of the current source 11 and the current control switch 12 are electrically connected to the control terminal G of the power semiconductor element 10. Figure 2B In the embodiment, the current control unit 1 is indirectly connected to the control terminal G via the driver circuit 42, and is connected to a position where current is supplied from the control terminal G side of the power semiconductor element 10. Hereinafter, as an example, a case where the other ends of the current source 11 and the current control switch 12 are electrically connected to the negative terminal S of the power semiconductor element 10 is described ( Figure 2A ).

[0044] Refer again Figure 1A The timing control unit 3 outputs a switch control signal 31 for controlling the current control switch 12 of the current control unit 1 according to the instruction 412 from the main control unit 41 of the gate driving unit 4. As described above, the main control unit 41 controls the driver circuit 42 and the timing control unit 3. As the main control unit 41, for example, a microprocessor, an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array) or other functional devices are used.

[0045] In addition, Figure 1A In the figure, the timing control unit 3 and the gate driving unit 4 are clearly distinguished for convenience of explanation, but the timing control unit 3 may also be included in the main control unit 41. In addition, the driver circuit 42 and the timing control unit 3 may be mounted on the same substrate, and the main control unit 41, the driver circuit 42, the timing control unit 3 and the current control unit 1 may all be mounted on the same substrate.

[0046] The peak detection circuit 5 is connected to the driver circuit 42 so as to receive the voltage between both ends of the current source 11 (inter-terminal voltage). A configuration example of the peak detection circuit 5 will be described later.

[0047] The voltage detection unit 6 detects the output voltage of the peak detection circuit 5. The temperature estimation unit 7 calculates the estimated temperature of the power semiconductor element 10 based on the output voltage value of the peak detection circuit 5 at a predetermined timing, based on the detection value of the voltage detection unit 6 and the control information 32 of the timing control unit 3. For example, as described below, the temperature estimation unit 7 calculates the resistance value of the power semiconductor element 10 based on the above-mentioned output voltage value. Furthermore, the temperature estimation unit 7 generates temperature information 71 including the estimated temperature obtained by converting the newly measured resistance value of the power semiconductor element 10 into temperature by comparing with conversion data indicating the relationship between the resistance value and the element temperature predetermined based on the measured value in the previous actual machine experiment.

[0048] The temperature information 71 is fed back to the main control unit 41. When the temperature is higher than a predetermined value, the main control unit 41 can change the drive mode to reduce the loss of the power semiconductor element or output a warning message to a higher-level system. Figure 1A For convenience of explanation, the main control unit 41 and the temperature estimation unit 7 are shown as independent structures. However, the function of the temperature estimation unit 7 may be included in the main control unit 41 .

[0049] Figure 3 It is shown Figure 1A A structural diagram of a modified example of the power module 101 is shown. Figure 3 The power module 101 shown in the figure has a gate wiring portion 2 in which the resistor 21 is connected to a wiring (source wiring) connected to the negative electrode terminal S instead of the wiring (gate wiring) connected to the control terminal G. Figure 1A In this case, the resistor element 21 also generates a voltage drop in the gate wiring portion 2 according to the current flowing between the control terminal G and the cathode terminal S. Figure 3 Other aspects of Figure 1A Therefore, the same reference numerals are attached to the same or corresponding parts without repeated description. Figure 1A as well as Figure 3 In each of the figures, the resistor element 21 is clearly shown outside the power semiconductor element 10 , but depending on the application, there may be a case where no gate resistor is provided outside the power semiconductor element 10 .

[0050] [Power semiconductor device temperature estimation method]

[0051] The following describes in more detail the use of Figure 1A A method for estimating the temperature of the power semiconductor element 10 of the semiconductor device 100 is provided. Figure 4 In Figure 1A A configuration example of a peak detection circuit 5. Figure 5 In the figure, it is shown to illustrate the use of the configuration Figure 41 is a timing chart of a temperature estimation method of the semiconductor device 100 using the peak detection circuit 5 shown.

[0052] like Figure 4 As shown in FIG. 1 , the peak detection circuit 5 can be composed of a detection circuit including a diode 51, a capacitor 52, and a discharge switch 53. The diode 51 is connected between the input node Nx and the node Ny with the direction from the input node Nx to the node Ny as the forward direction. The capacitor 52 is connected between the node Ny and the node Ns. The potential of the node Ns is also expressed as Vss. The potential of the node Ns is Figure 1B The reference potential node 90 is the same as the reference potential node 90, and the input voltage Vx of the peak detection circuit 5 is equivalent to the potential difference between the node Nx and the node Ns, that is, the potential difference between the control terminal G or the negative terminal S and the reference potential.

[0053] Discharge switch 53 is connected in parallel with capacitor 52, and is turned on and off according to switch control signal 35 from timing control unit 3. Discharge switch 53 can be formed of, for example, a MOSFET with a small leakage current in order to maintain the potential of node Ny in an off state.

[0054] As described above, the peak detection circuit 5 is connected so that the voltage between both ends of the current source 11 (terminal voltage) is input. Figure 2A In the case of connection in the manner of , the input node Nx and the node Ns of the peak detection circuit 5 are directly or indirectly connected to the negative terminal S of the power semiconductor element 10 and the reference potential node 90. That is, the input node Nx is electrically connected to the negative terminal S of the power semiconductor element 10. On the other hand, in the case of connection in the manner of Figure 2B When connected in the manner of , the input node Nx and the node Ns of the peak detection circuit 5 are directly or indirectly connected to the control terminal G of the power semiconductor element 10 and the reference potential node 90. That is, the input node Nx is electrically connected to the control terminal G of the power semiconductor element 10.

[0055] In the peak detection circuit 5, when the voltage of the input node Nx is higher than the voltage of the node Ny, the input voltage Vx is transmitted to the node Ny and is held by the capacitor 52. On the other hand, when the voltage of the input node Nx is lower than the voltage of the node Ny, the input voltage Vx is not transmitted to the node Ny, so the capacitor 52 holds and outputs the peak value of the voltage previously transmitted through the diode 51.

[0056] exist Figure 4 In the embodiment, the input node Nx corresponds to the “first node”, the node Ny corresponds to the “second node”, and the diode 51 corresponds to the “first diode”.

[0057] The voltage detection unit 6 detects the voltage (Vdet) of the capacitor 52, that is, the output voltage of the peak detection circuit 5 by sampling. Hereinafter, the voltage of the capacitor 52 equivalent to the input voltage of the voltage detection unit 6 is also referred to as the detection voltage Vdet. When the discharge switch 53 is in the on state, the detection voltage Vdet is cleared (Vdet=Vss).

[0058] Reference Figure 5 , the semiconductor device 100 ( Figure 1A ) temperature estimation method. Figure 5 The waveforms until time t2 represent voltage waveforms and signal waveforms in a normal switching operation without temperature measurement, and the waveforms after time t2 represent voltage waveforms and signal waveforms in a case where temperature measurement is performed together with the switching operation. First, the operation of the semiconductor device 100 in a normal switching operation is described.

[0059] (Normal Operation of Semiconductor Device)

[0060] The driver circuit 42 outputs a positive potential Vcc greater than a threshold voltage and a potential Vee less than the threshold voltage (usually a negative potential or a zero potential) to drive the power semiconductor element 10. Specifically, the driver circuit 42 applies a positive potential Vcc or a negative or zero potential Vee as a gate voltage to the control terminal G of the power semiconductor element 10 according to a driver input signal 411 from the main control unit 41. Thus, the driver circuit 42 causes the power semiconductor element 10 to transition between an on state and an off state.

[0061] In normal operation, the timing control unit 3 controls the current control switch 12 of the current control unit 1 to be always in the on state. Therefore, when an enhancement-type element such as an n-type MOSFET is used in the current control switch 12, a signal of a logic high (H) level is always input as the switch control signal 31 of the current control switch 12. When a trench-type element such as a p-type MOSFET is used in the current control switch 12, a signal of a logic low (L) level is always input as the switch control signal 31.

[0062] Specifically, refer to Figure 5 In the case of the on-action, when the driver input signal 411 to the driver circuit 42 changes from the L level to the H level at time t0, the positive potential Vcc is applied to the control terminal G of the power semiconductor element 10, and the gate voltage Vgs rises. The gate voltage Vgs reaches the positive potential Vcc at the time point of time t0x after a rising period with a time constant depending on the resistance value of the resistor 21 and the element capacitance of the power semiconductor element 10.

[0063] At this time, the gate current supplied from the driver circuit 42 to the power semiconductor element 10 flows directly to the reference potential node 90 via the current control switch 12. In addition, the current from the current source 11 also flows into the reference potential node 90 via the current control switch 12, and is not output to the driver circuit 42. In addition, the Miller period during which the gate voltage Vgs becomes a constant value is observed during the rising period between the time t0 and the time t0x.

[0064] In the case of the disconnection action, the driver input signal 411 changes from the H level to the L level at time t1. As a result, a negative or zero potential Vee is applied to the control terminal G of the power semiconductor element 10, and the gate voltage Vgs decreases. The gate voltage Vgs passes through a falling period in the same way as when it is turned on, and reaches a negative or zero potential Vee at the time point of time t1x. As in the case of the turn-on action, the gate current flows into the reference potential node 90 via the current control switch 12. The current from the current source 11 flows to the reference potential node 90 via the current control switch 12, and is not output to the driver circuit 42. In addition, the Miller period is also observed during the falling period from time t1 to t1x.

[0065] (Temperature measurement during the on-period)

[0066] Next, the operation of the semiconductor device 100 when temperature measurement is performed is described. Temperature measurement is performed during a period when the gate voltage is stable, other than during a period when the gate voltage rises and falls. During the period when the gate voltage is stable, there is a period when the gate voltage is stable at a positive potential Vcc (hereinafter referred to as an "on period") and a period when the gate voltage is stable at a negative or zero potential Vee (hereinafter referred to as an "off period").

[0067] First, the temperature measurement during the conduction period will be described. Figure 5 At time t2, which corresponds to the timing of the on command, the driver input signal 411 changes from the L level to the H level. At time t3, which is a certain delay period after time t2, the switch control signals 31 and 35 switch from the H level to the L level. In short, the delay time can be set to a time constant determined by the resistance value of the resistor 21 and the element capacitance of the power semiconductor element 10 or a time longer than the time constant.

[0068] When the delay time is short, the gate drive current from the driver circuit 42 also affects the detection voltage of the voltage detection unit 6, thereby affecting the accuracy of temperature measurement. On the other hand, when the delay time is long, the time t4 at which the switch control signal 31 returns to the H level is close to the disconnection start time t5. As a result, the gate drive current from the driver circuit 42 also affects the detection voltage of the voltage detection unit 6, thereby affecting the accuracy of temperature measurement.

[0069] When the switch control signal 31 becomes L level (time t3), Figure 1B The current control switch 12 is turned off. As a result, the current from the current source 11 flows to the power semiconductor element 10 instead of to the reference potential node 90. That is, the current control unit 1 supplies current between the control terminal G and the negative terminal S. During the current supply period, the input voltage Vx to the peak detection circuit 5 is expressed by the following formula (1).

[0070] [Mathematical formula 1]

[0071] ⋯(1)

[0073] In the formula (1), Vx(t-t3) represents the input voltage of the peak detection circuit 5 at the time t after the time t3. gint It is the value of the gate resistance (built-in gate resistance) existing in the power semiconductor element 10. For example, the built-in gate resistance is formed of a material such as polysilicon on the power semiconductor element 10. Alternatively, the built-in gate resistance includes parasitic resistance caused by a gate wiring pattern on the power semiconductor element 10.

[0074] R in formula (1) g represents the resistance of the driver circuit 42 and the value of the resistor 21, and represents the resistance component other than the resistance caused by the power semiconductor element 10 itself. g By providing the resistance external to the power semiconductor element 10, it is easy to select the resistance value and temperature characteristics. die represents the gate side of the power semiconductor element 10 ( Figure 2A ) or the source side ( Figure 2B The capacitance value is based on the situation of g represents the supply current from the current source 11.

[0075] In the current control section 1 ( Figure 1B In the example above, when the current control switch 12 is turned off, the current source 11 starts injecting current into the power semiconductor element 10. As a result, the input voltage Vx according to the formula (1) is input to the peak detection circuit 5.

[0076] Specifically, first, as shown in the first term on the right side of equation (1), a voltage V0=(R g +R gint )･I g .

[0077] Furthermore, as shown in the second term on the right side of equation (1), after time t3 when the current control switch 12 is turned off, the input voltage Vx increases according to (t-t3)･I g / C die The parasitic capacitance C die The current I of the current source 11 is constant and g When the input voltage Vx is a constant value, the input voltage Vx of the peak detection circuit 5 increases linearly. During the increase of the input voltage Vx, the change of the input voltage Vx is transmitted to the capacitor 52 via the node Ny, so after time t3, the detection voltage Vdet of the voltage detection unit 6 changes in the same manner as the input voltage Vx (Vdet=Vx).

[0078] At time t4, when the switch control signal 31 returns from the L level to the H level, the current control switch 12 in the current control unit 1 becomes conductive, so the current from the current source 11 flows into the reference potential node 90. At the same time, the charge accumulated in the parasitic capacitance of the power semiconductor element 10 is also discharged. Since the voltage between the terminals of the current source 11 becomes zero due to the conduction of the current control switch 12, the input voltage Vx of the peak detection circuit 5 becomes 0 at time t4.

[0079] On the other hand, the switch control signal 35 is maintained at the L level, so the discharge switch 53 is maintained in the OFF state in the peak detection circuit 5. Therefore, after time t4, the detection voltage Vdet of the voltage detection unit 6 is maintained at the voltage value at time t3.

[0080] At time t4x, when the switch control signal 35 changes from the L level to the H level, the peak detection circuit 5 ( Figure 4 ), the discharge switch 53 is turned on, so the voltage of the capacitor 52 becomes zero. Correspondingly, the detection voltage Vdet of the voltage detection unit 6 changes to 0. In addition, the time t4x can also be synchronized with the disconnection instruction timing of the driver input signal 411 changing from the H level to the L level described later.

[0081] As a result, in the temperature measurement during the on-period, during the period from time t4 to time t4x, the voltage detection unit 6 measures the input voltage Vx (t4) described below as the detection voltage Vdet.

[0082] [Formula 2]

[0083] ⋯(2)

[0085] At the current I gis a constant value and the time difference from time t3 to t4 (i.e., the length of the current supply period) is constant, the value obtained by removing the second term from the right equivalent to the charging voltage of the parasitic capacitance from Vx(t4), that is, the first term V0 on the right = (R g +R int ).I g becomes a value dependent on the resistance value (R g +R int ). In addition, usually, since the parasitic capacitance has little temperature dependence, the charging voltage of the parasitic capacitance can be regarded as a constant value.

[0086] Therefore, it is possible to use the voltage value V1 of the detection voltage Vdet at time t4, the time difference from time t3 to t4, and the known I g corresponding to the output current of the current source 11 to calculate the resistance value (R g +R gint ).

[0087] Here, the resistance values R g and R gint have temperature dependence respectively. When the resistance values R g , R gint have linear temperature dependence respectively, using the temperature coefficient K, the resistance values R g at temperature T (T) and R gint are expressed as R g (T) ≒ R g 0･(1 + K1･T), R gint (T) ≒ Rg int 0･(1 + K2･T).

[0088] If the temperature dependence of the resistance value R g other than the built-in gate resistance of the power semiconductor element 10 is sufficiently smaller than the temperature dependence of the built-in gate resistance value R gint of the power semiconductor element 10, that is, if the difference in resistance value due to temperature T is ΔR g <ΔR gint (K1 < K2), then the temperature dependence of the resistance value (R g +R gint ) represents the temperature dependence of the built-in gate resistance of the power semiconductor element 10. As described above, by selecting the resistance element (e.g., the resistance element 21) externally mounted to the power semiconductor element 10 for imparting the resistance value R g , it is possible to achieve K1 < K2.

[0089] Therefore, by comparing the resistance value (R g +R gint) and the calibration data indicating the relationship between the resistance value and the temperature recorded in advance, the estimated temperature of the power semiconductor element 10 can be calculated. For example, when the power module 101 is placed in a thermostatic chamber and the element temperature of the power semiconductor element 10 is changed from the outside, the resistance value (R g +R gint ), such correction data can be obtained.

[0090] Alternatively, when it is difficult to obtain the correction data, the built-in gate resistance value R based on the temperature is obtained in advance as information indicating the relationship between the temperature and the resistance value of the power semiconductor element 10. gint The rate of change (temperature coefficient K2) is calculated by using the resistance value (R g +R gint ), and the temperature coefficient K2 (K2>K1) acquired in advance, the temperature of the power semiconductor element 10 can also be calculated.

[0091] In addition, the output current (I g ) and the time difference between time t3 and time t4 (the length of the current supply period by the current control unit 1) are respectively maintained constant, the detection voltage Vdet includes only the resistance value (R) as a variable for the temperature change of the power semiconductor element 10. g +R gint Therefore, it is also possible to use a resistor value (R g +R gint ) is calculated directly from the detection voltage Vdet or V0 extracted from the detection voltage Vdet, and the information representing the relationship between the temperature and the resistance value of the power semiconductor element 10 is pre-set.

[0092] (Temperature measurement during the off period)

[0093] Next, the temperature measurement during the off time is described. Figure 5 In the embodiment, when the driver input signal 411 changes from the H level to the L level at the time t5 corresponding to the opening instruction timing, the switch control signal 31 switches from the H level to the L level at the time t6 after a certain delay period from the time t5. As described above, in simple terms, the delay time can be set to a time constant determined by the resistance value of the resistor 21 and the element capacitance of the power semiconductor element 10 or a time longer than the time constant.

[0094] At time t6, when the switch control signal 31 changes from the H level to the L level, the current control unit 1 ( Figure 1BThe current control switch 12 of the current source 11 is turned off. As a result, the current from the current source 11 does not flow to the reference potential node 90 but flows to the power semiconductor element 10. That is, the current control unit 1 supplies current between the control terminal G and the negative terminal S, and the current supply period is set in the off period.

[0095] When the current control switch 12 is turned off and the current source 11 starts injecting current into the power semiconductor element 10 , the input voltage Vx of the peak detection circuit 5 changes according to the above equation (1). However, the time t3 in the equation (1) is replaced by the time t6 .

[0096] Thus, in the current supply period provided after time t6, similarly to the above-mentioned time t3, the input voltage Vx of the peak detection circuit 5 and the detection voltage Vdet of the voltage detection unit 6 become the stably generated voltage V0=(R g +R gint )･I g The charging voltage of the parasitic capacitance of the power semiconductor element 10 is (t-t6)･I g / C die The sum of the input voltage Vx and the detection voltage Vdet increases as the time passes from time t6, and the parasitic capacitance is charged. That is, the behavior of the input voltage Vx and the detection voltage Vdet after time t6 is the same as that after time t3.

[0097] As in the case of measurement during the conduction period, when the switch control signal 31 is changed from the L level to the H level at time t7, the current control switch 12 in the current control unit 1 is turned on, and the input voltage Vx of the peak detection circuit 5 becomes 0. On the other hand, during the period until time t7x when the switch control signal 31 changes from the L level to the H level, the discharge switch 53 in the peak detection circuit 5 is maintained in the off state, so after time t7, the detection voltage Vdet of the voltage detection unit 6 is maintained at the voltage value at time t7.

[0098] Therefore, in the off period, as described in the on period, the voltage value V2 of the detection voltage Vdet at time t7 to t7x, the time difference between time t6 and t7 (the length of the current supply period), and the known I corresponding to the output current of the current source 11 can be used. g , to calculate the resistance value (R g +R gint ).

[0099] Furthermore, as described above, by making the resistance value R other than the built-in gate resistance of the power semiconductor element 10 g The temperature dependence of the built-in gate resistance value R of the power semiconductor element 10 gintThe semiconductor device 100 is designed so that the temperature dependence is sufficiently small, and the resistance value (R g +R gint ) and the calibration data indicating the relationship between the resistance value and the temperature recorded in advance, the estimated temperature of the power semiconductor element 10 can be calculated. Alternatively, as described above, it is also possible to use the pre-acquired built-in gate resistance value R gint The temperature coefficient K2 (K2>K1) and the calculated resistance value (R g +R gint ), to calculate the temperature of the power semiconductor element 10.

[0100] In addition, similarly to the description in the on-period, the output current (I g ) and the time difference between time t6 and time t7 (the length of the current supply period by the current control unit 1) are respectively maintained constant, the resistance value (R g +R gint ) and directly calculate the estimated temperature based on the detection voltage Vdet or V0 extracted from the detection voltage Vdet.

[0101] In addition, Figure 5 In the example, the timing of the switch control signal 31 migrating from the H level to the L level (starting timing from the current supply of the current source 11) and the timing of the switch control signal 35 migrating from the H level to the L level (equivalent to the start timing of the voltage detection) are synchronized, but a certain time difference can also be set between the two.

[0102] In addition, the lengths of time t3 to t4x and time t6 to t7x (i.e., the length of the current supply period) required for the temperature measurement during the on period and the off period are as follows: Figure 5 The result shown is the result of subtracting the period required for the on-off transition of the current control switch 12 and the period required for the on-off transition of the discharge switch 53 from the length of the on-period or off-period during switching, which can be set to, for example, several μs to several hundred μs. [Effects of Embodiment 1]

[0103] As described above, in the power module 101 of the embodiment, the current I injected from the current source 11 into the path between the control terminal G and the negative terminal S during the on-period or off-period of the power semiconductor element 10 is measured. gThe peak voltage between the control terminal G or the negative terminal S and the reference potential node 90 at the time of the current injection can be stably estimated to be the temperature of the power semiconductor element 10. The timing of the start of the injection of the above-mentioned current can be determined as a delay time which is simply set to a time constant determined by the gate resistance and the element capacitance or a time longer than the time constant from the rise and fall timing of the driver voltage. A variation of implementation example 1.

[0104] In the modification of the first embodiment, a modification of the configuration of the peak detection circuit 5 will be described.

[0105] Figure 6 1 is a circuit diagram for explaining the configuration of the peak detection circuit 5 according to a modification of the first embodiment. Figure 1A In the semiconductor device 100, the peak detection circuit 5 has Figure 6 The structure shown.

[0106] like Figure 6 As shown, in the peak detection circuit 5 of the modified example of the first embodiment, Figure 4 The discharge switch 53 in the circuit structure of is replaced by the resistor element 54. That is, in the modification of the first embodiment, the on-off control of the discharge switch 53 is unnecessary, and the structure of the peak detection circuit 5 is simplified.

[0107] Figure 7 This is a timing chart for explaining a temperature estimation method of a semiconductor device using a modification of the first embodiment.

[0108] Reference Figure 7 In the modified example of the first embodiment, the voltage waveform of the capacitor 52 in the peak detection circuit 5 changes, so the waveform of the detection voltage Vdet of the voltage detection unit 6 changes from the first embodiment ( Figure 5 )change. Figure 7 Other signal waveforms and voltage waveforms are Figure 5 The same, so no detailed description will be repeated.

[0109] exist Figure 7 In the embodiment, from the time t4 in the on period when the current control switch 12 of the current control unit 1 is turned off according to the switch control signal 31 and the time t7 in the off period, the capacitor 52 is discharged through the resistor 54. As a result, the detection voltage Vdet gradually decreases according to the RC time constant determined by the capacitance value of the capacitor 52 and the resistance value of the resistor 54.

[0110] In a variation of the first embodiment, relative to Figure 7 The detection voltage Vdet shown is fixed so that the elapsed time from time t4 or t7 becomes constant and is used to calculate the resistance value (R g+R gint )’s voltage value sampling timing.

[0111] Thus, the influence caused by the discharge of the capacitor 52 can be eliminated, and the voltage V0 generated by the temperature change of the power semiconductor element 10 can be extracted. g +R gint )･I g In addition, the voltage detection unit 6 can obtain the change in the embodiment 1 ( Figure 5 ) in the voltage values ​​V1 and V2.

[0112] Thus, in the modification of the first embodiment in which the configuration of the peak detection circuit 5 is simplified, the temperature of the power semiconductor element 10 can be stably obtained during the on-period or off-period of the power semiconductor element 10 , similarly to the first embodiment.

[0113] In addition, it is necessary to adjust the switching cycle of the power semiconductor element 10 (in Figure 7 The RC time constant in the peak detection circuit 5 is determined by discharging the capacitor 52 within a period determined by the time interval between the time points t0 and t2 (e.g., half of the switching cycle). For example, it is preferable to design the capacitor 52 and the resistor 54 so that the discharge of the capacitor 52 is completed in a few (μs) to several hundred (μs).

[0114] In contrast, in the peak detection circuit 5 of the first embodiment, the detection voltage Vdet is maintained constant after time t4 and t7, so that the voltage detection unit 6 can be configured more cheaply than the modification of the first embodiment using a simple detector with a slow time response speed. Implementation method 2.

[0115] In the second embodiment, a further modified example of the configuration of the peak detection circuit 5 will be described.

[0116] Figure 8 This is a circuit diagram for explaining a first configuration example of a peak detection circuit according to the second embodiment.

[0117] like Figure 8 As shown, the peak detection circuit 5 of the first structural example of the second embodiment has Figure 4 In addition to the structure shown, an operational amplifier 55 is included. The operational amplifier 55 is connected between the input node Nx and the diode 51 (anode).

[0118] The operational amplifier 55 is connected as a voltage follower, and transmits the voltage of the input node Nx to the anode of the diode 51. Therefore, the same input voltage Vx as in Embodiment 1 is input to the diode 51. Therefore, the detection voltage Vdet detected by the voltage detection unit 6 is also the same as in Embodiment 1, and the temperature of the power semiconductor element 10 can be stably obtained during the on-period or off-period of the power semiconductor element 10 by the same method as in Embodiment 1.

[0119] exist Figure 4 In the circuit structure of FIG. 1 , the current from the current control unit 1, that is, the supply current (I g ) is used to charge the capacitor 52. Therefore, when estimating the temperature based on the relationship of the above formula (1), there is a possibility that the temperature estimation accuracy is reduced due to the error in the amount of current flowing in the peak detection circuit 5.

[0120] In contrast, Figure 8 In the circuit structure of FIG. 5 , by connecting an input stage with high impedance to the input node Nx, the supply current of the current source 11 can be prevented from flowing into the peak detection circuit 5. In this way, by using an active element with high input impedance represented by the operational amplifier 55 in the input stage, the input impedance of the peak detection circuit 5 is increased, and almost all of the supply current from the current source 11 can flow into the power semiconductor element 10. That is, the operational amplifier 55 corresponds to an embodiment of the "impedance conversion circuit".

[0121] As a result, in the semiconductor device including the peak detection circuit of the first configuration example of the second embodiment, the error of the temperature calculated according to the relationship of equation (1) can be reduced, thereby improving the temperature estimation accuracy of the power semiconductor element 10 .

[0122] Fig. 9 This is a circuit diagram for explaining a second configuration example of the peak detection circuit according to the second embodiment.

[0123] like Fig. 9 As shown, the peak detection circuit 5 of the second structural example of the second embodiment has Figure 8 In addition to the configuration shown in (First Configuration Example), a diode 56 having the same characteristics as the diode 51 and an operational amplifier 58 are included.

[0124] The diode 56 is inserted into the feedback path of the voltage follower-connected operational amplifier 55, and generates a voltage drop equivalent to that of the diode 51. A negative bias voltage (V-) for stably conducting the diode 56 may be supplied to the cathode of the diode 56 via a resistor. The diode 56 corresponds to an embodiment of the "second diode".

[0125] In such a configuration, the difference between the voltage at the node Ny and the output voltage of the operational amplifier 55 (i.e., the voltage at the input node Nx) can be suppressed by eliminating the influence of the voltage drop caused by the diode 51. Thus, by suppressing the difference between the detection voltage Vdet detected by the voltage detection unit 6 and the input voltage Vx of the peak detection circuit 5, the temperature estimation accuracy of the power semiconductor element 10 can be further improved.

[0126] The operational amplifier 58 is connected between the node Ny and the voltage detection unit 6. The operational amplifier 58 is connected as a voltage follower, and outputs a voltage equal to the voltage of the node Ny as the detection voltage Vdet to the voltage detection unit 6. By configuring the operational amplifier 58, the output impedance of the peak detection circuit 5 becomes small. As a result, it is expected that the voltage detection accuracy in the voltage detection unit 6 can be improved. In addition, it is also possible to prevent the potential of the node Ny from changing due to the influence from the voltage detection unit 6, so according to this aspect, the detection accuracy of the detection voltage Vdet can also be improved.

[0127] In addition, operational amplifier 58 is Figure 8 In the first configuration example shown, it is also possible to additionally connect between the node Ny and the voltage detection unit 6. The operational amplifier 58 also corresponds to one embodiment of the "impedance conversion circuit".

[0128] Thus, by using the peak detection circuit of the second embodiment, the voltage change caused by the temperature change of the power semiconductor element 10 is more clearly and directly reflected in the detection voltage Vdet, so that the temperature estimation accuracy of the power semiconductor element 10 can be further improved. Figure 8 as well as Fig. 9 In the structural example, it can also be Figure 6 (Variation of Embodiment 1) Similarly, the discharge switch 53 is replaced with a resistor 54. Implementation method 3.

[0129] In the third embodiment, a modified example of the on-off control of the current control switch 12 of the current control unit 1 is described. In the first embodiment, as a period in which the gate voltage of the power semiconductor element 10 is stable other than the rising and falling periods, an example in which the off period of the current control switch 12 is set once in the on period and once in the off period is described, but in the third embodiment, the off period of the current control switch 12 is set multiple times.

[0130] Fig.10 1 is a timing chart for explaining the temperature estimation method of the semiconductor device using the third embodiment. Fig.10 In the OFF period of the power semiconductor element 10, the OFF period of the current control switch 12, that is, the current supply period from the current source 11 is provided multiple times.

[0131] exist Fig.10 In the example of FIG. 1 , the temperature measurement is performed during the off period after the time t5 at which the power semiconductor element 10 is turned off. Figure 5 Similarly, during the period from time t6 to time t7 after a certain delay period from time t5 corresponding to the timing of the off command, the switch control signal 31 is set to the L level, and a current supply period is provided from the current control unit 1. As described in the first embodiment, during this period, a current is supplied from the current source 11 to the power semiconductor element 10 via the gate wiring portion 2, and the input voltage Vx of the peak detection circuit 5 increases according to the above formula (1).

[0132] At time t7, the switch control signal 31 changes from L level to H level. During the H level period of the switch control signal 31, the current control switch 12 in the current control unit 1 is turned on, and both ends of the current source 11 have the same potential, so that the input voltage Vx=0.

[0133] After time t7, the switch control signal 31 is again kept at an L level during a period from time t8 to t9. Furthermore, after the switch control signal 31 changes from an L level to an H level at time t9, the switch control signal 31 is again kept at an L level during a period from time t10 to t11.

[0134] During the L level period of the switch control signal 31 between time t8 and time t9 and time t10 and time t11, the input voltage Vx of the peak detection circuit 5 increases according to the above-mentioned formula (1) similarly to time t6 and time t7.

[0135] In this way, Fig.10 In the example of , during the off period, the L level period of the switch control signal 31, that is, the current supply period from the current control unit 1 formed by turning off the current control switch 12, is set for multiple times such as time t6 to t7, time t8 to t9, time t10 to t11, ..., time tk-1 to tk. The time length of each L level period of the switch control signal 31 is set to be the same. Therefore, the behavior (waveform) of the input voltage Vx is the same during each L level period of the switch control signal 31. Therefore, the input voltage Vx at the end time point of each L level period of the switch control signal 31 becomes the same voltage value V2.

[0136] Even in Figure 5 In the peak detection circuit 5 shown in FIG. 1 , when the diode 51 becomes non-conductive during the off period of the discharge switch 53, the voltage of the node Ny gradually decreases due to the leakage current of the discharge switch 53 and the like. Fig.10, a slight decrease in the detection voltage Vdet due to this influence is also emphasized. For example, after time t7, as Vx=0, the diode 51 becomes non-conductive, and the detection voltage Vdet gradually decreases from V2.

[0137] At time t8-t9, the input voltage Vx rises similarly to time t6-t7 by setting the L level period of the switch control signal 31. As a result, when the input voltage Vx becomes higher than the voltage of the node Ny (detection voltage Vdet) again around time t7, the detection voltage Vdet can be restored to V2 by the conduction of the diode 51.

[0138] Thus, according to the third embodiment, by turning the current control switch 12 on and off multiple times and repeatedly setting the current supply period multiple times, it is possible to eliminate the attenuation of the output voltage of the peak detection circuit 5, that is, the detection voltage Vdet of the voltage detection unit 6. As a result, a simple detector with a slow time response speed can be used in the voltage detection unit 6. In addition, the on-off operation of the current control switch 12 can be repeated throughout the period when the gate voltage of the power semiconductor element 10 is stable, that is, the off period and the on period, except for the rising period and the falling period.

[0139] In addition, Fig.10 In order to simplify the description, an example is shown in which the off period of the current control switch 12 (the current supply period from the current control unit 1) is not set during the on period and the temperature measurement is not performed, but when the temperature measurement is performed in both the on period and the off period, the off period of the current control switch 12 (the current supply period from the current source 11) can be set multiple times in at least one of the temperature measurements.

[0140] In the third embodiment, the response delay of the peak detection circuit 5 can be alleviated by repeatedly turning on and off the current control switch 12 a plurality of times. Figure 6 In the peak detection circuit 5 shown, the response speed is limited by the RC time constant determined by the capacitor 52 and the resistor 54, and when the pulses of the input voltage Vx are small, there is a possibility that the peak value of the input voltage Vx becomes higher than the output voltage (detection voltage Vdet) of the peak detection circuit 5. In contrast, by repeatedly turning on and off the current control switch 12 multiple times as in the third embodiment, a plurality of pulse waveforms can be provided as the input voltage Vx, so that the peak detection circuit 5 can accurately reflect the peak value of the input voltage Vx to the detection voltage Vdet.

[0141] In addition, the off-period length of the current control switch 12 may not take exactly the same value due to the influence of the jitter of the controller. When the off-period length varies, the peak value of the input voltage Vx includes the change factor other than the temperature of the power semiconductor element 10, so there is a concern that the temperature estimation accuracy will be reduced. Even in such a case, by setting the off-period of the current control switch 12, that is, the measurement period of the input voltage Vx, within one off-period or one on-period as in Embodiment 3, the influence of the error caused by the jitter can be averaged. Thus, the temperature estimation accuracy can be prevented from being reduced. Implementation method 4.

[0142] In the fourth embodiment, an example is described in which the steady-state thermal resistance or the transient thermal resistance of the power semiconductor element 10 is calculated using the estimated temperature calculation value of the power semiconductor element 10 calculated in the first to third embodiments.

[0143] When calculating the steady-state thermal resistance, the power semiconductor element 10 needs to be thermally in a stable state (thermal equilibrium state). For example, this stable state can be achieved by causing a certain power loss by passing a certain DC current through the power semiconductor element 10 in a power cycle test, which is one of the general reliability tests of the power semiconductor element.

[0144] Alternatively, the simulated thermal equilibrium state can be formed by continuously switching the power semiconductor element 10 to control the current flowing through the power semiconductor element 10 to a constant value. For example, in a structure such as a full-bridge circuit using four power semiconductor elements to control the conduction direction of the current or in a structure using two power semiconductor elements in a half-bridge circuit connected to an inductive load or a resistive load, the current of each power semiconductor element can be controlled to a constant value to form a simulated thermal equilibrium state.

[0145] Fig.11 This is a configuration diagram showing an example of a power module according to a fourth embodiment.

[0146] like Fig.11 As shown, the power module 103 of the fourth embodiment is different from the power module 101 or 102 of the first embodiment ( Figure 1A , Figure 3 ), the main control unit 41 further includes: a main current detection unit 81 for measuring the main current Imt; and a main voltage detection unit 82 for detecting the main voltage (drain-source voltage) Vmt of the power semiconductor element 10. The main current Imt measured by the main current detection unit 81 and the main voltage Vmt detected by the main voltage detection unit 82 are input to the main control unit 41. Thus, the main control unit 41 can calculate the power loss generated in the power semiconductor element 10 by the product of the main voltage Vmt and the main current Imt.

[0147] Fig.12 This is a timing chart for explaining a method of estimating the thermal resistance and thermal impedance of the semiconductor device using the fourth embodiment. Fig.12 The control process shown can be executed by the main control unit 41, for example.

[0148] Reference Fig.12 The power semiconductor element 10 is controlled to switch multiple times in a manner to form the above-mentioned thermal equilibrium state until the time t5, and is then maintained in the off state after the time t5.

[0149] During the off period of the power semiconductor element 10, Vmt is generated, and Imt=0. On the contrary, during the on period of the power semiconductor element 10, Imt is generated, and a finite resistance (on resistance) is generated in the power semiconductor element 10. Therefore, during the on period, due to the on resistance, a power loss (conduction loss) of Pls=Vmt･Imt is generated. Furthermore, during the on and off period, a period in which Vmt･Imt does not become zero is generated, and during this period, a power loss (switching loss) of Pls=Vmt･Imt is generated. Due to these power losses Pls, the temperature Tj of the power semiconductor element 10 rises.

[0150] During the period after time t5 , no current flows through the power semiconductor element 10 , so the temperature Tj of the power semiconductor element 10 gradually decreases according to the thermal impedance between the power semiconductor element 10 and a cooler (not shown) and the cooling capacity of the cooler.

[0151] The time constant of the temperature change at this time can be simply estimated based on the thermal resistance and heat capacity of the heat dissipation path of the power semiconductor element 10. Generally speaking, in the vicinity of the power semiconductor element 10, the above time constant is in the range of tens (μs) to hundreds (μs). Generally speaking, this value is close to the value of the switching cycle of the power semiconductor element 10 or slightly longer than the switching cycle. In the embodiments 1 to 3 described above, it is assumed that the temperature of the power semiconductor element 10 during the on-off action is estimated, so the temperature change of the power semiconductor element 10 in the temperature measurement can be almost ignored.

[0152] In contrast, in the fourth embodiment, the thermal resistance and thermal impedance of the power semiconductor element 10 are measured by measuring the temperature change of the power semiconductor element 10 maintained in the off state for a long period of time using the method described in the third embodiment.

[0153] Specifically, in Fig.10After the same time t6, the current control switch 12 is repeatedly turned on and off by providing a predetermined L level period (i.e., current supply period) for a plurality of times in the switch control signal 31. As described in Embodiments 1 to 3, during each off period of the current control switch 12, the current control unit 1 (current source 11) supplies current, thereby generating an input voltage Vx reflecting the temperature Tj at that time point.

[0154] Therefore, by obtaining the peak value of the input voltage Vx from the detection voltage Vdet for each current supply period in which the current control switch 12 is turned off, it is possible to calculate the estimated temperature (estimated value of Tj) of the power semiconductor element 10 at each timing. Fig.12 In the example, the temperature measurement is performed N times from the first L level period from time t6 to t7 to the Nth (N: an integer greater than or equal to 2) L level period from time tn-1 to tn.

[0155] The power semiconductor element 10 is maintained in the off state after time t5, so it is gradually cooled. Therefore, the peak value of the input voltage Vx and the detection voltage Vdet gradually decrease due to the temperature of the power semiconductor element 10. The decrease in temperature Tj is calculated by the decrease in the detection voltage Vdet, so the peak detection circuit 5 needs to have a response speed that can reflect the decrease in the peak value of the input voltage Vx caused by the decrease in the temperature of the power semiconductor element 10 to the detection voltage Vdet. Therefore, the response time constant of the peak detection circuit 5 is preferably shorter than the thermal time constant of the power semiconductor element 10.

[0156] Fig.13 This is a flowchart for explaining the calculation process of the thermal resistance and thermal impedance of the semiconductor device according to the fourth embodiment. Fig.13 The series of processing shown is executed by, for example, the main control unit 41 .

[0157] When the power semiconductor element 10 is in the above-mentioned thermal equilibrium state, the main control unit 41 executes the processing of steps (hereinafter simply referred to as “S”) 110 to S150. Fig.12 In the process, before time t5, the processes of S110 to S150 are executed.

[0158] In S110, the main control unit 41 obtains the main voltage Vmt (instantaneous value) of the power semiconductor element 10 measured by the main voltage detection unit 82, and in S120, obtains the main current Imt (instantaneous value) of the power semiconductor element 10 measured by the main current detection unit 81. Since the main voltage Vmt obtained in S110 and the main current Imt obtained in S120 are measured values ​​at the same timing, the main control unit 41 calculates the power loss Pls (instantaneous value) generated in the power semiconductor element 10 based on the multiplication value of the main voltage Vmt and the main current Imt in S130.

[0159] The main control unit 41 determines "No" in S140 until the calculation timing of the thermal resistor arrives. When the main control unit 41 determines "No" in S140, it executes the process of calculating the power loss Plsc of each switching cycle of the power semiconductor element 10 through S150. Specifically, the power loss Plsc of each switching cycle is calculated by accumulating the power loss Pls calculated in S130 in each switching cycle. In S150, the accumulated value is cleared according to the end or start of each switching cycle.

[0160] In S140, Fig.12 In the example, it is determined as "yes" at time t5. The processing of S110 to S150 is repeatedly performed until it is determined as "yes" in S140. In addition, in S150, the moving average of the power loss Plsc of the latest X cycles (X: a predetermined integer greater than 2) can also be calculated.

[0161] When the main control unit 41 determines "yes" in S140, the process proceeds to S160 to start the calculation of the thermal resistance. In S160, the main control unit 41 determines the power P (W) used in the calculation of the thermal resistance Rth. For example, the power P can be set to the power loss Plsc in the switching cycle just before the calculation in S150 at the time point when the determination is "yes" in S140 or the latest moving average of the power loss Plsc.

[0162] The main control unit 41 is as follows Fig.12 As described in FIG. 1 , for each L level period (equal length) of the switch control signal 31, the estimated temperature (estimated value of Tj) of the power semiconductor element 10 is calculated based on the detection voltage Vdet obtained as the peak value of the input voltage Vx. Fig.12 In the description, a total of N temperature measurements are performed.

[0163] In S170 , the main control unit 41 performs the i-th (i: a natural number from 1 to N) temperature measurement and calculates the estimated temperature T(i) based on the detection voltage Vdet at that time. Fig.12In the case where i=1, the estimated temperature T(1) of the power semiconductor element 10 between time t6 and time t7 is calculated.

[0164] When i≥2, S180 calculates thermal resistance Rth=ΔT / P using temperature change ΔT(i)=T(i)-T(1) and power P determined in S160. In S180, thermal resistance Rth(i) is calculated in the i-th temperature measurement (i≥2).

[0165] The main control unit 41 determines whether the number of measurements i reaches a predetermined end condition (N) through S190. Until the end condition is reached (when it is determined as "No" in S190), the thermal resistor Rth (i) calculated in S180 is stored through S195. Therefore, when the number of measurements i reaches n and the end condition is met (when it is determined as "Yes" in S190), (N-1) thermal resistors Rth (2) to Rth (N) can be obtained. In addition, the end condition of the measurement in S190 can be determined by the length of time that has passed since it was determined as "Yes" in S140, in addition to the number of measurements.

[0166] When the measurement end condition is satisfied (when it is determined to be "yes" in S190), the main control unit 41 can calculate the thermal impedance Zth of the power semiconductor element 10 including the cooling system using the thermal resistance (herein, Rth(2) to Rth(N)) previously calculated corresponding to the temporal change of the temperature Tj of the power semiconductor element 10. In this way, the main control unit 41 executes Fig.13 The control process shown can constitute an embodiment of the "thermal resistance calculation unit".

[0167] Furthermore, in order to calculate the thermal impedance, it is necessary to determine the end condition of the measurement in S190 in such a way as to ensure sufficient cooling time for the power semiconductor element 10. The necessary cooling time depends on the thermal time constant of the cooling system of the power semiconductor element 10, and is generally in the range of several [s] to several hundred [s]. It is difficult to embed this degree of cooling time into the normal operation mode of a general power electronic machine, but, for example, in an inverter system, by utilizing current control that can keep the power semiconductor element disconnected for a certain period of time or the operation stop timing of the system, the disconnected state of the power semiconductor element 10 can be maintained for a relatively long period of time. Fig.13 The calculation process of thermal impedance is shown.

[0168] Thus, according to the fourth embodiment, the temperature estimation method of the power semiconductor element 10 described in the first to third embodiments can be used to calculate the thermal resistance Rth of the power semiconductor element 10. Furthermore, when the off period (cooling period) of the power semiconductor element 10 for measuring the temperature can be ensured, the thermal impedance Zth of the power semiconductor element 10 including the cooling system can be calculated. Implementation method 5.

[0169] Embodiment 5 is an example in which the power modules 101 to 103 of Embodiments 1 to 4 are applied to a power conversion device. The present disclosure is not limited to a specific power conversion device, but the following describes a case in which the present disclosure is applied to a three-phase inverter as Embodiment 5.

[0170] Fig.14 1 is a block diagram showing a configuration of a power conversion system to which the power conversion device according to the present embodiment is applied.

[0171] Fig.14 The power conversion system shown in the figure includes a power supply 120, a power conversion device 110, and a load 130. The power supply 120 is a DC power supply, and supplies DC power to the power conversion device 110. The power supply 120 can be composed of various examples, for example, it can be composed of a DC system, a solar cell, a storage battery, or a rectifier circuit connected to an AC system, or an AC / DC converter. In addition, the power supply 120 can also be composed of a DC / DC converter that converts the DC power output from the DC system into a set power.

[0172] The power conversion device 110 is a three-phase inverter connected between the power source 120 and the load 130, converts the DC power supplied from the power source 120 into AC power, and supplies the AC power to the load 130. Fig.14 As shown, the main conversion circuit 111 is provided with: a main conversion circuit 111 that converts DC power into AC power and outputs the AC power; and a control circuit 112 that outputs a control signal for controlling the main conversion circuit 111 to the main conversion circuit 111 .

[0173] Load 130 is a three-phase motor driven by AC power supplied from power converter 110. Load 130 is not limited to a specific use, and is a motor mounted on various electrical machines, such as a motor for hybrid vehicles, electric vehicles, railway vehicles, elevators, or air conditioners.

[0174] The power conversion device 110 is described in detail below. The main conversion circuit 111 includes a switching element and a freewheeling diode (not shown), and converts the DC power supplied from the power supply 120 into AC power by switching the switching element, and supplies it to the load 130. There are various examples of the specific circuit structure of the main conversion circuit 111, but the main conversion circuit 111 of this embodiment is a 2-level three-phase full-bridge circuit, which can be composed of 6 switching elements and 6 freewheeling diodes connected in anti-parallel with each switching element. At least any switching element of each switching element of the main conversion circuit 111 is the power semiconductor element 10 of the power module 101 of any embodiment of the above-mentioned embodiments 1 to 4. The 6 switching elements are connected in series for every 2 switching elements to form upper and lower branches, and each upper and lower branch constitutes each phase (U phase, V phase, W phase) of the full-bridge circuit. In addition, the output terminal of each upper and lower branch, that is, the three output terminals of the main conversion circuit 111, is connected to the load 130.

[0175] In addition, as described in the above-mentioned embodiments 1 to 4, the semiconductor device 100 (not shown) for driving each switching element is built into the power modules 101 to 103, so the main conversion circuit 111 includes the semiconductor device 100. The semiconductor device 100 generates a drive signal for driving the switching element of the main conversion circuit 111, and supplies it to the control electrode of the switching element of the main conversion circuit 111. Specifically, according to the control signal from the control circuit 112 described later, a drive signal for turning the switching element into a conductive state and a drive signal for turning the switching element into an off state are output to the control electrode of each switching element. When the switching element is maintained in a conductive state, the drive signal is a voltage signal (conduction signal) above the threshold voltage of the switching element, and when the switching element is maintained in an off state, the drive signal is a voltage signal (off signal) below the threshold voltage of the switching element.

[0176] The control circuit 112 controls the switch elements of the main conversion circuit 111 in such a manner that the desired power is supplied to the load 130. Specifically, the time (on-time) when each switch element of the main conversion circuit 111 should be in the on state is calculated according to the power to be supplied to the load 130. For example, the main conversion circuit 111 can be controlled by PWM (Pulse Width Modulation) control that modulates the on-time of the switch element according to the voltage to be output. In addition, a control instruction (control signal) is output to the semiconductor device 100 of the main conversion circuit 111 in such a manner that an on signal is output to the switch element that should be in the on state and an off signal is output to the switch element that should be in the off state at each time point. The semiconductor device 100 outputs an on signal or an off signal as a drive signal to the control electrode of each switch element in accordance with the control signal.

[0177] In the power conversion device of this embodiment, the power modules 101 to 103 of Embodiments 1 to 4 are applied as the power module 101 constituting the main conversion circuit 111 . Therefore, the reliability of the power conversion device can be improved based on the temperature measurement results of the power semiconductor elements.

[0178] In this embodiment, an example of applying the present disclosure to a 2-level three-phase inverter is described, but the present disclosure is not limited thereto and can be applied to various power conversion devices. In this embodiment, a 2-level power conversion device is used, but a 3-level or multi-level power conversion device can also be used. When power is supplied to a single-phase load, the present disclosure can also be applied to a single-phase inverter. In addition, when power is supplied to a DC load, the present disclosure can also be applied to a DC / DC converter or an AC / DC converter.

[0179] In addition, the power conversion device to which the present disclosure is applied is not limited to the case where the load is a motor, and can be used as a power supply device for, for example, an electric discharge machine, a laser processing machine, an induction heating cooker, or a contactless power supply system. Furthermore, the power conversion device to which the present disclosure is applied can also be used as a power conditioner for a solar power generation system, a power storage system, and the like.

[0180] It can be confirmed that the intention at the time of the application is that the structures described in the above-described embodiments can be appropriately combined within a range that does not cause incompatibility or contradiction, including combinations not mentioned in the specification.

[0181] The embodiments disclosed this time should be considered as illustrative in all aspects and not restrictive. The scope of the present disclosure is indicated by the claims rather than the above description, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0182] (Explanation of symbols)

[0183] 1: Current control unit; 2: Gate wiring unit; 3: Timing control unit; 4: Gate drive unit; 5: Peak detection circuit; 6: Voltage detection unit; 7: Temperature estimation unit; 10: Power semiconductor element; 11: Current source; 12: Current control switch; 20: Pulse current source; 21, 54: Resistor element; 31, 35: Switch control signal; 32: Control information; 41: Main control unit; 42: Driver circuit; 51, 56: Diode; 52: Capacitor; 53: Discharge switch; 55, 58: Operational amplifier; 71: Temperature information; 81: Main current detection unit; 82: Main current Voltage detection unit; 90: reference potential node; 100: semiconductor device; 101~103: power module; 110: power conversion device; 111: main conversion circuit; 112: control circuit; 120: power supply; 130: load; 411: driver input signal; 412: instruction; D: positive terminal; G: control terminal; Imt: main current (power semiconductor element); Ns, Nx, Ny: nodes; S: negative terminal; Vdet: detection voltage; Vgs: gate voltage; Vmt: main voltage (power semiconductor element); Vx: input voltage (peak detection circuit).

Claims

1. A semiconductor device for driving and controlling a semiconductor element, wherein: The semiconductor element has: a positive terminal; a negative terminal; and a control terminal to which a driving voltage for controlling a main current flowing between the positive terminal and the negative terminal is applied. The semiconductor device comprises: a driver circuit that causes the semiconductor element to transition between an on state and an off state by supplying the drive voltage to the control terminal; a current control unit provided to cause a current to flow between the control terminal and the negative electrode terminal in a pulsed manner; a timing control unit for controlling the timing at which the current control unit supplies the current; a peak detection circuit for outputting a peak value of an input voltage which is a potential difference between the control terminal or the negative terminal and a reference potential during a current supply period of the current control unit; a voltage detection unit, which samples the output voltage of the peak detection circuit; as well as a temperature estimation unit that calculates an estimated temperature of the semiconductor element based on the detection voltage detected by the voltage detection unit, The timing control unit operates the current control unit so as to provide the current supply period in at least one of an on period after the semiconductor element transitions to the on state and an off period after the semiconductor element transitions to the off state.

2. The semiconductor device according to claim 1, wherein The peak detection circuit comprises: a first diode having an anode connected to a first node electrically connected to the control terminal or the cathode terminal; a capacitor connected between a second node connected to the cathode of the first diode and a node to which the reference potential is supplied; and The discharge switch element or the discharge resistor is used to discharge the capacitor.

3. The semiconductor device according to claim 2, wherein: The peak detection circuit also includes: An impedance conversion circuit is disposed at least one of between the first node and the anode of the first diode and between the second node and the voltage detection unit.

4. The semiconductor device according to claim 3, wherein: The peak detection circuit: comprising an operational amplifier connected as the impedance conversion circuit between the first node and the anode of the first diode as a voltage follower, and It also includes a second diode inserted into a feedback path connected to the voltage follower connection and generating a voltage drop equivalent to that of the first diode.

5. The semiconductor device according to any one of claims 1 to 4, wherein: The timing control unit sets the current supply period a plurality of times in at least one of the on period and the off period.

6. The semiconductor device according to any one of claims 1 to 5, wherein: The timing control unit repeatedly sets the current supply period a plurality of times during the thermal resistance measurement period in which the semiconductor element is maintained in the off state. The semiconductor device further comprises: a main current detection unit for detecting the main current of the semiconductor element; a main voltage detection unit for detecting a main voltage between the positive terminal and the negative terminal of the semiconductor element; as well as The thermal resistance calculation unit calculates the power loss generated in each switching cycle in the semiconductor element before the thermal resistance measurement period, and calculates the thermal resistance of the semiconductor element based on the calculated power loss and the change in the estimated temperature calculated for each of the multiple current supply periods.

7. The semiconductor device according to any one of claims 1 to 6, wherein: The current control unit is arranged at a position where the current is supplied from the negative electrode terminal side of the semiconductor element.

8. The semiconductor device according to any one of claims 1 to 6, wherein: The current control unit is arranged at a position where the current is supplied from the control terminal side of the semiconductor element.

9. The semiconductor device according to any one of claims 1 to 8, wherein: The pulsed current has a predetermined amplitude. The current supply period is set to have a predetermined time length, The temperature estimation unit calculates the estimated temperature using the resistance value obtained from the detection voltage and the amplitude of the current during the current supply period and information indicating a relationship between the temperature of the semiconductor element and the resistance value obtained in advance.

10. A power conversion device comprising: A main conversion circuit, comprising a semiconductor device according to any one of claims 1 to 9 and a semiconductor element driven and controlled by the semiconductor device, the main conversion circuit converting input power and outputting the power; and The control circuit outputs a control signal for controlling power conversion performed by the main conversion circuit to the main conversion circuit.

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