Double-sided semiconductor wafer

Abstract

A semiconductor device is provided having one or more double-sided semiconductor wafers. The double-sided semiconductor wafer includes a first array of semiconductor dies on a first planar surface and a second array of semiconductor dies on a second planar surface opposite the first planar surface. The first semiconductor die array is electrically coupled via a first redistribution layer, and the second semiconductor die array is electrically coupled via a second redistribution layer. One or more through-silicon vias electrically couple the first array of semiconductor dies with the second array of semiconductor dies.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. non-provisional application No. 17 / 888,845, filed on August 16, 2022, entitled “BIFACIAL SEMICONDUCTOR WAFER,” and the entire contents of that U.S. non-provisional application are hereby incorporated by reference for all purposes. Background Art

[0003] In conventional high-capacity memory devices (such as, for example, three-dimensional (3D) NAND memory devices), semiconductor dies are stacked vertically on top of each other. To facilitate communication between different semiconductor dies, the edges of the stacked semiconductor dies are often offset relative to each other. Bonding wires are used to connect the bonding pads of one semiconductor die in the semiconductor die stack to the bonding pads of another semiconductor die in the stack.

[0004] To increase the storage capacity of a high-capacity memory device, additional semiconductor dies may be added to the stack. However, current high-capacity memory devices are limited in the number of semiconductor dies that can be included in the stack. For example, as additional semiconductor dies are added, the overall size of the high-capacity memory device increases and consumes more space, wire bonding becomes more difficult, and the semiconductor dies may experience warping, die tilt, or other manufacturing issues.

[0005] Accordingly, it would be advantageous to increase the storage capacity of a memory device while maintaining or reducing the size of the memory device and avoiding the other manufacturing issues outlined above. Summary of the invention

[0006] The present application describes a semiconductor device comprising a plurality of vertically stacked semiconductor wafers. In the examples described herein, the semiconductor wafer is double-sided. For example, a first surface or face of the semiconductor wafer comprises a first circuit layer. A second surface or face of the semiconductor wafer comprises a second circuit layer. In the examples, the first circuit layer and the second circuit layer may comprise a storage circuit system and / or a signal transmission circuit system.

[0007] The double-sided semiconductor wafer of the present disclosure is described as having a first circuit layer on a first surface and a second circuit layer on a second surface. It should be understood that the first circuit layer and its associated second circuit layer comprise a double-sided semiconductor die. In addition, it should be understood that the double-sided semiconductor wafer described herein may be composed of a series of double-sided semiconductor dies. In an example, the double-sided semiconductor die may be a NAND memory die.

[0008] The first circuit layer and the second circuit layer each include a corresponding redistribution layer or are otherwise associated with a corresponding redistribution layer. The redistribution layer enables each semiconductor die on a specific surface of the double-sided semiconductor wafer to communicate with other semiconductor dies on the specific surface. For example, the redistribution layer on the first surface of the double-sided semiconductor wafer enables signals to be transmitted between each of the semiconductor dies on the first surface. Similarly, the redistribution layer on the second surface of the double-sided semiconductor wafer enables signals to be transmitted between each of the semiconductor dies on the second surface. One or more through silicon vias electrically couple the first circuit layer and the second circuit layer. For example, the through silicon vias electrically couple the semiconductor die on the first surface with the semiconductor die on the second surface.

[0009] Accordingly, the present application describes a semiconductor device, which includes a double-sided semiconductor wafer having a first flat surface and a second flat surface opposite to the first flat surface. A first plurality of semiconductor dies are disposed on the first flat surface, and a second plurality of semiconductor dies are disposed on the second flat surface. A plurality of through silicon vias electrically couple the first plurality of semiconductor dies on the first flat surface with the second plurality of semiconductor dies on the second flat surface.

[0010] A semiconductor device is also described, the semiconductor device comprising a first double-sided semiconductor wafer and a second double-sided semiconductor wafer. The first double-sided semiconductor wafer has a first circuit layer on a first flat surface and a second circuit layer on a second flat surface opposite to the first flat surface. In an example, the first circuit layer is electrically coupled to the second circuit layer. The second double-sided semiconductor wafer is electrically coupled to the first double-sided semiconductor wafer. In an example, the second double-sided semiconductor wafer has a first circuit layer on a first flat surface and a second circuit layer on a second flat surface opposite to the first flat surface. The first circuit layer of the second double-sided semiconductor wafer is electrically coupled to the second circuit layer of the first double-sided semiconductor wafer.

[0011] The present application also describes a method for manufacturing a double-sided semiconductor wafer. In an example, the method includes manufacturing a first plurality of semiconductor die on a first flat surface of a first silicon wafer, and manufacturing a second plurality of semiconductor die on a first flat surface of a second silicon wafer. The second flat surface of the first silicon wafer is bonded to the second flat surface of the second silicon wafer. In an example, the second flat surface of the first silicon wafer is opposite to the first flat surface of the first silicon wafer, and the second flat surface of the second silicon wafer is opposite to the first flat surface of the second silicon wafer. The method also includes manufacturing one or more through silicon vias passing through the first silicon wafer and the second silicon wafer to electrically couple the first plurality of semiconductor die on the first flat surface of the first silicon wafer with the second plurality of semiconductor die on the first flat surface of the second silicon wafer.

[0012] This Summary is provided to introduce some concepts in a simplified form that are further described in the Detailed Description below. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Non-limiting and non-exhaustive examples are described with reference to the following figures.

[0014] Figure 1 A conventional semiconductor die used in a memory device (eg, a three-dimensional (3D) NAND memory device) is illustrated.

[0015] Figure 2 A double-sided semiconductor wafer having semiconductor dies on opposing planar surfaces according to an example is illustrated.

[0016] Figure 3 A cross-sectional view of a double-sided semiconductor wafer according to an example is illustrated.

[0017] Figure 4 A semiconductor device according to an example is illustrated in which a plurality of double-sided semiconductor wafers have been stacked on one another.

[0018] Figure 5 The example according to Figure 4 A partial cross-sectional view of a semiconductor device.

[0019] Figure 6 An example in which a plurality of double-sided semiconductor wafers are stacked and electrically coupled according to an example is illustrated.

[0020] Figure 7 A method for manufacturing a double-sided semiconductor wafer according to an example is illustrated.

[0021] FIG. 8A to FIG. 8C Various applications for double-sided semiconductor wafers such as described herein according to various examples are illustrated. DETAILED DESCRIPTION

[0022] In the following specific embodiments, reference is made to the accompanying drawings that form a part of the specific embodiments, and in the accompanying drawings, specific embodiments or examples are shown by way of illustration. Without departing from the present disclosure, these aspects can be combined, other aspects can be utilized, and the structure can be changed. Examples can be practiced as methods, systems, or devices. Accordingly, examples can take the form of hardware implementations, complete software implementations, or combined software and hardware implementations. Therefore, the following specific embodiments should not be considered to have a limiting meaning, and the scope of the present disclosure is limited by the appended claims and their equivalents.

[0023] In a conventional three-dimensional (3D) NAND memory device, a semiconductor wafer having a memory cell array is vertically stacked on another semiconductor wafer having another memory cell array. As the number of layers increases, the storage capacity of the memory device also increases.

[0024] However, current 3D NAND memory devices are limited in the number of layers that can be stacked together. For example, as additional semiconductor wafers are added to a 3D NAND memory device, the overall size of the 3D NAND memory device increases. In addition, as additional layers are added, manufacturing becomes more complex and expensive (in terms of time and / or materials). Adding additional semiconductor wafers may also increase the amount of stress induced on the semiconductor wafer, which may subsequently warp the semiconductor wafer. A warped semiconductor wafer may adversely affect the performance of the 3D NAND memory device.

[0025] To address the above issues, the present application describes a double-sided semiconductor wafer for use in a 3D NAND memory device. Although 3D NAND memory devices are specifically mentioned, the examples described herein may be used in a variety of memory devices and / or other semiconductor devices.

[0026] The double-sided semiconductor wafer of the present disclosure includes a first flat surface or face. A first circuit layer is disposed on the first flat surface. The first circuit layer may include a first semiconductor die (e.g., a memory die). The first flat surface of the double-sided semiconductor wafer may include a series or array of semiconductor dies. The first circuit layer also includes a redistribution layer (RDL) or is otherwise associated with a redistribution layer (RDL). The redistribution layer enables communication between various semiconductor dies on the first flat surface.

[0027] Likewise, the double-sided semiconductor wafer includes a second flat surface or face opposite to the first flat surface. A second circuit layer is disposed on the second flat surface. The second circuit layer may include a semiconductor die (e.g., a memory die). Similar to the first flat surface, the second flat surface of the double-sided semiconductor wafer may include a series or array of semiconductor dies. The second circuit layer also includes a redistribution layer (RDL) or is otherwise associated with a redistribution layer (RDL). The redistribution layer enables communication between various semiconductor dies on the second flat surface. One or more through silicon vias (TSVs) facilitate signal transmission between the semiconductor die on the first flat surface and the semiconductor die on the second flat surface.

[0028] In some examples, multiple double-sided semiconductor wafers can be stacked on top of each other to produce, for example, a high-capacity memory device. For example, a first planar surface of a first double-sided semiconductor wafer can be coupled or bonded to a second planar surface of a second double-sided semiconductor wafer. In an example, the first double-sided semiconductor wafer and the second double-sided semiconductor wafer can be coupled or otherwise bonded together by various wafer-to-wafer bonding processes (including but not limited to copper-to-copper bonding) and / or via one or more solder bumps / balls. The wafer-to-wafer bonding process enables high-speed signal transmission between double-sided semiconductor wafers and eliminates the need to use bonding wires to bond double-sided semiconductor wafers.

[0029] When the double-sided semiconductor wafers described herein are stacked on top of each other, these double-sided semiconductor wafers also reduce the risk of wafer warpage. For example, when a first circuit layer is manufactured on a first flat surface of a semiconductor wafer, stress is applied to the semiconductor wafer in a first direction. However, when a second circuit layer is manufactured and disposed on a second flat surface of the semiconductor wafer, a similar or identical amount of stress is applied to the semiconductor wafer in a second direction opposite to the first direction. The stress applied in the second direction effectively offsets the stress applied in the first direction, thereby reducing the risk of wafer warpage.

[0030] Accordingly, the double-sided semiconductor wafer of the present disclosure provides many technical benefits, including but not limited to effectively doubling the storage capacity of a memory device without significantly increasing the overall size of the package, reducing or minimizing the risk of wafer warping when the wafers are stacked together, high transfer speeds between double-sided semiconductor wafers due to the wafer-to-wafer bonding process, and reducing manufacturing costs in terms of time and materials.

[0031] About Figures 1 to 8C These and other examples are described in further detail.

[0032] Figure 1 A conventional semiconductor die 100 used in a memory device (eg, a three-dimensional (3D) NAND memory device) is illustrated. Figure 1 As shown, semiconductor wafer 100 includes a single circuit layer 110 disposed on a base layer 120. In an example, circuit layer 110 may include a semiconductor die. As briefly described above, in a conventional 3D NAND memory device, multiple semiconductor wafers 100 may be stacked on each other. In some examples, semiconductor wafer 100 may include one or more through silicon vias 130 that mechanically and / or electrically connect the individual semiconductor wafers together. In other examples, bonding wires may electrically couple bonding pads on a first semiconductor wafer to bonding pads on a second semiconductor wafer.

[0033] Figure 2A double-sided semiconductor wafer 200 having semiconductor dies on opposite planar surfaces according to an example is illustrated. The double-sided semiconductor wafer 200 can be used in a memory device such as, for example, a 3D NAND memory device. Although a 3D NAND memory device is specifically mentioned, the double-sided semiconductor wafer 200 can be used in various other semiconductor devices.

[0034] like Figure 2 As shown, the double-sided semiconductor wafer 200 includes a base layer 210. The base layer 210 may be made of silicon, such as, for example, silicon carbonitride (SiCN) and / or silicon dioxide (SiO2). The base layer 210 includes a first flat surface 220 and a second flat surface 230 opposite to the first flat surface 220.

[0035] The first circuit layer 240 is fabricated or otherwise disposed on the first planar surface 220. In an example, the first circuit layer 240 is fabricated on the first planar surface using a conventional fabrication process. The fabrication process may include one or more layering processes, one or more patterning processes, one or more doping processes, one or more heat treatment processes, one or more wafer cleaning processes, and / or one or more wafer smoothing processes. Figure 2 As shown, the first planar surface 220 may include a plurality of circuit layers or an array of semiconductor dies. In an example, the semiconductor dies may be memory dies.

[0036] In an example, the first circuit layer 240 includes or is otherwise associated with a redistribution layer 250. The redistribution layer 250 electrically connects each semiconductor die on the first planar surface 220 to other semiconductor die on the first planar surface 220.

[0037] The double-sided semiconductor wafer 200 also includes a second circuit layer 260. The second circuit layer 260 is fabricated or otherwise disposed on the second planar surface 230. In an example, the second circuit layer 260 is fabricated in a similar manner to the first circuit layer 240. For example, the first circuit layer can be fabricated on a first silicon wafer, the second circuit layer can be fabricated on a second silicon wafer, and the first silicon wafer can be bonded to the second silicon wafer, such as by bonding the first circuit layer 260 to the second silicon wafer. Figure 7 More detailed description. Figure 2 As shown in , the second planar surface 240 may include a plurality of circuit layers (eg, second circuit layer 260) or a semiconductor die array. In an example, the semiconductor die may be a memory die.

[0038] Similar to the first circuit layer 240 , the second circuit layer 260 may include or otherwise be associated with a redistribution layer 270 . The redistribution layer 270 electrically connects each semiconductor die on the second planar surface 230 to the other semiconductor die on the second planar surface 230 .

[0039] In an example, the double-sided semiconductor wafer 200 may further include one or more through silicon vias 280. The through silicon vias 280 may extend from the first circuit layer 240 through the base layer 210 to the second circuit layer 260. Thus, the through silicon vias 280 electrically couple the first circuit layer 240 or first side of the double-sided semiconductor wafer 200 to the second circuit layer 260 or second side of the double-sided semiconductor wafer 200. Although the through silicon vias 280 are shown in a circular pattern, the through silicon vias 280 may be arranged in any suitable manner.

[0040] Figure 3 A cross-sectional view of a double-sided semiconductor wafer 300 according to an example is illustrated. The double-sided semiconductor wafer 300 may be similar to the Figure 2 A double-sided semiconductor wafer 200 is shown and described.

[0041] For example, the double-sided semiconductor wafer 300 includes a base layer 310. The base layer 310 includes a first flat surface 320 and a second flat surface 330 opposite to the first flat surface 320. A first circuit layer 340 is manufactured on the first flat surface 320, and a second circuit layer 350 is manufactured on the second flat surface 330.

[0042] As indicated above, each of the first circuit layer 340 and the second circuit layer 350 may include a redistribution layer that enables signal transmission between various semiconductor dies disposed on the first planar surface 320 and the second planar surface 330. For example, a first redistribution layer 345 is disposed on the first planar surface 330 to enable signal transmission between various semiconductor dies on the first planar surface 320. Likewise, a second redistribution layer 355 is disposed on the second planar surface 330 to enable signal transmission between various semiconductor dies on the second planar surface 330.

[0043] The double-sided semiconductor wafer 300 also includes one or more through silicon vias 360. Each through silicon via 360 extends through the base layer 310 and enables signal transmission between the first circuit layer 340 and the second circuit layer 350.

[0044] Figure 4 A semiconductor device 400 according to an example is illustrated in which a plurality of double-sided semiconductor wafers (e.g., double-sided semiconductor wafer 410, double-sided semiconductor wafer 420, double-sided semiconductor wafer 430, and double-sided semiconductor wafer 440) have been stacked on each other. In the example shown, the semiconductor device 400 may be a memory device or a data storage device. When a conventional semiconductor wafer (e.g., semiconductor wafer 100 ( Figure 1 )) compared to typical memory devices, Figure 4The semiconductor device 400 shown can store twice the amount of data while consuming the same or similar amount of space. Figure 4 In the example shown, each double-sided semiconductor wafer in the semiconductor device 400 may be similar to Figure 2 A double-sided semiconductor wafer 200 is shown and described.

[0045] For example, the double-sided semiconductor wafer 410 may include a first planar surface 450 of the face. The first planar surface 450 may include an array or series of semiconductor dies 460. In an example, the plurality of semiconductor dies 460 are NAND memory dies, but other semiconductor dies may also be used. In an example, the first planar surface 450 also includes a redistribution layer such as described above to enable signal transmission between individual semiconductor dies in the array of semiconductor dies 460.

[0046] The double-sided semiconductor wafer 410 may also include a second planar surface 480 or face opposite the first planar surface 450. The second planar surface 480 also includes an array or series of semiconductor dies and redistribution layers, such as previously described. Figure 4 As shown, one or more through silicon vias 470 enable signal transmission between an array of semiconductor dies 460 on a first planar surface 450 and an array of semiconductor dies on a second planar surface 480 of the first double-sided semiconductor wafer 410. The same is true for other double-sided semiconductor wafers in the semiconductor device 400 (e.g., double-sided semiconductor wafer 420, double-sided semiconductor wafer 430, and double-sided semiconductor wafer 440).

[0047] When multiple double-sided semiconductor wafers are stacked together, such as Figure 4 As shown, the second planar surface (and / or one or more semiconductor dies on the second planar surface) of one double-sided semiconductor wafer is electrically coupled to the first planar surface (and / or one or more semiconductor dies on the first planar surface) of another double-sided semiconductor wafer. For example, the second planar surface 480 of the first double-sided semiconductor wafer 410 can be electrically coupled to the first planar surface 490 of the second double-sided semiconductor wafer 420.

[0048] although Figure 4 Four double-sided semiconductor wafers stacked together are shown, but the semiconductor device 400 can include any number of stacked double-sided semiconductor wafers without suffering from the various drawbacks of using conventional semiconductor wafers such as those described above. For example, the flat surfaces of each double-sided semiconductor wafer can be electrically coupled using a wafer-to-wafer bonding process. The wafer-to-wafer bonding process can be used to transmit signals between the respective double-sided semiconductor wafers in the double-sided semiconductor wafer, thereby eliminating the need to wire bond the different layers of the semiconductor device 400.

[0049] In an example, the wafer-to-wafer bonding process can be a copper-to-copper bonding process in which copper fingers or pillars from adjacent sides or surfaces of a double-sided semiconductor wafer can be bonded together using a high temperature annealing process. In another example, solder bumps can be used to electrically couple or otherwise bond adjacent surfaces or sides of a double-sided semiconductor wafer to each other.

[0050] When compared to conventional bonding wires, bonding such as described above enables higher signal transmission between double-sided semiconductor wafers. Accordingly, when compared to conventional wafer stacking, cost savings in terms of materials and / or time can be achieved by stacking double-sided semiconductor wafers in the manner described herein.

[0051] In an example, an outer edge or surface (or entire diameter) of a double-sided semiconductor wafer may be flush, aligned, or substantially aligned with each outer edge or surface of other double-sided semiconductor wafers in semiconductor device 400. Figure 4 As shown, outer edge 485 of first double-sided semiconductor wafer 410 is substantially aligned or flush with outer edge 495 of second double-sided semiconductor wafer 495. This arrangement is made possible by utilizing a wafer-to-wafer bonding process rather than bonding wires such as previously described.

[0052] As discussed above, in a typical stacked semiconductor device (e.g., a conventional 3D NAND memory device), the number of layers may be limited by the amount of stress induced on the semiconductor wafer when the circuit layers are fabricated on a single surface. As the number of wafers increases, the amount of stress also increases, which may subsequently warp the semiconductor wafer in the semiconductor device.

[0053] However, the double-sided semiconductor wafers described herein reduce the risk of wafer warpage because the amount of stress provided by the first circuit layer on the first flat surface of the semiconductor wafer is offset by the amount of stress provided by the second circuit layer on the second flat surface of the semiconductor wafer. Accordingly, any number of double-sided semiconductor wafers can be stacked on top of each other while eliminating or significantly reducing the risk of semiconductor wafer warpage. As such, the double-sided semiconductor wafers described herein can be used for ultra-large packaging capacity because n or more double-sided semiconductor wafers can be stacked.

[0054] Figure 5 The example according to Figure 4 A partial cross-sectional view of a semiconductor device 400 is shown. Figure 5 The partial cross-sectional view of FIG. 4 shows two different double-sided semiconductor wafers (eg, double-sided semiconductor wafer 410 and double-sided semiconductor wafer 420) electrically coupled or otherwise bonded together. Figure 4)). As with other double-sided semiconductor wafers shown and described herein, each double-sided semiconductor wafer includes a base layer 510. The base layer 510 includes a first planar surface 520 and a second planar surface 530 opposite to the first planar surface 520. A first circuit layer 540 is fabricated on the first planar surface 520, and a second circuit layer 550 is fabricated on the second planar surface 530.

[0055] As indicated above, each of the first circuit layer 540 and the second circuit layer 550 may include a redistribution layer (e.g., redistribution layer 545 and redistribution layer 555) that enables signal transmission between the various semiconductor dies included on the first planar surface 520 and the second planar surface 530. Each double-sided semiconductor wafer also includes one or more through silicon vias 560 that enable signal transmission between the first circuit layer 540 and the second circuit layer 550.

[0056] As also discussed above, each double-sided semiconductor wafer is electrically coupled or otherwise bonded together. For example, one or more copper bumps 570 or pillars may be disposed on or otherwise associated with the second flat surface 530 of one double-sided semiconductor wafer, and one or more copper bumps 580 or pillars may be disposed on or otherwise associated with the first flat surface 520 of another double-sided semiconductor wafer. A high temperature annealing process may be used to bond copper bumps 570 to copper bumps 580. The bonding force between copper bumps 570 and copper bumps 580 generated by high temperature may enable the stacking of double-sided semiconductor wafers to be completed or substantially completed during manufacturing. Accordingly, additional manufacturing steps of wafer attachment and wire bonding may not be required.

[0057] In some examples and such Figure 5 As shown, a silicon layer 590 or a silicon mixture (e.g., silicon dioxide or carbon nitride) or another substrate may be positioned on or otherwise associated with various planar surfaces and / or circuit layers. For example, a silicon layer 590 may be disposed on the outside / bottom surface of a second circuit layer 550 of one double-sided semiconductor wafer, while another silicon layer 590 may be disposed on the outside / top surface of a first circuit layer 540 of another double-sided semiconductor wafer on which the first double-sided semiconductor wafer is stacked. Copper bumps 570 or pillars may be disposed on or otherwise extend through the silicon layer 590 to enable signal transmission between double-sided semiconductor wafers.

[0058] Although copper bumps 570 or posts are specifically mentioned, solder bumps, solder balls, and / or other bonding processes may also be used to electrically couple the double-sided semiconductor wafer.

[0059] Figure 6It is illustrated how to electrically couple or bond the first double-sided semiconductor wafer 610 and the second double-sided semiconductor wafer 620 according to an example. Figure 6 It is also illustrated how the first double-sided semiconductor wafer 610 and the second double-sided semiconductor wafer 620 are electrically coupled or otherwise joined to the substrate 630 .

[0060] exist Figure 6 In the example shown, the first double-sided semiconductor wafer 610 and the second double-sided semiconductor wafer 620 are electrically coupled or otherwise bonded together using solder bumps 640 or solder balls. Figure 6 The bonding process shown and described can be performed at room temperature.

[0061] In order to bond the first double-sided semiconductor wafer 610 and the second double-sided semiconductor wafer 620, solder bumps 640 are bonded or otherwise provided on each surface (e.g., base layer, first circuit layer, second circuit layer) of the first double-sided semiconductor wafer 610. The first double-sided semiconductor wafer 610 can then be bonded to the substrate 630. In an example, the solder bumps 640 can be used for signal transmission between the first double-sided semiconductor wafer 610 and the substrate 630.

[0062] In a similar manner, a second double-sided semiconductor wafer 620 is added to the first double-sided semiconductor wafer 610. For example, solder bumps 640 are bonded or otherwise provided on each surface (e.g., base layer, first circuit layer, second circuit layer) of the second double-sided semiconductor wafer 620. The second double-sided semiconductor wafer 610 can then be bonded to the first double-sided semiconductor wafer 610. In an example, the solder bumps 640 can be used for signal transmission between the first double-sided semiconductor wafer 610 and the second double-sided semiconductor wafer 620. This process can be repeated for each additional double-sided semiconductor wafer added to the stack.

[0063] In an example, gaps 650 may exist between the respective double-sided semiconductor wafers and / or substrate 630. In this case, a mold compound (represented by shaded box 660) may be used to fill gaps 650. Although shaded box 660 is shown as partially covering the stack of double-sided semiconductor wafers, the mold compound may substantially surround or completely surround the gaps 650. Figure 6 The entire structure shown in FIG.

[0064] Figure 7 A method 700 for manufacturing a double-sided semiconductor wafer according to an example is illustrated. The method 700 can be used to manufacture various double-sided semiconductor wafers described herein.

[0065] Method 700 begins when a silicon wafer (710) is manufactured. In an example, the silicon wafer can be manufactured by any available or known manufacturing process. Once the silicon wafer is manufactured, a first circuit layer (720) is manufactured on a flat surface of the silicon wafer. In an example, the first circuit layer is manufactured using a conventional manufacturing process such as described above. As discussed above, although the first circuit layer is described, it should be understood that the manufacturing process can be used to produce a series or array of semiconductor dies on a flat surface of a silicon wafer. As part of the manufacturing process, a redistribution layer is added (730) to the first circuit layer / array of semiconductor dies or otherwise associated with the first circuit layer / array of semiconductor dies.

[0066] A carrier is then bonded (740) to the surface of the first circuit layer to protect and support the first circuit layer. In an example, the carrier can be an adhesive material. A thinning process (750) is then performed on the exposed surface of the silicon wafer. In an example, the silicon wafer can be thinned to about 100um (although other sizes can also be used). In an example, conventional thinning and / or grinding processes can be used.

[0067] Once the silicon wafer has been thinned, a doping process is performed 760 to add a doped layer on the exposed surface of the silicon wafer. The doped layer will act as a barrier between the first circuit layer and the second circuit layer (e.g., when the second circuit layer is combined with the first circuit layer, such as will be described in more detail below).

[0068] Once operations 710 to 760 have been performed on the first circuit layer, these operations are repeated to manufacture (770) the second circuit layer on a different second silicon wafer. Once the second circuit layer has been manufactured, the first silicon wafer and the second silicon wafer are bonded (780) together. In an example, this bonding process can be a high temperature annealing process. In an example, when the first silicon wafer and the second silicon wafer are bonded, the doped layer on the first silicon wafer faces the doped layer on the second silicon wafer. As described above, the doped layer prevents crosstalk between the first circuit layer and the second circuit layer. Once the wafers have been bonded, the carrier on the second circuit layer can be removed and silicon through vias (790) can be manufactured to enable the first circuit layer to communicate with the second circuit layer.

[0069] In some examples, a wafer (e.g., a CBA wafer) may have thermal constraints on the cell layer and the CMOS layer. For example, the CMOS layer is very sensitive to high temperature annealing processes. During manufacturing, the array layer typically undergoes many annealing processes. Thus, when manufacturing a wafer with thermal constraints, the array wafer may be prepared separately from the CMOS layer, and the two layers are joined together at the end to avoid subjecting the CMOS layer to annealing.

[0070] For example, a double-sided CMOS wafer can be as described above with respect to Figure 77. The process of manufacturing the through silicon vias may be performed in a similar manner as described above. For example, some or all of operations 710 to 780 may be used to manufacture the wafer. However, as an additional operation, two array wafers may be bonded on top of two different CMOS circuit surfaces. Once the array wafers have been bonded, through silicon vias may be manufactured between the two circuit surfaces. In an example, the through silicon via manufacturing process may be performed simultaneously (e.g., etching from the top surface / surface to the bottom surface / surface) or performed N times for each circuit layer.

[0071] FIG. 8A to FIG. 8C Various applications for double-sided semiconductor wafers such as described herein are illustrated according to various examples. For example, Fig. 8A A high-capacity memory device 800 is illustrated in which a plurality of double-sided semiconductor wafers 810 are stacked on a substrate 820. In an example, an application specific integrated circuit (ASIC) 830 may also be coupled to the substrate 800 to control various functions of the high-capacity memory device 800.

[0072] Figure 8B A multifunctional, double-sided high-capacity storage device 805 according to an example is illustrated. In this example, a first substrate 820 and an associated application specific integrated circuit (ASIC A) 830 are attached to a planar surface of a double-sided semiconductor wafer 810, while a second substrate 850 is attached to a planar surface of another double-sided semiconductor wafer 810. The second substrate may be associated with a second application specific integrated circuit (ASIC B) 840. The second substrate 850 and the second integrated circuit 840 may be different from the first substrate 820 and / or the first integrated circuit 830. For example, two different substrates and their associated application specific integrated circuits may be used to facilitate different writing and / or reading on different sides of the high-capacity storage device 805. For example, ASIC A 820 may control reading and / or writing at a first speed, while ASIC B 840 controls reading and / or writing at a different second speed.

[0073] Figure 8C A double-sided, high-speed, high-capacity storage device 815 according to an example is illustrated. In this example, the same or similar substrate (e.g., substrate 820) and similar application-specific integrated circuit (ASIC A) 830 are attached to two different double-sided semiconductor wafers 810. In this example, the substrate and its associated application-specific integrated circuit can be used to facilitate writing and / or reading on different sides of the high-capacity storage device 815 at the same or similar speed, thereby providing twice the data transfer speed when compared to the data transfer speed of the high-capacity storage device 800.

[0074] The description and illustration of one or more aspects provided in this disclosure are not intended to limit or restrict the scope of this disclosure in any way. The various aspects, examples, and details provided in this disclosure are considered to be sufficient to convey ownership and enable others to make and use the best way of the disclosed content protected by the claims.

[0075] The disclosure protected by the claims should not be understood to be limited to any aspect, example or detail provided in the present disclosure. Whether shown and described in combination or individually, various features (both structural features and method features) are intended to be selectively rearranged, included or omitted to produce an embodiment with a specific feature set. The description and illustration of the application have been provided, and those skilled in the art can envision changes, modifications and replacement aspects that fall within the spirit of the broader aspects of the general inventive concept embodied in the application and do not depart from the broader scope of the disclosure protected by the claims.

[0076] The use of names such as "first," "second," and the like to refer to elements herein does not generally limit the number or order of those elements. Rather, these names can be used as a method of distinguishing two or more elements or instances of elements. Thus, reference to a first element and a second element does not mean that only two elements may be used, nor does it mean that the first element must precede the second element. Additionally, unless otherwise specified, a group of elements may include one or more elements.

[0077] A term of the form "at least one of A, B, or C" or "A, B, C, or any combination thereof" used in the specification or claims means "A or B or C or any combination of these elements." For example, this term may include A, or B, or C, or A and B, or A and C, or A and B and C, or 2A, or 2B, or 2C, or 2A and B, etc. As an additional example, "at least one of A, B, or C" is intended to cover A, B, C, AB, AC, BC, and ABC, and multiples of the same member. Similarly, "at least one of A, B, and C" is intended to cover A, B, C, AB, AC, BC, and ABC, and multiples of the same member.

[0078] Similarly, as used herein, a phrase referring to a list of items linked with "and / or" refers to any combination of items. As an example, "A and / or B" is intended to cover A alone, B alone, or A and B together. As another example, "A, B, and / or C" is intended to cover A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together.

Claims

1. A semiconductor device, comprising: a double-sided semiconductor wafer having a first planar surface and a second planar surface opposite the first planar surface; a first plurality of semiconductor dies disposed on the first planar surface; a second plurality of semiconductor dies disposed on the second planar surface; and A plurality of through silicon vias electrically couples the first plurality of semiconductor dies on the first planar surface with the second plurality of semiconductor dies on the second planar surface. 2 . The semiconductor device of claim 1 , further comprising a first redistribution layer associated with the first plurality of semiconductor dies, the first redistribution layer enabling communication between the first plurality of semiconductor dies. 3 . The semiconductor device of claim 1 , further comprising a second redistribution layer associated with the second plurality of semiconductor dies, the second redistribution layer enabling communication between the second plurality of semiconductor dies.

4. The semiconductor device according to claim 1, wherein the double-sided semiconductor wafer is a first double-sided semiconductor wafer, and wherein the semiconductor device further comprises: a second double-sided semiconductor wafer having a first planar surface and a second planar surface opposite the first planar surface; a first plurality of semiconductor dies disposed on the first planar surface; a second plurality of semiconductor dies disposed on the second planar surface; and A plurality of through silicon vias electrically couples the first plurality of semiconductor dies on the first planar surface with the second plurality of semiconductor dies on the second planar surface. 5 . The semiconductor device according to claim 4 , wherein the first double-sided semiconductor wafer is electrically coupled to the second double-sided semiconductor wafer. 6 . The semiconductor device according to claim 5 , wherein the first double-sided semiconductor wafer is electrically coupled to the second double-sided semiconductor wafer via a copper-to-copper bond between the first double-sided semiconductor wafer and the second double-sided semiconductor wafer. 7 . The semiconductor device of claim 5 , wherein the first double-sided semiconductor wafer is electrically coupled to the second double-sided semiconductor wafer via one or more solder bumps. 8 . The semiconductor device of claim 5 , further comprising a molding compound disposed between a gap formed between the first double-sided semiconductor wafer and the second double-sided semiconductor wafer when the first double-sided semiconductor wafer and the second double-sided semiconductor wafer are electrically coupled. 9 . The semiconductor device of claim 1 , wherein the second planar surface is electrically coupled to a substrate.

10. A semiconductor device, comprising: a first double-sided semiconductor wafer having a first circuit layer on a first planar surface and a second circuit layer on a second planar surface opposite the first planar surface, the first circuit layer being electrically coupled to the second circuit layer; and a second double-sided semiconductor wafer, the second double-sided semiconductor wafer being electrically coupled to the first double-sided semiconductor wafer, the second double-sided semiconductor wafer having a first circuit layer on a first flat surface and a second circuit layer on a second flat surface opposite to the first flat surface, the first circuit layer of the second double-sided semiconductor wafer being electrically coupled to the second circuit layer of the first double-sided semiconductor wafer. 11 . The semiconductor device of claim 10 , further comprising a first redistribution layer associated with the first circuit layer and a second redistribution layer associated with the second circuit layer on the first double-sided semiconductor wafer. 12 . The semiconductor device according to claim 10 , further comprising one or more through silicon vias for electrically coupling the first circuit layer on the first double-sided semiconductor wafer with the second circuit layer on the first double-sided semiconductor wafer. 13 . The semiconductor device of claim 10 , wherein the first double-sided semiconductor wafer is electrically coupled to the second double-sided semiconductor wafer using copper-to-copper bonding. 14 . The semiconductor device of claim 10 , further comprising a substrate electrically coupled to the second circuit layer of the second double-sided semiconductor wafer. 15 . The semiconductor device according to claim 10 , wherein an outer edge of the first double-sided semiconductor wafer is substantially aligned with an outer edge of the second double-sided semiconductor wafer.

16. A method for manufacturing a semiconductor wafer, the method comprising: fabricating a first plurality of semiconductor die on a first planar surface of a first silicon wafer; fabricating a second plurality of semiconductor die on the first planar surface of the second silicon wafer; bonding the second planar surface of the first silicon wafer to the second planar surface of the second silicon wafer, the second planar surface of the first silicon wafer being opposite to the first planar surface of the first silicon wafer, and the second planar surface of the second silicon wafer being opposite to the first planar surface of the second silicon wafer; as well as One or more through silicon vias are fabricated through the first silicon wafer and the second silicon wafer to electrically couple the first plurality of semiconductor dies on the first planar surface of the first silicon wafer with the second plurality of semiconductor dies on the first planar surface of the second silicon wafer.

17. The method according to claim 16, further comprising: providing a first redistribution layer on the first planar surface of the first silicon wafer, the first redistribution layer electrically coupling the first plurality of semiconductor dies; as well as A second redistribution layer is provided on the first planar surface of the second silicon wafer, the second redistribution layer electrically coupling the second plurality of semiconductor dies.

18. The method of claim 16, further comprising doping the second planar surface of the first silicon wafer and the second planar surface of the second silicon wafer.

19. The method of claim 16, further comprising thinning the first silicon wafer and the second silicon wafer to a target thickness.

20. The method of claim 16, wherein the target thickness of the first silicon wafer and the second silicon wafer is approximately one hundred microns.

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