Preparation method and application of ferroelectric film

Abstract

The invention provides a preparation method of a ferroelectric film. The preparation method comprises the following steps: providing a first stress layer; depositing a hafnium elementary substance and a zirconium elementary substance on the first stress layer through a magnetron sputtering process to form a ferroelectric alloy layer; the ferroelectric alloy layer is oxidized, crystal defects and crystal phase transformation stress are generated in the ferroelectric alloy layer through heat released in the oxidation process, and a ferroelectric oxidation layer is formed; performing graphical processing on the ferroelectric oxide layer, and depositing a stress material in a graphical processing area of the ferroelectric oxide layer to form a second stress layer; and carrying out rapid thermal annealing treatment on a composite layer formed by the first stress layer, the ferroelectric alloy layer and the second stress layer to promote the crystalline phase of the ferroelectric alloy layer to be converted into a ferroelectric orthogonal phase so as to obtain the ferroelectric film. The invention also provides an application of the preparation method in a microelectronic device.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a method for preparing a ferroelectric thin film and its application. Background Art

[0002] Ferroelectric materials have been widely used in non-volatile semiconductor devices. Hafnium oxide (HfO2)-based ferroelectric materials have been widely studied and paid attention to due to their high scalability, good complementary metal oxide semiconductor (CMOS) compatibility and high performance in small-sized films. Among them, HfO2-based ferroelectric materials have shown good performance in non-volatile memory devices such as ferroelectric random access memory (FeRAM) and ferroelectric field effect transistor (FeFET).

[0003] However, the ferroelectric phase stability of HfO2-based ferroelectric materials and the manufacturing process of non-volatile semiconductor devices often have incompatibility issues. For example, the self-alignment technique in the manufacturing process of ferroelectric field effect transistors (FeFETs) is a technology widely used in microelectronics technology. It uses certain parts of the transistor structure (such as the gate) as a mask to automatically align other parts (such as the source and drain) in subsequent process steps, thereby reducing alignment errors and improving device performance and reliability. However, the self-alignment process usually diffuses the active area at high temperatures (1000°C). High temperatures will destroy the internal structure of the ferroelectric oxide film and thus affect the ferroelectricity. Therefore, traditional ferroelectric film preparation technology cannot directly realize the self-alignment process of FeFETs.

[0004] Therefore, designing a method for preparing ferroelectric thin films that is compatible with the stability of ferroelectric materials and high-temperature processing of semiconductors has far-reaching practical significance. Summary of the invention

[0005] In view of this, in order to solve at least one of the above-mentioned and other technical problems in the related art, the present disclosure proposes a method for preparing a ferroelectric thin film, including: providing a first stress layer; then depositing hafnium and zirconium on the first stress layer through a magnetron sputtering process to form a ferroelectric alloy layer; then oxidizing the ferroelectric alloy layer, using the heat released during the oxidation process to generate crystal defects and crystal phase transition stress in the ferroelectric alloy layer to form a ferroelectric oxide layer; then patterning the ferroelectric oxide layer, depositing stress material in the patterned area of ​​the ferroelectric oxide layer to form a second stress layer; finally, performing rapid thermal annealing on the composite layer formed by the first stress layer, the ferroelectric alloy layer and the second stress layer to promote the crystal phase of the ferroelectric alloy layer to transform into a ferroelectric orthorhombic phase to obtain a ferroelectric thin film.

[0006] According to an embodiment of the present disclosure, in the magnetron sputtering process, the sputtering ratio of hafnium element and zirconium element is 2:1.

[0007] According to an embodiment of the present disclosure, in the magnetron sputtering process, the sputtering gas atmosphere is a mixed gas of argon and oxygen, wherein the flux of argon is 40 sccm and the flux of oxygen is 0.6 sccm.

[0008] According to an embodiment of the present disclosure, in the oxidation treatment, the oxidation temperature is 300-400° C., and the oxidation time is 3 hours.

[0009] According to an embodiment of the present disclosure, a deposition method of the first stress layer and the second stress layer includes any one of an ion beam sputtering process, a direct current sputtering process, and a reactive sputtering process.

[0010] According to an embodiment of the present disclosure, in the ion beam sputtering process, the sputtering atmosphere is a mixed gas of argon and nitrogen, the beam voltage is 700-900V, the beam current is 40-60mA, and the acceleration voltage is 150-170V.

[0011] According to an embodiment of the present disclosure, the first stress layer and the second stress layer are symmetrical structures, and the stress material includes at least one of titanium nitride, tungsten, palladium nitride, high-conductivity silicon, indium, ruthenium, ruthenium dioxide, platinum and palladium.

[0012] According to an embodiment of the present disclosure, in the rapid thermal annealing process, the annealing atmosphere is nitrogen, the annealing temperature is 500-600° C., and the annealing time is 30 s-1 min.

[0013] According to an embodiment of the present disclosure, the patterning process includes: coating, exposing, and developing the ferroelectric oxide layer to obtain a patterning process region of the ferroelectric oxide layer.

[0014] In another aspect of the present disclosure, an application of the above-mentioned preparation method in a microelectronic device is also proposed, wherein the microelectronic device includes any one of a ferroelectric capacitor, a ferroelectric transistor, and a ferroelectric random access memory.

[0015] According to the embodiments of the present disclosure, unlike the preparation process of depositing hafnium and zirconium oxides in the related art, the present disclosure deposits hafnium and zirconium to form a ferroelectric alloy layer. The advantage of depositing a single substance is that it allows the oxygen content in the ferroelectric film to be more accurately controlled in the subsequent oxidation process. By adjusting the conditions of the oxidation treatment (such as oxygen partial pressure, temperature and time), the stoichiometric ratio of the components of the ferroelectric film can be finely controlled, thereby optimizing the ferroelectric properties of the film. During the oxidation process, the ferroelectric alloy layer is induced to have defects and transition stresses by continuously releasing heat. In the subsequent thermal annealing treatment, these defects and transition stresses are eliminated by rearrangement and diffusion of atoms, and ferroelectric domains are formed at the same time. Using the preparation method of the ferroelectric film proposed in the present disclosure, since the oxidation process has partially "preheated" the ferroelectric alloy layer, there are more defects and stresses inside the oxide film, so the energy required for the thermal annealing process is relatively low, which reduces the annealing temperature. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a flow chart of a method for preparing a ferroelectric thin film in an embodiment of the present disclosure;

[0017] Figure 2 It is a cross-sectional structure diagram of the device during the preparation process of the ferroelectric capacitor in Example 1 of the present disclosure, wherein a is a cross-sectional structure diagram of the substrate, b is a cross-sectional structure diagram after depositing the first stress layer, c is a cross-sectional structure diagram after depositing the ferroelectric alloy layer, and d is a cross-sectional structure diagram after depositing the second stress layer.

[0018] Description of Reference Numerals

[0019] The meanings of the reference numerals are:

[0020] 201 - substrate; 202 - first stress layer; 203 - ferroelectric alloy layer; 204 - second stress layer. DETAILED DESCRIPTION

[0021] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0022] The endpoints and any values ​​of the ranges disclosed in this disclosure are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, and these numerical ranges should be regarded as specifically disclosed in this disclosure.

[0023] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise", "include", etc. used herein indicate the existence of the features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

[0024] All terms (including technical and scientific terms) used herein have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0025] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the usual meanings understood by persons with ordinary skills in the field to which the present disclosure belongs. If the full text involves descriptions such as "first", "second", etc., the descriptions such as "first", "second", etc. are only used to distinguish similar objects, and cannot be understood as indicating or implying their relative importance, order of precedence, or implicitly indicating the number of technical features indicated. It should be understood that the data described by "first", "second", etc. can be interchangeable under appropriate circumstances.

[0026] In order to make the purpose, technical solution and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of them.

[0027] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise", "include", etc. used herein indicate the existence of the features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

[0028] Throughout the drawings, the same elements are represented by the same or similar reference numerals. Conventional structures or configurations will be omitted when they may cause confusion in the understanding of the present disclosure. The shapes, sizes, and positional relationships of the components in the drawings do not reflect the actual size, proportion, and actual positional relationship. In addition, in the present disclosure, any reference symbol between brackets should not be constructed as a limitation to the present disclosure.

[0029] Similarly, in order to simplify the present disclosure and help understand one or more of the various disclosed aspects, in the above description of the exemplary embodiments of the present disclosure, the various features of the present disclosure are sometimes grouped together into a single embodiment, figure, or description thereof. The description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" and the like means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0030] In addition, the technical solutions between the various embodiments can be combined with each other, but it must be based on the fact that ordinary technicians in the field can implement it. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this disclosure.

[0031] During the implementation of the present disclosure, it was found that the self-alignment step in the CMOS process usually needs to be performed at a high temperature (>1000°C) to ensure that the impurity elements can effectively diffuse into the semiconductor material to form the required PN junction or other structure. This high-temperature treatment is an indispensable part of the CMOS process. The traditional ferroelectric oxide film has a specific crystal structure and chemical composition, and these characteristics determine its ferroelectric properties. However, high-temperature treatment will destroy this fine crystal structure, resulting in a decrease or even loss of the ferroelectric properties of the film. Therefore, the ferroelectric oxide film is unstable at high temperatures. In summary, in order to overcome this technical difficulty, it is necessary to develop a new ferroelectric film preparation technology or improve the existing CMOS process. The present disclosure reduces the ferroelectric annealing temperature by designing the ferroelectric film preparation process into a single substance-oxidation state. At the same time, the self-alignment process can also be carried out in the oxidation state stage with better stability, and then thermal annealing is performed to induce the generation of the ferroelectric phase, thereby avoiding the influence of high temperature on the ferroelectric phase material.

[0032] Figure 1 It is a flow chart of the method for preparing the ferroelectric thin film in the embodiment of the present disclosure.

[0033] The present disclosure provides a method for preparing a ferroelectric thin film, such as Figure 1 As shown, including:

[0034] Step S101: providing a first stress layer;

[0035] Step S102: depositing hafnium and zirconium on the first stress layer by a magnetron sputtering process to form a ferroelectric alloy layer;

[0036] Step S103: oxidizing the ferroelectric alloy layer, using the heat released during the oxidation process to generate crystal defects and crystal phase transition stress in the ferroelectric alloy layer, thereby forming a ferroelectric oxide layer;

[0037] Step S104: performing patterning on the ferroelectric oxide layer, and depositing stress material in the patterned region of the ferroelectric oxide layer to form a second stress layer;

[0038] Step S105: performing rapid thermal annealing on the composite layer formed by the first stress layer, the ferroelectric alloy layer and the second stress layer to promote the crystal phase of the ferroelectric alloy layer to transform into a ferroelectric orthorhombic phase, thereby obtaining a ferroelectric thin film.

[0039] According to the embodiments of the present disclosure, unlike the preparation process of depositing hafnium and zirconium oxides in the related art, the present disclosure deposits hafnium and zirconium to form a ferroelectric alloy layer. The advantage of depositing a single substance is that it allows the oxygen content in the ferroelectric film to be more accurately controlled in the subsequent oxidation process. By adjusting the conditions of the oxidation treatment (such as oxygen partial pressure, temperature and time), the stoichiometric ratio of the components of the ferroelectric film can be finely controlled, thereby optimizing the ferroelectric properties of the film. During the oxidation process, the ferroelectric alloy layer is induced to have defects and transition stresses by continuously releasing heat. In the subsequent thermal annealing treatment, these defects and transition stresses are eliminated by rearrangement and diffusion of atoms, and ferroelectric domains are formed at the same time. Using the preparation method of the ferroelectric film proposed in the present disclosure, since the oxidation process has partially "preheated" the ferroelectric alloy layer, there are more defects and stresses inside the oxide film, so the energy required for the thermal annealing process is relatively low, which reduces the annealing temperature.

[0040] According to an embodiment of the present disclosure, in the magnetron sputtering process of step S102 , the sputtering ratio of hafnium element and zirconium element is 2:1.

[0041] According to the embodiments of the present disclosure, the component ratio of hafnium and zirconium in the ferroelectric alloy can be controlled by controlling the sputtering ratio of the two elements. Controlling the ratio of hafnium and zirconium is beneficial to designing the subsequent oxidation degree, thereby obtaining a ferroelectric film with good ferroelectric properties.

[0042] According to an embodiment of the present disclosure, in the magnetron sputtering process of step S102, the sputtering gas atmosphere is a mixed gas of argon and oxygen, wherein the flux of argon is 40 sccm and the flux of oxygen is 0.6 sccm.

[0043] According to the embodiments of the present disclosure, a trace amount of oxygen is added when sputtering a single substance in a magnetron sputtering process in order to achieve the specific coating effect and performance requirements of the present disclosure, rather than simply causing oxidation. By precisely controlling the sputtering process parameters and the oxygen content in the sputtering gas atmosphere, a hafnium-zirconium ferroelectric alloy layer with excellent ferroelectric properties can be obtained.

[0044] According to an embodiment of the present disclosure, in the oxidation treatment of step S103, the oxidation temperature is 300-400° C., and the oxidation time is 3 hours.

[0045] According to the embodiment of the present disclosure, in the method for preparing the ferroelectric thin film proposed in the present disclosure, the first thing to be deposited is a single-element thin film. In the subsequent oxidation process, the single-element thin film will react with oxygen to form an oxide. The oxidation process itself is an exothermic reaction and will release a certain amount of heat. Therefore, the temperature does not need to be too high during oxidation.

[0046] According to an embodiment of the present disclosure, the first stress layer and the second stress layer are symmetrical structures, and the stress material includes at least one of titanium nitride, tungsten, palladium nitride, high-conductivity silicon, indium, ruthenium, ruthenium dioxide, platinum and palladium.

[0047] According to an embodiment of the present disclosure, during the thermal annealing process of step S105, stresses will accumulate inside the ferroelectric oxide layer, and these stresses may come from factors such as thin film deposition or lattice mismatch during the preparation of the ferroelectric oxide layer. The stress layers on the upper and lower surfaces of the ferroelectric oxide layer can provide a mechanism to manage stress, optimize interface performance, and ensure the structural stability of the ferroelectric phase. At the same time, the symmetrical structure of the first stress layer and the second stress layer can ensure that the stresses received by the upper and lower surfaces of the ferroelectric oxide layer are the same, thereby ensuring stability.

[0048] According to an embodiment of the present disclosure, in step S101 and step S104, the deposition method of the first stress layer and the second stress layer includes any one of an ion beam sputtering process, direct current sputtering, and reactive sputtering.

[0049] According to an embodiment of the present disclosure, in step S101 and step S104, in the ion beam sputtering process, the sputtering atmosphere is a mixture of argon and nitrogen, the beam voltage is 700-900V, for example, it can be 700V, 750V, 800V, 850V, 900V, etc., the beam current is 40-60mA, for example, it can be 40mA, 45mA, 50mA, 55mA, 60mA, etc., and the acceleration voltage is 150-170V, for example, it can be 150V, 155V, 160V, 165V, 170V, etc.

[0050] According to an embodiment of the present disclosure, in the rapid thermal annealing treatment of step S105, the annealing atmosphere is nitrogen, the annealing temperature is 500-600°C, for example, it can be 500°C, 510°C, 520°C, 530°C, 540°C, 550°C, 560°C, 570°C, 580°C, 590°C, 600°C, etc., and the annealing time is 30s-1min, for example, it can be 30s, 30s, 30s, 1min, etc.

[0051] According to an embodiment of the present disclosure, the patterning process includes: coating, exposing, and developing the ferroelectric oxide layer to obtain a patterning process region of the ferroelectric oxide layer.

[0052] According to an embodiment of the present disclosure, in step S104, after the second stress layer is formed, cleaning is required to remove the photoresist and the excess deposited stress material.

[0053] In some specific embodiments, the first stress layer is deposited on a substrate, and the substrate may be made of a semiconductor material, for example, a substrate made of silicon or silicon oxide alone, or a multilayer substrate composed of silicon and silicon oxide, or a semiconductor substrate made of zirconium, arsenic oxide, etc. When silicon is used as the substrate, the thickness of the substrate may be 500um; when a multilayer substrate composed of silicon and silicon oxide is used, the thickness of silicon in the substrate may be 500um, and the thickness of hydrogenated silicon may be 300nm.

[0054] In another aspect of the present disclosure, an application of the above-mentioned preparation method in a microelectronic device is also proposed, wherein the microelectronic device includes any one of a ferroelectric capacitor, a ferroelectric transistor, and a ferroelectric random access memory.

[0055] According to the embodiments of the present disclosure, when the aforementioned method for preparing the ferroelectric thin film is applied to a ferroelectric capacitor, the first stress layer may be a first electrode, and the second stress layer may be a second electrode; when the aforementioned method for preparing the ferroelectric thin film is applied to a ferroelectric transistor, the first stress layer may be a semiconductor layer, a bottom electrode or a gate, and the second stress layer may be a metal layer, a top electrode or an insulating layer. A ferroelectric random access memory is generally composed of a field effect transistor and a ferroelectric capacitor.

[0056] It should be noted that the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments of the present disclosure, other embodiments obtained by ordinary technicians in the field without creative work are all within the scope of protection of the present disclosure.

[0057] Example 1

[0058] Taking the preparation process of ferroelectric capacitor as an example, the following explanation is given:

[0059] Figure 2 1 is a cross-sectional structure diagram of a device during the preparation process of a ferroelectric capacitor in Example 1 of the present disclosure, wherein (a) is a cross-sectional structure diagram of a substrate, (b) is a cross-sectional structure diagram after depositing a first stress layer, (c) is a cross-sectional structure diagram after depositing a ferroelectric alloy layer, and (d) is a cross-sectional structure diagram after depositing a second stress layer.

[0060] The substrate 201 is formed by using silicon Si as the substrate material, the first electrode 202 and the second electrode 204 are formed by using TiN, the first electrode 202 and the second electrode 204 are formed by using ion beam sputtering, and the metal alloy layer 203 is formed by using magnetron sputtering.

[0061] Under the conditions of a beam voltage of 800 V, a beam current of 50 mA, an acceleration voltage of 160 V, and argon (Ar) and nitrogen (N2) gases, a titanium nitride (TiN) target is sputtered on a substrate 201 to obtain a first electrode 202, wherein the flow rate of argon (Ar) is 8 sccm, and the flow rate of nitrogen (N2) is 5 sccm; the thickness of the prepared first electrode 202 is not less than 10 nm.

[0062] First, select Hf target and Zr target, the purity of the two targets is above 99%; install the Hf target and Zr target on the magnetron sputtering coating equipment, and set the sputtering power of the Hf target and the ZrO2 target based on the AC power supply, wherein the power of the two targets is adjusted to keep the composition ratio of Hf and Zr at about 2:1, and obtain the ferroelectric alloy layer 203 with a thickness of 10nm. The amount of Ar introduced is 40sccm, and the amount of O2 introduced is 0.6sccm.

[0063] The obtained substrate 201 - first electrode 202 - ferroelectric alloy layer 203 structure is oxidized in an oxygen (O2) atmosphere at 400°C for 3 hours to obtain a completely oxidized ferroelectric oxide layer.

[0064] A negative resist is coated on the ferroelectric oxide layer, and the layer can be baked at 150°C for 2 minutes, and then baked at 120°C for 2 minutes after exposure, and then immersed in a developer for 45 seconds for development, and then rinsed with deionized water and blown dry.

[0065] Under the conditions of beam voltage of 800V, beam current of 50mA, acceleration voltage of 160V, argon (Ar) and nitrogen (N2) as the gas, a titanium nitride (TiN) target is sputtered on the ferroelectric oxide layer to obtain a second electrode 204, the thickness of the second electrode 204 is not less than 10nm. The flow rate of argon (Ar) is 8sccm, and the flow rate of nitrogen (N2) is 5sccm.

[0066] The ferroelectric capacitor having the capacitor substrate layer 201, the first electrode 202, the oxide film layer 203 and the second electrode 204 obtained above is immersed in an acetone solution until the photoresist and the excess metal fall off; then immersed in anhydrous ethanol to remove the acetone; and then rinsed with deionized water and blown dry.

[0067] Finally, the rinsed and dried ferroelectric capacitor was annealed in a nitrogen (N2) atmosphere at 600°C for 30s to obtain a ferroelectric capacitor with ferroelectric properties.

[0068] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present disclosure. It should be understood that the above description is only a specific embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A method for preparing a ferroelectric thin film, comprising: providing a first stress layer; Depositing hafnium and zirconium on the first stress layer by magnetron sputtering to form a ferroelectric alloy layer; Oxidizing the ferroelectric alloy layer, using the heat released during the oxidation process to generate crystal defects and crystal phase transition stress in the ferroelectric alloy layer to form a ferroelectric oxide layer; Performing patterning on the ferroelectric oxide layer, and depositing stress material in the patterning region of the ferroelectric oxide layer to form a second stress layer; A composite layer formed by the first stress layer, the ferroelectric alloy layer and the second stress layer is subjected to rapid thermal annealing treatment to promote the crystal phase of the ferroelectric alloy layer to transform into a ferroelectric orthorhombic phase, thereby obtaining a ferroelectric thin film.

2. The preparation method according to claim 1, wherein In the magnetron sputtering process, the sputtering ratio of the hafnium element and the zirconium element is 2:

1.

3. The preparation method according to claim 2, wherein In the magnetron sputtering process, the sputtering gas atmosphere is a mixed gas of argon and oxygen, wherein the flux of argon is 40 sccm and the flux of oxygen is 0.6 sccm.

4. The preparation method according to claim 1, wherein In the oxidation treatment, the oxidation temperature is 300-400° C. and the oxidation time is 3 hours.

5. The preparation method according to claim 1, wherein The deposition method of the first stress layer and the second stress layer includes any one of ion beam sputtering, direct current sputtering, and reactive sputtering.

6. The preparation method according to claim 5, wherein: In the ion beam sputtering process, the sputtering atmosphere is a mixed gas of argon and nitrogen, the beam voltage is 700-900V, the beam current is 40-60mA, and the acceleration voltage is 150-170V.

7. The preparation method according to claim 1, wherein The first stress layer and the second stress layer are symmetrical structures, and the stress material includes at least one of titanium nitride, tungsten, palladium nitride, high-conductivity silicon, indium, ruthenium, ruthenium dioxide, platinum and palladium.

8. The preparation method according to claim 1, wherein In the rapid thermal annealing treatment, the annealing atmosphere is nitrogen, the annealing temperature is 500-600° C., and the annealing time is 30 seconds to 1 minute.

9. The preparation method according to claim 1, wherein: The patterning process includes: coating, exposing and developing the ferroelectric oxide layer to obtain a patterning process area of ​​the ferroelectric oxide layer.

10. Use of the preparation method according to any one of claims 1 to 9 in a microelectronic device, wherein: The microelectronic device includes any one of a ferroelectric capacitor, a ferroelectric transistor, and a ferroelectric random access memory.

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